Semiconductor integrated device

Abstract

The embodiment of the present application provides a kind of semiconductor integrated device, including cell, the shape of the cell is positive K polygon, wherein, the value of K is 4 or 6 or 8;The diagonal of the cell divides cell into K positive triangle structure, and one positive triangle structure contains one integrated HJD MOSFET or one integrated SBD MOSFET;Integrated HJD MOSFET is n, and integrated SBD MOSFET is m;Wherein, n and m are positive integer and the sum of n and m is K.The embodiment of the present application solves the technical problem that the reliability and turn-on capability of the conventional integrated schottky diode device are limited.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor integrated device. Background Technology

[0002] Silicon carbide VDMOS devices have advantages such as high voltage withstand capability, low on-resistance, faster switching speed, higher operating temperature, better heat dissipation and good radiation resistance, and are widely used in power electronic circuits.

[0003] To achieve better device performance in practical applications, in 2016, the BJ Baliga team at North Carolina State University proposed a method for integrating MOSFETs into diodes to optimize the device's third-quadrant characteristics. They used nickel (Ni) to form Schottky contacts, utilizing the P-well region to shield the electric field of the Schottky contact region, thus reducing leakage current. Figure 1-1 This type is also called a split-source SBD integrated MOSFET, where SBD is the abbreviation for Schottky barrier diode.

[0004] In 2017, patent CN107275407B proposed a split-gate SiC VDMOS, in which the MOSFET has a split gate in the middle ( Figure 1-2 The heterojunction diode HJD is integrated between the first polysilicon gate 2 and the second polysilicon gate 21. Figure 2 The P+ polysilicon layer 12, the P-type silicon carbide region 13 and the metal electrode 14) are etched into the surface of the JFET to form a trench. P-type doping is performed at the bottom of the trench to form the P-type silicon carbide region 13. Then, a Poly layer (first polysilicon gate 2 and second polysilicon gate 21) is deposited in the trench to form a heterojunction diode HJD.

[0005] Among them, such as Figure 1-2 As shown, the structure includes a first gate electrode 1, a second gate electrode 11, a P+ polysilicon layer 12, a P-type silicon carbide region 13, a metal electrode 14, a first polysilicon gate 2, a second polysilicon gate 21, a first metal source electrode 3, a second metal source electrode 31, a first gate dielectric layer 4, a second gate dielectric layer 41, a first P+ contact region 5, a second P+ contact region 51, a first N+ source region 6, a second N+ source region 61, a first Pbase region 7, a second Pbase region 71, an N- epitaxial layer 8, an N+ substrate 9, and a metal drain electrode 10.

[0006] In 2019, the University of Electronic Science and Technology of China applied for a patent for a 4H-SiC MOSFET device with a split gate, patent number CN110534576 A. This device achieves a low reverse conduction voltage drop by integrating a split gate (SBD) in the middle of the gate, with a Schottky contact in the middle. Figure 1-3 As shown.

[0007] Figure 2 A cross-sectional view of a structure consisting of half of two adjacent cells in a traditional VDMOS device; Figure 3 for Figure 2 The top perspective view of two adjacent cells at position AA shown. Figure 2 and Figure 3 In the diagram, the vertical dashed lines represent the cell boundaries. For example, ... Figure 2 and Figure 3 As shown, substrate 2-1, drift region 2-2, channel contact region 2-31, channel region 2-32, source 2-32-1, JFET region 2-33, ohmic contact region 2-41, isolation region 2-42, gate 2-42-1, and source metal 2-5. Figure 2 and Figure 3 The reason why the same area in the image displays different shapes is that... Figure 3 This is a top-down perspective view, and some areas are shown in perspective. (As shown in...) Figure 2 In this context, the individual ohmic contact area 2-41 is a relatively wide strip. Correspondingly, in... Figure 3 In the diagram, due to perspective, the ohmic contact area 2-4 is shown, but the narrower channel contact area 2-31 located below it is also visible. Figure 3 Visually, there are two narrow ohmic contact areas 2-41 on both sides of the channel contact area 2-31.

[0008] To improve reliability, current integrated Schottky diode devices (such as...) Figure 1-1 and Figure 1-3 The devices shown are integrated using strip cells on the layout, which sacrifices channel density and limits the device's conductivity. In order to ensure the device's low reverse conductivity, a lot of chip area is sacrificed to make Schottky contacts, which requires additional costs.

[0009] Traditional VDMOS devices also employ strip cell integration in their layout, such as... Figure 2 As shown.

[0010] Therefore, the conduction capability of traditional integrated Schottky diode devices is limited, which is a technical problem that urgently needs to be solved by those skilled in the art.

[0011] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0012] This application provides a semiconductor integrated device to solve the technical problem of limited conduction capability in traditional integrated Schottky diode devices, while ensuring the reliability of the semiconductor integrated device.

[0013] This application provides a semiconductor integrated device, including a cell, wherein the cell is a regular K-sided polygon, and K is 4, 6 or 8; the diagonal of the cell divides the cell into K equilateral triangle structures, and each equilateral triangle structure contains a MOSFET with integrated HJD or an integrated SBD.

[0014] There are n MOSFETs integrated with HJD and m MOSFETs integrated with SBD;

[0015] Where n and m are positive integers and the sum of n and m is K.

[0016] In practice, the cell is a regular hexagonal cell, and the three diagonals of the regular hexagon of the cell divide the cell into six equilateral triangle structures;

[0017] Where n and m are positive integers and the sum of n and m is six. The range of values ​​is greater than or equal to Less than or equal to 2.

[0018] The embodiments of this application, by adopting the above technical solutions, have the following technical effects:

[0019] Background technology includes split-source SBD integrated MOSFETs with strip cell arrangement design, such as Figure 2 As shown in the figure, this application integrates a heterojunction diode (HJD) and a Schottky diode (SBD) into a single cell, using a regular K-sided polygon, such as a hexagonal arrangement. The regular K-sided polygon increases channel density and conduction current, addressing the insufficient conduction capability of strip-cell array devices. Furthermore, the interleaved design of the HJD and SBD results in a lower reverse on-state voltage drop, improved reliability, a smaller chip area, and reduced cost. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0021] Figure 1-1 This is a schematic diagram of a split-source SBD integrated MOSFET proposed by the BJ Baliga team at North Carolina State University in 2016, as shown in the background art.

[0022] Figure 1-2 This is a schematic diagram of a split-gate SiC VDMOS according to patent CN107275407B;

[0023] Figure 1-3 This is a schematic diagram of patent application CN 110534576 A;

[0024] Figure 2 A cross-sectional view of a structure consisting of half of two adjacent cells in a traditional VDMOS device;

[0025] Figure 3 for Figure 2 Top perspective view of two adjacent cells at position AA shown;

[0026] Figure 4-1 This is a three-dimensional perspective view of the cell of the semiconductor integrated device according to an embodiment of this application;

[0027] Figure 4-2 for Figure 4-1 A three-dimensional perspective diagram of the partial deletion in the JFET region 33;

[0028] Figure 5 for Figure 4-2 A cross-sectional view of a structure consisting of half of the two cells adjacent to the OA position;

[0029] Figure 6 for Figure 4-2 A cross-sectional view of a structure consisting of half of two adjacent cells at position OB;

[0030] Figure 7 for Figure 4-1 The cell shown is in the state where the source metal is removed and in Figure 5 A perspective view of a single cell in the XY direction at the CC position;

[0031] Figure 8 for Figure 7 A magnified view of a portion of the image;

[0032] Figure 9 for Figure 4-1 The cell shown is in the case of removing the source metal and the first gate and in Figure 6 A perspective view of a single cell in the XY direction at the DD position shown.

[0033] Figure 10 for Figure 9 A magnified view of a portion of the image;

[0034] Figure 11-1 Simulation device modeling diagram for MOSFETs with integrated SBD in existing technology;

[0035] Figure 11-2 This is a simulation device modeling diagram of the cell of the semiconductor integrated device in the embodiment of this application;

[0036] Figure 12 for Figure 11-1 and Figure 11-2 The graph shows the on-current of the two devices as a function of the source-drain voltage Vsd.

[0037] Figure 13 for Figure 11-1 and Figure 11-2 The graph shows the drain current of the two devices as a function of drain voltage.

[0038] Figure 14 for Figure 13 A graph of the vertical axis index.

[0039] Figure label:

[0040] Substrate 1, Drift region 2,

[0041] Channel contact region 31, channel region 32, source electrode 32-1,

[0042] JFET region 33, P-poly region 33-1, second P+ injection region 33-2

[0043] Ohmic contact region 41, isolation region 42, first gate 42-1, second gate 42-2,

[0044] Schottky contact zone 43,

[0045] Source metal 5. Detailed Implementation

[0046] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0047] Example 1

[0048] like Figure 7 As shown, the semiconductor integrated device of this application embodiment includes a cell, the shape of which is a regular K-gon, wherein the value of K is 4, 6 or 8; the diagonal of the cell divides the cell into K equilateral triangle structures, and each equilateral triangle structure contains a MOSFET with integrated HJD or a MOSFET with integrated SBD.

[0049] There are n MOSFETs integrated with HJD and m MOSFETs integrated with SBD;

[0050] Where n and m are positive integers and the sum of n and m is K.

[0051] During implementation, such as Figure 7As shown, the cell is a regular hexagonal cell, and the three diagonals of the regular hexagonal cell divide the cell into six equilateral triangle structures;

[0052] There are n MOSFETs with integrated HJD and m MOSFETs with integrated SBD in the six equilateral triangle structures;

[0053] Where n and m are positive integers and the sum of n and m is six. The range of values ​​is greater than or equal to Less than or equal to 2.

[0054] Background technology includes split-source SBD integrated MOSFETs with strip cell arrangement design, such as Figure 2 As shown in the figure. In this application, a heterojunction diode (HJD) and a Schottky diode (SBD) are integrated into the same cell. The conduction capability of the heterojunction diode (HJD) is superior to that of the Schottky diode (SBD), making the conduction capability of the semiconductor integrated device of this application superior to that of existing devices integrating Schottky diodes.

[0055] Meanwhile, the use of hexagonal cell arrangement can increase channel density and conduction current, solving the problem of insufficient conduction capability of strip cell arrangement devices in the prior art.

[0056] Meanwhile, the interleaved design of HJD and SBD results in a lower reverse on-state voltage drop and improved device reliability.

[0057] Specifically, SBD is the abbreviation for Schottky barrier diode; HJD is the abbreviation for heterojunction diode.

[0058] As the first optional approach, m is 2, and there are two MOSFETs integrating the SBD;

[0059] n is 4, and there are four MOSFETs integrated with HJD.

[0060] That is, the area ratio of the MOSFET with integrated HJD to the MOSFET with integrated SBD is 2.

[0061] As a second option, m is 4, and there are four MOSFETs integrating the SBD;

[0062] With n = 2, there are two MOSFETs with integrated HJD (High-Job Diode) technology. These two MOSFETs are arranged in a regular hexagon with their vertices facing each other. Four MOSFETs with integrated SBD (Single-Digital Booster) technology are arranged in pairs at the two intervals between the two HJD MOSFETs. That is, the area ratio of the HJD MOSFETs to the SBD MOSFETs is 1:2.

[0063] The accompanying drawings of this application illustrate the first optional configuration (two MOSFETs integrated with SBD, and four MOSFETs integrated with HJD), arranged as follows: Figure 7 As shown:

[0064] The regular hexagon of the cell and its three diagonals are shown in dashed lines. The MOSFET of each integrated SBD is an equilateral triangle, and the MOSFET of each integrated HJD is an equilateral triangle.

[0065] Two MOSFETs with integrated SBDs are arranged in a regular hexagon with their vertices facing each other.

[0066] Four integrated HJD MOSFETs are positioned in pairs at two intervals between the two integrated SBD MOSFETs.

[0067] by Figure 7 The two integrated SBD MOSFETs and the two integrated SBD MOSFETs arranged in a manner that ensures symmetrical structure and high reliability of individual cells, further simplify the process of forming a semiconductor device by arranging multiple cells. Thus, the semiconductor integrated device of this application has a single-cell structure and a simple, repetitive arrangement, making its fabrication simple and rapid.

[0068] The semiconductor integrated device in this application embodiment:

[0069] First, each cell integrates two MOSFETs with integrated SBDs and four heterojunction diodes (HJDs).

[0070] Secondly, the arrangement of the two integrated SBD MOSFETs and the four integrated HJD MOSFETs is defined as follows: the two integrated SBD MOSFETs are arranged in a regular hexagon with their vertices facing each other, and the four integrated HJD MOSFETs are arranged in pairs at two intervals between the two integrated SBD MOSFETs.

[0071] Background technology includes split-source SBD integrated MOSFETs with strip cell arrangement design, such as Figure 2 As shown, the gate 2-42-1 of two adjacent cells is elongated. Figure 2 The middle gate 2-42-1 is a cross-section.

[0072] This application differs from others. The semiconductor integrated device of this application integrates heterojunction diodes (HJDs) and Schottky diodes (SBDs) in the middle of the first gate 42-1 of the regular hexagonal frame of two adjacent cells, forming each cell with four integrated HJD MOSFETs and two integrated SBD MOSFETs. Furthermore, the cell composed of the four integrated HJD MOSFETs and two integrated SBD MOSFETs is a regular hexagonal cell. This hexagonal arrangement can increase channel density and increase the conduction current. On the one hand, this application solves the problem of insufficient conduction capability of strip-cell arranged devices in the prior art; on the other hand, through the interleaved design of integrated HJD MOSFETs and integrated SBD MOSFETs, the semiconductor integrated device of this application has a lower reverse on-state voltage drop, improves device reliability, allows for a smaller chip area, and reduces cost.

[0073] It should be noted that, as Figure 7 As shown, the regular hexagon is roughly hexagonal, and the MOSFET with integrated HJD and the MOSFET with integrated SBD are also roughly triangular in structure.

[0074] Adjacent HJD MOSFETs share a side to allow for adaptive fine-tuning. The overall structure is roughly an equilateral triangle. The connection points between adjacent HJD MOSFETs are determined based on the manufacturing process.

[0075] During implementation, such as Figure 7 As shown, the two MOSFETs of the integrated SBD have the bottom edges of the Schottky contact regions as two oppositely arranged bottom edges of a regular hexagon;

[0076] The bottom edge of each MOSFET with integrated HJD anode is located at the bottom edge of a regular hexagon;

[0077] Among them, such as Figure 6 As shown, the HJD anode includes a P-poly region 33-1 and a second P+ injection region 33-2 formed sequentially from top to bottom.

[0078] During implementation, such as Figure 7 As shown, there are multiple cells;

[0079] In adjacent cells, adjacent integrated HJD MOSFETs share a single integrated HJD MOSFET with the bottom edge of the HJD anode.

[0080] Each MOSFET of the integrated SBD has its own bottom edge of a Schottky contact region, meaning that the bottom edges of the Schottky contact regions of adjacent MOSFETs of adjacent integrated SBDs in adjacent cells are not shared.

[0081] In adjacent cells, adjacent integrated HJD MOSFETs share the bottom edge of a single integrated HJD MOSFET, resulting in a smaller area occupied by all integrated HJD MOSFETs in the semiconductor integrated device. The area of ​​a semiconductor integrated device with the same number of integrated HJD MOSFETs can be made even smaller.

[0082] In addition, the feature that the bottom edge of the Schottky contact region of the MOSFETs of adjacent integrated SBDs in adjacent cells is not shared allows adjacent cells to be closely attached together, increasing the cell density of the semiconductor integrated device and enabling the semiconductor integrated device to have a smaller area.

[0083] During implementation, such as Figures 5 to 10 As shown, the semiconductor integrated device includes:

[0084] Substrate 1;

[0085] Drift region 2 located on the substrate;

[0086] The channel region 32 of the regular hexagonal frame is formed on the drift region 2;

[0087] The source electrode 32-1 of the regular hexagonal frame is formed on the channel region 32;

[0088] A hexagonal JFET region 33 is formed on the drift region 2 and is connected to the outer edge of the channel region 31. The JFET region has two first JFET frames and four second JFET frames. The two first JFET frames are arranged opposite each other and have flush top surfaces, serving as frames for the MOSFETs of the two integrated SBDs in the JFET region. The four second JFET frames have downward steps, and at the steps, P-poly regions 33-1 and second P+ injection regions 33-2 are formed sequentially from top to bottom. The P-poly regions 33-1 and second P+ injection regions 33-2 form the HJD anode.

[0089] The six borders of the hexagonal channel region 32 serve as the channel regions for two integrated SBD MOSFETs and four integrated HJD MOSFETs. In this way, the process of forming a hexagonal channel region 32 can form the channel regions for two integrated SBD MOSFETs and four integrated HJD MOSFETs in one step. The process is simple and easy to manufacture, and the structure of the hexagonal channel region 32 is also relatively simple.

[0090] The six borders of the hexagonal frame source 32-1 serve as the sources of two integrated SBD MOSFETs and four integrated HJD MOSFETs. Thus, the process of forming one hexagonal frame source 32-1 can simultaneously form the sources of two integrated SBD MOSFETs and four integrated HJD MOSFETs, making the process simple and easy to manufacture. The structure of the hexagonal frame source 32-1 is also relatively simple.

[0091] Two first JFET frames are positioned opposite each other and have flush top surfaces, serving as frames for the two integrated SBD MOSFETs in the JFET region. Four second JFET frames have downward steps, with P-poly region 33-1 and second P+ injection region 33-2 formed sequentially from top to bottom at the steps. This time, the corresponding layer structures are fabricated according to the structural requirements of the two integrated SBD MOSFETs and the four integrated HJD MOSFETs.

[0092] Figure 5 for Figure 4-2 A cross-sectional view of a structure consisting of half of the two cells adjacent to the OA position; Figure 6 for Figure 4-2 A cross-sectional view of a structure consisting of half of two adjacent cells at position OB. Figure 5 and Figure 6 In the middle, the vertical dashed lines are the dividing lines of the cells.

[0093] In practice, semiconductor integrated devices also include:

[0094] A regular hexagonal channel contact area 31 is formed on the drift area 2 and is sleeved and connected to the inner edge of the source electrode 32-1;

[0095] A regular hexagonal ohmic contact region 41 covers the channel contact region 31 and partially obscures the source electrode 32-1;

[0096] The isolation area 42 of the regular hexagonal frame is fitted onto the outer edge of the ohmic contact area 41;

[0097] The first gate 42-1 of the regular hexagonal frame is disposed within the isolation region 42 and is completely surrounded by the isolation region 42;

[0098] Two Schottky contact regions 43 are formed in the first JFET frame and connected to the outside of the isolation region 42;

[0099] The source metal 5 is formed on the ohmic contact region 41, the isolation region 42, the Schottky contact region 43, and the P-poly region 33-1;

[0100] The second gate 42-2 is formed above the middle of the HJD anode, and the first gate 42-1 and the second gate 42-2 are located in the same layer and connected.

[0101] The drain electrode is formed on the back side of the substrate.

[0102] That is, each cell of the semiconductor integrated device is divided according to the two first JFET borders and four second JFET borders of the JFET region 33 of the regular hexagonal frame. The two oppositely arranged first JFET borders and the structures above and below them form two integrated SBD MOSFETs, and the four second JFET borders and the structures above and below them form four integrated HJD MOSFETs.

[0103] In this way, the fabrication processes of the hexagonal channel contact region 31, the hexagonal ohmic contact region 41, and the first gate 42-1 of the hexagonal frame are simple, and their structures are also relatively simple. This, in turn, simplifies the fabrication process of the semiconductor integrated device, makes the structure more compact, and saves chip area.

[0104] The first gate 42-1 and the second gate 42-2 are located on the same layer and connected, which allows the first gate 42-1 and the second gate 42-2 to be formed in a single process while maintaining the same potential. That is, the gate of the MOSFET with integrated SBD (second gate 42-2) and the gate of the MOSFET with integrated HJD (first gate 42-1) are formed in a single process, which is simple to fabricate.

[0105] Figure 7 for Figure 4-1 The cell shown is in the state where the source metal is removed and in Figure 5 A perspective view of a single cell in the XY direction at the CC position; Figure 8 for Figure 7 A magnified view of a portion of the image.

[0106] Figure 9 for Figure 4-1 The cell shown is in the case of removing the source metal and the first gate and in Figure 6 A perspective view of a single cell in the XY direction at the DD position shown. Figure 10 for Figure 9 A magnified view of a portion of the image.

[0107] Figure 4-1 , Figure 7 and Figure 8 In the same area Figure 4-1 The shape shows that, with Figure 7 and Figure 8 The reason why the shapes in the images are displayed differently is that... Figure 7 and Figure 8This is a top-down perspective view, and some areas are shown in perspective.

[0108] Figure 4-1 , Figure 9 and Figure 10 In the same area Figure 4-1 The shape shows that, with Figure 9 and Figure 10 The reason why the shapes in the images are displayed differently is that... Figure 9 and Figure 10 This is a top-down perspective view, and some areas are shown in perspective.

[0109] The ohmic contact region 41 of the regular hexagon is in Figure 4-1 It is displayed as a wider bar. (Corresponding to...) Figure 7 and Figure 8 In the image, due to perspective, the hexagonal ohmic contact region 41 reveals the narrower channel contact region 31 located beneath it. Therefore, in... Figure 7 and Figure 8 In the middle, visually, the ohmic contact area 41 is a regular hexagonal frame.

[0110] Figure 10 middle, Figure 10 The regular hexagonal frame between the central channel area 32 and the isolation area 42 is Figure 5 The region where the first gate 42-1 and the source 32-1 overlap vertically.

[0111] Background technology includes split-source SBD integrated MOSFETs with strip cell arrangement design, such as Figure 2 As shown, two adjacent cells share a single elongated gate 2-42-1. This application integrates a heterojunction diode (HJD) and a Schottky diode (SBD) in the middle of the gates of two adjacent cells (between the two first gates 42-1 of the respective regular hexagonal frames of the two adjacent cells, as shown). Figure 6 As shown in the figure, the hexagonal cell arrangement increases the channel density, increases the conduction current, and provides stronger forward conduction capability, thus solving the problem of insufficient conduction capability of strip cell arrangement devices. Because the channel density is higher, the conduction current is greater for the same area, resulting in stronger forward conduction capability for MOSFETs with integrated HJD and MOSFETs with integrated SBD.

[0112] Meanwhile, the interleaved design of HJD and SBD results in a lower reverse on-state voltage drop, improved device reliability, smaller chip area, and reduced cost.

[0113] The following section explains the strong reverse conduction capability of MOSFETs with integrated HJD and integrated SBD:

[0114] Because of the use of hexagonal cell design, the reliability of hexagonal cells is weaker than that of bar cells, so the reliability will also be weaker after adding the SBD structure.

[0115] Therefore, it is necessary to introduce a region to shield the electric field at the SBD to improve device reliability. However, this would reduce the area of ​​the SBD, thereby reducing the reverse conduction voltage drop of the device. Therefore, the solution of introducing a HJD to protect the SBD can achieve both guaranteed reliability and a low reverse conduction voltage drop (because the HJD can also conduct).

[0116] In the middle of the gates of two adjacent cells (between the two first gates 42-1 of the respective regular hexagonal frames of the two adjacent cells, such as...) Figure 6 As shown, the integrated SBD and HJD structures are arranged in an interleaved manner on the layout, retaining the low conduction advantages of both SBD and HJD. Furthermore, because the second P+ injection region 33-2 is located below the HJD, and its area is twice that of the integrated SBD MOSFET (i.e., the area of ​​the MOSFET with integrated HJD is twice the area of ​​the MOSFET with integrated SBD), the surge protection and withstand voltage of the device can be improved, increasing the device's reliability. A well-designed SBD can also reduce reverse recovery losses in power electronic applications.

[0117] The semiconductor integrated device of this application has the following technical advantages:

[0118] Most existing SiC MOSFET devices with integrated SBDs or integrated HJDs employ a strip cell design. The semiconductor integrated device of this application uses a hexagonal cell arrangement design to increase channel density and conduction current.

[0119] Compared to existing SiC MOSFET devices that only integrate SBD, the semiconductor integrated device of this application can improve the surge protection and withstand voltage capabilities and increase the reliability of the device while achieving the aforementioned goals of increasing channel density and increasing conduction current. Furthermore, it does not require additional design of the JFET region size to prevent excessive electric field in the Schottky contact region.

[0120] While existing MOSFETs with integrated HJDs exhibit low reverse on-state voltage drop, their reverse recovery process is similar to that of a PiN diode, characterized by minority carrier injection, which increases reverse recovery losses. The semiconductor integrated device of this application integrates one-third of an integrated SBD MOSFET in each cell, significantly reducing minority carrier injection and resulting in lower reverse recovery losses.

[0121] Figure 11-1Modeling diagram of a simulation device (hereinafter referred to as device 1) of a MOSFET with integrated SBD in the prior art; Figure 11-2 for Figure 11-2 It is a simple combination structure of two SBDs and one HJD (hereinafter referred to as Device 2), which is not the present application, but only a simplified version of the present application. It does not have a MOS structure. The comparison between the two is to highlight the advantages of this combination. The advantages of the new structure are lower on-state voltage drop and higher withstand voltage (better reliability).

[0122] Figure 12 for Figure 11-1 and Figure 11-2 The graph shows the on-current of the two devices as a function of the source-drain voltage Vsd. Figure 12 As shown, the horizontal axis represents the source-drain voltage Vsd, in volts (V); the vertical axis represents the on-state current of the integrated diode (SBD and HJD are both integrated diodes), in amperes (A). Figure 12 As shown, curve ① is the curve of the on-state current of the integrated diode of device 1 as a function of the source-drain voltage Vsd; curve ② is the curve of the on-state current I of the integrated diode of device 2. total The curve showing the change of source-drain voltage Vsd; curve ③ is the current I flowing through the Schottky terminal of the integrated diode in device 2 during conduction. SBD Curve ④ shows the curves that change with the source-drain voltage Vsd; curve ④ is the heterojunction current I in the conduction current of the integrated diode of device 2. HJD The curve showing the change in source-drain voltage Vsd.

[0123] Device 2 (turn-on voltage approximately 1.3V) has a lower turn-on voltage than device 1 (turn-on voltage approximately 1.45V). Breaking down the current components of device 2, the total current I... total The current I flowing through the Schottky terminal SBD and heterojunction terminal current I HJD The sum, we have I total =I SBD +I HJD As can be seen, the MOSFET with integrated HJD has a lower on-state voltage drop than the MOSFET with integrated SBD, but the current is smaller after conduction. However, for device 2, the combined current carrying capacity of the two is very similar to that of device 1.

[0124] Figure 13 for Figure 11-1 and Figure 11-2 The graph shows the drain current of the two devices as a function of drain voltage. Figure 13 As shown, the horizontal axis represents the drain voltage in volts (V), and the vertical axis represents the drain current in amperes (A). Figure 13 As shown, curve ① represents the change in drain current of device 1 with drain voltage; curve ② represents the change in drain current of device 2 with drain voltage. Figure 13 As shown, due to the addition of the second P+ injection region 33-2, the withstand voltage of device 2 is improved (i.e., the breakdown voltage is higher) compared to device 1, and the reverse leakage current of device 2 is also lower.

[0125] Figure 14 for Figure 13 A graph of the vertical axis index; that is, relative to... Figure 13 , Figure 14 The unit of the vertical axis becomes smaller. For example... Figure 14 As shown, curve ① represents the change in drain current of device 1 with drain voltage; curve ② represents the change in drain current of device 2 with drain voltage. Figure 14 As shown, device 2 also has a lower reverse leakage current.

[0126] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0127] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0128] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0129] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0130] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0131] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A semiconductor integrated device, characterized in that, The unit includes a cell, the shape of which is a regular K-gon, where K is 6; the diagonal of the cell divides the cell into K equilateral triangle structures, and each equilateral triangle structure contains a MOSFET with integrated HJD or an integrated SBD. There are n MOSFETs integrated with HJD and m MOSFETs integrated with SBD; Where n and m are positive integers and the sum of n and m is K; The range of values ​​is greater than or equal to Less than or equal to 2.

2. The semiconductor integrated device according to claim 1, characterized in that, m is 2, and there are two MOSFETs integrated with the SBD; n is 4, and there are four MOSFETs integrated with HJD.

3. The semiconductor integrated device according to claim 1, characterized in that, m is 4, and there are four MOSFETs integrated with SBD; n is 2, and there are two MOSFETs integrated with HJD.

4. The semiconductor integrated device according to claim 2, characterized in that, The two MOSFETs of the integrated SBD are arranged in a regular hexagon with their vertices facing each other. The four MOSFETs of the integrated HJD are arranged in pairs at two intervals between the two MOSFETs of the integrated SBD; The two MOSFETs of the integrated SBD have the bottom edges of the Schottky contact regions as two oppositely arranged bottom edges of a regular hexagon; The bottom edge of each MOSFET with integrated HJD anode is located at the bottom edge of a regular hexagon.

5. The semiconductor integrated device according to claim 4, characterized in that, The unit cell is multiple; In adjacent cells, adjacent MOSFETs with integrated HJDs share a bottom edge with an HJD anode; Each of the MOSFETs in the integrated SBD has a bottom edge of a Schottky contact region.

6. The semiconductor integrated device according to claim 5, characterized in that, include: Substrate (1); Drift region located on the substrate (2); The channel region (32) of the regular hexagonal frame is formed on the drift region (2); The source electrode (32-1) of the regular hexagonal frame is formed on the channel region (32); A hexagonal JFET region (33) is formed on the drift region (2) and is connected to the outer edge of the channel region (32). The JFET region has two first JFET frames and four second JFET frames. The two first JFET frames are arranged opposite each other and have their top surfaces flush, and serve as frames for the MOSFETs of the two integrated SBDs in the JFET region. The four second JFET frames have downward steps and form HJD anodes at the steps, and serve as frames for the MOSFETs of the integrated HJDs.

7. The semiconductor integrated device according to claim 6, characterized in that, Also includes: A regular hexagonal channel contact area (31) is formed on the drift area (2) and is sleeved on the inner edge of the source electrode (32-1); A regular hexagonal ohmic contact region (41) covers the channel contact region (31) and partially obscures the source electrode (32-1). The isolation area (42) of the regular hexagonal frame is connected to the outer edge of the ohmic contact area (41); The first gate (42-1) of the regular hexagonal frame is disposed within the isolation region (42) and is completely surrounded by the isolation region (42); Two Schottky contact areas (43) are formed on the first JFET frame and connected to the outside of the isolation area (42); The second gate (42-2) is formed above the middle of the HJD anode, and the first gate (42-1) and the second gate (42-2) are located on the same layer and connected; Source metal (5) is formed on the ohmic contact region (41), isolation region (42), Schottky contact region (43) and HJD anode; The drain electrode is formed on the back side of the substrate.

8. The semiconductor integrated device according to claim 7, characterized in that, The inner edge of the JFET region (33) and the outer edge of the source electrode (32-1) are kept apart, and the inner edge of the JFET region (33) and the outer edge of the source electrode (32-1) form part of the channel region (32) to protect the side of the source electrode (32-1) facing the JFET region (33).

9. The semiconductor integrated device according to claim 8, characterized in that, The HJD anode is spaced apart from the inner edge of the JFET region (33), and the HJD anode is flush with the outer edge of the JFET region (33).

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