Vertical thin film transistor, preparation method, voltage source device, current generating device and low dropout regulator device

Abstract

The invention discloses a vertical thin film transistor, a preparation method, a voltage source device, a current generating device and a low dropout regulator device, and the transistor comprises a grid electrode which comprises a grid substrate and a grid electrode column; the second dielectric layer is arranged between the gate column and the semiconductor layer and between the gate substrate and the second electrode; the first electrode and the second electrode are respectively used as a source electrode and a drain electrode of the transistor; the first electrode is arranged at one end of the transistor away from the gate; the second electrode is arranged between the second dielectric layer and the first electrode and is exposed outside the transistor; the semiconductor layer surrounds the surface, away from the grid electrode, of the second dielectric layer and is electrically connected with the first electrode and the second electrode; the first dielectric layer is arranged between the first electrode and the second electrode, surrounds part of the surface of the semiconductor layer and isolates the first electrode from the second electrode; wherein the gate substrate is selectively and electrically connected with the second electrode so as to form a gate-drain connected vertical thin film transistor structure. The integration level of the voltage source device is improved.

Description

Technical Field

[0001] This invention relates to the field of thin-film transistors and voltage source technology, and particularly to a vertical thin-film transistor, a fabrication method, a voltage source device, a current generating device, and a low-dropout linear regulator device. Background Technology

[0002] Voltage sources are an indispensable basic module of electronic systems. An ideal voltage source needs to provide a stable bias voltage that is not affected by process deviations, power supply voltage fluctuations, and temperature (PVT) changes.

[0003] In the prior art, voltage source circuits based on two transistors, namely dual-transistor voltage source unit structures, reduce the circuit's sensitivity to changes in ambient temperature and generate stable output voltages by weighting and adding two output voltages with opposite temperature characteristics together.

[0004] Traditional planar transistors face the problem of excessively large cell area when applied to such dual-transistor voltage source units, which limits their layout in applications such as high-density storage or micro-sensor nodes. Summary of the Invention

[0005] This invention provides a vertical thin-film transistor, a fabrication method, a voltage source device, a current generating device, and a low-dropout linear regulator device, solving the problem of large cell area when existing transistors are applied to dual-transistor voltage source units.

[0006] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, a vertical thin-film transistor is provided, comprising: The gate includes a gate substrate disposed at one end of the transistor and a gate post extending a predetermined length from the center of the gate substrate to the other end of the transistor. A second dielectric layer is disposed between the gate pillar and the semiconductor layer, and between the gate substrate and the second electrode, to isolate the gate. A first electrode and a second electrode, wherein the first electrode serves as the source of the transistor and the second electrode serves as the drain of the transistor; the first electrode is disposed at the end of the transistor away from the gate; the second electrode is disposed between the second dielectric layer and the first electrode and is exposed to the outside of the transistor. A semiconductor layer surrounds the surface of the second dielectric layer away from the gate and is electrically connected to the first electrode and the second electrode; A first dielectric layer is disposed between the first electrode and the second electrode and surrounds a portion of the semiconductor layer away from the second dielectric layer, thereby isolating the first electrode from the second electrode. The gate substrate is optionally electrically connected to the second electrode to form a vertical thin-film transistor structure with the gate and drain connected. The semiconductor layer is an amorphous oxide semiconductor layer.

[0007] Secondly, a method for fabricating a vertical thin-film transistor is provided, comprising: S1: The first electrode, the first dielectric layer, and the second electrode are sequentially fabricated on the substrate; S2: Form a first columnar hole that penetrates the second electrode and the first dielectric layer and extends to the surface of the first electrode; S3: An amorphous oxide is prepared within the first columnar hole, and a second columnar hole is formed in the amorphous oxide to form a semiconductor layer; wherein the semiconductor layer forms an electrical connection with the first electrode and the second electrode; S4: Prepare a second medium within the second columnar pore, and form a third columnar pore in the second medium to form a second medium layer; S5: A gate is fabricated within the third columnar hole, the gate comprising a gate pillar filling the third columnar hole and a gate substrate covering the second dielectric layer and optionally electrically connected to the second electrode.

[0008] Thirdly, a voltage source device based on a vertical thin-film transistor is provided, comprising: First transistor and second transistor, The source of the first transistor is electrically connected to the first voltage level terminal. The gate and drain of the first transistor are electrically connected and then electrically connected to the source of the second transistor, serving as the output terminal of the voltage source device. The gate of the second transistor is electrically connected to the second voltage level terminal. In this transistor, the gate and drain are not electrically connected; The threshold voltage of the first transistor is positive, and the threshold voltage of the second transistor is negative, so as to form a threshold voltage difference between the two.

[0009] Fourthly, a current generating device is provided, comprising: A voltage source device based on a vertical thin-film transistor as described in the third aspect; At least one load unit; The input terminal of the load unit is electrically connected to the output terminal of the voltage source device. The voltage source device is used to provide a stable input voltage to the load unit, and the load unit generates an output current according to the input voltage. The load unit includes a third transistor and a fourth transistor; The drain of the third transistor is electrically connected to the output terminal of the voltage source device, the gate is electrically connected to the control signal terminal, and the source is electrically connected to the gate of the fourth transistor. The drain of the fourth transistor serves as the current output terminal, while the source is electrically connected to the voltage control terminal.

[0010] Fifthly, a low-dropout linear voltage regulator device is provided, comprising: The voltage source device based on a vertical thin-film transistor, as described in the third aspect, is used to provide a reference voltage to the input terminal of the low-dropout linear regulator device; At least one load unit, the input terminal of which is electrically connected to the output terminal of the low dropout linear regulator device, is used to generate a reference current and / or a load current under the drive of the low dropout linear regulator; The load unit includes a third transistor and a fourth transistor; The drain of the third transistor is electrically connected to the output terminal of the voltage source device, the gate is electrically connected to the control signal terminal, and the source is electrically connected to the gate of the fourth transistor. The drain of the fourth transistor serves as the current output terminal, and the source is electrically connected to the voltage control terminal. The low-dropout linear regulator device further includes a voltage input terminal, a voltage output terminal, and a feedback control circuit. The feedback control circuit is used to compare the output voltage of the voltage output terminal with the reference voltage output by the voltage source device, and adjust the control signal terminal and / or voltage control terminal of the load unit according to the comparison result to achieve regulated output under low-dropout conditions. Attached Figure Description

[0011] Figure 1 This application provides a schematic diagram of the structure of a non-gate-drain connected vertical thin-film transistor. Figure 2 This is a schematic diagram of a vertical thin-film transistor with gate-drain connection provided in an embodiment of this application; Figure 3 A perspective cross-sectional view of a vertical thin-film transistor provided in an embodiment of this application; Figure 4 A schematic flowchart illustrating a method for fabricating a vertical thin-film transistor according to an embodiment of this application; Figure 5 A circuit diagram of a voltage source device based on a vertical thin-film transistor provided in this application embodiment; Figure 6 A schematic diagram of a voltage source device based on a vertical thin-film transistor provided in an embodiment of this application; Figure 7An output voltage diagram of a voltage source device under different threshold voltage differences between a first transistor and a second transistor, provided in an embodiment of this application; Figure 8 A transistor transfer characteristic curve for different threshold voltages is provided for an embodiment of this application; Figure 9 An output voltage diagram of a voltage source device with different width-to-length ratios for a first transistor is provided in an embodiment of this application; Figure 10 The output voltage of a voltage source device with different width-to-length ratios for a second transistor is provided in the embodiments of this application; Figure 11 A circuit diagram of a parallel-connected voltage source device provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of a parallel-connected voltage source device provided in an embodiment of this application; Figure 13 A schematic diagram of another parallel-connected voltage source device provided in an embodiment of this application; Figure 14 A regulation-based approach provided for embodiments of this application Diagram showing the output voltage regulation effect of a voltage source device at the level terminal voltage. Figure 15 A structural block diagram of a current generating device based on the voltage source device provided in this application embodiment; Figure 16 A circuit diagram of a current generating device based on the voltage source device provided in this application embodiment; Figure 17 An output current regulation effect diagram of a current generating device based on the voltage source device provided in this application embodiment; Figure 18 A circuit diagram of another current generating device based on the voltage source device provided in this application embodiment; Figure 19 Another output current regulation effect diagram of a current generating device based on the voltage source device provided in this application embodiment; Figure 20 This is a diagram illustrating the output current regulation effect of a current generating device based on the voltage source device, as provided in another embodiment of this application. Detailed Implementation

[0012] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the technical solutions in the embodiments of this application are clearly described. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] The steps described in the specification and the flowcharts in the accompanying drawings of this invention are not necessarily strictly executed according to the step numbers; the execution order of the method steps can be changed. Furthermore, certain steps can be omitted, multiple steps can be combined into one step, and / or one step can be broken down into multiple steps.

[0015] This specification provides a vertical thin-film transistor, a method for fabricating a vertical thin-film transistor, a voltage source device based on a vertical thin-film transistor, a current generating device, and a computer-readable storage medium. These are described in detail below with reference to the accompanying drawings and preferred embodiments.

[0016] Please see Figure 1-3 This application provides a vertical thin-film transistor, comprising: Gate 101, the gate 101 includes a gate substrate 1010 disposed at one end of the transistor and a gate post 1011 extending a predetermined length from the center of the gate substrate 1010 to the other end of the transistor; The second dielectric layer 102 is disposed between the gate pillar 1011 and the semiconductor layer 104, and between the gate substrate 1010 and the second electrode 103, to isolate the gate 101; A first electrode 106 and a second electrode 103, wherein the first electrode 106 serves as the source of the transistor and the second electrode 103 serves as the drain of the transistor; the first electrode 106 is disposed at the end of the transistor away from the gate 101; the second electrode 103 is disposed between the second dielectric layer 102 and the first electrode 106 and is exposed to the outside of the transistor. A semiconductor layer 104 surrounds the surface of the second dielectric layer 102 away from the gate 101 and is electrically connected to the first electrode 106 and the second electrode 103. A first dielectric layer 105 is disposed between the first electrode 106 and the second electrode 103 and surrounds a portion of the surface of the semiconductor layer 104 away from the second dielectric layer 102, thereby isolating the first electrode 106 from the second electrode 103. The gate substrate 1010 is optionally electrically connected to the second electrode 103 to form a vertical thin-film transistor structure with the gate and drain connected. The semiconductor layer 104 is an amorphous oxide semiconductor layer.

[0017] In the vertical thin-film transistor of this application embodiment, since the gate and drain are electrically connected, the gate-source voltage will always be equal to the drain-source voltage, thereby forming a relatively stable voltage or current reference related to its own threshold voltage. When applied to a voltage source, this allows it to cooperate with another operating transistor.

[0018] When a sufficient voltage is applied to the gate pillar, a vertical, cylindrical, conductive path—a channel—is induced in the semiconductor layer surrounding its sidewalls, thus "connecting" the source and drain. If a voltage is applied between the source and drain, current flows vertically along the channel. Because the current flows vertically through the channel, it facilitates further reduction in feature size. More importantly, it creates a stackable fabrication capability, enabling three-dimensional integration.

[0019] When thin-film transistors (TFTs) are applied to voltage sources, their stackable manufacturing capability significantly reduces the cell size, greatly increasing circuit density and facilitating compact layouts within limited space. Simultaneously, the vertical structure is believed to allow for more precise current control, contributing to improved output voltage accuracy and stability.

[0020] Furthermore, the threshold voltage of the transistor is controlled by at least one of the following configurations: The chemical composition and oxygen vacancy concentration of the semiconductor layer 104 are changed; Different second dielectric layer 102 and / or interface engineering are employed to adjust interface charge and trap states; Change the work function of the gate metal and / or the electrode material; The thickness of the semiconductor layer 104 is changed.

[0021] In the vertical thin-film transistor of this application embodiment, when fabricating the semiconductor layer of the vertical thin-film transistor, it is preferable to use different amorphous oxides (different materials have different oxygen vacancy densities and free carrier densities), and / or use an argon-oxygen mixed gas during sputtering deposition. By changing the oxygen partial pressure, the density of oxygen vacancies can be controlled by controlling the target material ratio, annealing atmosphere, etc., thereby increasing or decreasing the free charge density and further regulating the threshold voltage.

[0022] Furthermore, the threshold voltage expression given in Formula 1, where The flat-band voltage is determined by the work function difference between the metal and semiconductor layers and the fixed charge in the gate dielectric layer. It is the total equivalent charge induced per unit area by the gate electric field, and its value is negative. It is the gate oxide capacitance per unit area.

[0023] (Formula 1) If the oxygen vacancy density in the oxide semiconductor layer is low, resulting in a lower free charge density, the threshold voltage will be controlled at a higher level. Conversely, if the oxygen vacancy density in the oxide semiconductor layer is high and the free charge density is large, the threshold voltage will decrease or even become negative.

[0024] By employing different gate dielectrics and interface engineering techniques to adjust interface charge and trapped states, different interface characteristics can be formed at the contact interface between the semiconductor layer and the source / drain electrodes and the gate dielectric layer, thereby adjusting interface charge, reducing trapped states, and further controlling the threshold voltage.

[0025] Furthermore, by selecting appropriate gate metal work function and electrode materials, the efficiency of gate-induced charge carriers can be changed, thereby further regulating the threshold voltage.

[0026] The threshold voltage can also be easily controlled by changing the thickness of the semiconductor layer thin film.

[0027] Therefore, when the vertical thin-film transistor of the present application embodiment is used as a voltage source, the threshold voltage of the first transistor and the second transistor can be controlled by using different amorphous oxide semiconductor layers.

[0028] See Figure 4 Corresponding to the above-described vertical thin-film transistor embodiments, this application provides a method for fabricating a vertical thin-film transistor, comprising: Step S1: Sequentially fabricate a first electrode 106, a first dielectric layer 105, and a second electrode 103 on a substrate 107; Step S2: Form a first columnar hole that penetrates the second electrode 103 and the first dielectric layer 105 and extends to the surface of the first electrode 106; Step S3: Prepare a set amorphous oxide in the first columnar hole, and form a second columnar hole in the amorphous oxide to form a semiconductor layer 104; wherein the semiconductor layer 104 forms an electrical connection with the first electrode 106 and the second electrode 103; Step S4: Prepare a second medium within the second columnar pore, and form a third columnar pore in the second medium to form a second medium layer 102; Step S5: A gate 101 is fabricated in the third columnar hole. The gate 101 includes a gate post 1011 that fills the third columnar hole and a gate substrate 1010 that covers the second dielectric layer 102 and is optionally electrically connected to the second electrode 103.

[0029] In the specific implementation process: First, a first electrode 106, a first dielectric layer 105, and a second electrode 103 are sequentially deposited on a substrate 107, stacked in that order. Here, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or other methods can be used to sequentially form the first electrode 106, the first dielectric layer 105, and the second electrode 103.

[0030] Then, a columnar hole is formed by patterned etching. The columnar hole is located at the center of the first electrode 106, the first dielectric layer 105, and the second electrode 103, and the bottom of the columnar hole extends to the first electrode 106. Here, the first dielectric layer 105 and the second electrode 103 can be etched using dry etching or wet etching.

[0031] A semiconductor layer 104 is formed on the sidewall of the columnar hole and is electrically connected to the first electrode 106 and the second electrode 103. The semiconductor layer can be formed using atomic layer deposition (ALD). This semiconductor layer is a single, continuous layer covering the exposed surfaces of the first electrode 106, the first dielectric layer 105, and the second electrode 103. The semiconductor film is then etched away, removing the semiconductor film formed on the sidewalls and bottom of the columnar hole, as well as on other parts such as the top of the second electrode 103 and the outside of the columnar hole, thereby forming the semiconductor layer 104.

[0032] A second dielectric layer 102 is formed, covering the semiconductor layer 104. Here, the second dielectric layer 102 can be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or other methods. The second dielectric layer is a single, continuous layer, covering the exposed surfaces of the semiconductor layer 104 and the second electrode 103. The second dielectric layer film is then etched away, removing the second dielectric layer film formed on the sidewalls and bottom of the columnar holes and on top of the semiconductor layer 104, as well as in other areas such as the top of the second electrode 103 and the outside of the columnar holes, thereby forming the second dielectric layer 102.

[0033] Finally, a gate 101 is formed, comprising a gate substrate 1010 and a gate post 1011 extending from the gate substrate 1010. The gate post 1011 extends into a columnar aperture, and the gate substrate 1010 is formed on the side of the gate post 1011 away from the first electrode 106 and extends downward to be electrically connected to the second electrode 103. Here, a conductive thin film can be formed by physical vapor deposition (PVD). The conductive thin film is then etched to form the gate 101.

[0034] The aforementioned manufacturing process involves low temperatures and allows for stacking, enabling voltage source devices based on this process to achieve three-dimensional integration and significantly improve circuit density.

[0035] See Figure 5 Corresponding to the above-described vertical thin-film transistor embodiments, this application provides a voltage source device 20 based on a vertical thin-film transistor, comprising: First transistor 201 and second transistor 202, The source of the first transistor 201 is electrically connected to the first level terminal 206. The gate and drain of the first transistor 201 are electrically connected and then electrically connected to the source of the second transistor 202, serving as the output terminal 205 of the voltage source device. The gate of the second transistor 202 is connected to... The level terminal 204 is electrically connected, and the drain of the second transistor 202 is electrically connected to the second level terminal 203; In this transistor, the gate and drain are not electrically connected; The threshold voltage of the first transistor 201 is positive, and the threshold voltage of the second transistor 202 is negative, so as to form a threshold voltage difference between the two.

[0036] Further, see Figure 6 The first transistor 201 and the second transistor 202 are stacked, with the first transistor 201 located at the bottom of the second transistor 202.

[0037] Figure 6 shows an actual structural example of a voltage source device 20 based on a vertical thin-film transistor. It consists of two vertical thin-film transistors and a connecting electrode 108. The difference is that the gate and drain of the first transistor 201 are electrically connected, while the gate and drain of the second transistor 202 are not electrically connected. The first transistor is located below the second transistor; a first dielectric layer fills the space between the first and second transistors, separating them. The gate 101b of the first transistor is connected to the first electrode 106a of the second transistor via the connecting electrode 108. The first electrode 106b of the first transistor is the first voltage level terminal, and the second electrode 103b of the first transistor is the output terminal. The second electrode 103a of the second transistor is the second voltage level terminal, and the gate 101a of the second transistor is... Level terminal.

[0038] In practice, the second voltage level is set higher than the first voltage level. The voltage level is configured as an adjustable voltage level. When the voltage source device is operating, it generates an output voltage that does not change with the second voltage level. At this time, the output voltage is determined solely by the threshold voltage difference between the first and second transistors, the channel width-to-length ratio, and... The voltage value set at the level terminal determines the stability of the output voltage. Its application and working principle will be further explained below.

[0039] In memory arrays based on dual-transistor capacitor-free cell structures, the stackable fabrication capability theoretically allows for cell feature sizes that can reach [size not specified]. It supports 3D integration, greatly improving storage density. However, in memory arrays based on dual-transistor capacitor-less cell structures, a reference circuit typically needs to drive multiple sensitive amplifiers. The reference circuit itself must have sufficient driving capability to ensure that multiple sensitive amplifiers can obtain normal and stable reference voltage inputs. If the reference circuit is affected by noise, its output reference voltage will fluctuate abnormally, which will be transmitted to the input terminals of all connected sensitive amplifiers, causing abnormal swings, resulting in read signal errors and affecting the read reliability of the memory.

[0040] The voltage source device in this application embodiment obtains its voltage through the threshold voltage difference between the first transistor and the second transistor, thus achieving insensitivity to power supply and temperature. A second voltage level is applied to the drain of the second transistor, while the gate of the second transistor is connected to... Level input. For the first transistor, the gate and drain are shorted, while the source is connected to the first level. Output. This is generated between the source of the second transistor and the drain of the first transistor. In the circuit, the gate-source voltage of the first transistor is equal to... The gate-source voltage of the second transistor is equal to - As the second voltage level increases from 0: Initially, the second transistor is off, which is equivalent to a large resistor being connected between the output voltage and ground. The first transistor is in the linear region, and the output voltage... It will increase as the second level rises; when When the voltage is increased to the absolute value of the threshold voltage of the second transistor, the second transistor enters the subthreshold region; As the number of transistors continues to increase, eventually both the first and second transistors will operate in the subthreshold region. It no longer changes with the increase of VDD. At this time, VDD is the minimum operating voltage of the voltage source device. When the second level is greater than the minimum operating voltage, the voltage source device can generate an output voltage that does not change with the second level. The threshold voltage difference between the first transistor and the second transistor and the channel width-to-length ratio are the only factors. The voltage value set at the level terminal determines the stability of the output voltage.

[0041] In some possible implementations, the method for regulating the output voltage of the voltage source device includes: (1) The output voltage is controlled by adjusting the threshold voltage difference between the first transistor and the second transistor.

[0042] (2) The output voltage is controlled by adjusting the width-to-length ratio of the first transistor or the second transistor.

[0043] (3) By adjusting The output voltage is adjusted by the voltage at the level terminal.

[0044] Methods (1) and (2) need to be preset in advance, while method (3) is adjustable. Specific details are as follows.

[0045] Method (1) Figure 7 As shown, by configuring the first transistor and the second transistor to have different threshold voltage differences, the voltage source device can obtain different output voltages.

[0046] Specifically, the semiconductor layers of the first transistor 201 and the second transistor 202 are configured with different amorphous oxide materials to form different threshold voltages, as shown in Figure 8. By using different amorphous oxide semiconductor layers to regulate the threshold voltages of the first transistor and the second transistor, the threshold voltage difference between the first transistor and the second transistor is changed, thereby regulating the output voltage of the voltage source device.

[0047] Method (2) As shown in Figures 9 to 11, by changing the width-to-length ratio of the first transistor 201 or the second transistor 202, the voltage source device can obtain different output voltages.

[0048] Specifically, multiple first transistors and second transistors with identical structures are connected in parallel; the gates of multiple first transistors are connected through gate / drain interconnect metal, the gates of multiple second transistors are connected through gate interconnect metal, the multiple second transistors are connected to the gates of multiple first transistors through their sources, and the gates of multiple adjacent first transistors are filled with a first dielectric layer and mutually insulated to form a multi-pillar parallel structure with an equivalent channel length that remains constant and an equivalent channel width that increases with the number of pillars. By configuring the number of parallel first and / or second transistor pillars, the equivalent width-to-length ratio of the first and second transistors can be adjusted, thereby enabling the setting and control of the output voltage.

[0049] As shown in Figure 11, the first transistor and the second transistor can form a "multi-pillar" structure by connecting multiple vertical transistors in parallel. The first transistor and the second transistor are composed of multiple corresponding types of transistor pillars, each pillar independently containing a source, drain, and gate structure. The gates of all pillars are electrically connected by a top metal, which enables synchronous control of all vertical transistors. The sources of adjacent pillars can be electrically connected by extending the first electrode 106, and the drains of adjacent pillars can be electrically connected by extending and growing the second electrode 103. The first dielectric layer 105 fills the spaces between adjacent transistors to form an isolation structure. The drain of the second transistor 202 is connected to the second level terminal 203, and the source of the first transistor is connected to the first level terminal 206.

[0050] For example, as shown in Figures 12 and 13, the gate of the second transistor is electrically connected via connecting metal 109, and the drain is electrically connected via an extension of the second electrode 103a. The second electrode 103b of the first transistor extends to electrically connect the source of the second transistor, the gate of the first transistor, and the drain, with the source connected via an extension of the first electrode 106b. Here, the electrode and dielectric layer can be formed using methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), and then the formed electrode or dielectric layer can be etched to remove excess material and sidewall portions, forming the extended electrode structure.

[0051] Each pillar provides an independent current path, and the total current flowing through the transistor is the sum of the currents in all pillars. The parallel-stacked multi-pillar structure increases the equivalent channel width of the transistor while maintaining the equivalent channel length. By stacking multiple vertical transistor pillars in parallel using a multi-pillar structure, the number of first or second transistors can be varied. The parallel-stacked vertical transistors increase the equivalent channel width while maintaining the same equivalent channel length, thereby controlling the width-to-length ratio of the voltage source device and consequently controlling the output voltage. The voltage source device can also consist of a first preset number of first transistors and a second preset number of second transistors.

[0052] Method (3) Figure 14 As shown, by directly setting different The voltage at the level terminal is used to generate different output voltages from the voltage source device.

[0053] See Figure 15 Corresponding to the voltage source device embodiment described above, this application embodiment provides a current generating device 40, including: A voltage source device 20 based on a vertical thin-film transistor, as described above; At least one load unit 30; The input terminal of the load unit 30 is electrically connected to the output terminal 205 of the voltage source device. The voltage source device is used to provide a stable input voltage to the load unit 30, and the load unit generates an output current according to the input voltage.

[0054] Furthermore, the load cell consists of two transistors, employing transistors that are isomorphic and identical to those in memory cells of memory arrays based on a dual-transistor capacitor-free cell structure (2T0C), requiring only an approximate word-bit line electrical connection method. Specifically, as... Figure 16 As shown, the load unit 30 includes a third transistor 403 and a fourth transistor 404; The drain of the third transistor 403 is electrically connected to the output terminal 205 of the voltage source device, the gate is electrically connected to the control signal terminal 408, and the source is electrically connected to the gate of the fourth transistor 404. The drain of the fourth transistor 404 serves as the current output terminal 409, and the source is electrically connected to the voltage control terminal 410.

[0055] For example, such as Figure 16 As shown, taking the current generating device 40 including a load unit 30 as an example, it includes a first transistor 201, a second transistor 202, a third transistor 403, a fourth transistor 404, and a second level terminal 203. Level terminal 204, first level terminal 206, control signal terminal 408, current output terminal 409, voltage control terminal 410.

[0056] In this configuration, the first transistor 201 and the second transistor 202 form a voltage source device, and the generated output voltage is applied to the drain of the third transistor 403. The third transistor 403 is a switching transistor, with its gate electrically connected to the control signal terminal 408 and its source electrically connected to the gate of the fourth transistor 404. The drain of the fourth transistor 404 generates current, and its source is electrically connected to the first level terminal.

[0057] Initially, the second level terminal 203 and the control signal terminal 408 are set to low level, and the current output terminal 409 and the voltage control terminal 410 are set to the same initial voltage. During operation, the second level terminal 203 is set to high voltage, and the voltage source device generates a stable output voltage, which is output to the drain of the third transistor 403. Subsequently, the signal control terminal 408 is set from low level to high level, causing the third transistor 403 to turn on, so that the output voltage is stored in the equivalent capacitance between the gate of the fourth transistor 404 and the source of the third transistor 403, and exists in the form of charge. Then, the potential of the source terminal 410 of the fourth transistor 404 is pulled down, setting a fixed voltage difference between the source and drain of the fourth transistor 404, so that the fourth transistor 404 operates in the saturation region. Since the voltage stored in the gate of the fourth transistor 404 remains unchanged, and the fourth transistor 404 operates in the saturation region, the current output terminal 409 generates a stable saturation current. Then, the voltage pull-down terminal 410 is reset to the initial voltage, the signal control terminal 408 is set to low level, and the output current is 0.

[0058] The current regulation method of the current generating device is as follows: Figure 17 As shown, different levels are set through the 204 level pin. The voltage source device generates different output voltages, which are then output to the drain of the third transistor 403. The third transistor 403 then turns on, storing the voltage in the equivalent capacitance between the gate of the fourth transistor 404 and the source of the third transistor 403, where it exists as a charge. Because different voltages are stored at the gate of the fourth transistor 404, the magnitude of the generated current is changed, thus controlling the output current.

[0059] For example, such as Figure 18 As shown, the current generating device 40 includes multiple load units 30, and its working principle is explained below: In each unit, the drain of the third transistor 403 is electrically connected to the voltage output terminal of the voltage source device, the gate of the third transistor 403 is electrically connected to the control signal terminal 408, and the source is electrically connected to the gate of the fourth transistor 404 (in the figure, n represents the corresponding element in the nth load unit, such as 403n representing the third transistor in the nth load unit).

[0060] When the device starts working, the voltage source generates a voltage and applies it to the drain of the third transistor 403 in each unit. Then, the signal control terminal 408 is changed from a low level to a high level, turning on the third transistor 403. This allows the voltage to be stored in the equivalent capacitance between the gate of the fourth transistor 404 and the source of the third transistor 403, existing as a charge. Subsequently, the potential of the source terminal 410 of the fourth transistor 404 is pulled down, establishing a fixed voltage difference between the source and drain of the fourth transistor 404. The current output terminal 409 then generates a stable saturation current. This allows a single voltage source to drive multiple current generation units to generate current. The effect is shown in Figures 19 and 20.

[0061] In memory arrays based on dual-transistor capacitor-free cell structures, the low leakage current characteristic of vertical thin-film transistors can extend memory data retention time to the order of kiloseconds, significantly reducing power consumption.

[0062] Corresponding to the above-described voltage source device embodiments, this application provides a low-dropout linear regulator device, comprising: The voltage source device based on the vertical thin-film transistor is used to provide a reference voltage to the input terminal of the low dropout linear regulator device; At least one load unit, the input terminal of which is electrically connected to the output terminal of the low dropout linear regulator device, is used to generate a reference current and / or a load current under the drive of the low dropout linear regulator; The load unit includes a third transistor and a fourth transistor; The drain of the third transistor is electrically connected to the output terminal of the voltage source device, the gate is electrically connected to the control signal terminal, and the source is electrically connected to the gate of the fourth transistor. The drain of the fourth transistor serves as the current output terminal, and the source is electrically connected to the voltage control terminal. The low-dropout linear regulator device further includes a voltage input terminal, a voltage output terminal, and a feedback control circuit. The feedback control circuit compares the output voltage of the voltage output terminal with the reference voltage output by the voltage source device, and adjusts the control signal terminal and / or voltage control terminal of the load unit according to the comparison result to achieve regulated output under low-dropout conditions. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.

[0063] It is understood that the embodiments of this application have been described above in conjunction with the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. As those skilled in the art will know, various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, those skilled in the art, under the guidance or instruction of this application, can modify these features and embodiments to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of this invention.

Claims

1. A vertical thin-film transistor, characterized in that, include: The gate includes a gate substrate disposed at one end of the transistor and a gate post extending a predetermined length from the center of the gate substrate to the other end of the transistor. A second dielectric layer is disposed between the gate pillar and the semiconductor layer, and between the gate substrate and the second electrode, to isolate the gate. The first electrode and the second electrode are used as the source and drain of the transistor, respectively. The first electrode is disposed at the end of the transistor away from the gate; the second electrode is disposed between the second dielectric layer and the first electrode, and is exposed to the outside of the transistor. A semiconductor layer surrounds the surface of the second dielectric layer away from the gate and is electrically connected to the first electrode and the second electrode; A first dielectric layer is disposed between the first electrode and the second electrode and surrounds a portion of the semiconductor layer away from the second dielectric layer, thereby isolating the first electrode from the second electrode. The gate substrate is optionally electrically connected to the second electrode to form a vertical thin-film transistor structure with the gate and drain connected. The semiconductor layer is an amorphous oxide semiconductor layer.

2. The vertical thin-film transistor according to claim 1, characterized in that, The threshold voltage of the transistor can be optionally controlled by at least one of the following configurations: The chemical composition and oxygen vacancy concentration of the semiconductor layer are altered. Different second dielectric layers and / or interface engineering are employed to modulate interface charge and trapped states; Change the work function of the gate metal and / or the electrode material; Change the thickness of the semiconductor layer.

3. A method for fabricating a vertical thin-film transistor, characterized in that, include: S1: The first electrode, the first dielectric layer, and the second electrode are sequentially fabricated on the substrate; S2: Form a first columnar hole that penetrates the second electrode and the first dielectric layer and extends to the first electrode; S3: An amorphous oxide is prepared within the first columnar hole, and a second columnar hole is formed in the amorphous oxide to form a semiconductor layer; wherein the semiconductor layer forms an electrical connection with the first electrode and the second electrode; S4: Prepare a second medium within the second columnar pore, and form a third columnar pore in the second medium to form a second medium layer; S5: A gate is fabricated within the third columnar hole, the gate comprising a gate pillar filling the third columnar hole and a gate substrate covering the second dielectric layer and optionally electrically connected to the second electrode.

4. A voltage source device based on a vertical thin-film transistor, characterized in that, include: First transistor and second transistor, The source of the first transistor is electrically connected to a first voltage level terminal. The gate and drain of the first transistor are electrically connected, and then electrically connected to the source of the second transistor, serving as the output terminal of the voltage source device. The gate of the second transistor is connected to... The level terminal is electrically connected, and the drain of the second transistor is electrically connected to the second level terminal; In this transistor, the gate and drain are not electrically connected; The threshold voltage of the first transistor is positive, and the threshold voltage of the second transistor is negative, so as to form a threshold voltage difference between the two.

5. The voltage source device based on a vertical thin-film transistor according to claim 4, characterized in that, The first transistor and the second transistor are stacked together, with the first transistor located at the bottom of the second transistor.

6. The voltage source device based on a vertical thin-film transistor according to claim 4, characterized in that, The output voltage is controlled by adjusting the threshold voltage difference between the first transistor and the second transistor.

7. The voltage source device based on a vertical thin-film transistor according to claim 6, characterized in that, Its features are, The threshold voltages of the first transistor and the second transistor can be optionally controlled by at least one of the following configurations: The chemical composition and oxygen vacancy concentration of the semiconductor layer are altered. Different second dielectric layers and / or interface engineering are employed to modulate interface charge and trapped states; Change the work function of the gate metal and / or the electrode material; Change the thickness of the semiconductor layer.

8. The voltage source device based on a vertical thin-film transistor according to claim 4, characterized in that, The output voltage is controlled by adjusting the width-to-length ratio of the first or second transistor; In this configuration, multiple first transistors and second transistors with identical structures are connected in parallel; the gates of multiple first transistors are connected through gate / drain interconnect metal, the gates of multiple second transistors are connected through gate interconnect metal, the multiple second transistors are connected to the gates of multiple first transistors through their sources, and the gates of multiple adjacent first transistors are filled with a first dielectric layer and mutually insulated to form a multi-pillar parallel structure with an equivalent channel length that remains constant and an equivalent channel width that increases with the number of pillars. By configuring the number of parallel first and / or second transistor pillars, the equivalent width-to-length ratio of the first and second transistors can be adjusted, thereby enabling the setting and control of the output voltage.

9. The voltage source device based on a vertical thin-film transistor according to claim 4, characterized in that, By adjusting The output voltage is adjusted by the voltage at the level terminal.

10. A current generating device, characterized in that, include: A voltage source device based on a vertical thin-film transistor as described in claim 4; At least one load unit; The input terminal of the load unit is electrically connected to the output terminal of the voltage source device. The voltage source device is used to provide a stable input voltage to the load unit, and the load unit generates an output current according to the input voltage. The load unit includes a third transistor and a fourth transistor; The drain of the third transistor is electrically connected to the output terminal of the voltage source device, the gate is electrically connected to the control signal terminal, and the source is electrically connected to the gate of the fourth transistor. The drain of the fourth transistor serves as the current output terminal, while the source is electrically connected to the voltage control terminal.

11. A low-dropout linear voltage regulator device, characterized in that, include: The voltage source device based on a vertical thin-film transistor as described in claim 4 is used to provide a reference voltage to the input terminal of the low-dropout linear regulator device; At least one load unit, the input terminal of which is electrically connected to the output terminal of the low dropout linear regulator device, is used to generate a reference current and / or a load current under the drive of the low dropout linear regulator; The load unit includes a third transistor and a fourth transistor; The drain of the third transistor is electrically connected to the output terminal of the voltage source device, the gate is electrically connected to the control signal terminal, and the source is electrically connected to the gate of the fourth transistor. The drain of the fourth transistor serves as the current output terminal, and the source is electrically connected to the voltage control terminal. The low-dropout linear regulator device further includes a voltage input terminal, a voltage output terminal, and a feedback control circuit. The feedback control circuit is used to compare the output voltage of the voltage output terminal with the reference voltage output by the voltage source device, and adjust the control signal terminal and / or voltage control terminal of the load unit according to the comparison result to achieve regulated output under low-dropout conditions.

Images