Integrated circuit device and manufacturing method thereof

Abstract

A single photon avalanche diode (SPAD) image sensor includes at least three device layers. The first device layer has an SPAD array. The second device layer provides a pixel internal circuit for the SPAD. The row driver circuit, the column readout circuit and other circuits are located in the third device layer or the fourth device layer. The first device layer may be fabricated using a streamlined process that does not produce any transistor. The second device layer may be fabricated with a mature process technology that provides a high voltage transistor. Third and optional fourth device layers may be fabricated with advanced process techniques that provide high density transistors with lower operating voltages than required for in-pixel circuitry. This structure increases the number of SPAD pixels that can be provided per unit device area, and is cost effective. The embodiment of the invention also discloses an integrated circuit device and a manufacturing method thereof.

Description

Integrated circuit devices and their manufacturing methods Technical Field

[0001] Embodiments of this application relate to integrated circuit devices and methods for manufacturing the same. Background Technology

[0002] A single-photon avalanche diode (SPAD) is a solid-state photodetector that records single photons for image acquisition, ranging, and other applications. A SPAD consists of an absorption region and a multiplication region. The multiplication region comprises a reverse-biased pn junction. Photons absorbed in the absorption region generate electron-hole pairs. Charge carriers are accelerated by the high electric field of the reverse-biased pn junction. The accelerated charge carriers cause impact ionization and avalanche multiplication processes, generating a detectable signal. In Gieger mode, the pn junction is reverse-biased above its breakdown voltage, allowing the avalanche process to be self-sustaining. After a detected event, a cutoff process resets the SPAD. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, an integrated circuit device is provided, comprising: a first device layer including a first semiconductor substrate and an array of single-photon avalanche diodes (SPADs); a second device layer including a second semiconductor substrate and bonded to the first device layer, the second device layer including in-pixel circuitry and row and column connectors, the in-pixel circuitry including cut-off and recharge circuitry configured to cut off avalanche events in the SPADs; and a third device layer including a third semiconductor substrate and bonded to the second device layer, the third device layer including row driver circuitry and column readout circuitry, the row driver circuitry and column readout circuitry being configured to address the in-pixel circuitry in the second device layer via the row and column connectors.

[0004] According to another aspect of the embodiments of this application, a method for manufacturing an integrated circuit device is provided, comprising: forming a first device layer including a first semiconductor substrate, the first device layer including an array of single-photon avalanche diodes (SPADs); and forming a second device layer including a second semiconductor substrate. The second device includes: in-pixel circuitry corresponding to the SPADs, including cutoff and recharge circuitry configured to block avalanche events in the SPADs; row and column connectors; and through-substrate vias (TSVs) corresponding to the row and column connectors. The method further comprises: bonding the first device layer to the second device layer such that each SPAD in the first device layer is electrically connected to a corresponding in-pixel circuitry in the second device layer via an independent bonding between the first and second device layers; forming a third device layer including a third semiconductor substrate, the third device layer including row driver circuitry and column readout circuitry; and bonding the third device layer to the second device layer such that the row and column connectors in the second device layer are electrically coupled to the row driver circuitry and column readout circuitry of the third device layer via TSVs.

[0005] According to another aspect of the embodiments of this application, a method for manufacturing an integrated circuit device is provided, comprising: processing a first semiconductor substrate, wherein the processing includes a first front-end process for forming an array of SPADs; processing a second semiconductor substrate, wherein processing the second semiconductor substrate includes a second front-end process and a back-end process, the second front-end process forming an in-pixel circuit array including cutoff and recharge circuits, and the back-end process forming row buses and column buses of the in-pixel circuit array; processing a third semiconductor substrate, wherein processing the third semiconductor substrate includes a third front-end process for forming row driver circuits and column readout circuits; bonding the second semiconductor substrate to the first semiconductor substrate, wherein bonding forms a pixel-level electrical connection between the array of SPADs and the in-pixel circuit array; and bonding the second semiconductor substrate to the third semiconductor substrate, wherein bonding forms an electrical connection between the row driver circuit and the row bus and between the column readout circuit and the column bus. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. As is standard industry practice, features are not drawn to scale. Furthermore, the dimensions of the various features in the various drawings may be arbitrarily increased or decreased relative to each other for illustrative purposes or to provide emphasis.

[0007] Figure 1 shows an exploded view of an integrated circuit (IC) device according to an embodiment of the present disclosure.

[0008] Figure 2 provides a circuit diagram of a SPAD pixel circuit according to an embodiment of the present disclosure.

[0009] Figure 3 shows a cross-sectional view of an IC device according to an embodiment of the present disclosure.

[0010] Figures 4-13 provide a series of cross-sectional views illustrating the IC device manufacturing process according to embodiments of the present disclosure.

[0011] Figure 14 provides a flowchart of a process according to an embodiment of the present disclosure. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, interval relationship terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. In addition to the orientations shown in the figures, interval relationship terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the interval relationship descriptors used herein may be interpreted accordingly. The terms “first,” “second,” “third,” “fourth,” etc., are merely general identifiers and are therefore interchangeable in various embodiments. For example, while in some embodiments an element (e.g., an opening) may be referred to as a “first” element, in other embodiments the element may be referred to as a “second” element.

[0014] The SPAD pn junction is reverse biased at a high voltage (>10V) above its breakdown voltage. Cut-off and recharge circuitry, as well as other in-pixel circuitry of the SPAD, uses transistors that operate at these high voltages. These high-voltage transistors utilize established semiconductor technologies that inherently have relatively large minimum transistor spacing. In multilayer devices, the in-pixel circuitry can be placed in an array on a second device layer and have approximately the same footprint as the SPAD array in the first device layer, allowing each in-pixel circuitry to be directly opposite and connected to its corresponding SPAD via short connections. The circuitry interfacing with the in-pixel circuitry, including at least row driver circuitry and column readout circuitry, is typically located in the peripheral region near the edge of the in-pixel circuitry array. The peripheral circuitry occupies a significant amount of space, thus limiting the SPAD in-pixel circuitry and the SPAD itself to 20-25% of the total chip area.

[0015] This disclosure addresses this issue by repositioning row driver circuitry, column readout circuitry, and other such circuitry to a third device layer. The third device layer can operate at a lower voltage (e.g., <2.8V) than the second device layer, and therefore can be fabricated using advanced process technologies that provide high-density transistors limited to lower operating voltages. In some embodiments, a fourth device layer is also included. The fourth device layer can provide an application-specific integrated circuit (ASIC). The reduction in peripheral circuitry area allows more chip area to be used for the SPAD, thereby improving the achievable resolution and efficiency of SPAD-based image sensors.

[0016] Therefore, one aspect of this disclosure is an integrated circuit device comprising at least three device layers. A first device layer comprises a semiconductor substrate having a SPAD array. In some embodiments, this layer is dedicated to photon detection and does not include any transistors, which allows the SPADs to be fabricated using simplified processes suitable for providing high sensitivity and high efficiency.

[0017] The second device layer of the first device layer is bonded at the pixel level and contains in-pixel circuitry, which includes at least cutoff and recharge circuitry for the SPAD. Because these in-pixel circuits operate at high voltages, this layer is fabricated using semiconductor processes suitable for high-voltage transistors, requiring relatively large transistor spacing. This can be a mature technology with high reliability and low cost.

[0018] The third device layer is bonded to the second device layer. The third device layer includes row driver circuitry, column readout circuitry, and other circuitry that may provide logic or control functions. Because these circuits do not need to operate at high voltages, they can be fabricated using more advanced semiconductor technologies with smaller transistor pitch, resulting in higher circuit density and a smaller circuit footprint. Electrical connections between the second and third device layers are facilitated by row and column connectors on the second device layer and by through-silicon vias (TSVs) (or through-substrate vias) extending through the second device. In some embodiments, the footprint of the row driver circuitry and column readout circuitry is the same as the area they occupy on the second device layer, located outside the footprint of the SPAD and the in-pixel circuitry array. This positioning maintains short connection lengths and allows for efficiencies comparable to those achieved if these circuits were located on the second device layer.

[0019] In some embodiments, additional functionality is integrated into a third device layer. In some embodiments, this additional functionality includes clock management circuitry, such as a phase-locked loop (PLL) and a delay-locked loop (DLL). In some embodiments, this additional functionality includes an image signal processor (ISP). The PLL, DLL, and ISP circuitry may reside within a placeholder area of ​​the SPAD array. In some embodiments, the integrated circuit device includes a fourth device layer. The fourth device layer may include an application-specific integrated circuit (ASIC) that provides advanced processing and interface functions. The first three device layers may be limited to image sensing functionality, while the ASIC may provide additional functions utilizing image sensing.

[0020] Another aspect of this disclosure is a method for manufacturing integrated circuit devices. This method includes forming and bonding three (or more) device layers in a manner that ensures reliable electrical connections, while allowing each layer to be fabricated using semiconductor processes optimized for its specific function. This method enables efficient integration of SPAD arrays with high-voltage circuitry, while allowing logic and control to be implemented with high-density low-voltage circuitry, thereby increasing the area available for photon detection.

[0021] Figure 1 shows an exploded view of an integrated circuit device 100 according to some embodiments. The integrated circuit device 100 includes a first device layer 101, a second device layer 103, and a third device layer 105 bonded together. The first device layer 101 includes a SPAD array 111. In some embodiments, the SPAD array 111 includes approximately 32x32 to approximately 320x232 pixels (a single SPAD). In some embodiments, the SPAD array 111 includes more than 320x232 pixels. In some embodiments, the SPAD array includes more than one million pixels. The more pixels, the higher the resolution. This disclosure provides a structure capable of providing more pixels on a chip of a given size.

[0022] The SPADs in the SPAD array 111 include absorption regions provided by photosensitive semiconductors. The absorption region can be a portion of the semiconductor substrate, embedded within the semiconductor substrate, or exist as a mesa on the semiconductor substrate. The absorption region can be any suitable semiconductor and is selected based on the wavelength of the light to be detected.

[0023] In some embodiments, the absorption region is silicon, etc. Silicon absorbs visible to near-infrared light, i.e., from about 300 nm to about 1100 nm, making it suitable for direct time-of-flight (dToF) and photon-counting image sensors. Silicon SPADs can be manufactured using CMOS-compatible processes. Applications of silicon SPADs include LiDAR and 3D imaging systems. Silicon pn junctions have reverse breakdown in the range of about 20 V to about 200 V. The appropriate bias voltage for a SPAD is the reverse breakdown voltage plus an over-bias voltage. For silicon SPADs, the over-bias voltage is from about 2 V to about 10 V. If the over-bias voltage is too low, photon detection efficiency will be compromised. If the over-bias voltage is too high, dark current may be excessive.

[0024] In some embodiments, the absorption region is germanium, etc. Germanium absorbs near-infrared and mid-infrared light, i.e., from about 800 nm to about 1500 nm, making it suitable for dToF (direct time-of-flight) and other lidar systems. Applications of germanium SPADs include long-range lidar and telecommunications systems. In some embodiments, the germanium SPAD is germanium-on-silicon. In some embodiments, the germanium-on-silicon SPAD comprises a heterojunction diode. For a germanium pn junction, the reverse breakdown voltage is from about 5V to about 30V, and the overbias voltage is from about 1V to about 3V. For a germanium-on-silicon SPAD, the reverse breakdown voltage is from about 10V to about 50V, and the overbias voltage is from about 2V to about 5V.

[0025] In some embodiments, the absorption region is indium gallium arsenide (InGaAs) on indium phosphide (InP) or the like. Indium gallium arsenide absorbs wavelengths in the range of about 1000 nm to about 1700 nm, making it suitable for dToF and photon counting systems. Applications include lidar, telecommunications, and imaging systems. The integrated circuit device 100 is shown as a dToF system, but can be readily adapted to any of these applications. For an InGaAs SPAD on InP, the reverse breakdown voltage is about 10 V to about 50 V, and the over-bias voltage is about 2 V to about 6 V.

[0026] The second device layer 103 includes an in-pixel circuitry array 121. The in-pixel circuitry array 121 has in-pixel circuitry corresponding one-to-one with the SPADs in the SPAD array 111. For each pixel, there is at least one electrical connection between the first device layer 101 and the second device layer 103. In some embodiments, the in-pixel circuitry array 121 is located within a berth of the SPAD array 111 and spans the width of a single pixel. Row connectors 123 and column connectors 125 are laterally disposed beside the in-pixel circuitry array 121 and coupled thereto via row buses and column buses (not shown). The in-pixel circuitry includes cutoff and recharge circuitry, as well as circuitry for generating digital or other low-voltage outputs from SPAD avalanche events.

[0027] The third device layer 105 includes row driver circuitry 133 and column readout circuitry 135. In some embodiments, the third device layer 105 further includes one or more of a phase-locked loop (PLL) 137, a delay phase-locked loop (DLL) 139, and an image signal processor (ISP) 131. In some embodiments, the row driver circuitry 133 and column readout circuitry 135 are located below the row connectors 123 and 125, outside the footprint of the SPAD array 111. In some embodiments, the PLL 137, DLL 139, and ISP are within the footprint of the SPAD array 111. This configuration limits the connection length between the circuitry of the row driver circuitry 133, the column readout circuitry 135, and the in-pixel circuitry array 121, while effectively utilizing the area in the third device layer 105.

[0028] The in-pixel circuitry includes at least a cutoff and recharge circuitry responsible for stopping avalanche events in the SPAD after photon detection and ensuring the diode is properly charged in subsequent detections, as well as signal processing circuitry to provide a low-voltage output signal in response to avalanche events. The cutoff and recharge circuitry can be a passive cutoff and recharge circuitry, where a high-value resistor is used to limit current and restore the SPAD to its operating bias. Alternatively, the cutoff and recharge circuitry can be an active cutoff and recharge circuitry, which includes a feedback-controlled transistor that can quickly pull down the SPAD voltage compared to a passive cutoff, stopping avalanche with greater speed and control.

[0029] Figure 2 provides a circuit diagram 200 illustrating the SPAD 241 and its in-pixel circuitry 201. The SPAD 241 is located in the first device layer 101. The in-pixel circuitry 201 is located in the second device layer 103 (see Figure 1) and provides active cutoff and recharge circuitry. Specifically, the in-pixel circuitry 201 includes cutoff and recharge circuitry 237, signal processing and output circuitry 207, and timing and control circuitry 209.

[0030] The signal processing and output circuit 207 converts the transient simulated avalanche event into a low-voltage (logic level) output signal. This circuit includes first, second, and third inverters 203, 204, and 205 connected in series. The first inverter 203 is powered by V... DD_comp The comparators are powered by a first inverter 203, which converts the avalanche pulse from SPAD 241 into a logic-level signal. The second and third inverters 204 and 205 are buffers and drivers that regulate (amplify and shape) the logic-level signal to V. DDL A clear digital pulse is generated at the point of origin, and this pulse is transmitted to the column bus shared by the first plurality of SPAD 241s. V DDL It is the operating voltage of the third device layer 105 (see Figure 1), and is less than the operating voltage V of the second device layer 103. DDH .

[0031] Timing and control circuitry 209 generates control signals for drive cutoff and recharge circuitry 237. It can interface with timing measurement (e.g., a time-to-digital converter or an external timing line) or be selected between internal and external timing signals. Timing and control circuitry 209 may include a fourth inverter 213, a capacitor 215, a multiplexer 217, and first, second, and third NAND gates 219, 221, and 223. The fourth inverter 213 receives a tap 208 from signal processing and output circuitry 207, which provides an indication that SPAD 241 is firing. The output of the fourth inverter helps shape the internal timing signal. Capacitor 215 modulates this timing. Switch 211 can be used to reset the output of the fourth inverter 213 to re-enable the timing circuitry between avalanche events.

[0032] Multiplexer 217 is based on time mode selection signal (T) sel The multiplexer selects between internal timing signals and external timing signals (column timers). The output of multiplexer 217 undergoes further logic processing, causing timing and control circuitry 209 to use one or more timing signals to control cutoff and recharge circuitry 237 based on the operating mode. Specifically, third NAND gate 223 selects between timing signals and active recharge enable (ARC). EN The setting of the signal provides the recharge control signal 224. The first NAND gate 219 and the second NAND gate 221 are based on the timing signal, the avalanche signal from tap 208 and the row selection signal (R). sel Provides cutoff enable signal 222. Row selection signal R sel It can be derived from the row bus shared by multiple SPAD 241s.

[0033] The cutoff and recharge circuit 237 includes a floating node 227, a recharge node 231, an active cutoff switch 225, a recharge switch 229, a cutoff bias transistor 233, and a recharge enable transistor 235. The floating node 227 is connected to the cathode of the SPAD 241. The active cutoff switch 225 is an NMOS transistor connected between the floating node 227 and ground. The recharge switch 229 is a PMOS transistor connected between the floating node 227 and the recharge node 231. Both the active cutoff switch 225 and the recharge switch 229 are controlled by a cutoff enable signal 222. According to the cutoff enable signal 222, these transistors can collectively force the floating node 227 to ground or allow it to be driven to the voltage of the recharge node 231.

[0034] The cutoff bias transistor 233 is connected to the high voltage V. DDH Between and recharge node 231. It is controlled by the cutoff bias signal (Q). sel) Adjustment to help eliminate avalanche events in a controlled manner. The recharge-enabled transistor 235 is also connected to the high voltage V. DDH Between and recharge node 231. Recharge enable transistor 235 provides a fast recharge path controlled by recharge control signal 224.

[0035] When a photon triggers an avalanche in SPAD 241, the voltage of floating node 227 drops rapidly (or rises, depending on polarity). Processing and output circuitry 207 detects the pulse and provides a low-voltage digital output signal to the column bus. Timing and control circuitry 209 detects the avalanche event and issues a cutoff enable signal 222, turning off the active cutoff switch 225 and reducing the voltage on floating node 227. After a brief delay, recharge control signal 224 becomes active, and floating node 227 returns to its reverse bias voltage.

[0036] Figure 3 shows a cross-sectional view of an integrated circuit device 300 according to some embodiments. The integrated circuit device 300 includes a first device layer 101, a second device layer 103, a third device layer 105, and a fourth device layer 373. The fourth device layer 373 includes a plurality of semiconductor devices, including transistors 353 on the front side 337F of a semiconductor substrate 337. The semiconductor devices are interconnected via metal interconnect structures 333 and form an ASIC. The fourth device layer 373 is bonded to the third device layer 105 via a bonding structure 369.

[0037] The third device layer 105 includes a semiconductor substrate 325 having a front side 325F and a back side 325B. A plurality of semiconductor devices, including transistors 349, are disposed on the front side 325F, interconnected by a metal interconnect structure 321, and provide PLL 137, DLL 139, and ISP 131 (see FIG. 1). A redistribution layer 329 is disposed on the back side 325B. A TSV 365 forms a connection between the metal interconnect structure 321 and the redistribution layer 329. The third device layer 105 is bonded to the second device layer 103 via a bonding structure 361.

[0038] The second device layer 103 includes a semiconductor substrate 313 having a front side 313F and a back side 313B. A plurality of semiconductor devices, including transistors 345, are disposed on the front side 313F, interconnected by a metal interconnect structure 309, and provide in-pixel circuitry such as cutoff and recharge circuitry 237, signal processing and output circuitry 207, and timing and control circuitry 209 (see FIG. 2). The metal interconnect structure 309 also provides row and column buses (not shown), row connectors 123 and column connectors 125 (see FIG. 1). A redistribution layer 317 is disposed on the back side 313B. A TSV 357 forms a connection between the row connectors 123 and column connectors 125 and the redistribution layer 317. The second device layer 103 is bonded to the first device layer 101 via a bonding structure 341.

[0039] The first device layer 101 includes a semiconductor substrate 301 having a front side 301F and a back side 301B. SPADs 241 are disposed in or on the front side 301F and connected to the in-pixel circuitry of the second device layer 103 via a metal interconnect structure 305 and a bonding structure 341 located above the front side 301F. An isolation structure (not shown) provides electrical isolation between the SPADs 241. Microlenses, color filters, etc., may be disposed on the back side 301B.

[0040] Figures 4-13 provide a series of cross-sectional views 400-1300 illustrating integrated circuit devices according to the present disclosure at different manufacturing stages of the process according to the present disclosure. Although Figures 4-13 are described with respect to a series of actions, it is understood that in some cases the order of the actions may change, and this series of actions applies to structures other than those shown. In some embodiments, some of these actions may be omitted in whole or in part. Furthermore, while Figures 4-13 are described with respect to a series of actions, it is understood that the structures shown in Figures 4-13 are not limited to the manufacturing method but can exist independently of the method.

[0041] As shown in cross-sectional view 400 of Figure 4, the process begins with separate front-end processing (FEOL) and back-end processing (BEOL) processes for each of the first device layer 101, the second device layer 103, the third device layer 105, and the fourth device layer 373. During this processing stage, each of these device layers can be in wafer form.

[0042] Each of the semiconductor substrates 301, 313, 325, and 337 may be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. At least the upper part of each is a semiconductor. The semiconductor may be silicon (Si), a III-V group semiconductor (e.g., GaAs), or some other binary semiconductor, ternary semiconductor (e.g., AlGaAs), higher-order semiconductor, or any other suitable semiconductor.

[0043] The FEOL process of the first device layer 101 forms a SPAD 241 in or on the semiconductor substrate 301. Forming the SPAD 241 may include doping the semiconductor substrate 301, embedding another semiconductor in the semiconductor substrate 301, or forming a mesa of another semiconductor on the semiconductor substrate 302. The FEOL process of the first device layer 101 may also include forming contact regions and isolation structures in the semiconductor substrate 301. The isolation structures may include shallow trench isolation structures, deep trench isolation structures, or doped regions that may include buried layers. The FEOL process of the first device layer 101 may be a dedicated process sequence structure surrounding the formation of the SPAD 241. In some embodiments, a characteristic of such a dedicated process sequence is the absence of process steps for forming polysilicon gates, metal gates, or other transistor structures on the front side 301F.

[0044] The FEOL process of the second device layer 103 forms a transistor 345 and other semiconductor devices on the front side 313F of the semiconductor substrate 313. These other semiconductor devices may include diodes, capacitors, thyristors, resistors, etc., or any combination thereof. The transistor 345 is a high-voltage transistor capable of operating at 10V or higher. In some embodiments, the transistor 345 is capable of operating at 20V or higher. In some embodiments, the transistor 345 is a planar transistor with a minimum pitch of 22nm or greater, the minimum pitch being determined by its formation process. In some embodiments, the transistor 345 has a minimum pitch of 28nm or greater. In some embodiments, the transistor 345 has a minimum pitch of 40nm or greater. In some embodiments, the transistor 345 has a polysilicon gate. In some embodiments, the transistor 345 has a tunneling dielectric layer, which is silicon dioxide (SiO2) or a medium-k dielectric (such as silicon nitride (SiN), silicon oxynitride (SiON), etc., with a dielectric constant higher than SiO2 but lower than 10). In some embodiments, the transistor 345 has a SiO2 tunneling dielectric layer. Planar transistors, larger transistor spacing, polysilicon gates, medium-k or SiO2 tunneling dielectric layers are associated with more mature process technologies that support higher operating voltages.

[0045] The FEOL process of the third device layer 105 forms transistors 349 and other semiconductor devices on the front side 325F of the semiconductor substrate 325. These other semiconductor devices may include diodes, capacitors, memory cells, thyristors, resistors, etc., or any combination thereof. In some embodiments, the third device layer 105 includes memory cells, while the second device layer 103 does not. The third device layer 105 has a maximum operating voltage of about 5V or lower. In some embodiments, the third device layer 105 has a maximum operating voltage of about 2.8V or lower.

[0046] The FEOL process of the third device layer 105 follows a different process than that of the FEOL process of the second device layer 103. These differences relate to more advanced process technologies that provide higher circuit density and lower maximum operating voltage. In some embodiments, the FEOL process of the third device layer 105 includes lithography using shorter wavelengths than those used in the FEOL process of the second device layer 103. In some embodiments, the FEOL process of the third device layer 105 uses extreme ultraviolet (EUV) lithography, while the FEOL process of the second device layer 103 uses deep ultraviolet (DUV) lithography. In some embodiments, the FEOL process of the third device layer 105 uses immersion lithography, while the FEOL process of the second device layer 103 uses air lithography. In some embodiments, the FEOL process of the third device layer 105 uses vacuum lithography, while the FEOL process of the second device layer 103 uses lithography in a non-vacuum environment. In some embodiments, the FEOL process of the third device layer 105 uses a multi-patterning process such as dual patterning, while the FEOL process of the second device layer 103 uses only a single patterning.

[0047] In some embodiments, transistor 349 of the third device layer 105 has a more advanced technical structure than transistor 345 of the second device layer 103. The advancement progresses from planar transistors to FinFETs, then to gate-all-around (GAA) transistors, and finally to complementary FETs (C-FETs). A C-FET is a GAA that vertically stacks nMOS and pMOS nanosheets to reduce footprint and improve performance. In some embodiments, transistor 349 is a FinFET. In some embodiments, transistor 349 is a GAA transistor. In some embodiments, transistor 349 has a metal gate, while transistor 345 has a non-metal gate. In some embodiments, transistor 349 has a metal gate, while transistor 345 has a non-metal gate. In some embodiments, transistor 349 has a tunneling dielectric with a higher k than transistor 345. In some embodiments, transistor 349 has a high-k tunneling dielectric, i.e., a tunneling dielectric with a dielectric constant of 10 or higher. Examples of high-k dielectrics include hafnium-based materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and hafnium aluminum oxide (HfO2-Al2O3) alloys. Other examples of high-k dielectrics include, but are not limited to, zirconium oxide (ZrO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), and strontium titanium oxide (SrTiO3).

[0048] The transistor 349 of the third device layer 105 has a smaller minimum pitch than the transistor 345 of the second device layer 103. In some embodiments, the transistor 349 has a minimum pitch of about 22 nm or less. In some embodiments, the transistor 349 has a minimum pitch of about 12 nm or less. In some embodiments, the transistor 349 has a minimum pitch of about 7 nm or less.

[0049] The FEOL process of the fourth device layer 373 forms transistors 353 and other semiconductor devices on the front side 337F of the semiconductor substrate 337. These other semiconductor devices may include diodes, capacitors, memory cells, thyristors, resistors, etc., or any combination thereof. The FEOL process of the fourth device layer 373 may use the same process sequence as the third device layer 105 or a different process sequence, but comparisons made between the processes used on the third device layer 105 and the processes used on the second device layer 103 can also be applied to comparisons between the processes used on the fourth device layer 373 and the processes used on the second device layer 103.

[0050] The BEOL process of the first, second, third, and fourth device layers 101, 103, 105, and 373 forms metal interconnect structures 305, 309, 321, and 333. These metal interconnect structures include multiple metallization layers separated by via layers. Each metallization layer includes a conductive trace surrounded by an interlayer dielectric (ILD). Each via layer includes a conductive via that interconnects the conductive trace and is surrounded by an ILD. The conductive trace and via can include one or more layers of copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, or any other suitable conductive material. The ILD can include one or more layers of silicon dioxide (SiO2), a low-k interlayer dielectric, or an extremely low-k dielectric. Low-k refers to a dielectric constant less than that of silicon dioxide (SiO2). The dielectric constant of SiO2 is approximately 3.9. Examples of low-k dielectrics include organosilicon glasses (OSGs), such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated silica glass (FSG)), organic polymer low-k dielectrics, and porous silicate glasses. Extremely low-k refers to materials with a dielectric constant of approximately 2.1 or lower. Extremely low-k dielectric materials are typically low-k dielectrics that form porous structures. Porosity reduces the effective dielectric constant.

[0051] In some embodiments, the metal interconnect structure 305 of the first device layer 101 has fewer metallization layers than the metal interconnect structures 309, 321, and 333 of the second, third, and fourth device layers 103, 105, and 373. The metal interconnect structure 305 may be limited to electrode connections and associated isolation structures for the SPAD 241, and these connections may be primarily vertical connections to in-pixel circuitry in the second device layer 103. The metal interconnect structure 309 of the second device layer 103 includes at least a grid of row and column buses. The metal interconnect structures 321 and 333 of the third and fourth device layers 105 and 373 provide complex electrical connections between semiconductor devices to provide functional circuitry disposed in these layers.

[0052] As shown in cross-sectional view 500 of Figure 5, the process continues by bonding the second device layer 103 to the first device layer 101. This bonding can be a metal-to-metal bonding or a combination of metal-to-metal and dielectric-to-dielectric bonding. This bonding is pixel-level bonding because each SPAD 241 in the SPAD array 111 forms at least one electrical connection (see Figure 1).

[0053] As shown in cross-sectional view 600 of Figure 6, the semiconductor substrate 313 is thinned from the back side 313B. The thinning process may include one or more of grinding, chemical mechanical polishing, plasma etching, or wet etching. Thinning can reduce the thickness of the semiconductor substrate 313 to about 150 μm or less.

[0054] As shown in cross-sectional view 700 of Figure 7, the TSV 357 is formed through the semiconductor substrate 313. The TSV 357 can be connected to the conductive trace 701 in the metal interconnect structure 309. The TSV 357 can be formed by etching a hole through the semiconductor substrate 313, padding the hole with a dielectric layer, an adhesive layer and / or a diffusion barrier layer, anisotropically etching to expose the contacts (such as the conductive trace 701) at the bottom of the hole, and filling the hole with a conductive material. The conductive material can be copper (Cu), tungsten (W), aluminum (Al), polysilicon, or any other suitable material.

[0055] As shown in cross-sectional view 800 of Figure 8, a redistribution layer 317 can be formed on the back side 313B. The redistribution layer may include a metallization layer, a via layer, and an ILD, similar to one of the metal interconnect structures.

[0056] As shown in cross-sectional view 900 of FIG9, the third device layer 105 is bonded to the second device layer 103. In some embodiments, the third device layer 105 is diced prior to bonding, such that bonding involves aligning and attaching a plurality of chips to the second device layer 103. This bonding may be a metal-to-metal bonding or a combination of metal-to-metal and dielectric-to-dielectric bonding.

[0057] As shown in cross-sectional view 1000 of Figure 10, the semiconductor substrate 325 is thinned from the back side 325B. The thinning process may include one or more of grinding, chemical mechanical polishing, plasma etching, or wet etching. Thinning can reduce the thickness of the semiconductor substrate 325 to about 150 μm or less.

[0058] As shown in cross-sectional view 1100 of Figure 11, the TSV 365 is formed through the semiconductor substrate 325. The TSV 365 can be connected to the conductive trace 1101 in the metal interconnect structure 321. The composition and process for forming the TSV 365 can be similar to the composition and process for forming the TSV 357.

[0059] As shown in the cross-sectional view 1200 of Figure 12, a redistribution layer 329 can be formed on the back side 325B. The redistribution layer may include a metallization layer, a via layer, and an ILD, similar to one of the metal interconnect structures.

[0060] As shown in the cross-sectional view 1300 of Figure 13, the fourth device layer 373 is bonded to the third device layer 105. In some embodiments, the fourth device layer 373 is cut prior to bonding, such that bonding involves aligning and attaching a plurality of chips to the third device layer 105. This bonding may be a metal-to-metal bonding or a combination of metal-to-metal and dielectric-to-dielectric bonding.

[0061] After bonding the fourth device layer 373 to the third device layer 105, the semiconductor substrate 337 is thinned from the back side 337B to form the integrated circuit device 300 or similar device of FIG. 3. The thinning process may include one or more of grinding, chemical mechanical polishing, plasma etching, or wet etching. Thinning may reduce the semiconductor substrate 337 to a thickness of about 50 μm or less. In some embodiments, thinning may reduce the semiconductor substrate 337 to a thickness of about 10 μm or less. After thinning, additional processing may be performed on the back side 337B. This additional processing may form one or more of a back-side deep trench isolation structure, passivation structure, metal mesh, color filter, or microlens.

[0062] Figure 14 provides a flowchart of a method 1400 for forming an image sensing integrated circuit device according to some embodiments. While method 1400 is shown and described below as a series of actions or events, it should be understood that the order of these actions or events shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events shown and / or described herein. Furthermore, not all actions shown need to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0063] Method 1400 begins with action 1401, performing separate FEOL and BEOL processes on each device layer. There are three, four, or more device layers. At least the first, second, and third device layers are formed through different process sequences. Cross-sectional view 400 of Figure 4 provides an example showing four device layers at the end of the FEOL and BEOL processes.

[0064] Action 1403 is to bond the front side of the second device layer to the back side of the first device layer. Cross-sectional view 500 of Figure 5 provides an example.

[0065] Action 1405 involves thinning the substrate of the second device layer from the back side. Cross-sectional view 600 in Figure 6 provides an example.

[0066] Action 1407 is the formation of a TSV through the substrate of the second device layer. Cross-sectional view 700 of Figure 7 provides an example.

[0067] Action 1409 involves forming a redistribution layer on the back side of the second device layer. Cross-sectional view 800 in Figure 8 provides an example.

[0068] Action 1411 is to bond the front side of the third device layer to the back side of the second device layer. Cross-sectional view 900 of Figure 9 provides an example.

[0069] Action 1413 involves thinning the substrate of the third device layer from the back side. A cross-sectional view 1000 in Figure 10 provides an example.

[0070] Action 1415 is the formation of a TSV through the substrate of the third device layer. Cross-sectional view 1100 of Figure 11 provides an example.

[0071] Action 1417 is to form a redistribution layer on the back side of the third device layer. Cross-sectional view 1200 of Figure 12 provides an example.

[0072] Action 1419 is to bond the front side of the fourth device layer to the back side of the third device layer. Cross-sectional view 1300 of Figure 13 provides an example.

[0073] Action 1421 involves thinning the substrate of the first device layer from the back side. Figure 3 provides an example of the final structure. Additional processes can be used to form microlenses or other structures on the back side of the first device layer.

[0074] Some aspects of this disclosure relate to integrated circuit devices, including first, second, and third device layers. The first device layer includes a first semiconductor substrate and an array of single-photon avalanche diodes (SPADs). The second device layer includes a second semiconductor substrate and is bonded to the first device layer. The second device layer includes in-pixel circuitry and row and column connectors. The in-pixel circuitry includes cutoff and recharge circuitry configured to block avalanche events in the SPADs. The third device layer includes a third semiconductor substrate and is bonded to the second device layer. The third device layer includes row driver circuitry and column readout circuitry configured to address the in-pixel circuitry in the second device layer via the row and column connectors.

[0075] In some embodiments, the first device layer does not include any transistors. In some embodiments, in-pixel circuitry forms a second array, with row and column connectors located on the sides of the second array; and row driver circuitry and column readout circuitry located on the sides of a vacancy area of ​​the second array. In some embodiments, the integrated circuit device further includes one or more of a phase-locked loop, a delay phase-locked loop, and an image signal processor located on a third device layer within a vacancy area of ​​the second array. In some embodiments, the integrated circuit device further includes a fourth device layer comprising a fourth semiconductor substrate and bonded to the third device layer, wherein the fourth device layer comprises an application-specific integrated circuit (ASIC).

[0076] In some embodiments, the third device layer has a smaller minimum transistor pitch than the second device layer. In some embodiments, the maximum operating voltage of the third device layer is 2.8V or lower, and the maximum operating voltage of the second device layer is 10V or higher. In some embodiments, the third device layer has a more advanced transistor structure than the second device layer. In some embodiments, the third device layer has FinFET or GAA transistors, while the second device layer has only planar transistors.

[0077] In some embodiments, each SPAD in the first device layer is electrically connected to a corresponding cutoff and recharge circuit in the second device layer via an independent junction between the first and second device layers. In some embodiments, row and column connectors in the second device layer are electrically coupled to row driver circuitry and column readout circuitry in the third device layer via through-silicon vias (TSVs) extending through a second semiconductor substrate. In some embodiments, the in-pixel circuitry each includes a comparator configured to receive avalanche current from a corresponding SPAD in the first device layer, the comparator circuitry being configured to generate a digitized signal in response to the avalanche current, wherein the voltage of the digitized signal is lower than the avalanche current, and is provided to the third device layer.

[0078] Some aspects of this disclosure relate to a method of manufacturing an integrated circuit device. The method includes forming a first device layer including a first semiconductor substrate, forming a second device layer including a second semiconductor substrate, and forming a three-device layer including a third semiconductor substrate. The first device layer includes an array of single-photon avalanche diodes (SPADs). The second device layer includes in-pixel circuitry corresponding to the SPADs, row and column connectors, and through-substrate vias (TSVs) corresponding to the row and column connectors. The in-pixel circuitry includes cutoff and recharge circuitry configured to block avalanche events in the SPADs. The third device layer includes row driver circuitry and column readout circuitry. The first device layer is bonded to the second device layer such that each SPAD in the first device layer is electrically connected to a corresponding in-pixel circuitry in the second device layer via an independent bonding between the first and second device layers. The third device layer is bonded to the second device layer such that the row and column connectors in the second device layer are electrically coupled to the row driver circuitry and column readout circuitry of the third device layer via TSVs.

[0079] In some embodiments, the first device layer is formed without transistors. In some embodiments, the second device layer is formed by a process sequence providing a minimum transistor size of at least 22 nm, and the third device layer is formed by a different process sequence providing transistors spaced less than 22 nm apart.

[0080] Some aspects of this disclosure relate to a method of manufacturing an integrated circuit device, the method comprising: processing a first semiconductor substrate, wherein the processing includes a first front-end process comprising forming an array of SPADs; processing a second semiconductor substrate, wherein the processing of the second semiconductor substrate includes a second front-end process and a back-end process, the second front-end process forming an in-pixel circuit array including cutoff and recharge circuitry, and the back-end process forming row buses and column buses of the in-pixel circuit array; processing a third semiconductor substrate, wherein the processing of the third semiconductor substrate includes a third front-end process comprising forming row driver circuitry and column readout circuitry; bonding the second semiconductor substrate to the first semiconductor substrate, wherein the bonding forms a pixel-level electrical connection between the array of SPADs and the in-pixel circuit array; and bonding the second semiconductor substrate to the third semiconductor substrate, wherein the bonding forms an electrical connection between the row driver circuitry and the row busry bus and between the column readout circuitry and the column busry bus.

[0081] In some embodiments, the third front-end process provides a higher transistor density than the second front-end process. In some embodiments, the second front-end process provides higher voltage transistors than the second front-end process. In some embodiments, the first front-end process does not form transistors. In some embodiments, the method further includes: processing a fourth semiconductor substrate, wherein the processing forms an application-specific integrated circuit; and bonding the fourth semiconductor substrate to the third semiconductor substrate.

[0082] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. An integrated circuit device, comprising: The first device layer includes a first semiconductor substrate and an array of single-photon avalanche diodes; A second device layer includes a second semiconductor substrate and is bonded to the first device layer. The second device layer includes in-pixel circuitry and row and column connectors. The in-pixel circuitry includes cutoff and recharge circuitry configured to block avalanche events in the single-photon avalanche diode. And a third device layer, including a third semiconductor substrate and bonded to the second device layer, the third device layer including row driver circuitry and column readout circuitry, the row driver circuitry and the column readout circuitry being configured to address the in-pixel circuitry in the second device layer via the row and column connectors.

2. The integrated circuit device according to claim 1, wherein, The first device layer does not include any transistors.

3. The integrated circuit device according to claim 1, wherein, The in-pixel circuitry forms a second array; the row and column connectors are located on the sides of the second array; and the row driver circuitry and the column readout circuitry are located on the sides of the occupancy area of ​​the second array.

4. The integrated circuit device of claim 1, further comprising a fourth device layer, including a fourth semiconductor substrate and bonded to the third device layer, wherein, The fourth device layer includes application-specific integrated circuits (ASICs).

5. The integrated circuit device according to claim 1, wherein, The third device layer has a smaller minimum transistor spacing than the second device layer.

6. The integrated circuit device according to claim 1, wherein, The maximum operating voltage of the third device layer is 2.8V or lower, and the maximum operating voltage of the second device layer is 10V or higher.

7. The integrated circuit device according to claim 1, wherein, Each single-photon avalanche diode in the first device layer is electrically connected to a corresponding cutoff and recharge circuit in the second device layer via an independent junction between the first device layer and the second device layer.

8. The integrated circuit device according to claim 1, wherein, Each of the in-pixel circuits includes a comparator configured to receive an avalanche current from a corresponding single-photon avalanche diode in the first device layer. The comparator circuit is configured to generate a digitized signal in response to the avalanche current, wherein the voltage of the digitized signal is lower than the avalanche current and is provided to the third device layer.

9. A method for manufacturing an integrated circuit device, comprising: A first device layer is formed, comprising a first semiconductor substrate, the first device layer comprising an array of single-photon avalanche diodes; A second device layer is formed, including a second semiconductor substrate, the second device including: in-pixel circuitry corresponding to the single-photon avalanche diode, including cut-off and recharge circuitry configured to cut off avalanche events in the single-photon avalanche diode; Row and column connectors; and through-substrate vias corresponding to the row and column connectors; bonding the first device layer to the second device layer such that each single-photon avalanche diode in the first device layer is electrically connected to a corresponding in-pixel circuit in the second device layer through an independent bonding between the first device layer and the second device layer; forming a third device layer including a third semiconductor substrate, the third device layer including row driver circuitry and column readout circuitry; and bonding the third device layer to the second device layer such that the row and column connectors in the second device layer are electrically coupled to the row driver circuitry and the column readout circuitry of the third device layer via the through-substrate vias.

10. A method for manufacturing an integrated circuit device, comprising: Processing a first semiconductor substrate, wherein the processing includes a first front-end fabrication process for forming an array of single-photon avalanche diodes; Processing a second semiconductor substrate, wherein processing the second semiconductor substrate includes a second front-end process and a back-end process, the second front-end process forming an in-pixel circuit array including cutoff and recharge circuits, and the back-end process forming a row bus and a column bus of the in-pixel circuit array; Processing a third semiconductor substrate, wherein processing the third semiconductor substrate includes a third front-end process for forming row driver circuitry and column readout circuitry; bonding a second semiconductor substrate to a first semiconductor substrate, wherein the bonding forms a pixel-level electrical connection between the array of single-photon avalanche diodes and the array of in-pixel circuitry. And bonding the second semiconductor substrate to the third semiconductor substrate, wherein the bonding of the second semiconductor substrate to the third semiconductor substrate forms an electrical connection between the row driver circuit and the row bus and between the column readout circuit and the column bus.

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