Radiation-resistant ultrafast response silicon detector and preparation method thereof
By forming a nested diamond-shaped hole structure on a silicon substrate, the performance degradation problem of traditional detectors in strong radiation environments has been solved, achieving high reliability and fast response detection effects, which are suitable for nuclear energy facilities and space exploration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EAST CHINA UNIV OF TECH
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional semiconductor detectors degrade rapidly under strong radiation environments, leading to decreased carrier mobility and increased leakage current, which affects their long-term reliable application in fields such as nuclear energy facilities and space exploration.
Si3N4 passivation layers are grown on both the upper and lower sides of a silicon substrate using chemical vapor deposition. Nested diamond-shaped hole patterns are formed by spin-coating negative photoresist and exposure and development. Combined with etching, a three-dimensional hole structure is formed, and metal electrodes are deposited. This design is a radiation-resistant ultrafast response silicon detector.
It significantly improves the detector's radiation resistance in strong radiation environments, reduces the probability of electrode damage and carrier capture, maintains high reliability and fast response capability, and is suitable for high-energy physics experiments and space particle detection.
Smart Images
Figure CN121968778A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor nuclear radiation detection technology, and in particular to a radiation-resistant ultrafast response silicon detector and its fabrication method. Background Technology
[0002] Semiconductor nuclear radiation detectors are core devices in nuclear radiation detection technology and are widely used for particle detection and dose monitoring in extreme nuclear radiation environments. However, traditional semiconductor detectors (such as conventional silicon-based detectors) have significant defects in strong radiation environments: when exposed to high-energy particles or ionizing radiation, their internal lattice structure is prone to defects, leading to a decrease in carrier mobility and an increase in leakage current, which in turn causes rapid degradation or even complete failure of detector performance. This limitation seriously restricts the long-term reliable application of detectors in key areas such as nuclear energy facilities, space exploration, and nuclear emergency monitoring.
[0003] To improve the reliability and service life of detectors under high radiation conditions, radiation-resistant detection technology has become a research hotspot. Currently, research on radiation-resistant detectors both domestically and internationally mainly focuses on the following directions: fabricating detectors using wide-bandgap semiconductor materials such as silicon carbide and gallium oxide; developing detector devices based on lead-bromine-cesium single crystals; and promoting the evolution of silicon-based detectors from traditional planar structures to three-dimensional structures. In China, three-dimensional silicon-based radiation-resistant detectors are still in their initial stages due to their complex manufacturing process and reliance on dedicated microfabrication platforms. Therefore, designing a silicon detector that combines radiation resistance with ultrafast response capabilities and its efficient fabrication method has become a key technological path to solving the long-term reliable application of detectors under extreme nuclear radiation environments. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a radiation-resistant ultrafast response silicon detector and its fabrication method.
[0005] The technical problem solved by this invention is achieved by the following technical solution: An ultrafast response radiation-resistant silicon detector uses silicon as a substrate. Si3N4 passivation layers are grown on both the top and bottom sides of the silicon substrate using chemical vapor deposition. A negative photoresist layer is spin-coated onto the Si3N4 passivation layer on one side using a spin coater. The negative photoresist layer is then exposed and developed. The above steps are repeated on the other side. The diamond-shaped hole patterns formed after photolithography on both sides are nested together. The exposed Si3N4 passivation layer and photoresist are removed. The sample is then immersed in an etching solution and subjected to constant temperature and ultrasonic treatment to etch the silicon substrate, thereby forming a three-dimensional hole structure. The remaining Si3N4 passivation layer on the surface is then removed. Metal electrodes are deposited on the front and back sides of the sample, respectively. The specific steps are as follows: S1, prepare an intrinsic silicon wafer with a (110) crystal plane as a substrate, with a resistivity of 10-20 kΩ·cm and a thickness of 300-500 μm; S2, Si3N4 passivation layers are grown on both the top and bottom sides of a silicon substrate using chemical vapor deposition. S3. Spin-coat a negative photoresist layer onto the front-side Si3N4 passivation layer, bake it in a baking machine, and after cooling, remove it and place it in the exposure position of the photolithography machine. Select photomask A with a diamond-shaped hole pattern, and align the bottom edge of the diamond-shaped holes on photomask A with the silicon wafer. Crystal orientation or The crystal orientation is kept parallel before exposure, followed by intermediate baking and development with a developer. After development, the developer is rinsed off, and the image is dried to form a photomask image. The sample is then placed face up on a spin coater, and a layer of negative photoresist is spin-coated. It is then baked in a baking oven, cooled, and placed in the exposure position of the photolithography machine, ensuring the bottom edge of the diamond-shaped hole pattern on photomask B aligns with the silicon wafer. Crystal orientation or The crystal orientation remains parallel, and then exposure is performed. The diamond-shaped hole patterns formed after photolithography on both sides are nested together. S4, the exposed portion of the Si3N4 passivation layer on the photolithographic mask image is removed using BOE solution; S5, the photoresist layer is removed using a photoresist remover; S6. The sample is immersed in an etching solution and subjected to constant temperature and ultrasonic treatment to etch the silicon substrate to form a three-dimensional porous structure. S7, the remaining Si3N4 passivation layer on the surface is removed using BOE solution; S8 utilizes thermal resistance evaporation deposition to deposit Au metal electrodes on the front side and Al metal electrodes on the back side of a three-dimensional rhombic hole structure.
[0006] Furthermore, the etching solution in S6 is a 50% KOH solution, the constant temperature range is 60-80℃, and the ultrasonic time is 3-6h.
[0007] Furthermore, in the three-dimensional perforated structure, the outer base length a of the front rhombus is 1-2 mm, the inner base length b is 500 μm, the base length c of the back rhombus is 100-490 μm, the adjacent side angles of the front and back rhombuses are 70.53° and 109.47° respectively, the perforation depth is 150-250 μm, and the perforation wall width d is 10-100 μm.
[0008] The present invention also provides a radiation-resistant ultrafast response silicon detector, which is prepared by the above-described preparation method. Beneficial effects
[0009] This invention solves the problem of severe performance degradation of traditional silicon-based detectors under high radiation environments through breakthroughs in both structural design and process optimization. Specifically, this technical solution fully utilizes the advantages of silicon materials, such as high process maturity, low cost, and strong compatibility. Combined with an innovative three-dimensional electrode design, by increasing the contact area between Schottky and Ohmic contacts and the substrate sides, it not only significantly reduces the probability of complete electrode damage in a radiation environment but also effectively shortens the charge collection path, reducing the possibility of charge carriers being trapped by defects before reaching the electrodes, thereby greatly reducing the impact of radiation damage on signal transmission. Compared with solutions relying on wide-bandgap semiconductors or special single-crystal materials, this invention, through a nested rhombic hole structure design, achieves a significant improvement in radiation resistance while maintaining the inherent advantages of silicon-based materials. It provides a highly reliable, low-performance degradation solution for extreme environments such as nuclear energy facilities and space exploration, making the detector's performance degradation under the same radiation fluence far less severe than that of conventional silicon-based detectors.
[0010] The silicon detector prepared by this invention exhibits excellent radiation resistance, withstanding a flux range of up to 1 MeV electron irradiation. It can maintain stable operating characteristics in high-energy electron irradiation environments and effectively resist performance degradation caused by radiation damage. At the same time, the detector has excellent response speed, achieving picosecond-level time resolution, enabling it to quickly capture and respond to radiation signals. It is suitable for applications with high time resolution requirements, such as high-energy physics experiments or space particle detection. This combination of radiation resistance and high-speed response allows it to maintain high-efficiency detection performance even under extreme irradiation conditions. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of the silicon substrate in a preferred embodiment of the present invention; Figure 2 This is a schematic diagram of the structure after double-sided deposition of Si3N4 passivation layers on a silicon substrate in a preferred embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after spin-coating a negative photoresist layer on the front side in a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after frontal exposure in a preferred embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after spin-coating a negative photoresist layer on the reverse side in a preferred embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after reverse exposure in a preferred embodiment of the present invention; Figure 7This is a schematic diagram of the structure of the Si3N4 passivation layer with the exposed portion etched away in a preferred embodiment of the present invention, wherein: (a) is the reverse side pattern of the sample; (b) is the front side pattern of the sample; and (c) is a cross-sectional view of the sample. Figure 8 This is a schematic diagram of the structure after removing the negative photoresist layers on both sides in a preferred embodiment of the present invention; wherein: (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is a cross-sectional view of the sample; Figure 9 This is a schematic diagram of the structure of the three-dimensional rhomboid hole in a preferred embodiment of the present invention; wherein: (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is a cross-sectional view of the sample; Figure 10 This is a schematic diagram of the structure after the remaining Si3N4 passivation layer has been etched away in a preferred embodiment of the present invention; wherein: (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is a cross-sectional view of the sample; Figure 11 This is a schematic diagram of the structure of the metal-plated electrodes on the front and back sides in a preferred embodiment of the present invention; wherein: (a) is the pattern on the back side of the sample, (b) is the pattern on the front side of the sample, and (c) is a cross-sectional view of the sample; Figure 12 This is a structural schematic diagram of the three-dimensional rhomboid hole with dimensions, representing a preferred embodiment of the present invention, used to illustrate the three-dimensional hole structure inside the detector. Detailed Implementation
[0012] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations. Example 1
[0013] A radiation-resistant ultrafast response silicon detector and its fabrication method are disclosed. The specific steps are as follows: S1, as Figure 1 As shown, firstly, an intrinsic silicon wafer with a (110) crystal plane is prepared as substrate 1, with a resistivity of 20 kΩ·cm and a thickness of 300 μm.
[0014] S2, as Figure 2 As shown, a 500 nm Si3N4 passivation layer 2 is grown on both the upper and lower sides of a silicon substrate 1 using chemical vapor deposition.
[0015] S3, as Figure 3As shown, a 1.5 μm thick NR9-3000P negative photoresist layer 3 was spin-coated onto the front-side Si3N4 passivation layer 2 using a spin coater. The sample material coated with the negative photoresist layer 3 was then placed in an oven and baked at 100°C for 100 seconds. After cooling, it was removed and placed in the exposure position of a photolithography machine. A photomask A with a diamond-shaped hole pattern was selected, and the sample was exposed under vacuum for 12 seconds to expose part of the Si3N4 passivation layer 2. After intermediate baking, the sample was developed with NMD-3 developer, the developer was rinsed off, and then dried with nitrogen gas before final baking. The resulting sample pattern is shown in the figure. Figure 4 .
[0016] like Figure 5 As shown, the sample is placed face up on a spin coater. A 1.50 μm thick NR9-3000P negative photoresist layer 3 is spin-coated onto the reverse Si3N4 passivation layer 2. The sample material coated with the negative photoresist layer 3 is then placed in an oven for baking. After cooling, it is removed and placed in the exposure position of a photolithography machine. Photolithography plate B with a diamond-shaped hole pattern is selected, and the sample is exposed for 12 seconds under vacuum to expose part of the Si3N4 passivation layer 2. After intermediate baking, the sample is developed with NMD-3 developer, the developer is washed off, and then the sample is dried with nitrogen and baked again to form the sample as shown in the image. Figure 6 The sample image shown.
[0017] S4, such as Figure 7 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is the cross-sectional view of the sample. The exposed part of the Si3N4 passivation layer 2 on the obtained sample photolithography mask image is removed with BOE solution. The sample is placed in BOE solution and sonicated for 2 min, and then sonicated in an ultrasonic machine with deionized water for 3 min before being taken out.
[0018] S5, such as Figure 8 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is the cross-sectional view of the sample. The material containing the negative photoresist layer 3 on the sample surface is removed by using a photoresist remover solution in a water bath at 60°C for 4 minutes.
[0019] S6, such as Figure 9 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is a cross-sectional view of the sample. The sample was immersed in a 50% KOH solution at a constant temperature of 60°C and then bathed in a water bath at 60°C for 4 hours to etch the silicon substrate 1, thereby forming a three-dimensional rhombic hole structure. The etching structure parameters are as follows: Figure 12 As shown, the outer base length a of the front rhombus is 2mm, the inner base length b is 500μm, the base length c of the back rhombus is 400μm, the adjacent side angles of the front and back rhombuses are 70.53° and 109.47° respectively, the hole depth is 150μm, and the hole wall width d is 100μm.
[0020] S7, such as Figure 10 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is the cross-sectional view of the sample. The remaining Si3N4 passivation layer 2 on the obtained sample was removed with BOE solution. The sample was placed in BOE solution and sonicated for 2 min, and then sonicated in an ultrasonic machine with deionized water for 3 min before being taken out.
[0021] S8, such as Figure 11 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is the cross-sectional view of the sample. Au metal was deposited on the front side of the three-dimensional rhombic hole structure as Schottky electrode 4 using thermal resistance evaporation coating method. The thickness of Au was 100 nm. Al metal was deposited on the back side of Si substrate layer 1 as ohmic contact electrode 5 using thermal resistance evaporation coating method. The thickness of Al was 100 nm. Example 2
[0022] S1, as Figure 1 As shown, firstly, an intrinsic silicon wafer with a (110) crystal plane is prepared as substrate 1, with a resistivity of 20 kΩ·cm and a thickness of 300 μm.
[0023] S2, as Figure 2 As shown, a 500 nm Si3N4 passivation layer 2 is grown on both the upper and lower sides of a silicon substrate 1 using chemical vapor deposition.
[0024] S3, as Figure 3 As shown, a 1.5 μm thick NR9-3000P negative photoresist layer 3 was spin-coated onto the front-side Si3N4 passivation layer 2 using a spin coater. The sample material coated with the negative photoresist layer 3 was then placed in an oven and baked at 100℃ for 120 seconds. After cooling, it was removed and placed in the exposure position of a photolithography machine. A photomask A with a diamond-shaped hole pattern was selected, and the sample was exposed under vacuum for 12 seconds to expose part of the Si3N4 passivation layer 2. After intermediate baking, the sample was developed with NMD-3 developer, the developer was rinsed off, and then dried with nitrogen gas before final baking. The resulting sample pattern is shown in the figure. Figure 4 .
[0025] like Figure 5 As shown, the sample is placed face up on a spin coater. A 1.50 μm thick NR9-3000P negative photoresist layer 3 is spin-coated onto the reverse Si3N4 passivation layer 2. The sample material coated with the negative photoresist layer 3 is then placed in an oven for baking. After cooling, it is removed and placed in the exposure position of a photolithography machine. A photomask B with a diamond-shaped hole pattern is selected, and the sample is exposed for 12 seconds under vacuum to expose part of the Si3N4 passivation layer 2. After intermediate baking, the sample is developed with NMD-3 developer. The developer is then rinsed off, and the sample is dried with nitrogen gas and then baked again to form the sample as shown in the image. Figure 6 The sample image shown.
[0026] S4, such as Figure 7 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is the cross-sectional view of the sample. The exposed part of the Si3N4 passivation layer 2 on the obtained sample photolithography mask image is removed with BOE solution. The sample is placed in BOE solution and sonicated for 2 min, and then sonicated in an ultrasonic machine with deionized water for 3 min before being taken out.
[0027] S5, such as Figure 8 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is the cross-sectional view of the sample. The material containing the negative photoresist layer 3 on the sample surface is removed by using a photoresist remover solution in a water bath at 60°C for 4 minutes.
[0028] S6, such as Figure 9 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is a cross-sectional view of the sample. The sample was immersed in a 50% KOH solution at a constant temperature of 60°C in a water bath to etch the silicon substrate 1, thereby forming a three-dimensional rhombic hole structure. The etching parameters are as follows: Figure 12 As shown, the outer base length a of the front rhombus is 1 mm, the inner base length b is 500 μm, the base length c of the back rhombus is 490 μm, the adjacent side angles of the front and back rhombuses are 70.53° and 109.47° respectively, the hole depth is 240 μm, and the hole wall width d is 10 μm.
[0029] S7, such as Figure 10 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is the cross-sectional view of the sample. The remaining Si3N4 passivation layer 2 on the obtained sample was removed with BOE solution. The sample was placed in BOE solution and sonicated for 2 min, and then sonicated in an ultrasonic machine with deionized water for 3 min before being taken out.
[0030] S8, such as Figure 11 As shown, (a) is the reverse side pattern of the sample, (b) is the front side pattern of the sample, and (c) is the cross-sectional view of the sample. Au metal was deposited on the front side of the three-dimensional rhombic hole structure as Schottky electrode 4 using thermal resistance evaporation coating method. The thickness of Au was 100 nm. Al metal was deposited on the back side of Si substrate layer 1 as ohmic contact electrode 5 using thermal resistance evaporation coating method. The thickness of Al was 100 nm.
Claims
1. A radiation-resistant, ultrafast-response silicon detector, characterized in that, Using silicon as the substrate, Si3N4 passivation layers are grown on both the top and bottom sides of the silicon substrate using chemical vapor deposition. A negative photoresist layer is spin-coated onto the Si3N4 passivation layer on one side using a spin coater. The negative photoresist layer is then exposed and developed. The above steps are repeated on the other side. The diamond-shaped hole patterns formed after photolithography on both sides are nested together. After removing the exposed Si3N4 passivation layer and the photoresist, the sample is immersed in an etching solution and subjected to constant temperature and ultrasonic treatment to etch the silicon substrate, thereby forming a three-dimensional hole structure. The remaining Si3N4 passivation layer on the surface is then removed, and metal electrodes are deposited on the front and back sides of the sample respectively. The specific steps are as follows: S1, prepare an intrinsic silicon wafer with a (110) crystal plane as a substrate, with a resistivity of 10-20 kΩ·cm and a thickness of 300-500 μm; S2, Si3N4 passivation layers are grown on both the top and bottom sides of a silicon substrate using chemical vapor deposition. S3. Spin-coat a negative photoresist layer onto the front-side Si3N4 passivation layer, bake it in a baking machine, and after cooling, remove it and place it in the exposure position of the photolithography machine. Select photomask A with a diamond-shaped hole pattern, and align the bottom edge of the diamond-shaped holes on photomask A with the silicon wafer. Crystal orientation or The crystal orientation is kept parallel before exposure, followed by intermediate baking and development with a developer. After development, the developer is rinsed off, and the image is dried to form a photomask image. The sample is then placed face up on a spin coater, and a layer of negative photoresist is spin-coated. It is then baked in a baking oven, cooled, and placed in the exposure position of the photolithography machine, ensuring the bottom edge of the diamond-shaped hole pattern on photomask B aligns with the silicon wafer. Crystal orientation or The crystal orientation remains parallel, and then exposure is performed. The diamond-shaped hole patterns formed after photolithography on both sides are nested together. S4, the exposed portion of the Si3N4 passivation layer on the photolithographic mask image is removed using BOE solution; S5, the photoresist layer is removed using a photoresist remover; S6. The sample is immersed in an etching solution and subjected to constant temperature and ultrasonic treatment to etch the silicon substrate to form a three-dimensional porous structure. S7, the remaining Si3N4 passivation layer on the surface is removed using BOE solution; S8 utilizes thermal resistance evaporation deposition to deposit Au metal electrodes on the front side and Al metal electrodes on the back side of a three-dimensional rhombic hole structure.
2. The radiation-resistant ultrafast response silicon detector according to claim 1, characterized in that, The etching solution in S6 is a 50% KOH solution, the constant temperature range is 60-80℃, and the ultrasonic time is 3-6h.
3. The radiation-resistant ultrafast response silicon detector according to claim 1, characterized in that, In the three-dimensional hole structure, the outer base length a of the front rhombus is 1-2 mm, the inner base length b is 500 μm, the base length c of the back rhombus is 100-490 μm, the adjacent side angles of the front and back rhombuses are 70.53° and 109.47° respectively, the hole depth is 150-250 μm, and the hole wall width d is 10-100 μm.
4. A radiation-resistant ultrafast response silicon detector, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 3.