Display device

Abstract

Disclosed is a display device including: a display panel including a display area provided with pixels and a non-display area provided around the display area; and at least one gate driver configured to apply a scan signal and a light emission signal to the pixels. The compensation capacitor is short-circuited during the light emission period, but is applied with a DC voltage during at least one other driving period.

Description

Display device

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0152994, filed on October 31, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure aims to improve the flicker performance and reliability of display panels. Background Technology

[0004] Based on the material of the emitting layer, electroluminescent displays are classified into inorganic electroluminescent displays and organic electroluminescent displays. Active-matrix organic light-emitting diode (OLED) displays include OLEDs (organic light-emitting diodes) capable of emitting light themselves, and possess many advantages, including fast response time, high emission efficiency, high brightness, and wide viewing angle. In an organic electroluminescent display, an OLED is formed in each of the pixels. Organic electroluminescent display devices not only possess fast response time, high emission efficiency, high brightness, and wide viewing angle, but also exhibit excellent contrast and color reproduction due to their ability to represent the black scale with full black.

[0005] The pixels of an organic electroluminescent display device include: a driving element for driving an OLED; and a pixel circuit including a capacitor connected to the driving element.

[0006] Due to process variations and device characteristic variations during manufacturing, differences in the electrical characteristics of driving elements across pixels may exist. These differences can increase further over time. To compensate for these differences in the electrical characteristics of the driving elements within a pixel, an internal compensation circuit can be added to the pixel circuitry. This internal compensation circuit samples the threshold voltage of the driving element and compensates for the gate voltage of the driving element by an amount equal to the threshold voltage. However, when a pixel driven by the internal compensation circuit is operated at low brightness, it may cause uneven brightness within the display panel screen. Summary of the Invention

[0007] Technical issues

[0008] The purpose of this disclosure is to use an internal compensation circuit to compensate the threshold voltage of the driving element in real time and improve the uniformity of screen brightness.

[0009] Technical solution

[0010] One embodiment is a display device comprising: a display panel including a display area and a non-display area surrounding the display area, the display area including pixels; a data driver configured to apply a data voltage to the pixels; and at least one gate driver configured to apply a scan signal and a light emission signal to the pixels.

[0011] At least one of the pixels may include: a light-emitting diode (LED) including an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode; a driving transistor having a first electrode connected to a third node, a gate electrode connected to a second node, and a second electrode connected to the first node; a switching transistor having a first electrode connected to a data line and a second electrode connected to the gate electrode of the driving transistor at the second node, the switching transistor having a gate electrode for receiving a first scan signal; a first initialization transistor having a first electrode connected to a reference voltage line and a second electrode connected to the second electrode of the switching transistor and the gate electrode of the driving transistor at the second node, the first initialization transistor having a gate electrode for receiving a second scan signal; and a first light-emitting transistor having a first electrode connected to a high-potential driving voltage line and a second electrode connected to the first electrode of the driving transistor at the third node, the first... A light-emitting transistor (LED) has a gate electrode for receiving a first light-emitting signal; a second LED has a first electrode connected to a second electrode of a driving transistor at a first node and a second electrode connected to an anode electrode of a light-emitting diode at a fourth node, the second LED having a gate electrode for receiving a second light-emitting signal; a first capacitor has a first electrode connected to a second electrode of a switching transistor, a second electrode of a first initialization transistor, and a gate electrode of a driving transistor at a second node, and a second electrode connected to a second electrode of the driving transistor and a first electrode of the LED at a first node; and a second capacitor has a second electrode connected to a second electrode of the first capacitor, a second electrode of the driving transistor, and a first electrode of the LED at a first node, and a second electrode connected to a second electrode of the LED and an anode electrode of the LED at a fourth node, wherein the driving transistor includes an oxide semiconductor layer.

[0012] In one embodiment, a pixel of a display device includes: a light-emitting diode (LED) including an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode; a driving transistor having a first electrode connected to a third node, a gate electrode connected to a second node, and a second electrode connected to the first node; a switching transistor having a first electrode connected to a data line and a second electrode connected to the gate electrode of the driving transistor at the second node, the switching transistor having a gate electrode for receiving a first scan signal; a light-emitting transistor having a first electrode connected to the second electrode of the driving transistor at the first node and a second electrode connected to the anode electrode of the LED at a fourth node, the light-emitting transistor having a gate electrode for receiving a light-emitting signal; and a first capacitor. The device comprises a first electrode having a second electrode connected at a second node to a second electrode of a switching transistor and a gate electrode of a driving transistor, and a second electrode connected at a first node to a second electrode of a driving transistor and a first electrode of a light-emitting transistor; and a second capacitor having a second electrode connected at a first node to a second electrode of a first capacitor, a second electrode of a driving transistor, and a first electrode of a light-emitting transistor, and a second electrode connected at a fourth node to a second electrode of a light-emitting transistor and an anode electrode of a light-emitting diode, wherein a pixel is driven during a plurality of time periods including a light-emitting period, during a light-emitting period, when the light-emitting transistor is turned on during the light-emitting period, the first electrode and the second electrode of the second capacitor are short-circuited, and during at least another time period of the plurality of time periods, when the light-emitting transistor is turned off, a DC voltage is applied to the second electrode of the second capacitor.

[0013] The technical problems to be solved by this disclosure are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which this disclosure pertains based on the following description.

[0014] Beneficial effects

[0015] The display device according to embodiments of this disclosure can accurately compensate for the threshold voltage of the driving element and improve the brightness uniformity of the entire screen when operating the pixels of the display panel at high speed. This is because the sensing step of sensing the threshold voltage of the driving element and the writing step of writing pixel data to the pixel are separated in time, so that the threshold voltage sensing time can be sufficiently ensured. Such a method can prevent error components from being introduced at the main node of the pixel circuit by separating the capacitor storing the threshold voltage of the driving element from the capacitor storing the data voltage.

[0016] In addition, by setting an anode reset voltage in addition to the reference voltage, the brightness difference between pixels can be minimized or at least reduced when the driving frequency of the pixel changes with the refresh rate. Furthermore, it can improve the flickering phenomenon when applying a variable driving frequency while using a smaller number of gate lines, thereby improving image quality.

[0017] The effects of this disclosure are not limited to those described above, and other effects not described herein can be derived by those skilled in the art from the following description of embodiments of this disclosure. Attached Figure Description

[0018] Figure 1 is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0019] Figure 2 is a cross-sectional view showing the laminated shape of a display device according to an embodiment of the present disclosure.

[0020] Figure 3 is a view showing the configuration of the gate driver in a display device according to an embodiment of the present disclosure.

[0021] Figure 4 is a view showing the pixel circuitry in a display device according to an embodiment of the present disclosure.

[0022] Figure 5 is an operation timing diagram of the pixel circuit in the display device shown in Figure 4 according to an embodiment of the present disclosure.

[0023] Figures 6A to 6E are diagrams illustrating in more detail the operation of the pixel circuit according to an embodiment of the present disclosure during each operating period.

[0024] Figures 7A and 7B are respectively a diagram of a pixel circuit in a display device according to another embodiment of the present disclosure and an operation timing diagram of the pixel circuit in the display device. Detailed Implementation

[0025] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become more apparent from the embodiments described in detail with reference to the accompanying drawings. However, this disclosure is not limited to the disclosed embodiments, but can be implemented in a variety of different ways. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. This disclosure will be defined only by the scope of the appended claims. Throughout the specification, similar reference numerals generally denote similar elements.

[0026] It should be understood that when an element is referred to as “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediate elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0027] The terminology used in this specification is for describing particular embodiments only and is not intended to limit the scope of this disclosure. Singular expressions include plural expressions unless the context clearly indicates the contrary. When used herein, the terms “comprising” and / or “including” specify the presence of stated elements, steps, operations, and / or components, but do not exclude the presence or addition of one or more other elements, steps, operations, and / or components.

[0028] While terms including ordinal numbers such as first, second, etc., can be used to describe various elements, structural elements are not limited by terms. Terms are only used to distinguish one element from another.

[0029] Therefore, in the technical conception of this disclosure, the first component referred to below may be the second component. Unless otherwise specified, all terms used herein, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in common dictionaries should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0030] Figure 1 is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0031] Referring to FIG1, the display device 1 includes a timing controller 10, a level shifter 11, a gate driver 20, a data driver 30, a power supply unit 40 (e.g., circuitry), and a display panel 50.

[0032] The timing controller 10 can receive video signals RGB and control signals CS from an external host system, etc. The video signal RGB may include multiple grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0033] The timing controller 10 processes the video signal RGB and the control signal CS to suit the operating conditions of the display panel 50, and can generate and output image data DATA, gate drive control signal CONT1, light emission drive control signal CONT2, data drive control signal CONT3 and power supply control signal CONT4.

[0034] The level shifter 11 can output start signals, clock signals (e.g., gate clock signals), etc. to the gate driver 20 based on the gate drive control signal CONT1 and the light emission drive control signal CONT2 input from the timing controller 10.

[0035] The gate driver 20 may include a scan drive circuit 20A configured to generate a scan signal based on a gate high voltage VGH and / or a gate low voltage VGL and a signal output from the level shifter 11. The scan drive circuit 20A can provide the generated scan signal to the pixel PX via multiple scan lines GL. In one embodiment, a pixel PX can be configured to receive multiple scan signals with different waveforms. In such an embodiment, the scan drive circuit 20A can provide multiple scan signals to the pixel PX respectively via scan lines GL corresponding to the multiple scan signals.

[0036] The gate driver 20 may further include a light-emitting driving circuit 20B configured to generate a light-emitting signal based on a signal output from the level shifter 11. The light-emitting driving circuit 20B can provide the generated light-emitting signal to the pixel PX via the light-emitting line EL.

[0037] The gate driver 20 can be configured as an in-panel gate, in which the gate driver 20 is mounted on the display panel 50. The gate driver 20 can be disposed on one side or both sides of the display panel 50 (e.g., left and right), as shown. Depending on the driving method, panel design, etc., the gate driver 20 can be disposed on both sides of the display panel 50 (e.g., left and right), or it can be connected to two or more of the four side surfaces of the display panel 50.

[0038] The data driver 30 can generate a data signal based on the data drive control signal CONT3 output from the timing controller 10 and the image data DATA. The data driver 30 can provide the generated data signal to the pixel PX through multiple data lines DL.

[0039] The data driver 30 may be configured with one or more integrated circuits (ICs) disposed on one side of the display panel 50. An array of demultiplexers (not shown) may also be included in the embodiment, disposed between the data driver 30 and the data line DL.

[0040] The demultiplexer array sequentially supplies data voltages output from the channels of the data driver 30 to the data line DL using multiple demultiplexers (DEMUX). The demultiplexers may include multiple transistors disposed on the display panel 50. When the demultiplexers are positioned between the output terminals of the data driver 30 and the data line DL, the number of channels of the data driver 30 can be reduced. The demultiplexer array can be omitted.

[0041] The timing controller 10 and the data driver 30 can be integrated into an integrated circuit in a mobile device or wearable device.

[0042] The power supply unit 40 can generate a high-potential driving voltage ELVDD and a low-potential driving voltage ELVSS, which is lower than the high-potential driving voltage ELVDD, to be supplied to the display panel 50 based on the power supply control signal CONT4. The power supply unit 40 can supply the generated driving voltages ELVDD and ELVSS to the pixel PX through the corresponding high-potential driving voltage line PL1 and low-potential driving voltage line PL2. In addition, the power supply unit 40 can also generate the reference voltage Vref and / or bias voltage VAR required to drive the pixel PX, and can supply the voltage to the pixel PX through the corresponding voltage lines VrefL and VARL, respectively.

[0043] On the display panel 50, a plurality of pixels PX (or subpixels) are arranged. Pixels PX may be arranged on the display panel 50, for example, in a matrix. Pixels arranged in a pixel row are connected to the same scan line GL and the same light emission line EL, and pixels arranged in a pixel column are connected to the same data line DL. Pixels PX can emit light at a brightness corresponding to the scan signal and data signal supplied through the scan line GL and the data line DL in response to a light emission signal applied through the light emission line EL.

[0044] Additionally, each of the pixels PX includes a light-emitting diode (LED) LD and pixel circuitry configured to control the operation of the LED LD. Here, the LED LD includes an anode electrode 171, a cathode electrode 173, and a light-emitting layer 172 between the anode electrode 171 and the cathode electrode 173. Each of the pixels PX includes pixel circuitry.

[0045] In one implementation, each pixel PX can display one of the colors red, green, and blue. In another implementation, each pixel PX can display one of the colors cyan, magenta, and yellow. In various implementations, each pixel PX can display one of the colors red, green, blue, and white.

[0046] Pixels can be set as real color pixels and pentile pixels. Pentile pixels can achieve a higher resolution than real color pixels by using a predefined pixel rendering algorithm to drive two sub-pixels—each of which has a different color—as a single pixel (PX). The pixel rendering algorithm can compensate for the lack of color representation in each pixel using the color of light emitted from neighboring pixels.

[0047] Display panel 50 can be implemented as a transmissive display panel or a non-transmissive display panel. A transmissive display panel can be applied to a transparent display device in which an image is displayed on the screen, and a real background object outside the display panel 50 is visible. Display panel 50 can be manufactured as a flexible display panel. A flexible display panel can be implemented as an OLED panel using a plastic substrate.

[0048] A touch sensor can be mounted on the display panel 50. Touch input can be sensed using an additional touch sensor or by pixels (PX). The touch sensor can be mounted on the screen of the display panel as an external (on-cell type) or add-on type, or it can be implemented as an in-cell type touch sensor embedded in the display panel 50.

[0049] The display device 1 may also include a touch sensor driver (not shown) for driving the touch sensor. The data driver 30 and the touch sensor driver may be integrated into a single driver IC (integrated circuit), or each of the data driver 30 and the touch sensor driver may be configured separately.

[0050] In an implementation, one or more optical regions OA1 and OA2 may be provided on the display panel 50. One or more optical regions OA1 and OA2 may be provided by overlapping with one or more optical electronic devices, such as photographic devices such as camera devices (image sensors) and detection sensors such as proximity sensors and illuminance sensors.

[0051] For the operation of optoelectronic devices, one or more optical regions OA1 and OA2 have a light-transmitting structure and a certain level or higher transmittance. The light-transmitting structure can be configured by patterning the cathode electrode in the portion where no pixel PX is set. The cathode electrode can be patterned by using laser removal or by selectively forming the cathode electrode through a cathode deposition prevention layer.

[0052] Alternatively, the light-transmitting structure can be configured by separating the light-emitting diode (LED) from the interior of the pixel PX. In such an implementation, the LED of the pixel PX can be disposed in optical regions OA1 and OA2, multiple transistors configuring the pixel PX can be disposed around optical regions OA1 and OA2, and the LED and the pixel can be electrically connected through a transparent metal layer.

[0053] The number of pixels per unit area in one or more optical regions OA1 and OA2 can be less than the number of pixels per unit area in the remaining regions other than optical regions OA1 and OA2. In other words, the resolution of one or more optical regions OA1 and OA2 can be lower than the resolution of the remaining regions.

[0054] In embodiments, the display device 1 according to the present disclosure can operate in a variable refresh rate mode, in which the driving frequency can be varied. For example, the display device 1 can operate at a refresh rate higher or lower than a predetermined reference refresh rate. Driving the display device 1 at a refresh rate lower than the reference refresh rate can be referred to as "low-speed driving" (e.g., first mode), and driving the display device 1 at a refresh rate higher than the reference refresh rate can be referred to as "high-speed driving" (e.g., second mode). The refresh rate can be determined according to the type of image displayed, etc., but is not limited thereto.

[0055] The timing controller 10 can generate control signals CONT1 to CONT4, enabling the pixel PX to operate at various refresh rates. For example, the timing controller 10 can change the refresh rate by altering the frequency of the clock signal included in the control signals CONT1 to CONT4, adjusting the timing of the horizontal or vertical synchronization signal, or driving the gate driver 20 in a masked manner.

[0056] Figure 2 is a cross-sectional view showing the laminated shape of a display device according to an embodiment of the present disclosure.

[0057] Referring to FIG2, the display panel 50 may include a display area AA where the pixel PX is located, and a non-display area NA disposed around the display area AA and in which the gate driver 20 and the data driver 30 are disposed. The display panel 50 includes a substrate 101, thin film transistors TFT1 and TFT2, a dam layer 165, a light-emitting diode LD, an encapsulation layer 180, a touch layer 190, a touch protection layer 197, dams DAM1 and DAM2, and pad portions 198.

[0058] The substrate 101 supports various components of the display panel 50. The substrate 101 can be formed from a transparent insulating material such as glass or plastic. When the substrate 101 is formed of plastic, it can be referred to as a plastic film or plastic substrate. For example, the substrate 101 can be in film form, including one of polyimide polymers, polyester polymers, silicone polymers, acrylic polymers, polyolefin polymers, and copolymers thereof, but embodiments of this disclosure are not limited thereto. Furthermore, when the substrate 101 is made of plastic, it can be formed with a dual structure. For example, the substrate 101 can have a dual structure having an adhesive layer disposed between a first polyimide layer and a second polyimide layer.

[0059] When the substrate 101 is made of glass, the substrate 101 can be referred to as a glass substrate. For example, the glass substrate may include a shielding metal 102 beneath the thin-film transistors TFT1 and TFT2, and may be used to protect the devices from external light or signal interference. Therefore, the shielding metal 102 may overlap at least with, for example, the thin-film transistor TFT1, which is a driving transistor.

[0060] Thin-film transistors (TFTs) 1 and TFT2, used to drive light-emitting diodes (LDs), can be disposed on substrate 101 in display area AA. TFTs 1 and TFT2 drive the light-emitting diodes (LDs) in display area AA.

[0061] For ease of description, Figure 2 shows one thin-film transistor TFT1 (e.g., driving transistor DT, FIG. 7) and one thin-film transistor TFT2 (e.g., fourth transistor T4, FIG. 7) that may be included in the display device 1; however, thin-film transistors TFT1 and TFT2 are not limited thereto. In the following description, examples of thin-film transistors having a coplanar structure are described; however, thin-film transistors TFT1 and TFT2 can be implemented with different structures, such as interleaved structures, etc., and are not limited thereto.

[0062] The second thin-film transistor (TFT) 2 may include a semiconductor layer 116, a gate electrode 126, and source and drain electrodes 140. The semiconductor layer 116 may be constructed of polycrystalline silicon (p-Si), and in this case, predetermined regions may be doped with impurities. Alternatively, the semiconductor layer 116 may be constructed of amorphous silicon (a-Si) or various organic semiconductor materials such as pentacene. The semiconductor layer 116 may be constructed of an oxide. Embodiments of this disclosure are not limited to these when it comes to the materials used to construct the semiconductor layer 116. The semiconductor layer 116 may be an active layer, and the terminology is not limited thereto.

[0063] The gate electrode 126 may be disposed on the semiconductor layer 116. The gate electrode 126 may be formed of various conductive materials such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, but the embodiments of the present disclosure are not limited thereto.

[0064] A gate insulating layer 122 may be disposed between the semiconductor layer 116 and the gate electrode 126. The gate insulating layer 122 may be a layer for insulating the semiconductor layer 116 and the gate electrode 126 from each other, and may be formed of an insulating material. For example, the gate insulating layer 122 may be constructed as a single-structure layer or a multi-structure layer of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto.

[0065] The source electrode and drain electrode 140 can be electrically connected to the semiconductor layer 116, can be spaced apart from the semiconductor layer 116, and can be constructed of copper Cu, aluminum Al, molybdenum Mo, titanium Ti or alloys thereof, but are not limited thereto.

[0066] A buffer layer 105, a shielding metal 102, and a first insulating layer 110 may be disposed between the semiconductor layer 116 and the substrate 101. The buffer layer 105 can delay the dispersion of moisture and / or oxygen that permeates into the substrate 101. The first insulating layer 110 can protect the semiconductor layer 116 and block various types of defects introduced from the substrate 101. The shielding metal 102 may be disposed between the buffer layer 105 and the first insulating layer 110, such that the shielding metal 102 can protect the second thin-film transistor TFT2 from external light or signal interference.

[0067] The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be formed of a material having etching characteristics different from those of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be formed of one of silicon nitride (SiNx) and silicon oxide (SiOx). The remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be formed of another of silicon nitride (SiNx) and silicon oxide (SiOx). For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be formed of silicon nitride (SiNx), and the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be formed of silicon oxide (SiOx), but this is not a limitation.

[0068] The first thin-film transistor TFT1 may include a semiconductor layer 115, a gate electrode 125, and source and drain electrodes 140. A second insulating layer 120 (gate insulating layer) may be disposed between the semiconductor layer 115 and the gate electrode 125.

[0069] An interlayer insulating layer 128 can be disposed between the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0070] The first thin-film transistor TFT1 may include: a semiconductor layer 115 disposed on an interlayer insulating layer 128; a gate electrode 125 overlapping the semiconductor layer 115, wherein a second insulating layer 120 is disposed between the gate electrode 125 and the semiconductor layer 115; and a source electrode and a drain electrode 140 disposed on a third insulating layer 135 and in contact with the semiconductor layer 115.

[0071] Semiconductor layer 115 may be the region in which a channel is formed when the thin-film transistor TFT2 is driven. Semiconductor layer 115 may be formed of oxide semiconductor, and may be formed of various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or pentacene, but is not limited thereto. Semiconductor layer 115 may be formed on interlayer insulating layer 128. Semiconductor layer 115 may have a channel region, a source region, and a drain region. The channel region may be formed such that the channel region overlaps with the gate electrode 125, wherein a second insulating layer 120 is disposed between the channel region and the gate electrode 125 to form a channel region between the second insulating layer 120 and the source and drain regions. The source region may be electrically connected to the source electrode 140 through contact holes penetrating the second insulating layer 120 and the third insulating layer 135. The drain region may be electrically connected to the drain electrode 140 through contact holes penetrating the second insulating layer 120 and the third insulating layer 135.

[0072] The gate electrode 125 may be formed on the second insulating layer 120 and may overlap with the channel region of the semiconductor layer 115, wherein the second insulating layer 120 is disposed between the gate electrode 125 and the channel region of the semiconductor layer 115. The gate electrode 125 may be formed of a first conductive material that is a single-layer or multi-layer structure, wherein the first conductive material is formed of one of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof, but is not limited thereto.

[0073] The source electrode 140 may contact the source region of the semiconductor layer 115 exposed through contact holes penetrating the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may face the source electrode 140 and may contact the drain region of the semiconductor layer 115 exposed through contact holes penetrating the second insulating layer 120 and the third insulating layer 135. The source electrode and drain electrode 140 may be formed of a second conductive material that is a single or multiple structural layers, wherein the second conductive material is formed of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more of the above, but is not limited thereto.

[0074] Capacitors C1 and C2 can also be disposed on the substrate 101. Capacitors C1 and C2 can be configured to include a first electrode 143, a second electrode 144, and a third electrode 142.

[0075] At least one insulating layer may be provided between the first electrode 143 and the second electrode 144, and at least one insulating layer may be provided between the second electrode 144 and the third electrode 142. At least one of the first electrode 143, the second electrode 144 and the third electrode 142 may be connected to the source electrode 140 or the drain electrode 140 of the thin-film transistors TFT1 and TFT2.

[0076] The first capacitor C1 includes a first electrode 143 and a second electrode 144 disposed on the same layer as the shielding metal 102. The second capacitor C2 includes a second electrode 144 and a third electrode 142, wherein the third electrode 142 is disposed on the same layer as the gate electrode 125 of the thin-film transistor TFT1.

[0077] A connection electrode 155 may be disposed between the first intermediate layer 150 and the second intermediate layer 160. The connection electrode 155 may be exposed to the drain electrode 140 by means of contact holes penetrating the protective layer 145 and the first intermediate layer 150. The connection electrode 155 may be formed of a material with low resistivity that is the same as or similar to that of the drain electrode 140, but is not limited thereto.

[0078] A light-emitting diode (LD) including a light-emitting layer 172 can be disposed on a second intermediate layer 160 and a dam layer 165. The LD may include an anode electrode 171, at least one light-emitting layer 172 disposed on the anode electrode 171, and a cathode electrode 173 formed on the light-emitting layer 172.

[0079] The anode electrode 171 can be electrically connected to the connection electrode 155 disposed on the first intermediate layer 150 through a contact hole that penetrates the second intermediate layer 160 and is exposed toward the upper side of the second intermediate layer 160.

[0080] The anode electrode 171 of each pixel is formed to be exposed through the dam layer 165. The dam layer 165 may be formed of an opaque material (e.g., black) to prevent optical interference between adjacent pixels. In this case, the dam layer 165 may include, but is not limited to, a light-shielding material formed of at least one of colored pigments, organic black, and carbon.

[0081] At least one light-emitting layer 172 may be formed on the anode electrode 171 in the light-emitting region provided by the dam layer 165. The at least one light-emitting layer 172 may include a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer 172, an electron injection layer, an electron blocking layer, and an electron transport layer on the anode electrode 171, and may be formed by laminating the aforementioned layers in a continuous or reverse order according to the light emission direction. Additionally, the light-emitting layer 172 may include a first light-emitting stack and a second light-emitting stack facing each other, wherein an electron-generating layer is disposed between the first and second light-emitting stacks. In this case, the light-emitting layer 172 of one of the first and second light-emitting stacks generates blue light, and the light-emitting layer 172 of the other generates yellow-green light, thereby generating white light through the first and second light-emitting stacks. The white light generated by the light-emitting stacks enters a color filter located above or below the light-emitting layer 172, thereby enabling a color image. As another example, without a separate color filter, each light-emitting layer 172 can enable a color image by generating color light corresponding to each pixel. For example, the light-emitting layer 172 of the red pixel can generate red light, the light-emitting layer 172 of the green pixel can generate green light, and the light-emitting layer 172 of the blue pixel can generate blue light.

[0082] The cathode electrode 173 can be formed facing the anode electrode 171, wherein the light-emitting layer 172 is disposed between the cathode electrode 173 and the anode electrode 171. The cathode electrode 173 can receive a low-potential driving voltage ELVSS.

[0083] Encapsulation layer 180 can prevent oxygen or external moisture from penetrating a light-emitting diode (LD) susceptible to oxygen or external moisture. For this purpose, encapsulation layer 180 may have at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In the following description, a structure of encapsulation layer 180 in which a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 are sequentially laminated is used as an example.

[0084] A first encapsulation layer 181 is formed on a substrate 101 on which a cathode electrode 173 is formed. A third encapsulation layer 183 is formed on a substrate 101 on which a second encapsulation layer 182 is formed, and may be formed to surround the upper surface, lower surface, and side surface of the second encapsulation layer 182 together with the first encapsulation layer 181. The first encapsulation layer 181 and the third encapsulation layer 183 can minimize or prevent oxygen or external moisture from penetrating the light-emitting diode (LD). The first encapsulation layer 181 and the third encapsulation layer 183 may be formed of an inorganic insulating material suitable for low-temperature lamination, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). The first encapsulation layer 181 and the third encapsulation layer 183 are laminated in a low-temperature atmosphere, and thus the light-emitting diode (LD), which is susceptible to damage in high-temperature atmospheres, can be prevented from being damaged during the lamination process.

[0085] The second encapsulation layer 182 acts as a buffer, reducing the tension between layers caused by the bending of the display device 1 (FIG. 1) and flattening the stepped portions between layers. On the substrate 101 on which the first encapsulation layer 181 is formed, the second encapsulation layer 182 can be formed of non-photosensitive organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, and polyethylene or silicon-oxygen-carbon (SiOC), or photosensitive organic insulating materials such as photoacrylic acid, but is not limited thereto. When the second encapsulation layer 182 is formed by inkjet printing, dams DAM1 and DAM2 can be provided to prevent the liquid form of the second encapsulation layer 182 from spreading to the edges of the substrate 101. Dams DAM1 and DAM2 can be positioned closer to the edges of the substrate 101 than the second encapsulation layer 182. Dams DAM1 and DAM2 prevent the second encapsulation layer 182 from spreading towards the pad area where conductive pads are disposed, which is located at the outermost edge of the substrate 101.

[0086] Dams DAM1 and DAM2 are designed to prevent the dispersion of the second encapsulation layer 182. However, when the second encapsulation layer 182 is formed during the process to exceed the height of dams DAM1 and DAM2, the second encapsulation layer 182, being an organic layer, can be exposed to the outside, making it easier for moisture and other substances to penetrate into the interior of the light-emitting diode (LD). Therefore, to prevent penetration, dams DAM1 and DAM2 can be formed to have at least two or more layers. The number of dams DAM1 and DAM2 can be two or more. In this case, each of the two or more dams DAM1 and DAM2 can be formed with the same or different structures from each other.

[0087] Dams DAM1 and DAM2 can be disposed on an interlayer insulating layer, which is disposed on a third insulating layer 135 in the non-display area NA. Embodiments of this disclosure are not limited thereto, and the interlayer insulating layer can be the third insulating layer 135.

[0088] The first dam DAM1 can be formed simultaneously with the second intermediate layer 160 and the levee layer 165. When the second intermediate layer 160 is formed, the lower layer of the first dam DAM1 is formed together with it, and when the levee layer 165 is formed, the upper layer of the first dam DAM1 is formed together with it, so that the first dam DAM1 can be laminated with a double structure.

[0089] In the first dam DAM1, a metal layer made of the same material as the anode electrode 171 can be provided between the upper and lower layers, and a metal layer made of the same material as the source and drain electrodes 140 of the thin film transistors TFT1 and TFT2 and a metal layer made of the same material as the connecting electrode 155 can be provided to be in contact with each other below the lower layer.

[0090] The second dam DAM2 can be formed simultaneously with the first intermediate layer 150, the second intermediate layer 160, and the levee layer 165. When the first intermediate layer 150 is formed, the lower layer of the second dam DAM2 is formed together with it; when the second intermediate layer 160 is formed, the intermediate layer of the second dam DAM2 is formed together with it; and when the levee layer 165 is formed, the upper layer of the second dam DAM2 is formed together with it, so that the second dam DAM2 can be laminated with a triple structure.

[0091] In the second dam DAM2, a metal layer made of the same material as the anode electrode 171 can be provided between the upper layer and the middle layer, a metal layer made of the same material as the connecting electrode 155 can be provided between the middle layer and the lower layer, and a metal layer made of the same material as the source electrode and drain electrode 140 of the thin film transistors TFT1 and TFT2 can be provided below the lower layer.

[0092] Therefore, dams DAM1 and DAM2 can be formed of the same material as the first intermediate layer 150, the second intermediate layer 160, and the dam layer 165, but are not limited thereto. Alternatively, dams DAM1 and DAM2 can have the following structure: at least one insulating layer including an interlayer insulating layer 128 is provided below the first intermediate layer 150.

[0093] Dams DAM1 and DAM2 may overlap with a portion of the low-potential drive voltage line PL2. For example, the low-potential drive voltage line PL2 may be formed on a layer below the area in the non-display area NA in which dams DAM1 and DAM2 are disposed.

[0094] The low-potential driving voltage line PL2 and the gate driver 20, configured in a GIP (gate in panel) manner, are formed in a shape that surrounds the periphery of the display panel. The low-potential driving voltage line PL2 can be located on the outer side of the gate driver 20 (FIG. 1), and at least some portions of the low-potential driving voltage line PL2 can overlap with the gate driver 20. Additionally, the low-potential driving voltage line PL2 can be connected to the cathode electrode 173, and a low-potential driving voltage ELVSS (FIG. 1) can be applied to it.

[0095] The low-potential driving voltage line PL2 can be disposed on the same layer as the connection electrode 155 on the first intermediate layer 150. Alternatively, the low-potential driving voltage line PL2 can be disposed on the same layer as the source electrode and drain electrode 140 of the thin-film transistor TFT on the third insulating layer 135, or it can be disposed on the same layer as the gate electrode 125 of the thin-film transistor TFT on the second insulating layer 120. Embodiments of this disclosure are not limited thereto.

[0096] At least one power bus VL can be provided between the gate driver 20 and the display area AA. The at least one power bus VL can be disposed on the same layer as the source and drain electrodes 140 of the thin-film transistor TFT. However, embodiments of this disclosure are not limited thereto. At least one power bus VL is simply shown in the cross-sectional view; however, the bias voltage line VARL and reference voltage line VrefL configuring the at least one power bus VL can be disposed parallel to each other on the same layer. Alternatively, the bias voltage line VARL and reference voltage line VrefL can be disposed parallel to another layer, or can be disposed overlapping another layer. At least one power bus VL is shown as being disposed between the gate driver 20 and the display area AA, but embodiments of this disclosure are not limited thereto.

[0097] A touch layer 190 can be disposed on the encapsulation layer 180. On the touch layer 190, a touch buffer layer 191 can be disposed between the touch sensor metal including touch electrode connection lines 192 and 194 and touch electrodes 195 and 196 and the cathode electrode 173 of the light-emitting diode LD.

[0098] The touch buffer layer 191 can prevent liquid chemicals (developing solutions or etching solutions) used in the manufacturing process of the touch sensor metal disposed on the touch buffer layer 191 or moisture from the outside from penetrating the light-emitting layer 172, which includes organic materials. Therefore, the touch buffer layer 191 can prevent damage to the light-emitting layer 172, which is susceptible to liquid chemicals or moisture.

[0099] The touch buffer layer 191 is formed of an organic insulating material to prevent or at least reduce damage to the light-emitting layer 172, which includes organic materials susceptible to high temperatures. This organic insulating material can be formed at low temperatures below a specific temperature (e.g., 100°C) and has a low dielectric constant of 1 to 3. For example, the touch buffer layer 191 can be formed of an acrylic-based material, an epoxy-based material, or a siloxane-based material. The touch buffer layer 191, formed of an organic insulating material and having a planarization function, can prevent damage to the encapsulation layer 180 due to bending of the organic electroluminescent display device and breakage of the touch sensor metal formed on the touch buffer layer 191.

[0100] According to the mutual capacitance-based touch sensor structure, touch electrodes 195 and 196 are disposed on the touch buffer layer 191, and touch electrodes 195 and 196 can intersect each other.

[0101] Touch electrode connecting lines 192 and 194 can electrically connect touch electrodes 195 and 196 to each other. Touch electrode connecting lines 192 and 194 and touch electrodes 195 and 196 can be formed in different layers, wherein a touch insulating layer 193 is placed between touch electrode connecting lines 192 and 194 and between touch electrodes 195 and 196.

[0102] The touch electrode connecting lines 192 and 194 can overlap with the embankment 165, and thus prevent a reduction in the aperture ratio.

[0103] Meanwhile, touch electrodes 195 and 196 can be electrically connected to the touch driving circuit (not shown) via touch pad portion 198, because a portion of touch electrode connection line 192 passes through the upper and side surfaces of encapsulation layer 180 and the upper and side surfaces of dams DAM1 and DAM2 and reaches the touch driving circuit (not shown). Therefore, touch electrode connection line 192 overlaps with dams DAM1 and DAM2.

[0104] A portion of the touch electrode connection line 192 can receive touch drive signals from the touch drive circuit, transmit the touch drive signals to touch electrodes 195 and 196, and transmit touch sensing signals in touch electrodes 195 and 196 to the touch drive circuit.

[0105] The touch electrode connection line 192 can be formed with a dual-line structure, and in this case, each layer of the touch electrode connection line 192 can be formed on the touch buffer layer 191 and the touch insulating layer 193 respectively.

[0106] A touch protective layer 197 may be provided on touch electrodes 195 and 196. In the accompanying drawings, the touch protective layer 197 is only provided on touch electrodes 195 and 196; however, it is not limited thereto, and the touch protective layer 197 may extend before or after dams DAM1 and DAM2 to be provided on touch electrode connecting lines 192 and 194.

[0107] The touch pads can be configured by including the following pad layers: a first pad layer formed on the same layer as the gate electrode 126 and made of the same material as the gate electrode 126; a second pad layer formed on the same layer as the source electrode and drain electrode 140 and made of the same material as the source electrode and drain electrode 140; and a third pad layer formed on the same layer as the touch electrodes 195 and 196 or the touch electrode connection lines 192 and 194 and made of the same material as the touch electrodes 195 and 196 or the touch electrode connection lines 192 and 194.

[0108] Alternatively, a color filter (not shown) may be provided on the encapsulation layer 180, and the color filter may be provided on the touch layer 190 or between the encapsulation layer 180 and the touch layer 190.

[0109] Figure 3 is a view showing the configuration of the gate driver in a display device according to an embodiment of the present disclosure.

[0110] Referring to FIG3, the display panel 50 may include a display area AA in which an image is displayed and a non-display area NAA surrounding the display area AA.

[0111] In the display area AA, an array of pixels PX (Figure 1) is set. In the non-display area NAA, at least a portion of the gate drivers can be mounted or connected. For example, the gate drivers 20 can be set on one or both sides (e.g., left or right) in the non-display area as shown. The gate drivers 20 set on both sides in the non-display area NAA can be configured in a symmetrical (mirror configuration) manner with the left and right gate drivers 20 symmetrical to each other. In the following, the configuration will be described based on the gate driver 20 set on the left side of the display area AA.

[0112] The gate driver 20 may be configured to have a first gate driver 21 to a fifth gate driver 25.

[0113] The first gate driver 21 to the third gate driver 23 configure the scan drive circuit 20A (FIG. 1) and are configured to output scan signals SC1, SC2 and SC3 (FIG. 7). For example, the first gate driver 21 may be a first scan driver configured to sequentially output the first scan signal SC1 through the first scan line GL1; the second gate driver 22 may be a second scan driver configured to sequentially output the second scan signal SC2 through the second scan line GL2; and the third gate driver 23 may be a third scan driver configured to sequentially output the third scan signal SC3 through the third scan line GL3.

[0114] Each of the first gate driver 21 to the third gate driver 23 can be configured as a stage circuit that is independently connected to each other. Each stage circuit is connected to the corresponding scan lines GL1, GL2, and GL3, and can output scan signals SC1, SC2, and SC3 to scan lines GL1, GL2, and GL3.

[0115] The first to third scan signals SC1, SC2 and SC3 can be used to drive at least one transistor disposed in pixel PX. For example, the first to third scan signals SC1, SC2 and SC3 can be used to program image data DATA (FIG. 1) into pixel PX, initialize the voltage stored in pixel PX, or compensate the characteristics of circuit elements.

[0116] The fourth gate driver 24 and the fifth gate driver 25 configure the light-emitting driving circuit 20B (FIG. 1) and are configured to output light-emitting signals EM1 and EM2 (FIG. 7). For example, the fourth gate driver 24 can be a first light-emitting driver configured to output the first light-emitting signal EM1 through the first light-emitting line EL1; and the fifth gate driver 25 can be a second light-emitting driver configured to output the second light-emitting signal EM2 through the second light-emitting line EL2. The fourth gate driver 24 can be disposed between the first gate driver 21 and the second gate driver 22. The third gate driver 23 can be disposed between the second gate driver 22 and the fifth gate driver 25.

[0117] The first light-emitting signal EM1 and the second light-emitting signal EM2 can be used to drive at least one transistor disposed in pixel PX. For example, the first light-emitting signal EM1 and the second light-emitting signal EM2 can be used to control the light emission of pixel PX.

[0118] Each of the first gate drivers 21 to the fifth gate driver 25 is driven by receiving a corresponding start signal and a corresponding clock signal via at least one start signal line and multiple clock signal lines. In this case, each of the clock signals may have a different phase.

[0119] Clock signals applied to the first gate driver 21 through the third gate driver 23 can be applied through adjacent clock signal lines, and clock signals applied to the fourth gate driver 24 and the fifth gate driver 25 can also be applied through adjacent clock signal lines. For example, the first gate driver 21 through the third gate driver 23 can receive a first gate clock signal and a second gate clock signal applied through adjacent clock signal lines, and the fourth gate driver 24 and the fifth gate driver 25 can receive a first light-emitting clock signal and a second light-emitting clock signal applied through adjacent clock signal lines. Here, adjacent clock signal lines can be formed as a pair.

[0120] In one embodiment, the first gate driver 21 can be configured to be adjacent to the display area AA. That is, among the first to fifth gate drivers, the first gate driver 21 can be the one closest to the display area AA. In this case, the first to third gate drivers 23 can be configured to be sequentially located away from the display area AA. In another embodiment, the fifth gate driver 25 can be located on the outermost region, and in this case, the fourth and fifth gate drivers 24 can be configured to be sequentially located away from the display area AA.

[0121] The first gate driver 21 to the third gate driver 23 can be configured to be adjacent to one of the fourth gate driver 24 and the fifth gate driver 25. For example, the first gate driver 21 and the second gate driver 22 can be configured to be adjacent to the fourth gate driver 24, and the third gate driver 23 can be configured to be adjacent to the fifth gate driver 25. In such an embodiment, the fourth gate driver 24 can be disposed between the first gate driver 21 and the second gate driver 22.

[0122] In one embodiment, the first gate driver 21 may include an odd-numbered first gate driver 21_O and an even-numbered first gate driver 21_E. In this case, as shown, the odd-numbered first gate driver 21_O and the even-numbered first gate driver 21_E may be disposed on opposite sides of the display area AA.

[0123] By dividing the first gate driver 21 into odd-numbered first gate driver 21_O and even-numbered first gate driver 21_E, the time required for applying the data voltage Vdata can be sufficiently ensured. Furthermore, by placing the odd-numbered first scan driver 21_O and even-numbered first scan driver 21_E on opposite sides of the display area AA, the deviation in the per-pixel application time of the data voltage Vdata can be reduced. Therefore, by driving the first gate driver 21, the time required for applying the data voltage Vdata can be sufficiently ensured, and the deviation in the per-pixel application time can be reduced, thereby improving the image quality of the display panel.

[0124] Two or more gate drivers arranged adjacent to each other can receive power by sharing a single gate power line. For example, the second gate driver 22 and the fourth gate driver 24 can share a single gate power line, and the third gate driver 23 and the fifth gate driver 25 can share a single gate power line. However, this embodiment is not limited to this.

[0125] One or more power buses VL can be provided between the gate driver 20 and the display area AA. The power bus VL may include, for example, a bias power line VARL, a reference voltage line VrefL, etc. Such a power bus VL can be connected to the pixels PX disposed in the display area AA via link lines (not shown) branching from the power bus VL.

[0126] In one implementation, the power bus VL can be arranged symmetrically on both sides of the display area AA. Alternatively, the power bus VL can be arranged only on one side of the display area AA, either the left and right sides or the top and bottom sides.

[0127] At least some of the power bus VL and link lines can be formed on the same layer as the source and drain electrodes 140 of the thin-film transistor TFT and made of the same material as the source and drain electrodes 140 of the thin-film transistor TFT, and can be formed on the same layer as the connection electrode 155 and made of the same material as the connection electrode 155. Alternatively, at least some of the power bus VL and link lines can be formed on the same layer as the gate electrodes 125 and 126 and made of the same material as the gate electrodes 125 and 126, or can be formed on the same layer as the semiconductor layers 115 and 116 and made of the same material as the semiconductor layers 115 and 116. Additionally, at least some of the power bus VL and link lines can be formed on the same layer as the touch electrode connection lines 192 and 194 or the touch electrodes 195 and 196 and made of the same material as the touch electrode connection lines 192 and 194 or the touch electrodes 195 and 196, or can be formed on the same layer as the shielding metal 102 and made of the same material as the shielding metal 102.

[0128] The arrangement of the first gate drivers 21 to the fifth gate drivers 25 is not limited to what is shown. The arrangement of the first gate drivers 21 to the fifth gate drivers 25 can be varied to a wide range of possibilities to reduce the size of the non-display area and the length and number of lines according to the specifications of the display panel 50.

[0129] Additionally, the first gate driver 21 can output the first scan signal SC1 to one pixel row connected to each of the stage circuits, and the second gate drivers 22 to the fifth gate drivers 25 can jointly output the scan signal to two or more pixel rows connected to each of the stage circuits. That is, since a pixel row is connected to each of the stage circuits in the first gate driver 21, a delayed output signal is supplied to each row; and since two adjacent pixel rows are connected to one of the stage circuits in the second gate drivers 22 to the fifth gate drivers 25, the second gate drivers 22 to the fifth gate drivers 25 can jointly apply the same output signal.

[0130] Some of the first gate drivers 21 to the fifth gate drivers 25 can be implemented as shift register circuits, and the remaining gate drivers can be implemented as edge-triggered circuits. For example, the first gate driver 21 can be implemented as a shift register circuit, and the second gate drivers 22 to the fifth gate drivers 25 can be implemented as edge-triggered circuits.

[0131] Therefore, the first gate driver 21, implemented as a shift register circuit, can be connected one by one to the odd-numbered pixel rows and the even-numbered pixel rows. Additionally, the second to fifth gate drivers 25, implemented as edge trigger circuits, can be connected together to both pixel rows.

[0132] Figure 4 is a view showing the pixel circuitry in a display device according to an embodiment of the present disclosure.

[0133] Referring to FIG4, a pixel PX according to an embodiment may include a driving transistor DT, a light-emitting diode LD connected to the driving transistor DT, and a control circuit configured to control the amount of driving current applied to the light-emitting diode LD through the driving transistor DT. For example, the control circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0134] The first electrode of the driving transistor DT is configured to receive a high-potential driving voltage ELVDD (connected to the high-potential driving voltage line PL1), and the second electrode of the driving transistor DT is connected to the first node N1. The gate electrode of the driving transistor DT is connected to the second node N2. The driving transistor DT can be turned on according to the voltage applied to the second node N2, and the amount of driving current flowing to the light-emitting diode LD can be controlled.

[0135] The first electrode of the first transistor T1 is connected to the data line DL, and the second electrode of the first transistor T1 is connected to the gate electrode of the driving transistor DT at the second node N2. The gate electrode of the first transistor T1 can be connected to the first scan line GL1 and can receive the first scan signal SC1 via the first scan line GL1. The first transistor T1 can be turned on according to the first scan signal SC1 applied to the first scan line GL1, and can transmit the data voltage Vdata applied to the data line DL to the second node N2. The first transistor T1 can be referred to as a switching transistor.

[0136] The first electrode of the second transistor T2 is configured to receive a reference voltage Vref (connected to the reference voltage line VrefL), and the second electrode of the second transistor T2 is connected to the second node N2. The gate electrode of the second transistor T2 can be connected to the second scan line GL2, and can receive the second scan signal SC2 via the second scan line GL2. The second transistor T2 can be turned on according to the second scan signal SC2 applied to the second scan line GL2, and can transmit the reference voltage Vref to the second node N2. The second transistor T2 can be referred to as the initialization transistor.

[0137] The first electrode of the third transistor T3 is connected to the bias voltage line VARL and is configured to receive the bias voltage VAR via the bias voltage line VARL. The second electrode of the third transistor T3 is connected to the anode electrode of the light-emitting diode LD at the fourth node N4. The gate electrode of the third transistor T3 can be connected to the third scan line GL3 and can receive the third scan signal SC3 via the third scan line GL3. The third transistor T3 can be turned on according to the third scan signal SC3 applied to the third scan line GL3 and can transmit the bias voltage VAR to the anode electrode of the light-emitting diode LD. The third transistor T3 can be referred to as the anode initialization transistor.

[0138] The first electrode of the fourth transistor T4 is connected to the high-potential drive voltage line PL1 and is configured to receive the high-potential drive voltage ELVDD via the high-potential drive voltage line PL1. The second electrode of the fourth transistor T4 is connected to the drive transistor DT at the third node N3. The gate electrode of the fourth transistor T4 can be connected to the first light-emitting line EL1 and can receive the first light-emitting signal EM1 via the first light-emitting line EL1. The fourth transistor T4 can connect the high-potential drive voltage line PL1 and the drive transistor DT to each other in response to the first light-emitting signal EM1 applied to the first light-emitting line EL1.

[0139] The first electrode of the fifth transistor T5 can be connected at the first node N1 to the second electrode of the driving transistor DT, the first capacitor C1, and the second capacitor C2. The second electrode of the fifth transistor T5 can be connected at the fourth node N4 to the light-emitting diode LD, the second capacitor C2, and the second electrode of the third transistor T3. The gate electrode of the fifth transistor T5 can be connected to the second light-emitting line EL2 and can receive the second light-emitting signal EM2 via the second light-emitting line EL2. The fifth transistor T5 can connect the driving transistor DT and the light-emitting diode LD to each other in response to the second light-emitting signal EM2 applied to the second light-emitting line EL2.

[0140] When the fourth transistor T4 and the fifth transistor T5 are turned on, a current path is formed between the high-potential drive voltage ELVDD and the low-potential drive voltage ELVSS, and the drive current flows to the light-emitting diode LD, so that the light-emitting diode LD can emit light. Such a fourth transistor T4 and a fifth transistor T5 can be called light-emitting transistors.

[0141] The first capacitor C1 is connected to the first node N1 and the second node N2. Therefore, the first electrode of the first capacitor C1 is connected at the second node N2 to the gate electrode of the driving transistor DT, the second electrode of the second transistor T2, and the second electrode of the first transistor T1, and the second electrode of the first capacitor C1 is connected at the first node N1 to the first electrode of the fifth transistor and the first electrode of the second capacitor C2. The first capacitor C1 can store a voltage corresponding to the voltage difference between the first node N1 and the second node N2. For example, the first capacitor C1 can store a voltage corresponding to the voltage difference between the data voltage Vdata applied to the data line DL and the second node N2, and maintain the stored voltage during a frame, thereby stabilizing the voltage at the gate electrode of the driving transistor DT (i.e., the second node N2). The first capacitor C1 can be referred to as a storage capacitor.

[0142] The second capacitor C2 is connected to the first node N1 and the fourth node N4. For example, the first electrode of the second capacitor C2 is connected at the first node N1 to the second electrode of the first capacitor C1 and the first electrode of the fifth transistor T5, and the second electrode of the second capacitor C2 is connected at the fourth node N4 to the second electrode of the fifth transistor, the second electrode of the third transistor T3, and the anode electrode of the light-emitting diode LD.

[0143] The second capacitor C2 can store a voltage corresponding to the voltage difference between the first node N1 and the fourth node N4. In the embodiment, during at least one of the remaining operating periods other than the light-emitting period described below (e.g., when the third transistor T3 is turned on), since one end of the second capacitor C2 (e.g., the second electrode) is fixed to the bias voltage VAR, the second capacitor C2 can store the voltage difference according to the change in voltage of the first node N1, thereby compensating for the driving characteristics of the driving transistor DT. Additionally, when the light-emitting diode LD emits light (e.g., during the light-emitting period), the two ends of the second capacitor C2 (e.g., the first and second electrodes) are short-circuited, so that the second capacitor C2 is unrelated to voltage changes at the nodes connected to the driving transistor DT. Therefore, the second capacitor C2 can be referred to as a compensation capacitor.

[0144] The anode of the LED (LD) can be connected to the fourth node N4, and the cathode of the LED can be connected to the low-level drive voltage ELVSS. When the drive transistor DT, the fourth transistor T4, and the fifth transistor T5 are turned on, a current path is formed between the high-level drive voltage ELVDD and the low-level drive voltage ELVSS, and the drive current can flow to the LED. The LED can emit light with a brightness corresponding to the drive current applied to it.

[0145] In the embodiment shown in Figure 4, the pixel PX may include an oxide semiconductor thin-film transistor (OSBMT). The OSBMT includes a gate electrode, a source electrode, and a drain electrode. The OSBMT has an active layer formed of oxide semiconductor. Here, the oxide semiconductor can be configured as an amorphous oxide semiconductor or a crystalline oxide semiconductor. The OSBMT can be configured as an n-type transistor. The OSBMT can be formed by cryogenic processing and has a lower charge mobility than that of low-temperature polycrystalline silicon (LTPS) thin-film transistors. Such OSBMTs exhibit excellent turn-off current characteristics.

[0146] In this embodiment, the driving transistor DT can be configured as an oxide semiconductor thin-film transistor. Additionally, at least one of transistors T1 to T5 can be configured as an oxide semiconductor thin-film transistor.

[0147] Alternatively, in an embodiment, the pixel PX may be a hybrid type that also includes LTPS (low-temperature polycrystalline silicon) thin-film transistors.

[0148] Figure 5 is an operation timing diagram of the pixel circuit in the display device shown in Figure 4, and Figures 6A to 6E are diagrams showing the operation of the pixel circuit in each operation period in more detail.

[0149] Referring together to Figures 5, 6A to 6E, a frame may include an initialization period I1, a sampling period I2, a programming period I3, an anode reset period I4, and an emission period I5.

[0150] During the initialization period I1, the second scan signal SC2 and the third scan signal SC3 are applied at the on level, and the second transistor T2 and the third transistor T3 are turned on. Additionally, during the initialization period I1, the second light emission signal EM2 is applied at the on level, and the fifth transistor T5 is turned on.

[0151] When the reference voltage Vref is applied to the second node N2 through the switched-on second transistor T2, the gate electrode of the driving transistor DT can be initialized to the reference voltage Vref. The reference voltage Vref can be a positive voltage at a low level, and can be a voltage corresponding to black brightness, but is not limited to these.

[0152] When the bias voltage VAR is applied to the fourth node N4 through the switched-on third transistor T3, the anode of the light-emitting diode LD can be initialized to the bias voltage VAR. The bias voltage VAR can also be applied to the first node N1 through the fifth transistor T5. The bias voltage VAR can be the same as or different from the reference voltage Vref. For example, the bias voltage VAR can be a voltage less than the reference voltage Vref, or a negative voltage, but it is not limited to these.

[0153] The first capacitor C1 stores the voltage corresponding to the difference between the voltage at the second node N2 and the voltage at the first node N1. That is, during the initialization period I1, the first capacitor C1 can store the voltage Vref-VAR corresponding to the difference between the reference voltage Vref and the bias voltage VAR.

[0154] When the fifth transistor T5 is in the ON state, the two ends of the second capacitor C2 can have the same voltage. That is, during the initialization period I1 when the fifth transistor T5 is in the ON state, the two ends of the second capacitor C2 are subjected to the same bias voltage VAR. Therefore, during the initialization period I1, the second capacitor C2 does not store any voltage.

[0155] During the sampling period I2 shown in Figure 6B, the first light-emitting signal EM1 can be switched to the on level, so that the fourth transistor T4 can be turned on, and the second light-emitting signal EM2 can be switched to the off level, so that the fifth transistor T5 can be turned off.

[0156] When the high-potential drive voltage ELVDD is applied to the third node N3 through the turned-on fourth transistor T4, the high-potential drive voltage ELVDD can be applied to the drain electrode of the drive transistor DT. The reference voltage Vref is applied to the gate electrode of the drive transistor DT through the second transistor T2. The source electrode of the drive transistor DT enters a variable voltage state.

[0157] Therefore, during the sampling period I2, the driving transistor DT can be turned on and operate as a source follower. That is, when the gate-source voltage reaches the threshold voltage Vth of the driving transistor DT, the driving transistor DT can supply drain-source current to the first node N1. The voltage of the first node N1 can be gradually increased from the bias voltage VAR and can converge to a voltage Vref-Vth corresponding to the difference between the reference voltage Vref and the threshold voltage Vth.

[0158] The first capacitor C1 stores the voltage corresponding to the difference between the voltage at the second node N2 and the voltage at the first node N1. After the driving transistor DT saturates, the first capacitor C1 can store the threshold voltage Vth corresponding to the difference between the reference voltage Vref and the voltage at the first node N1, Vref-Vth.

[0159] The second capacitor C2 stores the voltage corresponding to the difference between the voltage at the first node N1 and the voltage at the fourth node N4. After the driving transistor DT saturates, the second capacitor C2 can store the voltage Vref-Vth-VAR corresponding to the difference between the voltage Vref-Vth at the first node N1 and the bias voltage VAR.

[0160] During programming period I3 as shown in Figure 6C, the second scan signal SC2 switches to the off level, and the first light emission signal EM1 switches to the off level, thereby turning off the second transistor T2 and the fourth transistor T4, while the third transistor T3 remains on. Alternatively, during programming period I3, the first scan signal SC1 is applied at the on level, thereby turning on the first transistor T1.

[0161] When the data voltage Vdata is applied to the second node N2 through the turned-on first transistor T1, the data voltage Vdata can be applied to the second node of the driving transistor DT, which is the gate electrode of the driving transistor DT. In this case, since the bias voltage VAR is applied to the fourth node N4 through the turned-on third transistor T3, one end of the second capacitor C2 can be fixed to the bias voltage VAR as a DC voltage, and the voltage of the first node N1, which is the other end of the second capacitor C2, can change up to the relationship between the change in the voltage of the second node N2 from the reference voltage Vref to the data voltage Vdata and the voltage stored in the first capacitor C1 and the second capacitor C2. That is, during the programming period I3, the voltage of the first node N1 can change according to the change in the voltage of the second node N2. If the voltage value stored in the second capacitor C2 is very small, then according to the relationship, the change in the voltage of the first node N1 can be the same as the change in the voltage of the second node N2.

[0162] Therefore, the first capacitor C1 can store the voltage difference between the second node N2 and the first node N1, and the voltage difference between the second node N2 and the first node N1 can be a voltage that is programmed to be close to the voltage obtained by compensating the data voltage Vdata up to the threshold voltage Vth.

[0163] During the anode reset period I4 shown in Figure 6D, the first light-emitting signal EM1 can remain off, causing the fourth transistor T4 to turn off, and the second light-emitting signal EM2, which is at the on level, is applied, causing the fifth transistor T5 to turn on. The third transistor T3 can remain on, and the anode electrode of the light-emitting diode LD can be initialized to the bias voltage VAR.

[0164] During the anode reset period I4, the light-emitting diode LD does not emit light through the bias voltage VAR applied to its anode electrode. Alternatively, the voltage at the gate electrode of the driving transistor DT can be maintained at the voltage programmed during the previous programming period I3 through the first capacitor C1. In this case, the voltage across the second capacitor C2 is at the same potential as the bias voltage VAR, and there may be no voltage stored in the second capacitor C2.

[0165] During the light-emitting period I5 shown in Figure 6E, the first scan signal SC1 to the third scan signal SC3 are switched to the off level, and the first transistor to the third transistor T1, T2 and T3 are turned off. Additionally, during the light-emitting period I5, the first light-emitting signal EM1 and the second light-emitting signal EM2 are applied at the on level, and the fourth transistor T4 and the fifth transistor T5 are turned on.

[0166] By connecting the fourth transistor T4 and the fifth transistor T5, a current path is formed from the high-potential drive voltage ELVDD, through the drive transistor DT, and to the light-emitting diode LD. Therefore, a drive current with a magnitude corresponding to the voltage programmed into the drive transistor DT is provided to the light-emitting diode LD, so that the light-emitting diode LD can emit light with a brightness corresponding to the drive current.

[0167] Here, the voltage programmed into the driving transistor DT is the voltage programmed into the first capacitor C1, and it is the voltage that compensates for the data voltage Vdata up to the threshold voltage Vth. Therefore, degradation of the driving transistor DT can be compensated.

[0168] Simultaneously, during the light-emitting period I5, when the fifth transistor T5 is turned on, the voltage of the first node N1 may change drastically. If the second capacitor C2, with its large capacitance, is electrically connected to the corresponding node and forms a potential difference, voltage coupling can be generated between the first node N1 and the second capacitor C2. This interrupts the voltage change of the first node N1, and a delay may occur before the light-emitting diode LD emits light at the desired brightness. Furthermore, when the voltage of the first node N1 changes through voltage coupling, distortion can be generated in the voltage of the second node N2, which is indirectly connected to the first node N1, and the source-gate voltage of the driving transistor DT cannot be stably maintained.

[0169] In the embodiment described above, during the anode reset period I4 and the light emission period I5, the fifth transistor T5 is turned on, and the two ends of the second capacitor C2 are formed to have the same potential. Therefore, except for maintaining the threshold voltage Vth during the sampling period I2 and the programming period I3, the voltage of the second capacitor C2 is not related to the voltage of the first node N1 and the fourth node N4, which are the light emission nodes during the light emission period I5. That is, during the light emission period I5, the voltage coupling between the second capacitor C2 and the first node N1 can be eliminated or minimized. Therefore, during the light emission period I5, delays in light emission, brightness distortion, or degradation of display quality due to voltage coupling can be prevented.

[0170] Additionally, in the embodiment described above, the second capacitor C2 receives a bias voltage VAR via the third transistor T3. That is, during the compensation operation of the second capacitor C2, the voltage at one electrode of the second capacitor C2 can be fixed and stabilized as a DC voltage via the third transistor T3. Furthermore, since no additional circuit elements (e.g., transistors) and signal lines for supplying the voltage to the second capacitor C2 are required, the size and complexity of the circuit, as well as power consumption, can be reduced.

[0171] Meanwhile, in variable refresh rate mode, a frame can be configured with a combination of at least one refresh period RP and at least one skip period SP.

[0172] In this case, the refresh period RP can be operated as the initialization period I1, sampling period I2, programming period I3, and emission period I5, and the skip period SP can be operated as the anode reset period I4 and emission period I5.

[0173] During the anode reset period I4 of the skip period SP, the light-emitting diode LD does not emit light through the bias voltage VAR applied to the anode electrode of the light-emitting diode LD, and the voltage of the gate electrode of the driving transistor DT can be maintained as the voltage programmed in the previous refresh period RP.

[0174] Additionally, during the skip period SP, since the bias voltage VAR is directly applied to the anode electrode of the LED LD, the voltage at the anode electrode can discharge relatively quickly, thus improving the discharge delay of the LED LD. This anode initialization prevents deviations in the integration quantity of brightness according to the refresh rate and suppresses flickering caused by differences in the integration quantity of brightness.

[0175] Figures 7A and 7B are respectively a diagram of a pixel circuit in a display device according to another embodiment of the present disclosure and an operation timing diagram of the pixel circuit in the display device.

[0176] Referring to Figures 7A to 7B, in the pixel circuit of Figure 7A, compared with the pixel circuits and operating timing shown in Figures 4 to 6E, the fourth transistor T4 and the fifth transistor T5 that receive the first light emission signal EM1 can be configured interchangeably, and the voltage level of the first light emission signal EM1 can be reversed.

[0177] In other words, in the embodiments shown in Figures 7A and 7B, the fourth transistor T4 can be configured as an LTPS thin-film transistor (P-type transistor). Since the fourth transistor T4 is configured as an LTPS thin-film transistor with fast drive characteristics, the fourth transistor T4 can be turned on quickly when the first light-emitting signal EM1 is applied at the on level, and the light-emitting response speed can be increased.

[0178] An LTPS thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. An LTPS thin-film transistor includes an active layer formed of polycrystalline silicon. An LTPS thin-film transistor can be configured as a p-type thin-film transistor. LTPS thin-film transistors exhibit high electron mobility and therefore fast drive characteristics.

[0179] When the fourth transistor T4 is a p-type thin-film transistor, its on-state is low. Therefore, when the first light-emitting signal EM1 is applied at a high level, the fourth transistor T4 is off. Conversely, when the first light-emitting signal EM1 is applied at a low level, the fourth transistor T4 is on. Therefore, the first light-emitting signal EM1 can be a high gate voltage VGH in the first time period I1, the third time period I3, and the fourth time period I4, and can be a low gate voltage VGL in the second time period I2 and the fifth time period I5.

[0180] However, this embodiment is not limited to this. That is, in various other embodiments, at least some of the first transistors T1 to the fifth transistors T5 of the control circuit, other than the drive transistor DT, can also be configured as LTPS thin-film transistors.

[0181] The display device according to embodiments of the present disclosure can be described as follows.

[0182] One embodiment is a display device comprising: a display panel including a display area and a non-display area surrounding the display area, the display area including pixels; a data driver configured to apply a data voltage to the pixels; and (optionally) at least one gate driver configured to apply a scan signal and a light emission signal to the pixels, wherein at least one pixel may include: a light-emitting diode including an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode; a driving transistor having a first electrode connected to a third node, a gate electrode connected to a second node, and a second electrode connected to the first node; a switching transistor having a first electrode connected to a data line and a second electrode connected to the gate electrode of the driving transistor at the second node, the switching transistor having a gate electrode for receiving a first scan signal; and a first initialization transistor having a first electrode connected to a reference voltage line and a second electrode connected to the second electrode of the switching transistor and the gate electrode of the driving transistor at the second node, the first initialization transistor having a second scan signal for receiving a second scan signal. The first light-emitting transistor has a gate electrode; a first light-emitting transistor having a first electrode connected to a high-potential driving voltage line and a second electrode connected to a first electrode of a driving transistor at a third node, the first light-emitting transistor having a gate electrode for receiving a first light-emitting signal; a second light-emitting transistor having a first electrode connected to a second electrode of a driving transistor at a first node and a second electrode connected to an anode electrode of a light-emitting diode at a fourth node, the second light-emitting transistor having a gate electrode for receiving a second light-emitting signal; a first capacitor having a first electrode connected to a second electrode of a switching transistor, a second electrode of a first initialization transistor, and a gate electrode of a driving transistor at a second node, and a second electrode connected to a second electrode of a driving transistor and a first electrode of a second light-emitting transistor at a first node; and a second capacitor having a second electrode connected to a second electrode of a first capacitor, a second electrode of a driving transistor, and a first electrode of a second light-emitting transistor at a first node, and a second electrode connected to a second electrode of a second light-emitting transistor and an anode electrode of a light-emitting diode at a fourth node, wherein the driving transistor includes an oxide semiconductor layer.

[0183] In the display device according to the embodiments of the present disclosure, the driving transistor, the switching transistor, the first initialization transistor, the first light-emitting transistor, and the second light-emitting transistor are n-type transistors.

[0184] In a display device according to an embodiment of the present disclosure, at least one pixel may further include: a second initialization transistor, the second initialization transistor including a first electrode connected to a bias voltage line, an anode electrode connected to a light-emitting diode at a fourth node, a second electrode of a second capacitor and a second electrode of the second electrode of the second light-emitting transistor, and a gate electrode for receiving a third scan signal.

[0185] In the display device according to an embodiment of the present disclosure, each of the first capacitor and the second capacitor further includes a third electrode.

[0186] In a display device according to an embodiment of the present disclosure, the display device further includes: a shielding metal overlapping with a driving transistor, wherein a first electrode of at least one of a first capacitor and a second capacitor is on the same layer as the shielding metal, and a third electrode of at least one of the first capacitor and the second capacitor is on the same layer as the gate electrode of the driving transistor.

[0187] In a display device according to an embodiment of the present disclosure, the capacitor may include a storage capacitor and a compensation capacitor connected in series with each other.

[0188] In a display device according to an embodiment of the present disclosure, a portion of a first capacitor and a portion of a second capacitor overlap.

[0189] In a display device according to an embodiment of the present disclosure, the second electrode of the second capacitor receives a fixed DC voltage during a first time period, and the first and second electrodes of the second capacitor have the same potential during a second time period different from the first time period.

[0190] In a display device according to an embodiment of the present disclosure, a pixel is driven during the following time periods: an initialization period, during which a reference voltage supplied by a reference voltage line is applied to a second node by a first initialization transistor when the first initialization transistor is turned on during the initialization period; a sampling period, during which the driving transistor operates in a source follower mode; a programming period, during which a data voltage supplied by a data line is applied to the gate electrode of the driving transistor at the second node by a switching transistor; and an emission period, during which the driving transistor provides a driving current to a light-emitting diode.

[0191] In a display device according to an embodiment of the present disclosure, the first light-emitting transistor is a p-type transistor.

[0192] In a display device according to an embodiment of the present disclosure, the gate driver may include a plurality of transistors formed by the same process as the first light-emitting transistor. Therefore, the transistors of the gate driver may have the same structure as the first light-emitting transistor. Additionally, the transistors of the gate driver may be on the same layer as the first light-emitting transistor.

[0193] In a display device according to an embodiment of the present disclosure, in a non-display area, gate drivers may be disposed on both sides of the display area, and each includes a plurality of scan drivers and a plurality of light emission control drivers.

[0194] In a display device according to an embodiment of the present disclosure, at least one of a plurality of scan drivers may have a pixel row connected to a level circuit, and each of the remaining scan drivers may have two pixel rows connected to and adjacent to the level circuit.

[0195] In a display device according to an embodiment of the present disclosure, at least one of a plurality of light emission control drivers can apply the same light emission signal to two adjacent pixel rows, wherein the same light emission signal is a first light emission signal or a second light emission signal.

[0196] In a display device according to an embodiment of the present disclosure, the display device may further include: a low-potential driving voltage line that surrounds the periphery of the display panel in a non-display area.

[0197] In a display device according to an embodiment of the present disclosure, a low-potential drive voltage line may be disposed on an outer side further outward than the gate driver.

[0198] In a display device according to an embodiment of the present disclosure, the display device may further include a dam having a portion overlapping a low-potential driving voltage line.

[0199] In a display device according to an embodiment of the present disclosure, the display device may further include: a touch electrode connection line that overlaps with a dam.

[0200] In a display device according to an embodiment of the present disclosure, the touch electrode connection line can be formed in a dual wiring structure.

[0201] In one embodiment, a pixel of a display device includes: a light-emitting diode (LED) including an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode; a driving transistor having a first electrode connected to a third node, a gate electrode connected to a second node, and a second electrode connected to the first node; a switching transistor having a first electrode connected to a data line and a second electrode connected to the gate electrode of the driving transistor at the second node, the switching transistor having a gate electrode for receiving a first scan signal; a light-emitting transistor having a first electrode connected to the second electrode of the driving transistor at the first node and a second electrode connected to the anode electrode of the LED at a fourth node, the light-emitting transistor having a gate electrode for receiving a light-emitting signal; and a first capacitor. The device comprises a first electrode having a second electrode connected at a second node to a second electrode of a switching transistor and a gate electrode of a driving transistor, and a second electrode connected at a first node to a second electrode of a driving transistor and a first electrode of a light-emitting transistor; and a second capacitor having a second electrode connected at a first node to a second electrode of a first capacitor, a second electrode of a driving transistor, and a first electrode of a light-emitting transistor, and a second electrode connected at a fourth node to a second electrode of a light-emitting transistor and an anode electrode of a light-emitting diode, wherein a pixel is driven during a plurality of time periods including a light-emitting period, during a light-emitting period, when the light-emitting transistor is turned on during the light-emitting period, the first electrode and the second electrode of the second capacitor are short-circuited, and during at least another time period of the plurality of time periods, when the light-emitting transistor is turned off, a DC voltage is applied to the second electrode of the second capacitor.

[0202] In one embodiment, the light-emitting transistor is a second light-emitting transistor, and the pixel further includes: a first initialization transistor having a first electrode connected to a reference voltage line and a second electrode connected at a second node to a second electrode of a switching transistor and a gate electrode of a driving transistor, the first initialization transistor having a gate electrode for receiving a second scan signal; a first light-emitting transistor having a first electrode connected to a high-potential driving voltage line and a second electrode connected at a third node to a first electrode of the driving transistor, the first light-emitting transistor having a gate electrode for receiving a first light-emitting signal; and a second initialization transistor including a first electrode connected to a bias voltage line supplying a DC voltage, a second electrode connected at a fourth node to an anode electrode of a light-emitting diode, a second electrode of a second capacitor and a second electrode of a light-emitting transistor, and a gate electrode for receiving a third scan signal.

[0203] In one embodiment, the multiple time periods further include: an initialization period, in which a reference voltage supplied by a reference voltage line is applied to the second node by the first initialization transistor when the first initialization transistor is turned on during the initialization period, and the first and second electrodes of the second capacitor are short-circuited when the light-emitting transistor is turned on during the initialization period; a sampling period, in which a driving transistor operates in a source follower mode, and a DC voltage is applied to the second electrode of the second capacitor by the second initialization transistor when the light-emitting transistor is turned off during the sampling period; and a programming period, in which a data voltage supplied by a data line is applied to the gate electrode of the driving transistor at the second node by a switching transistor, and a DC voltage is applied to the second electrode of the second capacitor by the second initialization transistor when the light-emitting transistor is turned off during the programming period.

[0204] In one embodiment, the driving transistor, the switching transistor, the first initialization transistor, the second initialization transistor, the second light-emitting transistor, and the first light-emitting transistor are n-type transistors.

[0205] In one embodiment, the driving transistor, the switching transistor, the first initialization transistor, the second initialization transistor, and the second light-emitting transistor are n-type transistors, and the first light-emitting transistor is a p-type transistor.

[0206] In the above specification, the contents of the specification filling in the technical problems, technical solutions and beneficial effects do not specifically describe the basic features of the appended claims. Therefore, the scope of the claims is not limited by the contents described in this specification.

[0207] This disclosure has been described in more detail with reference to exemplary embodiments, but it is not limited to the exemplary embodiments. It will be apparent to those skilled in the art that various modifications can be made without departing from the spirit of this disclosure. Therefore, the exemplary embodiments disclosed herein are not intended to limit but rather to describe the spirit of this disclosure, and the spirit of this disclosure is not limited to the exemplary embodiments. Consequently, the foregoing exemplary embodiments are to be considered illustrative rather than restrictive in all respects. The scope of protection of this disclosure must be interpreted by the appended claims, and should be construed as including all technical spirit within the scope of the appended claims.

Claims

1. A display device, comprising: The display panel includes a display area and a non-display area surrounding the display area, the display area including pixels; and at least one gate driver configured to apply a scan signal and a light emission signal to the pixels, wherein at least one pixel includes: a light-emitting diode, the light-emitting diode including an anode electrode, a cathode electrode and a light-emitting layer between the anode electrode and the cathode electrode; a driving transistor having a first electrode connected to a third node, a gate electrode connected to a second node and a second electrode connected to the first node; a switching transistor having a first electrode connected to a data line and a second electrode connected to the gate electrode of the driving transistor at the second node, the switching transistor having a gate electrode for receiving a first scan signal; a first initialization transistor having a first electrode connected to a reference voltage line and a second electrode connected to the second electrode of the switching transistor and the gate electrode of the driving transistor at the second node, the first initialization transistor having a gate electrode for receiving a second scan signal; and a first light-emitting transistor having a first electrode connected to a high-potential driving voltage line and a second electrode connected to the second electrode of the driving transistor at the second node, the first initialization transistor having a gate electrode for receiving a second scan signal; and a first light-emitting transistor having a first electrode connected to a high-potential driving voltage line and a second electrode connected to the second node. The first light-emitting transistor has a gate electrode for receiving a first light-emitting signal; the second light-emitting transistor has a first electrode connected to the second electrode of the driving transistor at the first node and a second electrode connected to the anode electrode of the light-emitting diode at the fourth node, and a gate electrode for receiving a second light-emitting signal; the first capacitor has a first electrode connected to the second electrode of the switching transistor, the second electrode of the first initialization transistor, and the gate electrode of the driving transistor at the second node, and a second electrode connected to the second electrode of the driving transistor and the first electrode of the second light-emitting transistor at the first node; and the second capacitor has a second electrode connected to the second electrode of the first capacitor, the second electrode of the driving transistor, and the first electrode of the second light-emitting transistor at the first node, and a second electrode connected to the second electrode of the second light-emitting transistor and the anode electrode of the light-emitting diode at the fourth node, wherein the driving transistor includes an oxide semiconductor layer.

2. The display device according to claim 1, wherein, The driving transistor, the switching transistor, the first initialization transistor, the first light-emitting transistor, and the second light-emitting transistor are n-type transistors.

3. The display device according to claim 1, wherein, The at least one pixel further includes: a second initialization transistor, the second initialization transistor including: a first electrode connected to a bias voltage line, a second electrode connected at the fourth node to the anode electrode of the light-emitting diode, the second electrode of the second capacitor and the second electrode of the second light-emitting transistor, and a gate electrode for receiving a third scan signal.

4. The display device according to claim 3, further comprising: A shielding metal overlaps with the driving transistor, wherein one of the first electrode and one of the second electrode of the first capacitor and the second capacitor are on the same layer as the shielding metal, and one of the first electrode and one of the second electrode of the other capacitor are on the same layer as the gate electrode of the driving transistor.

5. The display device according to claim 4, wherein, The first capacitor is a storage capacitor, and the second capacitor is a compensation capacitor connected in series with the first capacitor.

6. The display device according to claim 5, wherein, A portion of the first capacitor and a portion of the second capacitor overlap.

7. The display device according to claim 5, wherein, The second electrode of the second capacitor receives a fixed DC voltage during a first time period, and the first and second electrodes of the second capacitor have the same potential during a second time period different from the first time period.

8. The display device according to claim 1, wherein, The first light-emitting transistor is a p-type transistor.

9. The display device according to claim 8, wherein, The at least one gate driver includes a plurality of transistors having the same structure as the first light-emitting transistor.

10. The display device according to claim 1, wherein, In the non-display area, the at least one gate driver includes a plurality of scan drivers, wherein in at least one of the plurality of scan drivers, a stage circuit is connected to a pixel row, and in the remaining scan drivers, a stage circuit is connected to two adjacent pixel rows.

11. The display device according to claim 1, wherein, In the non-display area, the at least one gate driver includes a plurality of light emission control drivers, and wherein at least one of the plurality of light emission control drivers applies the same light emission signal to two adjacent pixel rows, the same light emission signal being either the first light emission signal or the second light emission signal.

12. The display device according to claim 1, further comprising: A low-potential driving voltage line surrounds the periphery of the display panel in the non-display area, wherein the low-potential driving voltage line is on the outer side further outward than the at least one gate driver.

13. The display device according to claim 12, further comprising: The dam has a portion that overlaps with a portion of the low-potential drive voltage line; And a touch electrode connection line, which overlaps with the dam.

14. The display device according to claim 13, wherein, The touch electrode connection line includes a dual wiring structure.

15. A pixel of a display device, comprising: A light-emitting diode, the light-emitting diode comprising an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode; A driving transistor having a first electrode connected to a third node, a gate electrode connected to a second node, and a second electrode connected to the first node; A switching transistor having a first electrode connected to a data line and a second electrode connected to the gate electrode of the driving transistor at a second node, the switching transistor having a gate electrode that receives a first scan signal; A light-emitting transistor having a first electrode connected to the second electrode of the driving transistor at a first node, and a second electrode connected to the anode electrode of the light-emitting diode at a fourth node, the light-emitting transistor having a gate electrode for receiving light-emitting signals; A first capacitor has a first electrode connected at a second node to the second electrode of the switching transistor and the gate electrode of the driving transistor, and a second electrode connected at a first node to the second electrode of the driving transistor and the first electrode of the light-emitting transistor. And a second capacitor, the second capacitor having: a first electrode connected at the first node to the second electrode of the first capacitor, the second electrode of the driving transistor and the first electrode of the light-emitting transistor, and a second electrode connected at the fourth node to the second electrode of the light-emitting transistor and the anode electrode of the light-emitting diode, wherein the pixel is driven during a plurality of time periods including a light-emitting period, during the light-emitting period, when the light-emitting transistor is turned on during the light-emitting period, the first electrode and the second electrode of the second capacitor are short-circuited, and during at least another time period of the plurality of time periods, when the light-emitting transistor is turned off, a DC voltage is applied to the second electrode of the second capacitor.

16. The pixel according to claim 15, wherein, The light-emitting transistor is a second light-emitting transistor, and the pixel further includes: a first initialization transistor having a first electrode connected to a reference voltage line, and a second electrode connected at a second node to the second electrode of the switching transistor and the gate electrode of the driving transistor, the first initialization transistor having a gate electrode for receiving a second scan signal; a first light-emitting transistor having a first electrode connected to a high-potential driving voltage line, and a second electrode connected at a third node to the first electrode of the driving transistor, the first light-emitting transistor having a gate electrode for receiving a first light-emitting signal; and a second initialization transistor including: a first electrode connected to a bias voltage line supplying the DC voltage, a second electrode connected at a fourth node to the anode electrode of the light-emitting diode, the second electrode of the second capacitor and the second electrode of the light-emitting transistor, and a gate electrode for receiving a third scan signal.

17. The pixel according to claim 16, wherein, The plurality of time periods further include: an initialization period, wherein when the first initialization transistor is turned on during the initialization period, a reference voltage supplied by the reference voltage line is applied to the second node by the first initialization transistor, and when the light-emitting transistor is turned on during the initialization period, the first electrode and the second electrode of the second capacitor are short-circuited; a sampling period, wherein the driving transistor operates in a source follower mode during the sampling period, and when the light-emitting transistor is turned off during the sampling period, the second initialization transistor applies the DC voltage to the second electrode of the second capacitor; and a programming period, wherein during the programming period, a data voltage supplied by the data line is applied to the gate electrode of the driving transistor at the second node by the switching transistor, and when the light-emitting transistor is turned off during the programming period, the second initialization transistor applies the DC voltage to the second electrode of the second capacitor.

18. The pixel according to claim 16, wherein, The driving transistor, the switching transistor, the first initialization transistor, the second initialization transistor, the second light-emitting transistor, and the first light-emitting transistor are n-type transistors.

19. The pixel according to claim 16, wherein, The driving transistor, the switching transistor, the first initialization transistor, the second initialization transistor, and the second light-emitting transistor are n-type transistors, and the first light-emitting transistor is a p-type transistor.

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