Detection of error conditions on serial data buses

Abstract

A controller is provided that includes a serial data (SDA) line interface for connecting the controller to an SDA line of a two-line shared serial data bus. The controller includes circuitry to provide output data for transmission onto the SDA line via the output SDA pad buffer. The controller includes a logic circuit that is external to the circuit and that monitors data on the SDA line as the output data is transmitted onto the SDA line. The logic circuit compares the monitored data on the SDA line to the output data to detect an error condition when the monitored data is different from the output data. The logic circuitry disables an output SDA pad buffer of the SDA line interface for a current byte of the output data provided by the circuitry, and subsequently causes a stop condition on the data bus.

Description

[0001] This application claims priority to U.S. non-provisional patent application No. 18 / 410,615, filed January 11, 2024, entitled “Detection of an Error Condition on a Serial Data Bus,” and Indian provisional patent application No. 202341063537, filed September 21, 2023, entitled “Detection and Recovery from a Read-Write Data Conflict on a Serial Data Bus,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates in general to serial communication, and more specifically to the detection of error conditions on a serial data bus. Background Technology

[0003] Serial communication plays a crucial role in facilitating inter-chip communication within electronic systems. Serial communication involves sending data bit-by-bit sequentially over a communication link between devices. Compared to parallel communication, this approach offers advantages such as simplicity, low pin count, and the ability to send data over longer distances.

[0004] A common serial communication protocol is I2C (Inter-Integrated Circuit), developed by Philips Semiconductor (NXP Semiconductors) in the early 1980s. I2C is a two-wire bus protocol that allows multiple devices to communicate with each other using a shared Serial Data (SDA) line and a Serial Clock (SCL) line. I2C supports a controller-target (master-slave) architecture, where the controller device initiates and controls communication, and the target device responds to commands or requests from the controller. I2C is commonly used to connect various devices in embedded systems, consumer electronics, and computer peripherals.

[0005] With technological advancements and the growing demand for higher data transfer rates, increased flexibility, and improved power efficiency, the MIPI Alliance developed I3C (Improved Integrated Circuit Interconnect). Introduced in 2017, I3C builds upon the strengths of I2C while offering enhancements and additional features. I3C is backward compatible with I2C, allowing I2C devices to coexist on the same data bus. It introduces higher data transfer rates, increased flexibility for connecting multiple devices, multi-controller support, hot-join capability, dynamic address allocation, in-band interrupts, and other improvements. I3C has gained popularity in applications such as smartphones, tablets, Internet of Things (IoT) devices, and automotive systems.

[0006] Serial communication protocols such as I2C and I3C have become an essential part of inter-chip communication within electronic systems. They enable devices to exchange data, commands, and control signals efficiently and reliably. These protocols have been widely adopted and standardized, allowing interoperability between devices from different manufacturers and simplifying the integration of various components within electronic systems. The continuous evolution and development of serial communication protocols contribute to the advancement of inter-chip communication and the seamless operation of modern electronic devices.

[0007] As serial communication protocols evolve, it may become possible that commercially available circuits (such as semiconductor intellectual property cores (IP blocks) that enable controllers to support serial communication on serial data buses) may not support certain errors. Summary of the Invention

[0008] In I3C, a controller can initiate transactions with a target, such as read transactions, write transactions, or receive in-band interrupts (IBI); however, in some examples, error type CE1 may occur. Error type CE1 may occur when a controller in write mode detects that the input data on the data bus differs from the data the controller intends to transmit on the data bus as output data. This can happen when the target misinterprets one or more messages or acknowledgments indicating a read or write transaction during a transaction (including when an in-band interrupt initiated by the target occurs approximately simultaneously with a dedicated write transaction initiated by the controller). When the controller actually intends to initiate a write transaction, the target may behave as if it were responding to a read transaction. When this occurs, write data from the controller on the data bus may conflict with read data from the target. In I3C, when a controller detects a CE1 error condition, the controller should stop transmitting, then assert a stop condition on the data bus and retry transmitting. However, current devices and circuitry providing output data for transmission to the SDA line do not properly support the CE1 error condition. Such circuitry can be implemented in commercially available and difficult-to-modify intellectual property blocks.

[0009] Therefore, exemplary embodiments of this disclosure involve detecting CE1 error conditions from outside a circuit, such as a semiconductor intellectual property core (IP block), which enables the controller to support serial communication over a serial data bus. This disclosure includes, but is not limited to, the following exemplary embodiments.

[0010] Some example implementations provide a controller comprising: a serial data (SDA) line interface for connecting the controller to an SDA line of a two-wire shared serial data bus, the SDA line interface including an output SDA pad buffer; circuitry for providing output data for transmission to the SDA line via the output SDA pad buffer; and logic circuitry external to the circuitry, the logic circuitry being configured to at least: monitor data on the SDA line when the output data is transmitted to the SDA line; compare the monitored data on the SDA line with the output data to detect an error condition when the monitored data on the SDA line differs from the output data; and, based on the detected error condition, disable the output SDA pad buffer for the current byte of the output data provided by the circuitry, and subsequently cause a stop condition on the data bus.

[0011] Some example implementations provide a method comprising: providing output data from a circuit for transmission via an Output Serial Data (SDA) pad buffer to an SDA line of a two-wire shared serial data bus; and monitoring data on the SDA line as the output data is transmitted to the SDA line via logic circuitry external to the circuit; comparing the monitored data on the SDA line with the output data to detect an error condition when the monitored data on the SDA line differs from the output data; and, based on the detected error condition, disabling the output SDA pad buffer for the current byte of the output data provided by the circuit, and subsequently inducing a stop condition on the data bus.

[0012] These and other features, aspects, and advantages of this disclosure will be apparent from the following detailed description and the accompanying drawings, which are briefly described below. This disclosure includes any combination of two, three, four, or more features or elements set forth herein, whether such features or elements are expressly combined or otherwise described in the particular exemplary embodiments described herein. This disclosure is intended to be read holistically such that, unless the context of this disclosure clearly specifies otherwise, any separable features or elements of this disclosure shall be considered composable in all aspects and in any aspect and exemplary embodiment.

[0013] Therefore, it will be understood that this summary is provided merely to outline some exemplary embodiments in order to provide a basic understanding of some aspects of this disclosure. It will also be understood that the exemplary embodiments described above are merely examples and should not be construed as narrowing the scope or substance of this disclosure in any way. Other exemplary embodiments, aspects, and advantages will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of some of the described exemplary embodiments by way of example. Attached Figure Description

[0014] Therefore, specific embodiments of this disclosure have been described in general terms, and reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0015] Figure 1 The controller is illustrated with some examples of specific implementations according to this disclosure;

[0016] Figure 2 Examples of specific implementations based on some examples are provided. Figure 1 The system of controllers;

[0017] Figure 3 Examples are provided for specific implementations that can be combined with... Figure 2 The corresponding system includes multiple controllers and targets;

[0018] Figure 4A , Figure 4B and Figure 4C It is based on specific examples and is targeted at Figure 2 or Figure 3 The timing diagram of signals on the data bus lines of the system's data bus, including specified start conditions, stop conditions, and restart conditions. Figure 4A ), address header ( Figure 4B ) and data words ( Figure 4C );

[0019] Figure 5 It is implemented based on some specific examples. Figure 1 Functional block diagram of the controller; and

[0020] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G and Figure 6H It is a flowchart illustrating the various steps in a method implemented according to various examples. Detailed Implementation

[0021] Some specific embodiments of this disclosure will now be described more fully below with reference to the accompanying drawings, in which some, but not all, specific embodiments of this disclosure are shown. In fact, various specific embodiments of this disclosure may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein; rather, these exemplary specific embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. Similar reference numerals throughout denote similar elements.

[0022] Unless otherwise specified or clear from the context, references to first, second, etc., should not be construed as implying a particular order. A feature described as above another feature (unless otherwise specified or clear from the context) may alternatively be below, and vice versa; and similarly, a feature described as to the left of another feature may alternatively be to the right, and vice versa. Furthermore, while references may be made herein to quantitative measurements, values, geometric relationships, etc., any one or more (if not all) of these quantitative measurements, values, geometric relationships, etc., may be approximate to account for acceptable variations that may occur, such as variations due to engineering tolerances, etc., unless otherwise stated.

[0023] As used herein, unless otherwise specified or clearly indicated from the context, an "OR" of a set of operands is an "inclusive OR," and thus the "OR" is true if and only if one or more of the operands are true, as opposed to an "exclusive OR," which is false when all of the operands are true. Therefore, for example, "[A] OR [B]" is true if [A] is true, or if [B] is true, or if both [A] and [B] are true. Furthermore, unless otherwise specified or clearly indicated from the context, the article "a" means "one or more." Additionally, it should be understood that, unless otherwise specified, the terms "data," "content," "digital content," "information," and similar terms are sometimes used interchangeably.

[0024] Furthermore, while this document may use terminology specific to a particular system or architecture, it should be understood that the exemplary embodiments of this disclosure are equally applicable to any of the many systems and architectures. In this regard, some exemplary embodiments may be described within the context of serial communication standards for inter-chip communication, such as I3C and its predecessor I2C. However, it should be understood that the exemplary embodiments are equally applicable to other serial communication standards.

[0025] The exemplary implementations of this disclosure relate to serial communication in general, and more specifically to the detection and recovery of read / write data conflicts on a serial data bus.

[0026] Figure 1A controller 100 is illustrated according to some examples of implementations of this disclosure. The controller may be an electronic device, such as an integrated circuit (IC). As explained in more detail below, the controller includes circuitry 102 and logic circuitry 104 external to circuitry 102. The controller may also include one or more interfaces for connecting the controller to a data bus 104 through which the controller can communicate with other electronic devices. In the context of serial communication standards such as I2C and I3C, the data bus may be a two-wire shared serial data bus 104. In this regard, the data bus may include a serial data (SDA) line 104A for sending and receiving data between electronic devices connected to the data bus. The controller may include an SDA line interface 106 for connecting targets to the SDA line, and the SDA line interface may include an output SDA pad buffer 108 for driving output data 110 onto the SDA line.

[0027] Figure 2 A system 200 including a controller 100 is illustrated according to some examples of implementations of this disclosure. As shown, the system includes multiple electronic devices 202, such as ICs, connected to a data bus 104. In addition to the SDA line 104A, the data bus may also include an SCL line 204B, which provides a clock signal for synchronizing data transmission between the electronic devices 202. Subsequently, in some examples, the controller 100 may also include an SCL line interface for connecting the controller to the SCL line.

[0028] System 200 can operate according to a controller-target architecture, wherein electronic device 202 can be used as a controller 100 to initiate and control communication (timing and data) on data bus 104, and another electronic device can be used as a target 208 in response to commands or requests from the controller. In some examples, the system can support multiple controllers and targets.

[0029] Figure 3 Examples are provided for specific implementations that can be combined with... Figure 2System 200 corresponds to system 300, which includes multiple controllers and targets. As shown, for example, system 300 may include a master controller 100A and one or more auxiliary controllers 100B, any of which can be the active controller currently controlling the data bus 104. The master controller 100A can initialize the data bus and perform the configuration of target 208. The master controller 100A can act as the authority of the data bus in its initial state and becomes the first active controller once the data bus is configured. The auxiliary controllers 100B can initially be used as targets, but can accept control from the master controller 100A and become new active controllers. In the context of I3C, the system may include an I3C master controller 100A and one or more I3C auxiliary controllers 100B.

[0030] System 300 may also include one or more targets 208. The system may also include one or more legacy targets 304 from earlier communication standards to which system 300 is compatible. Similarly, in the context of I3C, the system may include one or more I3C targets 208, and the system may include one or more I2C targets 304.

[0031] return Figure 2 System 200 can support multiple data transmission modes, allowing electronic device 202 to communicate at different speeds based on its capabilities. These modes can include Single Data Rate (SDR) mode and various High Data Rate (HDR) modes with increased data transmission rates and corresponding signal integrity requirements. Specifically, SDR mode can be used for various purposes, such as performing private messaging from controller 100 to target 208, and entering other modes and states (e.g., HDR mode). In the context of I3C, SDR mode can be used to implement built-in I3C features such as Common Command Code (CCC), In-Band Interrupt (IBI), and hot access. SDR mode can also be used for transitioning from I2C to I3C via dynamic address assignment, and for performing legacy I2C transactions on data bus 104.

[0032] Electronic device 202 can operate in various output modes to drive signals on data bus 104. Examples of suitable modes include open-drain mode and push-pull mode, which define how the electronic device controls the voltage levels on SDA line 104A and SCL line 204B. In open-drain mode, the electronic device can be configured as an open-drain or open-collector at its output. In open-drain mode, the electronic device can actively draw current to pull the signal lines (SDA or SCL) to a low voltage level (logic 0), but electronic device 202 does not have an active element to pull the signal lines to a high voltage level (logic 1). Instead, an external pull-up resistor can be used to pull the lines to a high voltage level (logic 1). In push-pull mode, the electronic device can be configured as a push-pull driver at its output. In push-pull mode, the electronic device can actively drive both high (logic 1) and low (logic 0) voltage levels on the signal lines.

[0033] Figure 4A , Figure 4B and Figure 4C This is a timing diagram of the signals on SDA line 104A and SCL line 204B for read / write transactions on data bus 104, based on some specific implementation examples. (Example...) Figure 4A As shown, a read / write transaction on the data bus can begin with a start condition, which can be asserted by controller 100 and implemented as a high-to-low transition on the SDA line, while the SCL line is maintained at a constant high by controller 100. Similarly, a read / write transaction on the data bus can end with a stop condition asserted by the controller. The stop condition can be implemented as a low-to-high transition on the SDA line during a high voltage level on the SCL line 204B. As an alternative to the stop condition, a restart condition can allow multiple messages to be transmitted within the same frame without needing to send stop and start statements between messages. A restart condition on the data bus may appear identical to a start condition.

[0034] After a startup / restart condition is met, a read / write transaction on the data bus 104 may include an address header (which may include a destination address), indicating a read or write transaction and providing acknowledgment. The address header may be sent on the SDA line 104A during the cycle of the SCL line 204B transitioning from low to high (rising edge) or from high to low (falling edge). Figure 4BThis is a timing diagram of the SDA and SCL lines for the address header, implemented according to some specific examples. In the context of I2C and I3C, the address header may include seven address bits, a read / write (R / W) bit, and an acknowledgment (ACK) / non-acknowledgment (NACK) bit. In the context of I3C, the R / W bit may be referred to as the R / W̅ bit or RnW bit. In some examples, controller 100 may send the address and R / W bits. Controller 100 can use the address bits to address target 208, and the controller can use the R / W bit to specify a write mode (controller 100 writes data to target 208) or a read mode (controller 100 reads data from target 208). In this regard, controller 100 may send a low signal (R / W bit = 0) on SDA line 104A to indicate write mode, or send a high signal (R / W bit = 1) on the SDA line to indicate read mode.

[0035] Once controller 100 sends the address bits and R / W bits of the address header on data bus 104, the controller can wait for target 208 to acknowledge (or not acknowledge) the request. This can be done via the ACK / NACK bits in the address header. The target can respond with an ACK by pulling SDA line 104A low (ACK / NACK bit = 0), or by releasing SDA line high (ACK / NACK bit = 1) to respond with a NACK.

[0036] One or more data words may follow the address header, such as Figure 4C As shown (in push-pull mode). Similar to the address header, data words can be transmitted on SDA line 104A during the cycle of SCL line 204B transitioning from low to high (rising edge) or from high to low (falling edge). In the context of I3C, the data word can be nine bits wide, including eight data bits and a ninth transition bit (T bit). When controller 100 is writing data to target 208, the T bit of each data word can be a parity bit calculated using odd parity, which helps detect errors caused by noise on the data bus. Conversely, when controller 100 is reading data returned from the target, the T bit of each data word can represent a data end bit. In this respect, target 208 can use the T bit to control the number of data words returned by the target. The T bit can also cause controller 100 to prematurely abort the read. To end the message, target 208 can return the T bit to "0". To continue the message, the target can return the T bit to "1" and monitor the SDA line. If the SDA line remains high on the next falling edge of SCL, the target can continue transmitting the next data value. If the SDA line goes low on the next falling edge of SCL (restart), the controller 100 has stopped data transmission, and the target 208 does not transmit the next data.

[0037] Electronic device 202 can implement one or more error detection and recovery methods to handle various error conditions during read / write transactions on data bus 104. In this regard, in the context of I3C, if an error occurs in the R / W bits of the address header, target 208 might behave as if it is responding to a read transaction, while controller 100 is actually attempting to initiate a write transaction. When this happens, write data from the controller on the data bus may conflict with read data from the target. This is addressed in the MIPI I3C protocol released by the Mobile Industry Processor Interface (MIPI) Alliance. ® Instruction manual (MIPI I3C) ® In the Specification, this error condition is referred to as error type CE1 when detected by the controller. As specified, when the controller 100 sends a write transaction on the SDA line 104A of the data bus 104, the controller 100 shall monitor the SDA line 104A of the data bus 104, which allows the controller to detect the CE1 error condition when the monitored data is different from the data that the controller intends to send.

[0038] According to MIPI I3C ® According to the specification, when controller 100 detects a CE1 error condition during an attempted dedicated write transaction with target 208 (i.e., when target 208 is responding to a dedicated read transaction while controller 100 has already attempted to perform a dedicated write transaction), controller 100 can stop transmission and subsequently assert a stop condition on SDA line 104A and retry transmission. An exemplary embodiment of this disclosure provides logic circuitry for detecting such CE1 errors and taking action to avoid prolonged conflicting data on data bus 104, thereby reducing power consumption and preventing potential damage.

[0039] According to some specific embodiments of this disclosure, controller 100 can operate in write mode to perform a write transaction to transfer output data 110 to data bus 104. When the controller is in write mode, it can monitor data 112 on SDA line 104A, compare data 112 on SDA line 104A with output data 110, and detect an error condition when data 112 on SDA line 104A differs from output data 110. Subsequently, based on this error condition, the controller can disable the internal output SDA pad buffer 108 driving output data 110 on SDA line 104A until the transfer of the current byte of data 112 on SDA line 104A is complete. The controller can then assert a stop condition on SDA line 104A of data bus 104.

[0040] like Figure 1 As shown, for example, to provide output data 110 for transmission to circuit 102 on SDA line 104A, data 112 is sent via output SDA pad buffer 108. Logic circuit 104 can monitor data 112 on SDA line 104A as output data 110 is transmitted to SDA line 104A. Logic circuit 104 can compare the monitored data 112 on SDA line 104A with output data 110 to detect an error condition (e.g., CE1 error condition) when the monitored data 112 on SDA line 104A differs from the output data 110. Based on the detected error condition, logic circuit 104 can disable output SDA pad buffer 108 for the current byte of output data 110 provided by circuit 102, and subsequently cause a stop condition on the data bus.

[0041] To further illustrate some specific implementation examples of this disclosure, Figure 5 This is a block diagram of a controller 100 implemented according to some examples. As shown, controller 100 includes circuitry 102, such as a semiconductor intellectual property core (IP block), which enables controller 100 to support serial communication on data bus 104. In this regard, circuitry 102 can provide output data 110 (SDA_OUT) for transmission to SDA line 104A via output SDA pad buffer 108 of SDA line interface 106. In some examples, output SDA pad buffer 108 can be a tri-state buffer, and circuitry 102 can enable output SDA pad buffer to drive output data 110, for example, when controller 100 is in a write state. Circuitry 102 can be provided to not support CE1 errors.

[0042] In some examples, the SDA line interface 106 also includes an input SDA pad buffer 502 to receive monitored data 112 (SDA_IN) on the SDA line 104A. The input SDA pad buffer can filter out noise in the monitored data 112 on the SDA line 104A to produce filtered data. More specifically, for example, the input SDA pad buffer 502 may include a glitch filter (sometimes referred to as a spike filter) to filter out unwanted noise in the monitored data 112, such as by suppressing extreme changes in voltage levels on the SDA line. The monitored data can then be filtered data.

[0043] As also shown in the figure, the logic circuit 104 of the controller 100 may include a state machine 504 and a detector 506 for monitoring data 112 on the SDA line 104A. In this regard, the state machine 504 may receive an indication from the circuit 102 that an address header has been sent on the SDA line 104A, which may be sent by the circuit 102 or read by the state machine 504 from the circuit 102 as part of a debug signal or port of the circuit 102, and enable the detector 506 to monitor one or more data words following the address header in the data 112 on the SDA line 104A.

[0044] Detector 506 may include logic gates, such as an XOR gate 508. The logic gates may perform a bit-by-bit comparison of one or more data words of monitored data 112 on SDA line 104A with one or more data words of output data 110 transmitted by circuit 102 on line SDA_OUT. Detector 506 may also include one or more sequential logic elements, such as a multiplexer 510 and a D flip-flop 512. When a bit-by-bit comparison indicates that one or more data words of monitored data 112 on SDA line 104A differ from one or more data words of output data 110, the one or more sequential logic elements may set a flag to indicate that an error condition has been detected.

[0045] In some more specific examples, when one or more data words of monitored data 112 on SDA line 104A differ from one or more data words of output data 110, XOR gate 508 can produce a high gate output (logic 1), which is fed to the first input of multiplexer 510. Multiplexer 510, in response to an assertion enable signal (EN) from state machine 504, can pass the output of XOR gate 508 to the D input of D flip-flop 512, which is timed by a signal that can be an SCL clock, a synchronous SCL clock, or a faster clock signal, and the D flip-flop can then latch the output of XOR gate 508.

[0046] If one or more data words of monitored data 112 on SDA line 104A differ from one or more data words of output data 110, D flip-flop 512 will therefore latch a high output as a flag (sometimes referred to as the CE1 error flag), which can be represented as a CE1_ERROR signal provided to state machine 504 to indicate that a CE1 condition has been encountered. In response to the set CE1 error flag, i.e., the valid CE1_ERROR signal, state machine 504 can de-assert the enable signal of multiplexer 510, thereby latching the CE1 error flag, which is fed back to the second input of multiplexer 510. In other examples, multiplexer 510 and D flip-flop 512 are not required, and state machine 504 responds to the CE1 error flag without latching the CE1 error flag. Similarly, when detector 506 is not used or the controller exits the write state, state machine 504 can clear D flip-flop 512, thereby clearing the CE1 error flag.

[0047] In some examples, logic circuit 104 can disable output SDA pad buffer 108 when the CE1 error flag is set. In some examples where output SDA pad buffer 108 is a tri-state buffer, logic circuit 104 can disable output SDA pad buffer 108 via the enable / disable input (ENB) of the tri-state buffer.

[0048] In some examples, controller 100 includes a 2:1 multiplexer 514, and logic circuitry 104 includes a pad buffer control block 516. The 2:1 multiplexer 514 may include output lines coupled to enable / disable inputs of output SDA pad buffer 108, and corresponding outputs coupled to circuitry 102 to allow circuitry 102 to enable first input lines of the output SDA pad buffer when the controller is in a write state or when circuitry 102 sends an instruction or address on SDA line 104A.

[0049] The 2:1 multiplexer 514 may also include a second input line coupled to ground (logic 0) and a line coupled to the pad buffer control block 516 to allow the pad buffer control block to select either the first or second input line of the 2:1 multiplexer 514. The pad buffer control block 516 can select the first input line to allow circuit 102 to control the output SDA pad buffer 108, such as enabling the SDA pad buffer 108 in a write state. However, when state machine 504 detects the CE1 error flag, state machine 504 can control the pad buffer control block to select the second input line of the 2:1 multiplexer, thereby connecting the enable / disable input of the output SDA pad buffer to ground to disable the output SDA pad buffer. Therefore, state machine 504 and detector 506 can detect the CE1 error condition and perform operations based on the error condition outside circuit 102 (e.g., IP block) without interrupting the circuit.

[0050] Regardless of the exact manner in which logic circuit 104 disables the output SDA pad buffer 108, in one example, logic circuit 104 can then cause a stop condition on data bus 104, such as causing target 208 to terminate the transmission of monitored data 112 on SDA line 104A. Specifically, state machine 504 of logic circuit 104 can cause a stop condition on the data bus to cause target 208 to terminate the transmission of monitored data 112 on SDA line 104A.

[0051] In some examples, logic circuitry 104 may include a counter block 516, which state machine 504 can use to count the bit positions of the current data word of monitored data 112 on SDA line 104A. The state machine can thus identify the ACK / NACK bit positions of the current data word of monitored data 112 on SDA line 104A. Subsequently, when the ACK / NACK bit positions of the current data word of monitored data 112 on SDA line 104A are identified, the state machine can induce a stop condition on the data bus. In some examples, the state machine can induce a low-to-high transition of the voltage level on SDA line 104A during a high voltage level on SCL line 204B.

[0052] Logic circuit 104 can induce a stop condition on data bus 104 in any of a variety of different ways. In some examples, the logic circuit can instruct circuit 102 to assert a stop condition on data bus 104. Specifically, for example, state machine 504 can use test SCL and SDA test coverage to induce circuit 102 to assert a stop condition.

[0053] In some examples, the logic circuitry may assert a stop condition on the data bus 104. In some of these examples, the controller 100 includes a second 2:1 multiplexer 518, and the second 2:1 multiplexer 518 may include an input line coupled to the SDA_OUT line of circuitry 102 and an output line coupled to the output SDA pad buffer 108 to allow circuitry 102 to provide output data 110 for transmission to the SDA line 104A via the output SDA pad buffer 108.

[0054] The second 2:1 multiplexer 518 may also include a second input line (SDA_OVRD) and a selection line (SDA_OVRD_EN) coupled to a corresponding output of the pad buffer control block 516. The selection line allows the pad buffer control block 516 to select either a first input line or a second input line of the second 2:1 multiplexer 518. The pad buffer control block 516 can select the first input line to allow circuitry 102 to provide data to the output SDA pad buffer 108, such as to drive data to the SDA pad buffer 108 in a write state. When a CE1 error flag is detected, state machine 504 can control the pad buffer control block 516 to select the second input line of the second 2:1 multiplexer 518, thereby connecting the second input line of the second 2:1 multiplexer to the output SDA pad buffer 108. The second 2:1 multiplexer 518 can provide a coverage signal on the second input line of the second 2:1 multiplexer to cause a low-to-high transition of the voltage level on the SDA line 104A during a high voltage level on the SCL line 204B, and thereby assert a stop condition on the data bus 104.

[0055] After, simultaneously with, or immediately before the stop condition is triggered, state machine 504 can assert an enable signal to multiplexer 510, clear D flip-flop 512, and signal pad buffer control block 516 to reselect the first input of 2:1 multiplexer 514 to enable output SDA pad buffer 108 of circuit 102 again.

[0056] Figures 6A to 6H This is a flowchart illustrating various steps in a method 600 implemented according to various examples. The method includes providing output data from a circuit for transmission via an Output Serial Data (SDA) pad buffer to the SDA line of a two-wire shared serial data bus, such as... Figure 6AAs shown in box 602. Subsequently, via external logic circuitry, the method includes monitoring data on the SDA line as output data is transmitted to the SDA line, as shown in box 604. The method includes comparing the monitored data on the SDA line with the output data to detect an error condition when the monitored data on the SDA line differs from the output data, as shown in box 606. Based on the detected error condition, the method includes disabling the output SDA pad buffer for the current byte of output data provided by the circuitry, and subsequently inducing a stop condition on the data bus, as shown in boxes 608 and 610.

[0057] In some examples, method 600 includes filtering noise from the data on the SDA line to produce filtered data, such as Figure 6B As shown in box 612. In some of these examples, the monitored data is filtered data.

[0058] In some examples, monitoring data on the SDA line at box 604 includes an indication that an address header has been sent on the SDA line, such as... Figure 6C As shown in box 614. In some of these examples, monitoring the data on the SDA line also includes monitoring one or more data words following the address header in the data on the SDA line, as shown in box 616.

[0059] In some examples, comparing the monitored data on the SDA line with the output data at block 606 includes performing a bit-by-bit comparison of one or more data words of the monitored data on the SDA line with one or more data words of the output data (i.e., one or more data words output by circuit 102), such as... Figure 6D As shown in box 618. When one or more data words of the monitored data on the bit-by-bit comparison indicator SDA line differ from one or more data words of the output data, a flag is set to indicate that an error condition has been detected, as shown in box 620. In some of these examples, when the flag is set, the output SDA pad buffer is disabled at box 608, and a stop condition is subsequently caused at box 610.

[0060] In some examples, the output SDA pad buffer is a tri-state buffer with an enable / disable input, which disables the output SDA pad buffer at block 608 via the enable / disable input.

[0061] In some examples, a stop condition is caused on the data bus at box 610 so that the target terminates the transmission of the monitored data on the SDA line.

[0062] In some examples, the stop condition at box 610 includes counting the bit positions of the current data word of the monitored data on the SDA line to identify the acknowledgment / negative acknowledgment (ACK / NACK) bit positions of the current data word of the monitored data on the SDA line, such as... Figure 6E As shown in box 622. In some of these examples, a stop condition on the data bus is triggered when the ACK / NACK bit position of the current data word of the monitored data on the SDA line is identified, as shown in box 624.

[0063] In some examples, the data bus includes an SDA line and a serial clock (SCL) line. In some of these examples, the stopping condition at block 610 causes a low-to-high transition of the voltage level on the SDA line during a high voltage level on the SCL line, such as... Figure 6F As shown in box 626.

[0064] In some examples, the stop condition on the data bus caused at block 610 includes a stop condition asserted on the data bus by a logic circuit indicating that the circuitry has made a stop condition, such as... Figure 6G As shown in box 628.

[0065] In some examples, the stop condition on the data bus at block 610 includes the stop condition on the data bus being asserted by logic circuitry, such as... Figure 6H As shown in box 630.

[0066] As explained above and reiterated below, this disclosure includes, but is not limited to, the following specific examples.

[0067] Clause 1. A controller comprising: a serial data (SDA) line interface for connecting the controller to an SDA line of a two-wire shared serial data bus, the SDA line interface including an output SDA pad buffer; circuitry for providing output data for transmission to the SDA line via the output SDA pad buffer; and logic circuitry external to the circuitry, the logic circuitry being configured at least to: monitor data on the SDA line while the output data is being transmitted to the SDA line; compare the monitored data on the SDA line with the output data to detect an error condition when the monitored data on the SDA line differs from the output data; and, based on the detected error condition, disable the output SDA pad buffer for the current byte of the output data provided by the circuitry, and subsequently cause a stop condition on the data bus.

[0068] Clause 2. The controller according to Clause 1, wherein the SDA line interface includes an input SDA pad buffer for receiving monitored data on the SDA line, the input SDA pad buffer being used to filter out noise in the monitored data on the SDA line to produce filtered data, and the monitored data being the filtered data.

[0069] Clause 3. The controller according to Clause 1 or Clause 2, wherein the logic circuitry includes a state machine and a detector for monitoring the data on the SDA line, the state machine being configured to at least: receive an indication that an address header on the SDA line has been sent; and enable the detector to monitor one or more data words in the data on the SDA line following the address header.

[0070] Clause 4. The controller according to any one of Clauses 1 to 3, wherein the logic circuitry includes a detector for comparing monitored data on the SDA line with the output data, the detector comprising: a logic gate for performing a bit-by-bit comparison of one or more data words of the monitored data on the SDA line with one or more data words of the output data; and one or more sequential logic elements for setting a flag to indicate that the error condition has been detected when the bit-by-bit comparison indicates that the one or more data words of the monitored data on the SDA line are different from the one or more data words of the output data, and wherein, when the flag is set, the logic circuitry disables the output SDA pad buffer and subsequently causes the stop condition.

[0071] Clause 5. The controller according to any one of Clauses 1 to 4, wherein the output SDA pad buffer is a tri-state buffer having an enable / disable input, and the logic circuit disables the output SDA pad buffer via the enable / disable input.

[0072] Clause 6. The controller according to any one of Clauses 1 to 5, wherein the logic circuitry is configured to cause the stop condition on the data bus such that the target terminates the transmission of the data on the SDA line.

[0073] Clause 7. The controller according to any one of Clauses 1 to 6, wherein the logic circuitry for inducing the stop condition includes the logic circuitry performing the following operations: counting the bit positions of the current data word of the monitored data on the SDA line to identify the ACK / NACK bit positions of the current data word of the monitored data on the SDA line; and inducing the stop condition on the data bus when the ACK / NACK bit positions of the current data word of the monitored data on the SDA line are identified.

[0074] Clause 8. The controller according to any one of Clauses 1 to 7, wherein the data bus includes the SDA line and the serial clock (SCL) line; and wherein the logic circuitry for causing the stop condition on the data bus includes the logic circuitry for causing a low-to-high transition of the voltage level on the SDA line during a high voltage level on the SCL line.

[0075] Clause 9. The controller according to any one of Clauses 1 to 8, wherein the logic circuitry for causing the stop condition on the data bus includes the logic circuitry for instructing the circuitry to assert the stop condition on the data bus.

[0076] Clause 10. The controller according to any one of Clauses 1 to 9, wherein the logic circuitry for causing the stop condition on the data bus includes the logic circuitry for asserting the stop condition on the data bus.

[0077] Clause 11. A method comprising: providing output data from circuitry for transmission via an Output Serial Data (SDA) pad buffer to an SDA line of a two-wire shared serial data bus; and monitoring data on the SDA line as the output data is transmitted to the SDA line via logic circuitry external to the circuitry; comparing the monitored data on the SDA line with the output data to detect an error condition when the monitored data on the SDA line differs from the output data; and, based on the detected error condition, disabling the output SDA pad buffer for the current byte of the output data provided by the circuitry, and subsequently inducing a stop condition on the data bus.

[0078] Clause 12. The method according to Clause 11, the method comprising filtering noise from the data on the SDA line to produce filtered data, wherein the monitored data is the filtered data.

[0079] Clause 13. The method according to Clause 11 or Clause 12, wherein monitoring the data on the SDA line comprises: receiving an indication that an address header on the SDA line has been sent; and monitoring one or more data words following the address header in the data on the SDA line.

[0080] Clause 14. The method according to any one of Clauses 11 to 13, wherein comparing the monitored data on the SDA line with the output data comprises: performing a bit-by-bit comparison of one or more data words of the monitored data on the SDA line with one or more data words of the output data; and setting a flag to indicate that the error condition has been detected when the bit-by-bit comparison indicates that the one or more data words of the monitored data on the SDA line are different from the one or more data words of the output data, and wherein when the flag is set, the output SDA pad buffer is disabled, and subsequently the stop condition is triggered.

[0081] Clause 15. The method according to any one of Clauses 11 to 14, wherein the output SDA pad buffer is a tri-state buffer having an enable / disable input, the output SDA pad buffer being disabled via the enable / disable input.

[0082] Clause 16. The method according to any one of Clauses 11 to 15, wherein the stop condition on the data bus is caused such that the target terminates the transmission of the monitored data on the SDA line.

[0083] Clause 17. The method according to any one of Clauses 11 to 16, wherein causing the stop condition comprises: counting the bit positions of the current data word of the monitored data on the SDA line to identify the ACK / NACK bit positions of the current data word of the monitored data on the SDA line; and causing the stop condition on the data bus when the ACK / NACK bit positions of the current data word of the monitored data on the SDA line are identified.

[0084] Clause 18. The method according to any one of Clauses 11 to 17, wherein the data bus includes the SDA line and the serial clock (SCL) line, and wherein the stopping condition causing the data bus includes causing a low-to-high transition of the voltage level on the SDA line during a high voltage level on the SCL line.

[0085] Clause 19. The method according to any one of Clauses 11 to 18, wherein causing the stop condition on the data bus includes the logic circuit instructing the circuit to assert the stop condition on the data bus.

[0086] Clause 20. The method according to any one of Clauses 11 to 19, wherein causing the stop condition on the data bus includes asserting the stop condition on the data bus by the logic circuitry.

[0087] Benefiting from the teachings presented in the foregoing description and associated drawings, those skilled in the art to which this disclosure pertains will conceive of numerous modifications and other embodiments of this disclosure set forth herein. Therefore, it should be understood that this disclosure is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Furthermore, although the foregoing description and associated drawings describe exemplary embodiments in the context of certain example combinations of elements and / or functions, it should be understood that different combinations of elements and / or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, combinations different from those expressly described above are also contemplated, for example, as may be set forth in some of the appended claims. Although specific terminology is used herein, it is used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A controller, the controller comprising: A serial data (SDA) line interface for connecting the controller to an SDA line of a two-wire shared serial data bus, the SDA line interface including an output SDA pad buffer; A circuit for providing output data for transmission to the SDA line via the output SDA pad buffer; and A logic circuit, external to the circuit, is at least used for: Monitor the data on the SDA line while the output data is being transmitted to the SDA line; The monitored data on the SDA line is compared with the output data to detect error conditions when the monitored data on the SDA line differs from the output data. And based on the detected error conditions, For the current byte of the output data provided by the circuit, disable the output SDA pad buffer, and subsequently trigger a stop condition on the data bus.

2. The controller of claim 1, wherein the SDA line interface includes an input SDA pad buffer for receiving monitored data on the SDA line, the input SDA pad buffer being used to filter out noise in the monitored data on the SDA line to generate filtered data, and the monitored data being the filtered data.

3. The controller of claim 1, wherein the logic circuit includes a state machine and a detector, the detector being used to monitor the data on the SDA line, and the state machine being used at least for: Receive an indication that the address header on the SDA line has been sent; and This enables the detector to monitor one or more data words following the address header in the data on the SDA line.

4. The controller of claim 1, wherein the logic circuitry includes a detector for comparing monitored data on the SDA line with the output data, the detector comprising: A logic gate, the logic gate being used to perform a bit-by-bit comparison between one or more data words of the monitored data on the SDA line and one or more data words of the output data; and One or more timing logic elements, the one or more timing logic elements being configured to set a flag to indicate that an error condition has been detected when the bit-by-bit comparison indicates that the one or more data words of the monitored data on the SDA line are different from the one or more data words of the output data, and When the flag is set, the logic circuit disables the output SDA pad buffer and subsequently triggers the stop condition.

5. The controller of claim 1, wherein the output SDA pad buffer is a tri-state buffer having an enable / disable input, and the logic circuitry is configured to disable the output SDA pad buffer via the enable / disable input.

6. The controller of claim 1, wherein the logic circuitry is configured to cause the stop condition on the data bus to cause the target to terminate the transmission of data on the SDA line.

7. The controller of claim 1, wherein the logic circuitry for inducing the stop condition includes the logic circuitry performing the following operations: The bit positions of the current data word of the monitored data on the SDA line are counted to identify the acknowledgment / negative acknowledgment (ACK / NACK) bit positions of the current data word of the monitored data on the SDA line; and The stop condition on the data bus is triggered when the position of the ACK / NACK bit of the current data word of the monitored data on the SDA line is identified.

8. The controller of claim 1, wherein the data bus comprises the SDA line and the serial clock (SCL) line; and The logic circuitry used to cause the stop condition on the data bus includes the logic circuitry causing a low-to-high transition of the voltage level on the SDA line during a high voltage level on the SCL line.

9. The controller of claim 1, wherein the logic circuitry for causing the stop condition on the data bus includes the logic circuitry for instructing the circuitry to assert the stop condition on the data bus.

10. The controller of claim 1, wherein the logic circuitry for causing the stop condition on the data bus includes the logic circuitry for asserting the stop condition on the data bus.

11. A method, the method comprising: Output data is provided from the circuit for transmission via the Output Serial Data (SDA) pad buffer to the SDA line of the two-wire shared serial data bus; And through logic circuits outside the circuit, Monitor the data on the SDA line while the output data is being transmitted to the SDA line; The monitored data on the SDA line is compared with the output data to detect error conditions when the monitored data on the SDA line differs from the output data. And based on the detected error conditions, For the current byte of the output data provided by the circuit, disable the output SDA pad buffer, and This then triggers a stop condition on the data bus.

12. The method of claim 11, the method comprising filtering noise from the data on the SDA line to generate filtered data, and wherein the monitored data is the filtered data.

13. The method of claim 11, wherein monitoring the data on the SDA line comprises: Receive an indication that the address header on the SDA line has been sent; as well as Monitor one or more data words following the address header in the data on the SDA line.

14. The method of claim 11, wherein comparing the monitored data on the SDA line with the output data comprises: Perform a bit-by-bit comparison between one or more data words of the monitored data on the SDA line and one or more data words of the output data; as well as When the bit-by-bit comparison indicates that one or more data words of the monitored data on the SDA line are different from one or more data words of the output data, a flag is set to indicate that the error condition has been detected, and When the flag is set, the output SDA pad buffer is disabled, which subsequently triggers the stop condition.

15. The method of claim 11, wherein the output SDA pad buffer is a tri-state buffer having an enable / disable input, and the output SDA pad buffer is disabled via the enable / disable input.

16. The method of claim 11, wherein the stop condition on the data bus is triggered to cause the target to terminate the transmission of monitored data on the SDA line.

17. The method of claim 11, wherein the stopping condition comprises: The bit positions of the current data word of the monitored data on the SDA line are counted to identify the acknowledgment / negative acknowledgment (ACK / NACK) bit positions of the current data word of the monitored data on the SDA line. as well as The stop condition on the data bus is triggered when the position of the ACK / NACK bit of the current data word of the monitored data on the SDA line is identified.

18. The method of claim 11, wherein the data bus comprises the SDA line and the serial clock (SCL) line, and The stop condition that causes the data bus includes a low-to-high voltage transition on the SDA line during a high voltage level on the SCL line.

19. The method of claim 11, wherein causing the stop condition on the data bus includes the logic circuit instructing the circuit to assert the stop condition on the data bus.

20. The method of claim 11, wherein causing the stop condition on the data bus includes asserting the stop condition on the data bus by the logic circuitry.

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