Display panel and display device

Abstract

The invention relates to the technical field of display, and provides a display panel and a display device.The display panel comprises a substrate, a plurality of light-emitting units and a plurality of pixel driving circuits, the pixel driving circuits are used for driving the light-emitting units to emit light, and orthographic projections of the pixel driving circuits on the substrate are distributed in an array mode in the row and column directions; wherein the pixel driving circuit comprises a driving transistor and a capacitor, a first electrode of the driving transistor is connected with a first power line, and a second electrode is connected with a light-emitting unit; the capacitor is connected between the grid electrode of the driving transistor and the second electrode of the driving transistor; in the pixel driving circuits located in the same row, at least parts of orthographic projections of at least one group of adjacent two pixel driving circuits on the substrate are arranged in a mirror symmetry mode relative to a symmetry axis extending in the column direction. The pixel driving circuit has a relatively high integration level.

Description

Display panel, display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, display panels include pixel driving circuits, which in turn include driving transistors. Display panels using oxide transistors as driving transistors have advantages such as high uniformity and low manufacturing cost. However, pixel driving circuits using oxide transistors as driving transistors suffer from low space utilization.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0006] Substrate;

[0007] Multiple light-emitting units;

[0008] Multiple pixel driving circuits are provided to drive the light-emitting unit to emit light, and the orthogonal projections of the multiple pixel driving circuits on the substrate are arranged in an array in the row and column directions.

[0009] The pixel driving circuit includes a driving transistor and a capacitor. The first electrode of the driving transistor is connected to a first power supply line, and the second electrode is connected to the light-emitting unit.

[0010] The capacitor is connected between the gate of the driving transistor and the second electrode of the driving transistor;

[0011] In the pixel driving circuits located in the same row, there is at least one set of two adjacent pixel driving circuits whose orthogonal projections on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

[0012] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuit groups, and the orthographic projections of the plurality of pixel driving circuit groups on the substrate are arrayed along the row and column directions;

[0013] The pixel driving circuit group includes a plurality of pixel driving circuits that are adjacent in the row direction. In the same pixel driving circuit group, there is at least one set of two adjacent pixel driving circuits whose orthogonal projections on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

[0014] In one exemplary embodiment of this disclosure, at least a portion of the pixel driving circuit group includes three adjacent pixel driving circuits in the row direction, the three pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit;

[0015] The second pixel driving circuit is located between the first pixel driving circuit and the third pixel driving circuit, and the orthographic projections of the first pixel driving circuit and the second pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

[0016] In one exemplary embodiment of this disclosure, at least a portion of the pixel driving circuit group includes three adjacent pixel driving circuits in the row direction, the three pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit;

[0017] The second pixel driving circuit is located between the first pixel driving circuit and the third pixel driving circuit, and the orthographic projections of the second pixel driving circuit and the third pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

[0018] In an exemplary embodiment of this disclosure, at least a portion of the pixel driving circuit group includes six adjacent pixel driving circuits in the row direction, the six pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, a third pixel driving circuit, a fourth pixel driving circuit, a fifth pixel driving circuit, and a sixth pixel driving circuit.

[0019] The first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit are sequentially distributed along the row direction on the orthogonal projection of the substrate.

[0020] Wherein, the orthographic projections of the first pixel driving circuit and the second pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction; the orthographic projections of the third pixel driving circuit and the fourth pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction; and the orthographic projections of the fifth pixel driving circuit and the sixth pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

[0021] In an exemplary embodiment of this disclosure, at least a portion of the pixel driving circuit group includes six adjacent pixel driving circuits in the row direction, the six pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, a third pixel driving circuit, a fourth pixel driving circuit, a fifth pixel driving circuit, and a sixth pixel driving circuit.

[0022] The first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit are sequentially distributed along the row direction on the orthogonal projection of the substrate.

[0023] The orthographic projections of the first pixel driving circuit and the second pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction. The orthographic projections of the fourth pixel driving circuit and the fifth pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

[0024] In an exemplary embodiment of this disclosure, at least a portion of the pixel driving circuit group includes six adjacent pixel driving circuits in the row direction, the six pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, a third pixel driving circuit, a fourth pixel driving circuit, a fifth pixel driving circuit, and a sixth pixel driving circuit.

[0025] The first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit are sequentially distributed along the row direction on the orthogonal projection of the substrate.

[0026] The orthographic projections of the second pixel driving circuit and the third pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction. The orthographic projections of the fifth pixel driving circuit and the sixth pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

[0027] In one exemplary embodiment of this disclosure, the display panel includes three light-emitting units of different colors: a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit. Light-emitting units of the same color are connected to pixel driving circuits located in the same column, and the pixel driving circuits connected to the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are distributed sequentially in the row direction.

[0028] In one exemplary embodiment of this disclosure, in a two-pixel driving circuit in which the orthographic projection on the substrate is at least partially mirror-symmetrical, the channels of the same type of transistor are arranged mirror-symmetrically with respect to an axis of symmetry extending along the column direction.

[0029] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes one or more switching transistors, at least some of the same type of switching transistors that are orthographically mirror-symmetrical on the substrate share the same conductive portion as a gate.

[0030] In one exemplary embodiment of this disclosure, the pixel driving circuit includes two capacitors, namely a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0031] One or more switching transistors include a first transistor, a second transistor, and a fourth transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the first electrode of the first capacitor;

[0032] The first terminal of the second transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor;

[0033] The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the gate of the driving transistor.

[0034] Two first transistors, which are mirror-symmetrical in orthographic projection on the substrate, share the same conductive portion as their gate; two second transistors, which are mirror-symmetrical in orthographic projection on the substrate, share the same conductive portion as their gate; and two fourth transistors, which are mirror-symmetrical in orthographic projection on the substrate, share the same conductive portion as their gate.

[0035] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to a second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit;

[0036] The display panel also includes:

[0037] An active layer is located on one side of the substrate. The active layer includes a seventh active portion and a sixteenth active portion. The seventh active portion is used to form the channel region of the seventh transistor. The seventh active portion, which is mirror-symmetrical to the orthographic projection on the substrate, is connected through the sixteenth active portion.

[0038] In one exemplary embodiment of this disclosure, the pixel driving circuit includes two capacitors, namely a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0039] The display panel also includes:

[0040] A first gate layer is located on one side of the substrate. The first gate layer includes a first conductive portion and a second conductive portion connected in the same layer. The first conductive portion is used to form a first electrode of the first capacitor, and the second conductive portion is used to form a first electrode of the second capacitor.

[0041] A second gate layer is located on the side of the first gate layer opposite to the substrate. The second gate layer includes a sixth conductive portion and a seventh conductive portion. The orthographic projection of the sixth conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The sixth conductive portion is used to form the second electrode of the first capacitor. The orthographic projection of the seventh conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate at least partially overlap. The seventh conductive portion is used to form the second electrode of the second capacitor.

[0042] The orthographic projections of the sixth conductive part and the seventh conductive part on the substrate are distributed along the column direction.

[0043] In one exemplary embodiment of this disclosure, the pixel driving circuit includes two capacitors, namely a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0044] The display panel also includes:

[0045] A second gate layer is located on one side of the substrate. The second gate layer includes a sixth conductive portion, which is used to form the second electrode of the first capacitor.

[0046] An active layer is located on the side of the second gate layer away from the substrate. The active layer includes a third active portion, which is used to form the channel region of the driving transistor.

[0047] Wherein, the orthogonal projection of the sixth conductive part on the substrate covers the orthogonal projection of the third active part on the substrate.

[0048] In one exemplary embodiment of this disclosure, the pixel driving circuit includes two capacitors, a fifth transistor, and a sixth transistor. The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor.

[0049] The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the third enable signal line.

[0050] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the fourth enable signal line.

[0051] The display panel also includes:

[0052] The second gate layer is located on one side of the substrate. The second gate layer includes a sixth conductive portion, a seventh conductive portion, the third enable signal line, and a fourth enable signal line. The sixth conductive portion is used to form the second electrode of the first capacitor, the seventh conductive portion is used to form the second electrode of the second capacitor, a portion of the structure of the third enable signal line is used to form the bottom gate of the fifth transistor, and a portion of the structure of the fourth enable signal line is used to form the bottom gate of the sixth transistor.

[0053] Wherein, the orthographic projections of the third enable signal line and the fourth enable signal line on the substrate extend along the row direction. In the same pixel driving circuit, the orthographic projections of the sixth conductive part and the seventh conductive part on the substrate are located between the orthographic projections of the third enable signal line and the fourth enable signal line on the substrate.

[0054] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0055] The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the first enable signal line.

[0056] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second enable signal line.

[0057] The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the first reset signal line.

[0058] The display panel also includes:

[0059] An active layer, wherein a portion of the structure of the active layer is used to form the channel regions of the driving transistor, the fifth transistor, the sixth transistor, and the seventh transistor;

[0060] The third gate layer is located on the side of the active layer away from the substrate. The third gate layer includes a first enable signal line, a second enable signal line, a first reset signal line, and an eleventh conductive portion. A portion of the structure of the first enable signal line is used to form the top gate of the fifth transistor, a portion of the structure of the second enable signal line is used to form the top gate of the sixth transistor, a portion of the structure of the first reset signal line is used to form the top gate of the seventh transistor, and the eleventh conductive portion is used to form the top gate of the driving transistor.

[0061] In the same pixel driving circuit, the orthographic projections of the first enable signal line, the second enable signal line, and the first reset signal line on the substrate extend along the row direction and are distributed at intervals along the column direction. The orthographic projection of the eleventh conductive part on the substrate is located between the orthographic projections of the first enable signal line and the second enable signal line on the substrate. The orthographic projection of the first reset signal line on the substrate is located on the side of the orthographic projection of the second enable signal line on the substrate that is away from the orthographic projection of the eleventh conductive part on the substrate.

[0062] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, a second transistor, and a fourth transistor;

[0063] The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor.

[0064] The first terminal of the second transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor;

[0065] The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the gate of the driving transistor.

[0066] The display panel also includes:

[0067] An active layer, wherein a portion of the structure of the active layer is used to form the channel regions of the first transistor, the second transistor, and the fourth transistor;

[0068] The third gate layer is located on the side of the active layer away from the substrate. The third gate layer includes an eighth conductive portion, a ninth conductive portion, and a tenth conductive portion. The eighth conductive portion is used to form the top gate of the first transistor, the ninth conductive portion is used to form the top gate of the second transistor, and the tenth conductive portion is used to form the top gate of the fourth transistor.

[0069] The first source / drain layer is located on the side of the third gate layer opposite to the substrate. The first source / drain layer includes a gate line, a second reset signal line, and a third reset signal line. The gate line is connected to the tenth conductive part through a via. The second reset signal line is connected to the ninth conductive part through a via. The third reset signal line is connected to the eighth conductive part through a via. The orthogonal projection of the gate line, the second reset signal line, and the third reset signal line on the substrate extends along the row direction.

[0070] In the same pixel driving circuit, the orthographic projection of the gate line on the substrate is located between the orthographic projection of the first enable signal line on the substrate and the orthographic projection of the eleventh conductive part on the substrate; the orthographic projection of the second reset signal line on the substrate is located between the orthographic projection of the eleventh conductive part on the substrate and the orthographic projection of the second enable signal line on the substrate; and the orthographic projection of the third reset signal line on the substrate is located between the orthographic projection of the second reset signal line on the substrate and the orthographic projection of the second enable signal line on the substrate.

[0071] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0072] The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor.

[0073] The first terminal of the second transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor;

[0074] The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the gate of the driving transistor.

[0075] The first terminal of the fifth transistor is connected to the first power supply line, and the second terminal is connected to the first terminal of the driving transistor.

[0076] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit.

[0077] The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit.

[0078] The display panel also includes:

[0079] An active layer, the active layer including a first main active portion and a second main active portion, wherein the orthographic projection of the first main active portion on the substrate and the orthographic projection of the second main active portion on the substrate extend along the column direction and are spaced apart in the row direction;

[0080] The first main active portion includes a first active portion, a second active portion, and a fourth active portion that are sequentially spaced along the column direction. The first active portion is used to form the channel region of the first transistor, the second active portion is used to form the channel region of the second transistor, and the fourth active portion is used to form the channel region of the fourth transistor.

[0081] The second main active portion includes a sixth active portion, a third active portion, and a fifth active portion that are sequentially spaced along the column direction. The sixth active portion is used to form the channel region of the sixth transistor, the third active portion is used to form the channel region of the driving transistor, and the fifth active portion is used to form the channel region of the fifth transistor.

[0082] In one exemplary embodiment of this disclosure, the display panel further includes:

[0083] A first source / drain layer is located on one side of the substrate. The first source / drain layer includes multiple second power lines. The orthographic projection of the multiple second power lines on the substrate extends along the row direction and is spaced apart along the column direction. The second power lines are connected to the second electrode of the light-emitting unit.

[0084] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple second power connection lines. The orthographic projection of the multiple second power connection lines on the substrate extends along the column direction and is spaced apart along the row direction.

[0085] The second power line is connected to the intersecting second power connection line via a via.

[0086] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0087] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0088] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0089] Figure 1 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0090] Figure 2 is a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 1;

[0091] Figure 3 is a structural layout of an exemplary embodiment of the display panel of this disclosure;

[0092] Figure 4 is a structural layout of the first gate layer in the display panel shown in Figure 3;

[0093] Figure 5 is a structural layout of the second gate layer in the display panel shown in Figure 3;

[0094] Figure 6 is a structural layout of the active layer in the display panel shown in Figure 3;

[0095] Figure 7 is a structural layout of the third gate layer in the display panel shown in Figure 3;

[0096] Figure 8 is a structural layout of the first source / drain layer in the display panel shown in Figure 3;

[0097] Figure 9 is a structural layout of the second source / drain layer in the display panel shown in Figure 3;

[0098] Figure 10 is a structural layout of the electrode layer in the display panel shown in Figure 3;

[0099] Figure 11 is a structural layout of the first gate layer and the second gate layer in the display panel shown in Figure 3;

[0100] Figure 12 is a structural layout of the first gate layer, the second gate layer, and the active layer in the display panel shown in Figure 3;

[0101] Figure 13 is a structural layout of the first gate layer, the second gate layer, the active layer, and the third gate layer in the display panel shown in Figure 3;

[0102] Figure 14 is a structural layout of the first gate layer, second gate layer, active layer, third gate layer, and first source / drain layer in the display panel shown in Figure 3.

[0103] Figure 15 is a structural layout of the first gate layer, second gate layer, active layer, third gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 3.

[0104] Figure 16 is a partial cross-sectional view of the display panel shown in Figure 3, cut along the dashed line AA;

[0105] Figure 17 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0106] Figure 18 is a structural layout of the first gate layer in the display panel shown in Figure 17;

[0107] Figure 19 is a structural layout of the second gate layer in the display panel shown in Figure 17;

[0108] Figure 20 is a structural layout of the active layer in the display panel shown in Figure 17;

[0109] Figure 21 is a structural layout of the third gate layer in the display panel shown in Figure 17;

[0110] Figure 22 is a structural layout of the first source / drain layer in the display panel shown in Figure 17;

[0111] Figure 23 is a structural layout of the second source / drain layer in the display panel shown in Figure 17;

[0112] Figure 24 is a structural layout of the electrode layer in the display panel shown in Figure 17;

[0113] Figure 25 is a structural layout of the first gate layer and the second gate layer in the display panel shown in Figure 17;

[0114] Figure 26 is a structural layout of the first gate layer, the second gate layer, and the active layer in the display panel shown in Figure 17;

[0115] Figure 27 is a structural layout of the first gate layer, the second gate layer, the active layer, and the third gate layer in the display panel shown in Figure 17;

[0116] Figure 28 is a structural layout of the first gate layer, second gate layer, active layer, third gate layer, and first source / drain layer in the display panel shown in Figure 17;

[0117] Figure 29 is a structural layout of the first gate layer, second gate layer, active layer, third gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 17.

[0118] Figure 30 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0119] Figure 31 is a structural layout of the first gate layer in the display panel shown in Figure 30;

[0120] Figure 32 is a structural layout of the second gate layer in the display panel shown in Figure 30;

[0121] Figure 33 is a structural layout of the active layer in the display panel shown in Figure 30;

[0122] Figure 34 is a structural layout of the third gate layer in the display panel shown in Figure 30;

[0123] Figure 35 is a structural layout of the first source / drain layer in the display panel shown in Figure 30;

[0124] Figure 36 is a structural layout of the second source / drain layer in the display panel shown in Figure 30;

[0125] Figure 37 is a structural layout of the electrode layer in the display panel shown in Figure 30;

[0126] Figure 38 is a structural layout of the first gate layer and the second gate layer in the display panel shown in Figure 30;

[0127] Figure 39 is a structural layout of the first gate layer, the second gate layer, and the active layer in the display panel shown in Figure 30;

[0128] Figure 40 is a structural layout of the first gate layer, second gate layer, active layer and third gate layer in the display panel shown in Figure 30;

[0129] Figure 41 is a structural layout of the first gate layer, second gate layer, active layer, third gate layer, and first source / drain layer in the display panel shown in Figure 30.

[0130] Figure 42 is a structural layout of the first gate layer, second gate layer, active layer, third gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 30.

[0131] Figure 43 is a structural layout of another exemplary embodiment of the display panel of this disclosure;

[0132] Figure 44 is a structural layout of another exemplary embodiment of the display panel of this disclosure. Detailed Implementation

[0133] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0134] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0135] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0136] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0137] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0138] Figure 1 shows a schematic diagram of a pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. This pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes: multiple switching transistors, a driving transistor T3, a first capacitor C1, and a second capacitor C2. The multiple switching transistors include: a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the driving transistor T3 is connected to a first node N1, its first electrode is connected to a second node N2, and its second electrode is connected to a third node N3; the first electrode of the second capacitor C2 is connected to a fourth node N4, and its second electrode is connected to a first node N1; the first electrode of the first capacitor C1 is connected to a fourth node N4, and its second electrode is connected to a third node N3; the first electrode of the first transistor T1 is connected to a first initial signal terminal Vinit1, its second electrode is connected to a fourth node N4, and its gate is connected to a third reset signal terminal Re3; the first electrode of the second transistor T2 is connected to the first initial signal terminal Vinit1, its second electrode is connected to a first node N1, and its gate is connected to a second reset signal terminal Re2; the fourth transistor T3... The first electrode of transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the fifth node N5, and the gate is connected to the gate drive signal terminal Gate; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate is connected to the first enable signal terminal EM1; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the first electrode of the light-emitting unit L, and the gate is connected to the second enable signal terminal EM2; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the first reset signal terminal Re1; the second electrode of the light-emitting unit L is connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be an anode, and the second electrode can be a cathode.

[0139] As shown in Figure 1, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be N-type transistors.

[0140] Figure 2 shows the timing diagram of each node in one driving method of the pixel driving circuit shown in Figure 1. The driving method of this pixel driving circuit includes: reset stage t1, threshold compensation stage t2, data writing stage t3, and light emission stage t4.

[0141] During the reset phase t1: the first reset signal terminal Re1, the second reset signal terminal Re2, the third reset signal terminal Re3, and the second enable signal terminal EM2 output high-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on. The first initial signal terminal Vinit1 outputs the first initial signal to the first node N1 and the fourth node N4. The second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit L and the third node N3.

[0142] During the threshold compensation stage t2: the second reset signal terminal Re2, the third reset signal terminal Re3, and the first enable signal terminal EM1 output high-level signals, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, and the first power supply terminal VDD inputs the compensation voltage V1-Vth to the third node N3, where V1 is the voltage of the first initial signal and Vth is the threshold voltage of the driving transistor.

[0143] During the data writing phase t3: the third reset signal terminal Re3 and the gate drive signal terminal Gate output high-level signals, the first transistor T1 and the fourth transistor T4 are turned on, and the data signal terminal Da inputs a data signal to the first node N1. The voltage of the first node N1 is Vdata, and Vdata is the voltage of the data signal.

[0144] During the light-emitting stage t4: the first enable signal terminal EM1 and the second enable signal terminal EM2 output high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 increases the driving current to the light-emitting unit L. The output current of the driving transistor T3 is I = (μWCox / 2L)(Vgs-Vth). 2 =(μWCox / 2L)(Vdata-(V1-Vth)-Vth) 2 =(μWCox / 2L)(Vdata-V1) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current, where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor.

[0145] This exemplary embodiment also provides a display panel, which may include a first gate layer, a second gate layer, an active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer is disposed between the aforementioned layers. As shown in Figures 3-15, Figure 3 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 4 is a structural layout diagram of the first gate layer in the display panel shown in Figure 3; Figure 5 is a structural layout diagram of the second gate layer in the display panel shown in Figure 3; Figure 6 is a structural layout diagram of the active layer in the display panel shown in Figure 3; Figure 7 is a structural layout diagram of the third gate layer in the display panel shown in Figure 3; Figure 8 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 3; Figure 9 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 3; Figure 10 is a structural layout diagram of the electrode layer in the display panel shown in Figure 3; Figure 11 is a structural layout diagram of… Figure 3 shows the structural layout of the first gate layer and the second gate layer in the display panel shown in Figure 3. Figure 12 shows the structural layout of the first gate layer, the second gate layer, and the active layer in the display panel shown in Figure 3. Figure 13 shows the structural layout of the first gate layer, the second gate layer, the active layer, and the third gate layer in the display panel shown in Figure 3. Figure 14 shows the structural layout of the first gate layer, the second gate layer, the active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 3. Figure 15 shows the structural layout of the first gate layer, the second gate layer, the active layer, the third gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 3.

[0146] As shown in Figure 15, the display panel may include multiple pixel driving circuit groups Pz, which can be arrayed along the row direction X and the column direction Y. Each pixel driving circuit group includes three adjacent pixel driving circuits in the row direction X: a first pixel driving circuit Pix1, a second pixel driving circuit Pix2, and a third pixel driving circuit Pix3. The structure of the pixel driving circuit can be as shown in Figure 1.

[0147] As shown in Figure 15, at least a portion of the orthographic projections of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 onto the substrate are mirror-symmetrically arranged with respect to the axis of symmetry BB1 extending along the column direction Y.

[0148] This exemplary embodiment arranges at least a portion of the orthographic projections of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 onto the substrate in a mirror-symmetrical manner, thereby improving the integration density of the pixel driving circuit. Furthermore, if the values ​​of the first capacitor C1 and the second capacitor C2 are small, during the light-emitting phase, the voltage change at the first node N1 is less than the voltage change at the third node N3, resulting in some loss in the threshold compensation value. In this exemplary embodiment, the mirror-symmetrical arrangement of the pixel driving circuit can increase the values ​​of the first capacitor C1 and the second capacitor C2, thereby improving the aforementioned threshold compensation value problem.

[0149] As shown in Figures 3, 4, and 11, the first gate layer may include a first conductive portion 11, a second conductive portion 12, and a first via connection portion 13. The first conductive portion 11 is connected between the second conductive portion 12 and the first via connection portion 13. The first conductive portion 11 is used to form the first electrode of the first capacitor C1, and the second conductive portion 12 is used to form the first electrode of the second capacitor C2.

[0150] As shown in Figures 3, 5, and 11, the second gate layer includes: a third enable signal line 2EM1, a fourth enable signal line 2EM2, a fourth reset signal line 2Re1, a third conductive portion 23, a fourth conductive portion 24, a fifth conductive portion 25, a sixth conductive portion 26, and a seventh conductive portion 27. The orthogonal projections of the third enable signal line 2EM1, the fourth enable signal line 2EM2, and the fourth reset signal line 2Re1 onto the substrate extend along the row direction X. The third enable signal line 2EM1 provides the first enable signal terminal in Figure 1, the fourth enable signal line 2EM2 provides the second enable signal terminal in Figure 1, and the fourth reset signal line 2Re1 provides the first reset signal terminal in Figure 1. The sixth conductive portion 26 forms the second electrode of the first capacitor C1; the seventh conductive portion 27 forms the second electrode of the second capacitor C2.

[0151] As shown in Figures 3, 6, and 12, the active layer may include: a first main active unit 701, a second main active unit 702, a seventh active unit 77, and a sixteenth active unit 716. The first main active unit 701 includes: a first active unit 71, a second active unit 72, a fourth active unit 74, an eighth active unit 78, a ninth active unit 79, a tenth active unit 710, an eleventh active unit 711, and a twelfth active unit 712. The second main active unit 702 includes: a third active unit 73, a fifth active unit 75, a sixth active unit 76, a thirteenth active unit 713, a fourteenth active unit 714, and a fifteenth active unit 715. The first active portion 71 is used to form the channel region of the first transistor T1; the second active portion 72 is used to form the channel region of the second transistor T2; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 is connected to the end of the first active portion 71 away from the second active portion 72; and the ninth active portion 79 is connected to the first active portion 71 and the second active portion 72. Between the active portions 72, the tenth active portion 710 is connected between the second active portion 72 and the fourth active portion 74; the eleventh active portion 711 is connected between the tenth active portion 710 and the fourth active portion 74; the twelfth active portion 712 is connected to the end of the fourth active portion 74 away from the second active portion 72; the thirteenth active portion 713 is connected to the end of the fifth active portion 75 away from the third active portion 73; the fourteenth active portion 714 is connected between the third active portion 73 and the sixth active portion 76; the fifteenth active portion 715 is connected between the sixth active portion 76 and the seventh active portion 77; and the sixteenth active portion 716 is connected to the end of the seventh active portion 77 away from the sixth active portion 76. The active layer can be formed of indium gallium zinc oxide (IGaZn), and correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be N-type metal-oxide thin-film transistors.

[0152] As shown in Figures 3, 5, 6, and 12, the orthographic projection of the sixth conductive portion 26 on the substrate covers the orthographic projection of the third active portion 73 on the substrate. The sixth conductive portion 26 can shield the third active portion 73 from light to reduce the influence of light on the characteristics of the driving transistor T3. The orthographic projection of the third conductive portion 23 on the substrate covers the orthographic projection of the first active portion 71 on the substrate. The third conductive portion 23 is used to form the bottom gate of the first transistor T1. The orthographic projection of the fourth conductive portion 24 on the substrate covers the orthographic projection of the second active portion 72 on the substrate. The fourth conductive portion 24 is used to form the bottom gate of the second transistor T2. The orthographic projection of the fifth conductive portion 25 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate. The fifth conductive portion 25 is used to form the bottom gate of the fourth transistor T4. The orthogonal projection of the third enable signal line 2EM1 on the substrate can cover the orthogonal projection of the fifth active part 75 on the substrate. A portion of the structure of the third enable signal line 2EM1 can be used to form the bottom gate of the fifth transistor T5. The orthogonal projection of the fourth enable signal line 2EM2 on the substrate can cover the orthogonal projection of the sixth active part 76 on the substrate. A portion of the structure of the fourth enable signal line 2EM2 can be used to form the bottom gate of the sixth transistor T6. The orthogonal projection of the fourth reset signal line 2Re1 on the substrate can cover the orthogonal projection of the seventh active part 77 on the substrate. A portion of the structure of the fourth reset signal line 2Re1 can be used to form the bottom gate of the seventh transistor T7.

[0153] As shown in Figures 3, 5, 6, and 12, the orthographic projections of the sixth conductive portion 26 and the seventh conductive portion 27 on the substrate are distributed along the column direction. In the same pixel driving circuit, the orthographic projections of the sixth conductive portion 26 and the seventh conductive portion 27 on the substrate are located between the orthographic projections of the third enable signal line 2EM1 and the fourth enable signal line 2EM2 on the substrate.

[0154] As shown in Figures 3, 7, and 13, the third gate layer may include: a first enable signal line 3EM1, a second enable signal line 3EM2, a first reset signal line 3Re1, an eighth conductive portion 38, a ninth conductive portion 39, a tenth conductive portion 310, and an eleventh conductive portion 311. The first enable signal line 3EM1, the second enable signal line 3EM2, and the first reset signal line 3Re1 extend along the row direction X on the substrate. The first enable signal line 3EM1 provides the first enable signal terminal in Figure 1, the second enable signal line 3EM2 provides the second enable signal terminal in Figure 1, and the first reset signal line 3Re1 provides the first reset signal terminal in Figure 1. The first enable signal line 3EM1 and the third enable signal line 3EM2 can be connected via vias in the display area or the bezel area; the second enable signal line 3EM2 and the fourth enable signal line 2EM2 can be connected via vias in the display area or the bezel area; and the first reset signal line 3Re1 and the fourth reset signal line 2Re1 can be connected via vias in the display area or the bezel area.

[0155] As shown in Figures 3, 7, and 13, the orthogonal projection of the first enable signal line 3EM1 on the substrate can cover the orthogonal projection of the fifth active part 75 on the substrate. A portion of the structure of the first enable signal line 3EM1 can be used to form the top gate of the fifth transistor T5. The orthogonal projection of the second enable signal line 3EM2 on the substrate can cover the orthogonal projection of the sixth active part 76 on the substrate. A portion of the structure of the second enable signal line 3EM2 can be used to form the top gate of the sixth transistor T6. The orthogonal projection of the first reset signal line 3Re1 on the substrate can cover the orthogonal projection of the seventh active part 77 on the substrate. A portion of the structure of the first reset signal line 3Re1 can be used to form the top gate of the seventh transistor T7. The orthographic projection of the eighth conductive portion 38 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. The eighth conductive portion 38 is used to form the top gate of the first transistor T1. The orthographic projection of the ninth conductive portion 39 onto the substrate covers the orthographic projection of the second active portion 72 onto the substrate. The ninth conductive portion 39 is used to form the top gate of the second transistor. The orthographic projection of the tenth conductive portion 310 onto the substrate covers the orthographic projection of the fourth active portion 74 onto the substrate. The tenth conductive portion 310 is used to form the top gate of the fourth transistor T4. The orthographic projection of the eleventh conductive portion 311 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The eleventh conductive portion 311 is used to form the top gate of the driving transistor T3. This display panel can use the third gate layer as a mask to perform conductor processing on the active layer. That is, the area of ​​the active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the third gate layer forms a conductor structure.

[0156] As shown in Figures 3, 7, and 13, in the same pixel driving circuit, the orthographic projections of the first enable signal line 3EM1, the second enable signal line 3EM2, and the first reset signal line 3Re1 on the substrate extend along the row direction X and are sequentially spaced along the column direction Y. The orthographic projection of the eleventh conductive part 311 on the substrate is located between the orthographic projections of the first enable signal line 3EM1 and the second enable signal line 3EM2 on the substrate. The orthographic projection of the first reset signal line 3Re1 on the substrate is located on the side of the second enable signal line 3EM2 on the substrate away from the orthographic projection of the eleventh conductive part 311 on the substrate.

[0157] As shown in Figures 3, 8, and 14, the first source / drain layer may include: a first power supply line VDD, a gate line Gate, a second reset signal line Re2, a first initial signal line Vinit1, a third reset signal line Re3, a second initial signal line Vinit2, a second power supply line VSS, a first bridging section 41, a second bridging section 42, a third bridging section 43, a fourth bridging section 44, a fifth bridging section 45, and a sixth bridging section 46. The first power line VDD, gate line Gate, second reset signal line Re2, first initial signal line Vinit1, third reset signal line Re3, second initial signal line Vinit2, and second power line VSS are projected onto the substrate along the row direction X. The first power line VDD provides the first power supply terminal in Figure 1; the gate line Gate provides the gate drive signal terminal in Figure 1; the second reset signal line Re2 provides the second reset signal terminal in Figure 1; the first initial signal line Vinit1 provides the first initial signal terminal in Figure 1; the third reset signal line Re3 provides the third reset signal terminal in Figure 1; the second initial signal line Vinit2 provides the second initial signal terminal in Figure 1; and the second power line VSS provides the second power supply terminal in Figure 1. The first power line VDD is connected to the thirteenth active part 713 via a via to connect to the first terminal of the fifth transistor T5. The gate line Gate is connected to the fifth conductive part 25 and the tenth conductive part 310 via vias to connect the gate drive signal terminal and the bottom gate and top gate of the fourth transistor T4. The second reset signal line Re2 is connected to the fourth conductive part 24 and the ninth conductive part 39 through vias, respectively, to connect the second reset signal terminal and the bottom gate and top gate of the second transistor T2. The first initial signal line Vinit1 is connected to the ninth active part 79 through vias, to connect the first initial signal terminal and the first electrode of the second transistor T2 and the first electrode of the first transistor T1. The third reset signal line Re3 is connected to the third conductive part 23 and the eighth conductive part 38 through vias, respectively, to connect the third reset signal terminal and the bottom gate and top gate of the first transistor T1. The second initial signal line Vinit2 is connected to the sixteenth active part 716 through vias, to connect the second initial signal terminal and the first electrode of the seventh transistor T7. The first bridging part 41 can be connected to the twelfth active part 712 through vias, to connect the first electrode of the fourth transistor T4. The second bridging part 42 can be connected to the seventh conductive part 27 and the eleventh active part 711 through vias, respectively, to connect the second electrode of the second capacitor C2 and the second electrode of the fourth transistor T4 and the second electrode of the second transistor T2. The third bridging portion 43 can be connected to the eleventh conductive portion 311 and the tenth active portion 710 through vias, respectively, to connect the gate of the driving transistor T3 and the second terminal of the fourth transistor T4 and the second terminal of the second transistor T2. The fourth bridging portion 44 is connected to the fourteenth active portion 714 and the sixth conductive portion 26 through vias, respectively, to connect the second terminal of the driving transistor T3 and the second terminal of the first capacitor C1.The fifth bridging section 45 connects to the first via connection section 13 and the eighth active section 78 via vias, respectively, to connect the second electrode of the first transistor T1 and the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2. The sixth bridging section 46 connects to the fifteenth active section 715 via vias, to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0158] As shown in Figures 3, 8, and 14, in the same pixel driving circuit, the orthographic projection of the gate line Gate on the substrate is located between the orthographic projection of the first enable signal line 3EM1 on the substrate and the orthographic projection of the eleventh conductive part 311 on the substrate. The orthographic projection of the second reset signal line Re2 on the substrate is located between the orthographic projection of the eleventh conductive part 311 on the substrate and the orthographic projection of the second enable signal line 3EM2 on the substrate. The orthographic projection of the third reset signal line Re3 on the substrate is located between the orthographic projection of the second reset signal line Re2 on the substrate and the orthographic projection of the second enable signal line 3EM2 on the substrate.

[0159] As shown in Figures 3, 9, and 15, the second source / drain layer includes: a data line Da, a second power connection line 5VSS, a signal connection line Lx, and a seventh bridging portion 57. The orthographic projections of the data line Da, the second power connection line 5VSS, and the signal connection line Lx on the substrate extend along the column direction Y. The data line Da provides the data signal terminal shown in Figure 1. The second power connection line 5VSS is connected via a via to a second power line 4VSS that intersects with its orthographic projection on the substrate. The second power connection line 5VSS and the second power line 4VSS form a mesh structure at least in the display area. This mesh structure can be connected to a common cathode in the display panel to reduce the voltage difference of the second power terminals at different locations on the display panel. The common cathode in the display panel forms the cathode of the light-emitting unit, and the common cathode can be located on the side of the light-emitting unit L facing away from the substrate. The seventh bridging portion 57 can be connected to a sixth bridging portion 46 via a via. The signal connection line Lx can be any one of a first initial connection line, a second initial connection line, or a first power connection line. The first initial connection line can be connected to the intersecting first initial signal line via a via, the second initial connection line can be connected to the intersecting second initial signal line via a via, and the first power connection line can be connected to the intersecting first power line via a via. Each column of pixel driving circuits can be provided with one signal connection line Lx, and the display panel can be provided with multiple signal connection lines Lx. Some signal connection lines Lx can form the first initial connection line, some signal connection lines Lx can form the second initial connection line, and some signal connection lines Lx can form the first power connection line. For example, the orthographic projections of the first initial connection line, the second initial connection line, and the first power connection line on the substrate can be alternately distributed along the row direction.

[0160] As shown in Figures 3 and 10, the electrode layer includes multiple electrode sections, including a first electrode section R, a second electrode section G, and a third electrode section B. The first electrode section R forms the first electrode of the red light-emitting unit, the second electrode section G forms the first electrode of the green light-emitting unit, and the third electrode section B forms the first electrode of the blue light-emitting unit. Each electrode section is connected to its corresponding seventh bridge section 57 via vias to connect the second electrode of the sixth transistor T6 and the first electrode of the light-emitting unit. Specifically, the first pixel driving circuit Pix1 drives the red light-emitting unit, the second pixel driving circuit Pix2 drives the green light-emitting unit, and the third pixel driving circuit Pix3 drives the blue light-emitting unit.

[0161] Figure 16 shows a partial cross-sectional view of the display panel shown in Figure 3, cut along the dashed line AA. The display panel may further include a first insulating layer 101, a buffer layer 102, a second insulating layer 103, a dielectric layer 104, a passivation layer 105, a first planarization layer 106, and a second planarization layer 107. The substrate 100, first gate layer, first insulating layer 101, second gate layer, buffer layer 102, active layer, second insulating layer 103, third gate layer, dielectric layer 104, first source / drain layer, passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, and electrode layer are sequentially stacked. The buffer layer 102, the first insulating layer 101, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 102, the first insulating layer 101, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of any one of the first and second source / drain layers can be less than the sheet resistance of any one of the first, second, and third gate layers.

[0162] This exemplary embodiment also provides another display panel, which also includes a first gate layer, a second gate layer, an active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer is disposed between the aforementioned layers. As shown in Figures 17-29, Figure 17 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 18 is a structural layout diagram of the first gate layer in the display panel shown in Figure 17; Figure 19 is a structural layout diagram of the second gate layer in the display panel shown in Figure 17; Figure 20 is a structural layout diagram of the active layer in the display panel shown in Figure 17; Figure 21 is a structural layout diagram of the third gate layer in the display panel shown in Figure 17; Figure 22 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 17; Figure 23 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 17; and Figure 24 is a structural layout diagram of the electrode layer in the display panel shown in Figure 17. Figure 25 is a structural layout of the first gate layer and the second gate layer in the display panel shown in Figure 17. Figure 26 is a structural layout of the first gate layer, the second gate layer, and the active layer in the display panel shown in Figure 17. Figure 27 is a structural layout of the first gate layer, the second gate layer, the active layer, and the third gate layer in the display panel shown in Figure 17. Figure 28 is a structural layout of the first gate layer, the second gate layer, the active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 17. Figure 29 is a structural layout of the first gate layer, the second gate layer, the active layer, the third gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 17.

[0163] As shown in Figure 29, the display panel may include multiple pixel driving circuit groups arranged in an array along the row and column directions. Each pixel driving circuit group includes three adjacent pixel driving circuits in the row direction X: a first pixel driving circuit Pix1, a second pixel driving circuit Pix2, and a third pixel driving circuit Pix3. The first pixel driving circuit Pix1 is used to drive the red light-emitting unit, the second pixel driving circuit Pix2 is used to drive the green light-emitting unit, and the third pixel driving circuit Pix3 is used to drive the blue light-emitting unit.

[0164] As shown in Figure 29, unlike the display panel shown in Figure 15, in the display panel shown in Figure 29, the orthogonal projections of the second pixel driving circuit Pix2 and the third pixel driving circuit Pix3 on the substrate are at least partially symmetrical with respect to the axis of symmetry BB2 extending along the column direction.

[0165] As shown in Figures 15 and 29, the structure of the pixel driving circuit in the display panel shown in Figure 29 can be the same as the structure of the pixel driving circuit in the display panel shown in Figure 15.

[0166] This exemplary embodiment also provides another display panel, which also includes a first gate layer, a second gate layer, an active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer is disposed between the aforementioned layers. As shown in Figures 30-42, Figure 30 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 31 is a structural layout diagram of the first gate layer in the display panel shown in Figure 30; Figure 32 is a structural layout diagram of the second gate layer in the display panel shown in Figure 30; Figure 33 is a structural layout diagram of the active layer in the display panel shown in Figure 30; Figure 34 is a structural layout diagram of the third gate layer in the display panel shown in Figure 30; Figure 35 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 30; Figure 36 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 30; and Figure 37 is a structural layout diagram of the electrode layer in the display panel shown in Figure 30. Figure 38 is a structural layout of the first gate layer and the second gate layer in the display panel shown in Figure 30. Figure 39 is a structural layout of the first gate layer, the second gate layer, and the active layer in the display panel shown in Figure 30. Figure 40 is a structural layout of the first gate layer, the second gate layer, the active layer, and the third gate layer in the display panel shown in Figure 30. Figure 41 is a structural layout of the first gate layer, the second gate layer, the active layer, the third gate layer, and the first source / drain layer in the display panel shown in Figure 30. Figure 42 is a structural layout of the first gate layer, the second gate layer, the active layer, the third gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 30.

[0167] As shown in Figure 42, the display panel may include multiple pixel driving circuit groups arranged in an array along the row and column directions. Each pixel driving circuit group includes six adjacent pixel driving circuits in the row direction X: a first pixel driving circuit Pix1, a second pixel driving circuit Pix2, a third pixel driving circuit Pix3, a fourth pixel driving circuit Pix4, a fifth pixel driving circuit Pix5, and a sixth pixel driving circuit Pix6. Specifically, the first pixel driving circuit Pix1 drives the red light-emitting unit, the second pixel driving circuit Pix2 drives the green light-emitting unit, the third pixel driving circuit Pix3 drives the blue light-emitting unit, the fourth pixel driving circuit Pix4 drives the red light-emitting unit, the fifth pixel driving circuit Pix5 drives the green light-emitting unit, and the sixth pixel driving circuit Pix6 drives the blue light-emitting unit.

[0168] As shown in Figure 42, unlike the display panel shown in Figure 15, in the display panel shown in Figure 42, the orthographic projections of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 on the substrate are at least partially symmetrically arranged with respect to the axis of symmetry BB3 extending along the column direction; the orthographic projections of the third pixel driving circuit Pix3 and the fourth pixel driving circuit Pix4 on the substrate are at least partially symmetrically arranged with respect to the axis of symmetry BB4 extending along the column direction; and the orthographic projections of the fifth pixel driving circuit Pix5 and the sixth pixel driving circuit Pix6 on the substrate are at least partially symmetrically arranged with respect to the axis of symmetry BB5 extending along the column direction.

[0169] As shown in Figures 15 and 42, the pixel driving circuit in the display panel shown in Figure 42 and the pixel driving circuit in the display panel shown in Figure 15 can have the same structure.

[0170] Furthermore, as shown in Figure 3-42, the two pixel driving circuits, which are at least partially mirror-symmetrical, can share the same third conductive part 23, and the shared third conductive part 23 can be connected to the third reset signal line Re3 through a via. The two pixel driving circuits, which are at least partially mirror-symmetrical, can also share the same eighth conductive part 38, and the shared eighth conductive part 38 can be connected to the third reset signal line Re3 through a via.

[0171] As shown in Figure 3-42, the two pixel driving circuits, which are at least partially mirror-symmetrical, can share the same fourth conductive part 24, and the shared fourth conductive part 24 can be connected to the second reset signal line Re2 through a via. The two pixel driving circuits, which are at least partially mirror-symmetrical, can share the same ninth conductive part 39, and the shared ninth conductive part 39 can be connected to the second reset signal line Re2 through a via.

[0172] As shown in Figure 3-42, at least partially mirror-symmetrical two pixel driving circuits can share the same fifth conductive part 25, and the shared fifth conductive part 25 can be connected to the gate line via a via. At least partially mirror-symmetrical two pixel driving circuits can share the same tenth conductive part 310, and the shared tenth conductive part 310 can be connected to the gate line via a via.

[0173] In this exemplary embodiment, at least a portion of the same type of switching transistors, which are orthographically mirror-symmetrical on the substrate, share the same conductive portion as their gate. This arrangement can improve the integration density of the pixel driving circuit. It should be understood that in other exemplary embodiments, other switching transistors may also share the same conductive portion as their gate.

[0174] As shown in Figure 3-42, in a two-pixel driving circuit that is at least partially mirror-symmetric, the two seventh active units 77 can be connected through the sixteenth active unit 716.

[0175] Figure 43 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Figure 43 only shows the structural layout of the first gate layer in the pixel driving circuit. The structure of the pixel driving circuit in the display panel shown in Figure 43 and the display panel shown in Figure 15 can be the same.

[0176] As shown in Figure 43, the display panel may include multiple pixel driving circuit groups, which can be arrayed along the row direction X and column direction Y. Each pixel driving circuit group may include six adjacent pixel driving circuits in the row direction X: a first pixel driving circuit Pix1, a second pixel driving circuit Pix2, a third pixel driving circuit Pix3, a fourth pixel driving circuit Pix4, a fifth pixel driving circuit Pix5, and a sixth pixel driving circuit Pix6. Specifically, the first pixel driving circuit Pix1 drives the red light-emitting unit, the second pixel driving circuit Pix2 drives the green light-emitting unit, the third pixel driving circuit Pix3 drives the blue light-emitting unit, the fourth pixel driving circuit Pix4 drives the red light-emitting unit, the fifth pixel driving circuit Pix5 drives the green light-emitting unit, and the sixth pixel driving circuit Pix6 drives the blue light-emitting unit.

[0177] As shown in Figure 43, the orthographic projections of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 on the substrate are at least partially symmetrical about an axis of symmetry extending along the column direction. The orthographic projections of the fourth pixel driving circuit Pix4 and the fifth pixel driving circuit Pix5 on the substrate are at least partially symmetrical about an axis of symmetry extending along the column direction.

[0178] Figure 44 shows a structural layout of another exemplary embodiment of the display panel of this disclosure. Figure 44 only shows the structural layout of the first gate layer in the pixel driving circuit. The structure of the pixel driving circuit in the display panel shown in Figure 44 and the display panel shown in Figure 15 can be the same.

[0179] As shown in Figure 44, the display panel may include multiple pixel driving circuit groups, which can be arrayed along the row direction X and the column direction Y. Taking six adjacent pixel driving circuits in the row direction X as an example: a first pixel driving circuit Pix1, a second pixel driving circuit Pix2, a third pixel driving circuit Pix3, a fourth pixel driving circuit Pix4, a fifth pixel driving circuit Pix5, and a sixth pixel driving circuit Pix6. Specifically, the first pixel driving circuit Pix1 drives the red light-emitting unit, the second pixel driving circuit Pix2 drives the green light-emitting unit, the third pixel driving circuit Pix3 drives the blue light-emitting unit, the fourth pixel driving circuit Pix4 drives the red light-emitting unit, the fifth pixel driving circuit Pix5 drives the green light-emitting unit, and the sixth pixel driving circuit Pix6 drives the blue light-emitting unit.

[0180] As shown in Figure 44, the orthographic projections of the second pixel driving circuit Pix2 and the third pixel driving circuit Pix3 on the substrate are at least partially symmetrical with respect to the axis of symmetry extending along the column direction. The orthographic projections of the fifth pixel driving circuit Pix5 and the sixth pixel driving circuit Pix6 on the substrate are at least partially symmetrical with respect to the axis of symmetry extending along the column direction.

[0181] In this exemplary embodiment, as shown in Figures 3-44, in a two-pixel driving circuit that is at least partially mirror-symmetrical, the orthographic projections of the channel regions of two identical transistors onto the substrate are mirror-symmetrically arranged with respect to an axis of symmetry extending along the column direction Y. For example, the orthographic projections of driving transistor T3 in one pixel driving circuit and driving transistor T1 in another pixel driving circuit onto the substrate are mirror-symmetrically arranged with respect to an axis of symmetry extending along the column direction Y, and the orthographic projections of first transistor T1 in one pixel driving circuit and first transistor T1 in another pixel driving circuit onto the substrate are mirror-symmetrically arranged with respect to an axis of symmetry extending along the column direction Y.

[0182] It should be noted that, as shown in Figures 3-44, the structures of multiple pixel driving circuit groups in the display panel can be the same or different. For example, the display panel may include one or more of the pixel driving circuit groups shown in Figures 15, 29, 42, 43, and 44. Furthermore, the mirror symmetry of the pixel driving circuits in the pixel driving circuit group can also take other forms.

[0183] In this exemplary embodiment, as shown in Figures 3-44, the display panel includes three light-emitting units of different colors: a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit. The first light-emitting unit can be a red light-emitting unit, the second light-emitting unit can be a green light-emitting unit, and the third light-emitting unit can be a blue light-emitting unit. Light-emitting units of the same color are connected to pixel driving circuits located in the same column, and the pixel driving circuits connected to the first, second, and third light-emitting units are distributed sequentially in the row direction. It should be understood that in other exemplary embodiments, the light-emitting units may have other distribution methods.

[0184] It should be noted that, as shown in Figure 3-44, the chamfered black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black rectangles drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different locations can penetrate different insulating layers.

[0185] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0186] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0187] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0188] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Substrate; Multiple light-emitting units; Multiple pixel driving circuits are provided to drive the light-emitting unit to emit light, and the orthogonal projections of the multiple pixel driving circuits on the substrate are arranged in an array in the row and column directions. The pixel driving circuit includes a driving transistor and a capacitor. The first electrode of the driving transistor is connected to a first power supply line, and the second electrode is connected to the light-emitting unit. The capacitor is connected between the gate of the driving transistor and the second electrode of the driving transistor; In the pixel driving circuits located in the same row, there is at least one set of two adjacent pixel driving circuits whose orthogonal projections on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

2. The display panel according to claim 1, wherein, The display panel includes multiple pixel driving circuit groups, and the orthogonal projections of the multiple pixel driving circuit groups on the substrate are arranged in an array along the row and column directions. The pixel driving circuit group includes a plurality of pixel driving circuits that are adjacent in the row direction. In the same pixel driving circuit group, there is at least one set of two adjacent pixel driving circuits whose orthogonal projections on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

3. The display panel according to claim 2, wherein, At least part of the pixel driving circuit group includes three adjacent pixel driving circuits in the row direction, the three pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; The second pixel driving circuit is located between the first pixel driving circuit and the third pixel driving circuit, and the orthographic projections of the first pixel driving circuit and the second pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

4. The display panel according to claim 2, wherein, At least part of the pixel driving circuit group includes three adjacent pixel driving circuits in the row direction, the three pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; The second pixel driving circuit is located between the first pixel driving circuit and the third pixel driving circuit, and the orthographic projections of the second pixel driving circuit and the third pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

5. The display panel according to claim 2, wherein, At least a portion of the pixel driving circuit group includes six adjacent pixel driving circuits in the row direction, the six pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, a third pixel driving circuit, a fourth pixel driving circuit, a fifth pixel driving circuit, and a sixth pixel driving circuit. The first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit are sequentially distributed along the row direction on the orthogonal projection of the substrate. Wherein, the orthographic projections of the first pixel driving circuit and the second pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction; the orthographic projections of the third pixel driving circuit and the fourth pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction; and the orthographic projections of the fifth pixel driving circuit and the sixth pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

6. The display panel according to claim 2, wherein, At least a portion of the pixel driving circuit group includes six adjacent pixel driving circuits in the row direction, the six pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, a third pixel driving circuit, a fourth pixel driving circuit, a fifth pixel driving circuit, and a sixth pixel driving circuit. The first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit are sequentially distributed along the row direction on the orthogonal projection of the substrate. The orthographic projections of the first pixel driving circuit and the second pixel driving circuit on the substrate are at least partially mirror-symmetrical about an axis of symmetry extending along the column direction. The orthographic projections of the fourth pixel driving circuit and the fifth pixel driving circuit on the substrate are at least partially mirror-symmetrical about an axis of symmetry extending along the column direction. It is set in a mirror symmetry relative to the axis of symmetry extending along the column direction.

7. The display panel according to claim 2, wherein, At least a portion of the pixel driving circuit group includes six adjacent pixel driving circuits in the row direction, the six pixel driving circuits including: a first pixel driving circuit, a second pixel driving circuit, a third pixel driving circuit, a fourth pixel driving circuit, a fifth pixel driving circuit, and a sixth pixel driving circuit. The first pixel driving circuit, the second pixel driving circuit, the third pixel driving circuit, the fourth pixel driving circuit, the fifth pixel driving circuit, and the sixth pixel driving circuit are sequentially distributed along the row direction on the orthogonal projection of the substrate. The orthographic projections of the second pixel driving circuit and the third pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction. The orthographic projections of the fifth pixel driving circuit and the sixth pixel driving circuit on the substrate are at least partially mirror-symmetrical with respect to an axis of symmetry extending along the column direction.

8. The display panel according to any one of claims 1-7, wherein, The display panel includes three light-emitting units of different colors: a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit. Light-emitting units of the same color are connected to pixel driving circuits located in the same column, and the pixel driving circuits connected to the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are distributed sequentially in the row direction.

9. The display panel according to any one of claims 1-7, wherein, In a two-pixel driving circuit where the orthogonal projection on the substrate is at least partially mirror-symmetrical, the orthogonal projection of the channel of the same transistor on the substrate is mirror-symmetrical with respect to the axis of symmetry extending along the column direction.

10. The display panel according to claim 9, wherein, The pixel driving circuit further includes one or more switching transistors, at least some of which are the same type of switching transistors that are orthographically mirror-symmetrical on the substrate share the same conductive portion as the gate.

11. The display panel according to claim 10, wherein, The pixel driving circuit includes two capacitors, namely a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. One or more switching transistors include a first transistor, a second transistor, and a fourth transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the first electrode of the first capacitor; The first terminal of the second transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor; The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the gate of the driving transistor. Two first transistors, which are mirror-symmetrical in orthographic projection on the substrate, share the same conductive portion as their gate; two second transistors, which are mirror-symmetrical in orthographic projection on the substrate, share the same conductive portion as their gate; and two fourth transistors, which are mirror-symmetrical in orthographic projection on the substrate, share the same conductive portion as their gate.

12. The display panel according to claim 9, wherein, The pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to the second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit. The display panel also includes: An active layer is located on one side of the substrate. The active layer includes a seventh active portion and a sixteenth active portion. The seventh active portion is used to form the channel region of the seventh transistor. The seventh active portion, which is mirror-symmetrical to the orthographic projection on the substrate, is connected through the sixteenth active portion.

13. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit includes two capacitors, namely a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The display panel also includes: A first gate layer is located on one side of the substrate. The first gate layer includes a first conductive portion and a second conductive portion connected in the same layer. The first conductive portion is used to form a first electrode of the first capacitor, and the second conductive portion is used to form a first electrode of the second capacitor. The second gate layer is located on the side of the first gate layer that faces away from the substrate. The second gate layer includes a sixth conductive portion and a seventh conductive portion. The orthographic projection of the sixth conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The sixth conductive portion is used to form the second electrode of the first capacitor. The orthographic projection of the seventh conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate at least partially overlap. The seventh conductive portion is used to form the second electrode of the second capacitor. The orthographic projections of the sixth conductive part and the seventh conductive part on the substrate are distributed along the column direction.

14. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit includes two capacitors, namely a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The display panel also includes: A second gate layer is located on one side of the substrate. The second gate layer includes a sixth conductive portion, which is used to form the second electrode of the first capacitor. An active layer is located on the side of the second gate layer away from the substrate. The active layer includes a third active portion, which is used to form the channel region of the driving transistor. Wherein, the orthogonal projection of the sixth conductive part on the substrate covers the orthogonal projection of the third active part on the substrate.

15. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit includes two capacitors, a fifth transistor, and a sixth transistor. The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the third enable signal line. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the fourth enable signal line. The display panel also includes: The second gate layer is located on one side of the substrate. The second gate layer includes a sixth conductive portion, a seventh conductive portion, the third enable signal line, and a fourth enable signal line. The sixth conductive portion is used to form the second electrode of the first capacitor, the seventh conductive portion is used to form the second electrode of the second capacitor, a portion of the structure of the third enable signal line is used to form the bottom gate of the fifth transistor, and a portion of the structure of the fourth enable signal line is used to form the bottom gate of the sixth transistor. Wherein, the orthographic projections of the third enable signal line and the fourth enable signal line on the substrate extend along the row direction. In the same pixel driving circuit, the orthographic projections of the sixth conductive part and the seventh conductive part on the substrate are located between the orthographic projections of the third enable signal line and the fourth enable signal line on the substrate.

16. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit also includes a fifth transistor, a sixth transistor, and a seventh transistor; The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the first enable signal line. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second enable signal line. The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the first reset signal line. The display panel also includes: An active layer, wherein a portion of the structure of the active layer is used to form the channel regions of the driving transistor, the fifth transistor, the sixth transistor, and the seventh transistor; The third gate layer is located on the side of the active layer away from the substrate. The third gate layer includes a first enable signal line, a second enable signal line, a first reset signal line, and an eleventh conductive portion. A portion of the structure of the first enable signal line is used to form the top gate of the fifth transistor, a portion of the structure of the second enable signal line is used to form the top gate of the sixth transistor, a portion of the structure of the first reset signal line is used to form the top gate of the seventh transistor, and the eleventh conductive portion is used to form the top gate of the driving transistor. In the same pixel driving circuit, the orthographic projections of the first enable signal line, the second enable signal line, and the first reset signal line onto the substrate extend along the row direction and along the column direction. The directions are distributed sequentially at intervals. The orthographic projection of the eleventh conductive part on the substrate is located between the orthographic projections of the first enable signal line and the second enable signal line on the substrate. The orthographic projection of the first reset signal line on the substrate is located on the side of the second enable signal line on the substrate away from the orthographic projection of the eleventh conductive part on the substrate.

17. The display panel according to claim 16, wherein, The pixel driving circuit also includes a first transistor, a second transistor, a fourth transistor, and two capacitors; The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor. The first terminal of the second transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor; The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the gate of the driving transistor. The display panel also includes: An active layer, wherein a portion of the structure of the active layer is used to form the channel regions of the first transistor, the second transistor, and the fourth transistor; The third gate layer is located on the side of the active layer away from the substrate. The third gate layer includes an eighth conductive portion, a ninth conductive portion, and a tenth conductive portion. The eighth conductive portion is used to form the top gate of the first transistor, the ninth conductive portion is used to form the top gate of the second transistor, and the tenth conductive portion is used to form the top gate of the fourth transistor. The first source / drain layer is located on the side of the third gate layer opposite to the substrate. The first source / drain layer includes a gate line, a second reset signal line, and a third reset signal line. The gate line is connected to the tenth conductive part through a via. The second reset signal line is connected to the ninth conductive part through a via. The third reset signal line is connected to the eighth conductive part through a via. The orthogonal projection of the gate line, the second reset signal line, and the third reset signal line on the substrate extends along the row direction. In the same pixel driving circuit, the orthogonal projection of the gate line on the substrate is located at the orthogonal projection of the first enable signal line on the substrate and the eleventh guide line. The first reset signal line is positioned between the orthogonal projections of the eleventh conductive part on the substrate and the second enable signal line on the substrate. The second reset signal line is positioned between the orthogonal projections of the eleventh conductive part on the substrate and the second enable signal line on the substrate. The third reset signal line is positioned between the orthogonal projections of the second reset signal line on the substrate and the second enable signal line on the substrate.

18. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and two capacitors; The two capacitors include a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The first terminal of the first transistor is connected to the first initial signal line, and the second terminal is connected to the first electrode of the first capacitor. The first terminal of the second transistor is connected to the first initial signal line, and the second terminal is connected to the gate of the driving transistor; The first terminal of the fourth transistor is connected to the data line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the fifth transistor is connected to the first power supply line, and the second terminal is connected to the first terminal of the driving transistor. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit. The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel also includes: An active layer, the active layer including a first main active portion and a second main active portion, wherein the orthographic projection of the first main active portion on the substrate and the orthographic projection of the second main active portion on the substrate extend along the column direction and are spaced apart in the row direction; The first main active portion includes a first active portion, a second active portion, and a fourth active portion that are sequentially spaced along the column direction. The first active portion is used to form the channel region of the first transistor, the second active portion is used to form the channel region of the second transistor, and the fourth active portion is used to form the channel region of the second transistor. The part is used to form the channel region of the fourth transistor; The second main active portion includes a sixth active portion, a third active portion, and a fifth active portion that are sequentially spaced along the column direction. The sixth active portion is used to form the channel region of the sixth transistor, the third active portion is used to form the channel region of the driving transistor, and the fifth active portion is used to form the channel region of the fifth transistor.

19. The display panel according to any one of claims 1-7, wherein, The display panel also includes: A first source / drain layer is located on one side of the substrate. The first source / drain layer includes multiple second power lines. The orthographic projection of the multiple second power lines on the substrate extends along the row direction and is spaced apart along the column direction. The second power lines are connected to the second electrode of the light-emitting unit. The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes multiple second power connection lines. The orthographic projection of the multiple second power connection lines on the substrate extends along the column direction and is spaced apart along the row direction. The second power line is connected to the intersecting second power connection line via a via.

20. A display device, wherein, The display device includes the display panel as described in any one of claims 1-19.

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