Pixel driving circuit, driving method thereof, display panel and display device

Abstract

The invention discloses a pixel driving circuit, a driving method thereof, a display panel and a display device, and the pixel driving circuit comprises a power compensation circuit (1) which is configured to respond to a signal of a first control signal end (G1), provide a signal of a first reference voltage end (V1) to a first node (A), respond to a signal of a second control signal end (G2), and provide a signal of a second reference voltage end (V2) to the first node (A); the driving transistor (TD) is coupled between the first power supply end (VDD) and the first pole of the light emitting device (F); the compensation capacitor (Cst) is coupled between the grid electrode of the driving transistor (TD) and the first node (A); the data write-in circuit (2) is configured to respond to a signal of a first scanning signal end (G3) and provide a data voltage (Vdata) for a first electrode of the driving transistor (TD), so that when the light-emitting device (F) is driven, the brightness of the light-emitting device (F) is only related to a signal of a first reference voltage end (V1) and the data voltage (Vdata) and is not related to a power supply voltage input by a first power supply end (VDD), and the brightness of the light-emitting device (F) is not related to the data voltage (Vdata). Therefore, the influence of the voltage drop on the power line for transmitting the power voltage on the luminance can be avoided, and the display effect is improved.

Description

A pixel driving circuit, its driving method, a display panel, and a display device.

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411217736.4, filed on August 30, 2024, entitled "A pixel driving circuit, its driving method, and a display panel and display device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to pixel driving circuits, driving methods thereof, display panels and display devices. Background Technology

[0004] Voltage drops typically exist on power supply traces used to transmit power supply voltage. This causes differences in the power supply voltage received by the pixel driving circuits at different locations on the display panel. Consequently, the driving current generated by the pixel driving circuits at different locations varies, resulting in differences in brightness on the display panel and reducing the display effect. Summary of the Invention

[0005] This disclosure provides a pixel driving circuit, including:

[0006] The power compensation circuit is configured to provide a signal from a first reference voltage terminal to a first node in response to a signal from a first control signal terminal, and to provide a signal from a second reference voltage terminal to the first node in response to a signal from a second control signal terminal.

[0007] A driving transistor is coupled between the first power supply terminal and the first electrode of the light-emitting device;

[0008] A compensation capacitor is coupled between the gate of the driving transistor and the first node;

[0009] The data writing circuit is configured to provide a data voltage to the first terminal of the driving transistor in response to a signal at the first scan signal terminal.

[0010] In some possible implementations, the power compensation circuit includes: a first transistor and a second transistor;

[0011] The first terminal of the first transistor is coupled to the first reference voltage terminal, the second terminal of the first transistor is coupled to the first node, and the gate of the first transistor is coupled to the first control signal terminal.

[0012] The first terminal of the second transistor is coupled to the second reference voltage terminal, the second terminal of the second transistor is coupled to the first node, and the gate of the second transistor is coupled to the second control signal terminal.

[0013] In some possible implementations, the first transistor and the second transistor are of the same type, and the signal at the first control signal terminal is out of phase with the signal at the second control signal terminal.

[0014] In some possible implementations, the first transistor and the second transistor are of different types, and the first control signal terminal and the second control signal terminal are the same signal terminal.

[0015] In some possible implementations, the data writing circuit is coupled to a data signal terminal and configured to provide the data voltage input to the data signal terminal to the first pole of the driving transistor in response to a signal from the first scan signal terminal.

[0016] In some possible implementations, it also includes:

[0017] A data compensation circuit, coupled to a data signal terminal and a second node, is configured to provide the data voltage input at the data signal terminal to the second node in response to a signal at the data compensation signal terminal.

[0018] The data writing circuit is coupled to the second node and is configured to provide the data voltage of the second node to the first terminal of the driving transistor in response to a signal at the first scan signal terminal.

[0019] In some possible implementations, the data compensation circuit includes: a third transistor and a first capacitor;

[0020] The first terminal of the third transistor is coupled to the data signal terminal, the second terminal of the third transistor is coupled to the second node, and the gate of the third transistor is coupled to the data compensation signal terminal.

[0021] The first terminal of the first capacitor is coupled to the third reference voltage terminal, and the second terminal of the first capacitor is coupled to the second node.

[0022] In some possible implementations, the third reference voltage terminal is the same signal terminal as the first reference voltage terminal.

[0023] In some possible implementations, it also includes:

[0024] A first reset circuit is configured to provide a signal from a first initialization signal terminal to a first electrode of the light-emitting device in response to a signal from a first reset signal terminal.

[0025] The second reset circuit is configured to provide a signal from the second initialization signal terminal to the gate or second electrode of the driving transistor in response to a signal from the second reset signal terminal.

[0026] In some possible implementations, at least two of the first initialization signal terminal, the second initialization signal terminal, and the first reference voltage terminal are the same signal terminal.

[0027] In some possible implementations, it also includes:

[0028] A threshold compensation circuit is configured to turn on the second terminal and gate of the driving transistor in response to a signal at the second scan signal terminal.

[0029] In some possible implementations, the first scan signal terminal and the second scan signal terminal are the same signal terminal.

[0030] In some possible implementations, it also includes:

[0031] A first light-emitting control circuit, coupled between the first power supply terminal and the first electrode of the driving transistor, is configured to provide the power supply voltage of the first power supply terminal to the first electrode of the driving transistor in response to a signal from the light-emitting control signal terminal.

[0032] In some possible implementations, it also includes:

[0033] The second light-emitting control circuit is coupled between the second terminal of the driving transistor and the first terminal of the light-emitting device, and is configured to conduct the second terminal of the driving transistor and the first terminal of the light-emitting device in response to a signal at the light-emitting control signal terminal.

[0034] In some possible implementations, the second control signal terminal and the light emission control signal terminal are the same signal terminal.

[0035] In some possible implementations, the first scanning signal terminal and the first control signal terminal are the same signal terminal; or,

[0036] The second reference voltage terminal and the first power supply terminal are the same signal terminal.

[0037] This disclosure also provides a driving method for the above-described pixel driving circuit, including:

[0038] In the first stage, the power compensation circuit responds to the signal at the first control signal terminal and provides the signal at the first reference voltage terminal to the first node.

[0039] In the second stage, the power compensation circuit responds to the signal at the first control signal terminal by providing the signal at the first reference voltage terminal to the first node; the data writing circuit responds to the signal at the first scan signal terminal by providing the data voltage to the first terminal of the driving transistor.

[0040] In the third stage, the power compensation circuit responds to the signal at the second control signal terminal and provides the signal at the second reference voltage terminal to the first node; the compensation capacitor couples the voltage change value of the first node to the gate of the driving transistor; the driving transistor responds to the voltage change value and the data voltage, generates a driving current and outputs it to the first electrode of the light-emitting device.

[0041] This disclosure also provides a display panel including the pixel driving circuit described above.

[0042] In some possible implementations, it further includes: a first gate driving circuit, the first gate driving circuit including a plurality of cascaded first shift register units;

[0043] Each of the first shift register units includes a gate signal generation circuit and an inverting circuit. The gate signal generation circuit is configured to output a first control signal to the first control signal terminal of the pixel driving circuit and the inverting circuit. The inverting circuit is configured to invert the first control signal and then output a second control signal to the second control signal terminal of the pixel driving circuit.

[0044] In some possible implementations, it further includes: a second gate driving circuit, the second gate driving circuit including a plurality of cascaded second shift register units;

[0045] The signal output terminal of the second shift register unit of the nth stage is coupled to the first control signal terminal and the first scan signal terminal of the pixel driving circuit of the i-th row; where n and i are both positive integers.

[0046] In some possible implementations, the signal output terminal of the (n-1)th stage second shift register unit is coupled to the first reset signal terminal and the second reset signal terminal of the i-th row pixel driving circuit, and the signal output terminal of the (n+1)th stage second shift register unit is coupled to the data compensation signal terminal of the i-th row pixel driving circuit.

[0047] In some possible implementations, it further includes: multiple initialization signal lines, wherein the first reference voltage terminal, the third reference voltage terminal, the first initialization signal terminal, and the second initialization signal terminal of a row pixel driving circuit are coupled to the same initialization signal line, or,

[0048] The first reference voltage terminal, the third reference voltage terminal, the first initialization signal terminal, and the second initialization signal terminal of a pixel driving circuit are coupled to the same initialization signal line.

[0049] This disclosure also provides a display device, including the display panel described above. Attached Figure Description

[0050] Figures 1 to 5 and Figures 8 to 12 are some structural schematic diagrams of the pixel driving circuit provided in the embodiments of this disclosure;

[0051] Figures 6 to 7 and Figures 13 to 14 are some signal timing diagrams of the pixel driving circuit provided in the embodiments of this disclosure;

[0052] Figures 15, 17 and 18 are schematic diagrams of some structures of the display panel provided in the embodiments of this disclosure;

[0053] Figure 16 is a schematic diagram of some structures of the first shift register unit of the first gate drive circuit provided in the embodiments of this disclosure. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0056] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0057] In LED (Light-emitting diode) display products, each LED is driven by current, and the brightness of the LED varies under different driving currents. Typically, to reduce the threshold voltage drift of the driving transistor, threshold voltage compensation is performed on the gate of the driving transistor. The magnitude of the current in the saturation region of the compensated driving transistor is I = 1 / 2 × μ × Cox × W / L × (Vdata - Vdd)², where μ, Cox, W, and L represent parameters related to the driving transistor, Vdata represents the data voltage, and Vdd represents the power supply voltage. Therefore, the magnitude of the saturation current of the driving transistor depends on the data voltage Vdata and the power supply voltage Vdd.

[0058] The power supply voltage is transmitted through the power supply lines, and there is a voltage drop on the power supply lines. This causes the pixel driving circuits at different locations to receive different power supply voltages, which in turn causes different currents to drive the LEDs at different locations, resulting in brightness differences and reducing the display effect.

[0059] To address the aforementioned issues, the pixel driving circuit provided in this embodiment drives the light-emitting device with a current independent of the power supply voltage, thereby avoiding the influence of voltage drop on the light emission brightness on the power supply line and improving the display effect.

[0060] In this embodiment of the disclosure, as shown in FIG1, the pixel driving circuit may include:

[0061] The power compensation circuit 1 is configured to provide the signal of the first reference voltage terminal V1 to the first node A in response to the signal of the first control signal terminal G1, and to provide the signal of the second reference voltage terminal V2 to the first node A in response to the signal of the second control signal terminal G2.

[0062] The driving transistor TD is coupled between the first power supply terminal VDD and the first electrode of the light-emitting device F;

[0063] The compensation capacitor Cst is coupled between the gate of the driving transistor TD and the first node A;

[0064] The data writing circuit 2 is configured to provide the data voltage Vdata to the first terminal of the driving transistor TD in response to the signal of the first scan signal terminal G3.

[0065] The pixel driving circuit provided in this embodiment of the present disclosure, by setting a power compensation circuit, ensures that when driving the light-emitting device, the brightness of the light-emitting device is only related to the signal and data voltage of the first reference voltage terminal, and is not related to the power supply voltage input to the first power supply terminal. This avoids the influence of voltage drop on the power supply line transmitting the power supply voltage on the light-emitting brightness and improves the display effect.

[0066] For example, as shown in FIG1, the data writing circuit 2 is coupled to the data signal terminal Data and is configured to provide the data voltage Vdata input to the data signal terminal Data to the first terminal of the driving transistor TD in response to the signal of the first scan signal terminal G3.

[0067] For example, as shown in Figures 2 and 3, the pixel driving circuit described above further includes:

[0068] The first reset circuit 3 is configured to provide the signal of the first initialization signal terminal Vinit1 to the first pole of the light-emitting device F in response to the signal of the first reset signal terminal R1.

[0069] The second reset circuit 4 is configured to provide the signal of the second initialization signal terminal Vinit2 to the gate or second terminal of the driving transistor TD in response to the signal of the second reset signal terminal R2.

[0070] By setting up a first reset circuit and a second reset circuit, the light-emitting device and the driving transistor are reset before driving the light-emitting device, so as to eliminate the residual charge in the pixel driving circuit after driving the previous frame, improve the reliability of the pixel driving circuit, and thus improve the display effect.

[0071] For example, at least two of the first initialization signal terminal Vinit1, the second initialization signal terminal Vinit2, and the first reference voltage terminal V1 are the same signal terminal. For example, as shown in FIG2, the first initialization signal terminal Vinit1, the second initialization signal terminal Vinit2, and the first reference voltage terminal V1 are the same signal terminal.

[0072] For example, as shown in FIG3, the pixel driving circuit described above further includes:

[0073] The third reset circuit 5 is configured to provide the signal of the third initialization signal terminal Vinit3 to the first terminal of the driving transistor TD in response to the signal of the third reset signal terminal R3.

[0074] For example, as shown in Figures 2 and 3, the pixel driving circuit described above further includes:

[0075] The threshold compensation circuit 6 is configured to turn on the second terminal and gate of the driving transistor TD in response to the signal of the second scan signal terminal G4.

[0076] For example, as shown in FIG2, the first scan signal terminal G3 and the second scan signal terminal G4 are the same signal terminal.

[0077] For example, as shown in Figures 2 and 3, the pixel driving circuit described above further includes:

[0078] The first light-emitting control circuit 7 is coupled between the first power supply terminal VDD and the first terminal of the driving transistor TD, and is configured to provide the power supply voltage of the first power supply terminal VDD to the first terminal of the driving transistor TD in response to the signal of the light-emitting control signal terminal EM.

[0079] For example, as shown in Figures 2 and 3, the pixel driving circuit described above further includes:

[0080] The second light-emitting control circuit 8 is coupled between the second terminal of the driving transistor TD and the first terminal of the light-emitting device F, and is configured to conduct the second terminal of the driving transistor TD and the first terminal of the light-emitting device F in response to the signal of the light-emitting control signal terminal EM.

[0081] For example, as shown in Figures 2 and 3, the second control signal terminal G2 and the light emission control signal terminal EM are the same signal terminal.

[0082] For example, as shown in FIG2, the first scan signal terminal G3 and the first control signal terminal G1 are the same signal terminal; or, the second reference voltage terminal V2 and the first power supply terminal VDD are the same signal terminal.

[0083] For example, as shown in Figures 4 and 5, the power compensation circuit 1 includes: a first transistor T1 and a second transistor T2;

[0084] The first terminal of the first transistor T1 is coupled to the first reference voltage terminal V1, the second terminal of the first transistor T1 is coupled to the first node A, and the gate of the first transistor T1 is coupled to the first control signal terminal G1.

[0085] The first terminal of the second transistor T2 is coupled to the second reference voltage terminal V2, the second terminal of the second transistor T2 is coupled to the first node A, and the gate of the second transistor T2 is coupled to the second control signal terminal G2.

[0086] For example, at least one of the first transistor T1 and the second transistor T2 is an oxide thin-film transistor. Using oxide thin-film transistors for the first transistor T1 and the second transistor T2 can reduce leakage current and ensure the stability of the gate voltage of the driving transistor TD, thereby improving the reliability of the pixel driving circuit and enhancing the display effect.

[0087] For example, the first transistor T1 and the second transistor T2 are of the same type, and the signal at the first control signal terminal G1 is out of phase with the signal at the second control signal terminal G2.

[0088] For example, the first transistor T1 and the second transistor T2 are of different types, and the first control signal terminal G1 and the second control signal terminal G2 are the same signal terminal.

[0089] For example, as shown in Figures 4 and 5, both the first transistor T1 and the second transistor T2 are P-type transistors. By setting the signal of the first control signal terminal G1 to be inversely phase with the signal of the second control signal terminal G2, it is possible to ensure that the first transistor T1 and the second transistor T2 cannot be turned on simultaneously. This allows the signals of the first reference voltage terminal V1 and the second reference voltage terminal V2 to be loaded onto the first node A sequentially, causing the voltage of the first node A to jump from the voltage of the first reference voltage terminal V1 to the voltage of the second reference voltage terminal V2. Thus, through the coupling effect of the compensation capacitor Cst, the voltage change value of the first node A can be coupled to the gate of the driving transistor TD. This enables the driving transistor TD to generate a driving current whose magnitude is independent of the power supply voltage Vdd input at the first power supply terminal VDD, avoiding brightness differences caused by voltage drops on the power supply lines and improving the display effect.

[0090] For example, as shown in Figures 4 and 5, the data writing circuit 2 includes a fifth transistor T5, wherein the first terminal of the fifth transistor T5 is coupled to the data signal terminal Data, the second terminal of the fifth transistor T5 is coupled to the first terminal of the driving transistor TD, and the gate of the fifth transistor T5 is coupled to the first scan signal terminal G3.

[0091] For example, as shown in Figures 4 and 5, the first reset circuit 3 includes a ninth transistor T9, wherein the first terminal of the ninth transistor T9 is coupled to the first initialization signal terminal Vinit1, the second terminal of the ninth transistor T9 is coupled to the first terminal of the light-emitting device F, and the gate of the ninth transistor T9 is coupled to the first reset signal terminal R1.

[0092] For example, as shown in Figures 4 and 5, the second reset circuit 4 includes an eighth transistor T8, wherein the first terminal of the eighth transistor T8 is coupled to the second initialization signal terminal Vinit2, the second terminal of the eighth transistor T8 is coupled to the gate or second terminal of the driving transistor TD, and the gate of the eighth transistor T8 is coupled to the second reset signal terminal R2.

[0093] For example, as shown in FIG5, the third reset circuit 5 includes a tenth transistor T10, wherein the first terminal of the tenth transistor T10 is coupled to the third initialization signal terminal Vinit3, the second terminal of the tenth transistor T10 is coupled to the first terminal of the driving transistor TD, and the gate of the tenth transistor T10 is coupled to the third reset signal terminal R3.

[0094] For example, the voltages of the signals at the first initialization signal terminal Vinit1, the second initialization signal terminal Vinit2, and the third initialization signal terminal Vinit3 can be positive or negative voltages.

[0095] For example, as shown in Figures 4 and 5, the threshold compensation circuit 6 includes a fourth transistor T4, wherein the first terminal of the fourth transistor T4 is coupled to the second terminal of the driving transistor TD, the second terminal of the fourth transistor T4 is coupled to the gate of the driving transistor TD, and the gate of the fourth transistor T4 is coupled to the second scan signal terminal G4.

[0096] For example, as shown in Figures 4 and 5, the first light-emitting control circuit 7 includes a sixth transistor T6, wherein the first terminal of the sixth transistor T6 is coupled to the first power supply terminal VDD, the second terminal of the sixth transistor T6 is coupled to the first terminal of the driving transistor TD, and the gate of the sixth transistor T6 is coupled to the light-emitting control signal terminal EM.

[0097] For example, as shown in Figures 4 and 5, the second light-emitting control circuit 8 includes a seventh transistor T7. The first terminal of the seventh transistor T7 is coupled to the second terminal of the driving transistor TD, the second terminal of the seventh transistor T7 is coupled to the first terminal of the light-emitting device F, and the gate of the seventh transistor T7 is coupled to the light-emitting control signal terminal EM.

[0098] For example, as shown in Figures 4 and 5, the second electrode of the light-emitting device F is coupled to the second power supply terminal VSS.

[0099] For example, the first power supply terminal VDD can be configured to apply a constant positive voltage, and the second power supply terminal VSS can be configured to apply a constant negative voltage.

[0100] In some embodiments of this disclosure, the first terminal of the transistor can be used as its source and the second terminal as its drain, depending on the type of the transistor and the signal received by its control terminal; or, conversely, the first terminal of the transistor can be used as its drain and the second terminal as its source. This can be designed and determined according to the actual application environment, and no specific distinction is made here.

[0101] This disclosure also provides a driving method for driving the pixel driving circuit shown in FIG1, including:

[0102] In the first stage, the power compensation circuit 1 responds to the signal of the first control signal terminal G1 and provides the signal of the first reference voltage terminal V1 to the first node A.

[0103] In the second stage, the power compensation circuit 1 responds to the signal of the first control signal terminal G1 and provides the signal of the first reference voltage terminal V1 to the first node A; the data writing circuit 2 responds to the signal of the first scan signal terminal G3 and provides the data voltage Vdata to the first terminal of the driving transistor TD.

[0104] In the third stage, the power supply compensation circuit 1 responds to the signal of the second control signal terminal G2 and provides the signal of the second reference voltage terminal V2 to the first node A; the compensation capacitor Cst couples the voltage change value of the first node A to the gate of the driving transistor TD; the driving transistor TD responds to the voltage change value and the data voltage Vdata, generates a driving current and outputs it to the first pole of the light-emitting device F.

[0105] The following describes the operation of the pixel driving circuit provided in the present disclosure embodiment, taking the pixel driving circuit shown in Figure 4 as an example and referring to the signal timing diagram shown in Figure 6. The second reference voltage terminal V2 and the first power supply terminal VDD are the same signal terminal, that is, the voltage of the signal at the second reference voltage terminal is the power supply voltage Vdd.

[0106] Specifically, the first stage t1, the second stage t2, and the third stage t3 are selected from the signal timing diagram shown in Figure 6. It should be noted that the signal timing diagram shown in Figure 6 only represents the operation of a single pixel driving circuit within one frame. The operation of this pixel driving circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0107] In the first stage t1, a low-level signal Reset1 is applied to the first reset signal terminal R1, a low-level signal Reset2 is applied to the second reset signal terminal R2, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a high-level signal Gate4 is applied to the second scan signal terminal G4, and a high-level signal em is applied to the light emission control signal terminal EM.

[0108] The eighth transistor T8 is turned on under the control of the Reset2 signal at the second reset signal terminal R2. The turned-on eighth transistor T8 provides the signal at the second initialization signal terminal Vinit2 to the gate of the driving transistor TD. The ninth transistor T9 is turned on under the control of the Reset1 signal at the first reset signal terminal R1. The turned-on ninth transistor T9 provides the signal at the first initialization signal terminal Vinit1 to the first terminal of the light-emitting device F. The first transistor T1 is turned on under the control of the Gate1 signal at the first control signal terminal G1. The turned-on first transistor T1 provides the signal at the first reference voltage terminal V1 to the first node A. At this time, the voltage of the first node A is the voltage Vgh of the signal at the first reference voltage terminal V1.

[0109] In the second stage t2, a high-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a low-level signal Gate3 is applied to the first scan signal terminal G3, a low-level signal Gate4 is applied to the second scan signal terminal G4, and a high-level signal em is applied to the light emission control signal terminal EM.

[0110] The first transistor T1 is turned on under the control of the first control signal terminal G1 signal Gate1. The turned-on first transistor T1 provides the signal of the first reference voltage terminal V1 to the first node A, and the voltage of the first node A is still Vgh. The fifth transistor T5 is turned on under the control of the first scan signal terminal G3 signal Gate3. The fourth transistor T4 is turned on under the control of the second scan signal terminal G4 signal Gate4. The driving transistor TD maintains the conducting state of the previous stage under the storage function of the compensation capacitor Cst. The turned-on fifth transistor T5, driving transistor TD, and fourth transistor T4 provide the data voltage Vdata input at the data signal terminal Data to the gate of the driving transistor TD. The gate voltage Vg of the driving transistor TD becomes Vdata+Vth, where Vth represents the threshold voltage of the driving transistor TD.

[0111] In the third stage t3, a high-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Gate1 is applied to the first control signal terminal G1, a low-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a high-level signal Gate4 is applied to the second scan signal terminal G4, and a low-level signal em is applied to the light emission control signal terminal EM.

[0112] The second transistor T2 is turned on under the control of the signal Gate2 at the second control signal terminal G2. The turned-on second transistor T2 provides the signal of the second reference voltage terminal V2 to the first node A. At this time, the voltage of the first node A jumps from the voltage Vgh of the signal at the first reference voltage terminal V1 to the voltage Vdd of the signal at the second reference voltage terminal V2. The compensation capacitor Cst couples the voltage change value (Vdd-Vgh) of the first node A to the gate of the driving transistor TD. At this time, the gate voltage Vg of the driving transistor TD becomes Vdata+Vth+(Vdd-Vgh). The sixth transistor T6 and the seventh transistor T7 are turned on under the control of the signal em at the light emission control signal terminal EM. The turned-on sixth transistor T6 provides the power supply voltage Vdd input at the first power supply terminal VDD to the first terminal of the driving transistor TD. At this time, the source voltage Vs of the driving transistor TD is Vdd. The driving transistor TD generates a driving current, which flows through the turned-on seventh transistor T7 to the first terminal of the light emission device F.

[0113] In the third stage t3, the driving current for the light-emitting device F is the current flowing through the driving transistor TD. Therefore, the driving current I can be expressed as: I = 1 / 2 × μ × Cox × W / L × (Vgs - Vth) 2

[0114] Where μ is the effective carrier mobility of the driving transistor TD, Cox is the capacitance per unit area of ​​the gate oxide of the driving transistor TD, W is the width of the channel of the driving transistor TD, L is the length of the channel of the driving transistor TD, and Vgs is the difference between the gate voltage Vg and the source voltage Vs of the driving transistor TD. Then: Vgs=Vdata+Vth+(Vdd-Vgh)-Vdd=Vdata+Vth-Vgh

[0115] At this point, the driving current I can be expressed as: I = 1 / 2 × μ × Cox × W / L × (Vdata + Vth - Vgh - Vth) 2

[0116] The driving current I = 1 / 2 × μ × Cox × W / L × (Vdata - Vgh) 2

[0117] Therefore, the driving current I is related only to the data voltage Vdata and the voltage Vgh of the signal at the first reference voltage terminal V1, in addition to the parameters of the driving transistor TD itself. It is not related to the power supply voltage Vdd input at the first power supply terminal. This avoids the influence of the voltage drop of the power supply voltage Vdd on the power supply line on the driving current, thereby improving the driving effect of the pixel driving circuit on the light-emitting device.

[0118] Furthermore, when the driving transistor TD is a P-type transistor, Vgs must be less than Vth for the driving transistor TD to turn on. That is, the voltage Vgh of the signal at the first reference voltage terminal V1 must be greater than the data voltage Vdata. Therefore, when the driving transistor TD is a P-type transistor, the voltage Vgh of the signal at the first reference voltage terminal V1 should be set to always be greater than the maximum value of the data voltage Vdata. Correspondingly, when the driving transistor TD is an N-type transistor, the voltage Vgh of the signal at the first reference voltage terminal V1 should be set to always be less than the minimum value of the data voltage Vdata.

[0119] When the first reference voltage terminal V1 and the first initialization signal terminal Vinit1 are the same signal terminal, the voltage of the first initialization signal terminal Vinit1 should be set to always be greater than the maximum value of the data voltage Vdata when the driving transistor TD is a P-type transistor. Correspondingly, when the driving transistor TD is an N-type transistor, the voltage of the first initialization signal terminal Vinit1 should be set to always be less than the minimum value of the data voltage Vdata.

[0120] When the first reference voltage terminal V1 and the second initialization signal terminal Vinit2 are the same signal terminal, then when the driving transistor TD is a P-type transistor, the voltage of the signal at the second initialization signal terminal Vinit2 should be set to always be greater than the maximum value of the data voltage Vdata. Correspondingly, when the driving transistor TD is an N-type transistor, the voltage of the signal at the second initialization signal terminal Vinit2 should be set to always be less than the minimum value of the data voltage Vdata.

[0121] When the first reference voltage terminal V1, the first initialization signal terminal Vinit1, and the second initialization signal terminal Vinit2 are the same signal terminal, for example, when the voltages of the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2 are both Vit, then when the driving transistor TD is a P-type transistor, Vit should be set to always be greater than the maximum value of the data voltage Vdata. Correspondingly, when the driving transistor TD is an N-type transistor, Vit should be set to always be less than the minimum value of the data voltage Vdata.

[0122] The operation of the pixel driving circuit provided in the embodiments of this disclosure will be described below using the pixel driving circuit shown in Figure 5 as an example and in conjunction with the signal timing diagram shown in Figure 7.

[0123] Specifically, the first stage t1, the second stage t2, the third stage t3, and the fourth stage t4 are selected from the signal timing diagram shown in Figure 7. It should be noted that the signal timing diagram shown in Figure 7 only represents the operation of a single pixel driving circuit within one frame. The operation of this pixel driving circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0124] In the first stage t1, a high-level signal Reset1 is applied to the first reset signal terminal R1, a low-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Reset3 is applied to the third reset signal terminal R3, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a low-level signal Gate4 is applied to the second scan signal terminal G4, and a high-level signal em is applied to the light emission control signal terminal EM.

[0125] The first transistor T1 is turned on under the control of the signal Gate1 at the first control signal terminal G1. The turned-on first transistor T1 provides the signal of the first reference voltage terminal V1 to the first node A. At this time, the voltage of the first node A is the voltage Vgh of the signal of the first reference voltage terminal V1. The eighth transistor T8 is turned on under the control of the signal Reset2 at the second reset signal terminal R2. It provides the signal of the second initialization signal terminal Vinit2 to the first terminal of the fourth transistor T4. The fourth transistor T4 is turned on under the control of the signal Gate4 at the second scan signal terminal G4. The turned-on fourth transistor T4 provides the initialization signal received at the first terminal to the gate of the driving transistor TD.

[0126] In the second stage t2, a high-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Reset3 is applied to the third reset signal terminal R3, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a low-level signal Gate3 is applied to the first scan signal terminal G3, a low-level signal Gate4 is applied to the second scan signal terminal G4, and a high-level signal em is applied to the light emission control signal terminal EM.

[0127] The first transistor T1 is turned on under the control of the first control signal terminal G1 signal Gate1. The turned-on first transistor T1 provides the signal of the first reference voltage terminal V1 to the first node A, and the voltage of the first node A is still Vgh. The fifth transistor T5 is turned on under the control of the first scan signal terminal G3 signal Gate3. The fourth transistor T4 is turned on under the control of the second scan signal terminal G4 signal Gate4. At the same time, under the storage function of the compensation capacitor Cst, the driving transistor TD maintains the conducting state of the previous stage. The turned-on fourth transistor T4, driving transistor TD, and fifth transistor T5 provide the data voltage Vdata input at the data signal terminal Data to the gate of the driving transistor TD. At this time, the gate voltage Vg of the driving transistor TD is Vdata + Vth.

[0128] In the third stage t3, a low-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a low-level signal Reset3 is applied to the third reset signal terminal R3, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a high-level signal Gate4 is applied to the second scan signal terminal G4, and a high-level signal em is applied to the light emission control signal terminal EM.

[0129] The first transistor T1 is turned on under the control of the Gate1 signal at the first control signal terminal G1. The turned-on first transistor T1 provides the signal at the first reference voltage terminal V1 to the first node A, and the voltage of the first node A remains Vgh. The ninth transistor T9 is turned on under the control of the Reset1 signal at the first reset signal terminal R1. The turned-on ninth transistor T9 provides the signal at the Vinit signal at the first initialization signal terminal F to the first terminal of the light-emitting device F. The tenth transistor T10 is turned on under the control of the Reset3 signal at the third reset signal terminal R3. The turned-on tenth transistor T10 provides the signal at the Vinit3 signal at the third initialization signal terminal TD to the first terminal of the driving transistor TD. At the same time, under the storage function of the compensation capacitor Cst, the driving transistor TD maintains the conducting state of the previous stage. The turned-on driving transistor TD provides the initialization signal received at the first terminal to the second terminal to charge and reset the driving transistor TD.

[0130] In the fourth stage t4, a high-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Reset3 is applied to the third reset signal terminal R3, a high-level signal Gate1 is applied to the first control signal terminal G1, a low-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a high-level signal Gate4 is applied to the second scan signal terminal G4, and a low-level signal em is applied to the light emission control signal terminal EM.

[0131] The second transistor T2 is turned on under the control of the signal Gate2 at the second control signal terminal G2. The turned-on second transistor T2 provides the signal of the second reference voltage terminal V2 to the first node A. The voltage of the first node A jumps from Vgh to the voltage of the signal of the second reference voltage terminal V2. The compensation capacitor Cst couples the voltage change value ΔV of the first node A to the gate of the driving transistor TD. The gate voltage Vg of the driving transistor TD becomes Vdata+Vth+ΔV.

[0132] The sixth transistor T6 and the seventh transistor T7 are turned on under the control of the light-emitting control signal EM. The turned-on sixth transistor T6 provides the power supply voltage Vdd input at the first power supply terminal VDD to the source of the driving transistor TD. Then the source voltage Vs of the driving transistor TD is Vdd. The driving transistor TD generates a driving current whose magnitude is independent of the power supply voltage Vdd. The driving current flows through the turned-on transistor and reaches the first electrode of the light-emitting device F, and the light-emitting device F emits light.

[0133] Typically, before a pixel driving circuit drives a light-emitting device to emit light, it writes data voltage. The time required for writing the data voltage (i.e., the black insertion time) is generally between two and ten microseconds. During this time, the display product does not emit light and displays black stripes. The longer the black insertion time, the more obvious the black stripes become, resulting in flickering and reducing the display effect.

[0134] To address the aforementioned issues, a data compensation circuit is implemented to write the data voltage of the current display frame into the pixel drive circuit in advance during the illumination phase of the previous display frame. This improves the delay in data voltage input, reduces black insertion time, avoids flickering caused by excessive black insertion time, and enhances the display effect.

[0135] Figures 8 to 10 show schematic diagrams of some ultrasonic pixel circuits provided in the embodiments of this application. Referring to Figures 8 to 10, this embodiment modifies the implementation methods of the embodiments shown in Figures 1 to 3. The differences between this embodiment and the above embodiments are only described below, and the similarities are not repeated here.

[0136] For example, as shown in Figures 8 to 10, the pixel driving circuit described above further includes:

[0137] The data compensation circuit 9, coupled to the data signal terminal Data and the second node B, is configured to provide the data voltage Vdata input at the data signal terminal Data to the second node B in response to the signal of the data compensation signal terminal S.

[0138] The data writing circuit 2 is coupled to the second node B and is configured to provide the data voltage Vdata of the second node B to the first terminal of the driving transistor TD in response to the signal of the first scan signal terminal G3.

[0139] For example, as shown in Figures 11 and 12, the data compensation circuit 9 includes: a third transistor T3 and a first capacitor C1;

[0140] The first terminal of the third transistor T3 is coupled to the data signal terminal Data, the second terminal of the third transistor T3 is coupled to the second node B, and the gate of the third transistor T3 is coupled to the data compensation signal terminal S.

[0141] The first terminal of the first capacitor C1 is coupled to the third reference voltage terminal V3, and the second terminal of the first capacitor C1 is coupled to the second node B.

[0142] For example, as shown in the timing diagram of the data compensation signal terminal S as shown in Figure 13, the low level on the left indicates that the signal sw of the data compensation signal terminal S is low during the illumination phase of the previous display frame, which is used to control the third transistor T3 to write the data voltage of the current display frame into the second node B in advance during the illumination phase of the previous display frame; the low level on the right indicates that the signal sw of the data compensation signal terminal S is low during the illumination phase of the current display frame, which is used to control the third transistor T3 to write the data voltage of the next display frame into the second node B in advance during the illumination phase of the current display frame.

[0143] For example, the third transistor T3 is an oxide thin-film transistor. Using an oxide thin-film transistor for the third transistor T3 can reduce leakage current, improve the reliability of the pixel driving circuit, and enhance the display effect.

[0144] As shown in Figures 11 and 12, in the pixel driving circuit, the larger the capacitance value of the first capacitor C1, the slower the data voltage Vdata of the second node B decays. Therefore, a first capacitor C1 with a larger capacitance value can be used to improve the stability of the data voltage Vdata of the second node B.

[0145] Simulation of the pixel driving circuit shown in Figure 11 yields the following Table 1, where the first capacitor C1 uses different capacitance values:

[0146] Table 1

[0147] Where Vd represents the drain voltage of the driving transistor TD, and Vgd represents the difference between the source and drain voltages of the driving transistor TD; in the Vdata column, "Initial" indicates the initial value of the data voltage Vdata provided by the third transistor T3 to the second node B, and "Output" indicates the value of the data voltage Vdata provided by the second node B to the fifth transistor T5. Table 1 shows that when the capacitance of the first capacitor C1 is 0.5pF, the data voltage Vdata decays by approximately 7%; when the capacitance of the first capacitor C1 is 2pF, the data voltage Vdata decays by approximately 1%. That is, the larger the capacitance of the first capacitor C1, the slower the data voltage Vdata stored in the second node B decays, and vice versa. Therefore, the capacitance value of the first capacitor C1 can be selected according to the requirements of the data voltage Vdata, without specific limitations.

[0148] As shown in Figures 11 and 12, the magnitude of the driving current is related to the W / L ratio of the driving transistor TD channel. The larger the driving current, the larger the W / L ratio of the driving transistor TD channel needs to be. Since the sixth transistor T6 and the seventh transistor T7 are located in the light-emitting path, they need to carry a large current, and the voltage across their terminals should be small. Therefore, the W / L ratio of their channels needs to be greater than that of the driving transistor TD channel. Other transistors are mainly used as switches and do not need to carry a large current, so the W / L ratio of their channels can be set to be smaller.

[0149] For example, the third reference voltage terminal V3 and the first reference voltage terminal V1 are the same signal terminal.

[0150] For example, in the pixel driving circuit shown in FIG11, the first reference voltage terminal V1, the third reference voltage terminal V3, the first initialization signal terminal Vinit1, and the second initialization signal terminal Vinit2 are the same signal terminal, thereby reducing the number of signal terminals, reducing the complexity of the pixel driving circuit, and reducing production costs.

[0151] This disclosure also provides a driving method for driving the pixel driving circuit shown in FIG8, including:

[0152] In the first stage, the power compensation circuit 1 responds to the signal of the first control signal terminal G1 and provides the signal of the first reference voltage terminal V1 to the first node A.

[0153] In the second stage, the power compensation circuit 1 responds to the signal of the first control signal terminal G1 and provides the signal of the first reference voltage terminal V1 to the first node A; the data writing circuit 2 responds to the signal of the first scan signal terminal G3 and provides the data voltage Vdata of the second node B to the first terminal of the driving transistor TD.

[0154] In the third stage of the previous display frame, the data compensation circuit 9 responds to the signal of the data compensation signal terminal S and provides the data voltage Vdata of the current display frame input by the data signal terminal Data to the second node B. Under the storage effect of the first capacitor C1, the voltage of the second node B is maintained at the data voltage Vdata.

[0155] In the third stage, the power compensation circuit 1 responds to the signal of the second control signal terminal G2 and provides the signal of the second reference voltage terminal V2 to the first node A; the compensation capacitor Cst couples the voltage change value of the first node A to the gate of the driving transistor TD; the driving transistor TD responds to the voltage change value and the data voltage Vdata, generates a driving current and outputs it to the first pole of the light-emitting device F;

[0156] The data compensation circuit 9 responds to the signal at the data compensation signal terminal S and provides the data voltage Vdata of the next display frame input at the data signal terminal Data to the second node B. Under the storage effect of the first capacitor C1, the voltage of the second node B is maintained at the data voltage Vdata.

[0157] In the pixel driving circuit shown in Figure 11, the first reset signal terminal R1 and the second reset signal terminal R2 are the same signal terminal; the first control signal terminal G1, the first scan signal terminal G3, and the second scan signal terminal G4 are the same signal terminal; the second control signal terminal G2 and the light emission control signal terminal EM are the same signal terminal; the first initialization signal terminal Vinit1 and the second initialization signal terminal Vinit2 are the same signal terminal; and the second reference voltage terminal V2 and the first power supply terminal VDD are the same signal terminal. The following description, using this pixel driving circuit as an example and referring to the signal timing diagram shown in Figure 13, illustrates the operation of the pixel driving circuit provided in this embodiment.

[0158] Specifically, the first stage t1, the second stage t2, and the third stage t3 are selected from the signal timing diagram shown in Figure 13. It should be noted that the signal timing diagram shown in Figure 13 only represents the operation of a single pixel driving circuit within one frame. The operation of this pixel driving circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0159] In the first stage t1, a low-level signal Reset1 is applied to the first reset signal terminal R1, a low-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a high-level signal Gate4 is applied to the second scan signal terminal G4, a high-level signal em is applied to the light emission control signal terminal EM, and a high-level signal sw is applied to the data compensation signal terminal S.

[0160] The eighth transistor T8 is turned on under the control of the signal Reset2 at the second reset signal terminal R2. The turned-on eighth transistor T8 provides the signal Vinit2 at the second initialization signal terminal to the gate of the driving transistor TD. The ninth transistor T9 is turned on under the control of the signal Reset1 at the first reset signal terminal R1. The turned-on ninth transistor T9 provides the signal Vinit1 at the first initialization signal terminal to the first electrode of the light-emitting device F.

[0161] In the second stage t2, a high-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a low-level signal Gate3 is applied to the first scan signal terminal G3, a low-level signal Gate4 is applied to the second scan signal terminal G4, a high-level signal em is applied to the light emission control signal terminal EM, and a high-level signal sw is applied to the data compensation signal terminal S.

[0162] The first transistor T1 is turned on under the control of the first control signal terminal G1 signal Gate1. The turned-on first transistor T1 provides the signal of the first reference voltage terminal V1 to the first node A. At this time, the voltage of the first node A is the voltage Vgh of the signal of the first reference voltage terminal V1. The fifth transistor T5 is turned on under the control of the first scan signal terminal G3 signal Gate3. The fourth transistor T4 is turned on under the control of the second scan signal terminal G4 signal Gate4. The driving transistor TD maintains the conducting state of the previous stage under the storage function of the compensation capacitor Cst. The turned-on fifth transistor T5, driving transistor TD, and fourth transistor T4 provide the data voltage Vdata of the second node B to the gate of the driving transistor TD. The gate voltage Vg of the driving transistor TD becomes Vdata + Vth.

[0163] In the third stage t3 of the previous display frame, the third transistor T3 is turned on under the control of the signal sw at the data compensation signal terminal S. The turned-on third transistor T3 provides the data voltage Vdata of the current display frame input at the data signal terminal Data to the second node B.

[0164] In the third stage t3, a high-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Gate1 is applied to the first control signal terminal G1, a low-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a high-level signal Gate4 is applied to the second scan signal terminal G4, a low-level signal em is applied to the light emission control signal terminal EM, and a low-level signal sw is applied to the data compensation signal terminal S.

[0165] The second transistor T2 is turned on under the control of the signal Gate2 at the second control signal terminal G2. The turned-on second transistor T2 provides the signal at the second reference voltage terminal V2 to the first node A. At this time, the voltage of the first node A jumps from the voltage Vgh of the signal at the first reference voltage terminal V1 to the voltage of the signal at the second reference voltage terminal V2, which is the power supply voltage Vdd input at the first power supply terminal VDD. The compensation capacitor Cst couples the voltage change value (Vdd-Vgh) of the first node A to the gate of the driving transistor TD. At this time, the gate voltage Vg of the driving transistor TD becomes Vdata+Vth+(Vdd-Vgh); the sixth transistor T6, the seventh transistor... The body transistor T7 is turned on under the control of the light-emitting control signal EM signal em. The turned-on sixth transistor T6 provides the power supply voltage Vdd input from the first power supply terminal VDD to the first terminal of the driving transistor TD. At this time, the source voltage Vs of the driving transistor TD is Vdd. The driving transistor TD generates a driving current whose magnitude is independent of the power supply voltage Vdd. The driving current flows through the turned-on seventh transistor T7 to the first terminal of the light-emitting device. The third transistor T3 is turned on under the control of the data compensation signal terminal S signal sw. The turned-on third transistor T3 provides the data voltage Vdata of the next display frame input from the data signal terminal Data to the second node B.

[0166] The operation of the pixel driving circuit provided in the embodiments of this disclosure will be described below using the pixel driving circuit shown in Figure 12 as an example and in conjunction with the signal timing diagram shown in Figure 14.

[0167] Specifically, the first stage t1, the second stage t2, the third stage t3, and the fourth stage t4 are selected from the signal timing diagram shown in Figure 14. It should be noted that the signal timing diagram shown in Figure 14 only represents the operation of a single pixel driving circuit within one frame. The operation of this pixel driving circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0168] In the first stage t1, a high-level signal Reset1 is applied to the first reset signal terminal R1, a low-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Reset3 is applied to the third reset signal terminal R3, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a low-level signal Gate4 is applied to the second scan signal terminal G4, a high-level signal em is applied to the light emission control signal terminal EM, and a high-level signal sw is applied to the data compensation signal terminal S.

[0169] The first transistor T1 is turned on under the control of the signal Gate1 at the first control signal terminal G1. The turned-on first transistor T1 provides the signal of the first reference voltage terminal V1 to the first node A. At this time, the voltage of the first node A is the voltage Vgh of the signal of the first reference voltage terminal V1. The eighth transistor T8 is turned on under the control of the signal Reset2 at the second reset signal terminal R2. The turned-on eighth transistor T8 provides the signal of the second initialization signal terminal Vinit2 to the first terminal of the fourth transistor T4. The fourth transistor T4 is turned on under the control of the signal Gate4 at the second scan signal terminal G4. The turned-on fourth transistor T4 provides the initialization signal received at the first terminal to the gate of the driving transistor TD.

[0170] In the second stage t2, a high-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Reset3 is applied to the third reset signal terminal R3, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a low-level signal Gate3 is applied to the first scan signal terminal G3, a low-level signal Gate4 is applied to the second scan signal terminal G4, a high-level signal em is applied to the light emission control signal terminal EM, and a high-level signal sw is applied to the data compensation signal terminal S.

[0171] The first transistor T1 is turned on under the control of the first control signal terminal G1 signal Gate1. The turned-on first transistor T1 provides the signal of the first reference voltage terminal V1 to the first node A, and the voltage of the first node A is still Vgh. The fifth transistor T5 is turned on under the control of the first scan signal terminal G3 signal Gate3. The fourth transistor T4 is turned on under the control of the second scan signal terminal G4 signal Gate4. At the same time, under the storage function of the compensation capacitor Cst, the driving transistor TD maintains the conducting state of the previous stage. The turned-on fourth transistor T4, driving transistor TD, and fifth transistor T5 provide the data voltage Vdata of the second node B to the gate of the driving transistor TD. At this time, the gate voltage Vg of the driving transistor TD is Vdata + Vth.

[0172] In the fourth stage t4 of the previous display frame, the third transistor T3 is turned on under the control of the signal sw at the data compensation signal terminal S. The turned-on third transistor T3 provides the data voltage Vdata of the current display frame input at the data signal terminal Data to the second node B.

[0173] In the third stage t3, a low-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a low-level signal Reset3 is applied to the third reset signal terminal R3, a low-level signal Gate1 is applied to the first control signal terminal G1, a high-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a high-level signal Gate4 is applied to the second scan signal terminal G4, a high-level signal em is applied to the light emission control signal terminal EM, and a high-level signal sw is applied to the data compensation signal terminal S.

[0174] The first transistor T1 is turned on under the control of the Gate1 signal at the first control signal terminal G1. The turned-on first transistor T1 provides the signal at the first reference voltage terminal V1 to the first node A, and the voltage of the first node A remains Vgh. The ninth transistor T9 is turned on under the control of the Reset1 signal at the first reset signal terminal R1. The turned-on ninth transistor T9 provides the signal at the Vinit signal at the first initialization signal terminal F to the first terminal of the light-emitting device F. The tenth transistor T10 is turned on under the control of the Reset3 signal at the third reset signal terminal R3. The turned-on tenth transistor T10 provides the signal at the Vinit3 signal at the third initialization signal terminal TD to the first terminal of the driving transistor TD. At the same time, under the storage function of the compensation capacitor Cst, the driving transistor TD maintains the conducting state of the previous stage. The turned-on driving transistor TD provides the initialization signal received at the first terminal to the second terminal to charge and reset the driving transistor TD.

[0175] In the fourth stage t4, a high-level signal Reset1 is applied to the first reset signal terminal R1, a high-level signal Reset2 is applied to the second reset signal terminal R2, a high-level signal Reset3 is applied to the third reset signal terminal R3, a high-level signal Gate1 is applied to the first control signal terminal G1, a low-level signal Gate2 is applied to the second control signal terminal G2, a high-level signal Gate3 is applied to the first scan signal terminal G3, a high-level signal Gate4 is applied to the second scan signal terminal G4, a low-level signal em is applied to the light emission control signal terminal EM, and a low-level signal sw is applied to the data compensation signal terminal S.

[0176] The second transistor T2 is turned on under the control of the signal Gate2 at the second control signal terminal G2. The turned-on second transistor T2 provides the signal of the second reference voltage terminal V2 to the first node A. The voltage of the first node A jumps from Vgh to the voltage of the signal of the second reference voltage terminal V2. The compensation capacitor Cst couples the voltage change value ΔV of the first node A to the gate of the driving transistor TD. The gate voltage Vg of the driving transistor TD becomes Vdata+Vth+ΔV.

[0177] The sixth transistor T6 and the seventh transistor T7 are turned on under the control of the light-emitting control signal EM. The turned-on sixth transistor T6 provides the power supply voltage Vdd input at the first power supply terminal VDD to the first terminal of the driving transistor TD. Then the source voltage Vs of the driving transistor TD is Vdd. The driving transistor TD generates a driving current whose magnitude is independent of the power supply voltage Vdd. The driving current flows through the turned-on seventh transistor T7 to the first terminal of the light-emitting device F, and the light-emitting device F emits light.

[0178] The third transistor T3 is turned on under the control of the signal sw at the data compensation signal terminal S. The turned-on third transistor T3 provides the data voltage Vdata of the next display frame input at the data signal terminal Data to the second node B.

[0179] This disclosure also provides a display panel, as shown in FIG15, including a pixel driving circuit px as shown in FIG11.

[0180] For example, as shown in FIG15, the display panel further includes: a first gate drive circuit GOA1, the first gate drive circuit GOA1 including a plurality of cascaded first shift register units SR1;

[0181] Each first shift register unit SR1 includes a gate signal generation circuit M and an inverting circuit N. The gate signal generation circuit M is configured to output a first control signal to the first control signal terminal G1 of the pixel driving circuit px and the inverting circuit N. The inverting circuit N is configured to invert the first control signal and then output a second control signal to the second control signal terminal G2 of the pixel driving circuit px.

[0182] For example, as shown in Figure 15, in the first-stage shift register unit SR1(1), the input signal terminal of the gate signal generation circuit M is coupled to the frame trigger signal terminal (not shown in the figure), and the signal output terminal of the gate signal generation circuit M is coupled to the input signal terminal of the inverting circuit N, the first control signal terminal G1 of the first row pixel driving circuit px, and the input signal terminal of the gate signal generation circuit M in the second-stage shift register unit SR1(2). The signal output terminal of the inverting circuit N is coupled to the second control signal terminal G2 of the first row pixel driving circuit px. In the second-stage shift register unit SR1(2), the signal output terminal of the gate signal generation circuit M is coupled to the input signal terminal of the inverting circuit N, the first control signal terminal G1 of the second row pixel driving circuit px, and the input signal terminal of the gate signal generation circuit M in the third-stage shift register unit SR1(3). The signal output terminal of the inverting circuit N is coupled to the second control signal terminal G2 of the second row pixel driving circuit px. The other first shift register units SR1 have the same connection logic, which will not be described in detail here.

[0183] For example, in the nth stage first shift register unit SR1(n) shown in FIG16, the signal output terminal Gn(1) of the gate signal generation circuit M is coupled to the input signal terminal of the inverting circuit N, the input signal terminal of the gate signal generation circuit M is coupled to the signal output terminal Gn-1(1) of the (n-1)th stage first shift register unit SR1(n-1), and the signal output terminal Gn(2) of the inverting circuit N is coupled to the second control signal terminal G2 of the nth row pixel driving circuit.

[0184] As shown in Figure 16, the gate signal generation circuit M includes transistors M1-M8 and capacitors C1 and C2. The first terminal of transistor M1 is coupled to the signal output terminal Gn-1(1) of the gate signal generation circuit M of the (n-1)th stage first shift register unit SR1(n-1). The second terminal of transistor M1 is coupled to the first node A, and the gate of transistor M1 is coupled to the first clock signal terminal CK. The first terminal of transistor M2 is coupled to the first clock signal terminal CK, the second terminal of transistor M2 is coupled to the second node B, and the gate of transistor M2 is coupled to the first node A. The first terminal of transistor M3 is coupled to the first power supply voltage terminal VL, the second terminal of transistor M3 is coupled to the second node B, and the gate of transistor M3 is coupled to the first clock signal terminal CK. The first terminal of transistor M4 is coupled to the second power supply voltage terminal VH, and the second terminal of transistor M4 is coupled to the signal output terminal Gn(1). The gate of transistor M4 is coupled to the second node B; the first terminal of transistor M5 is coupled to the second clock signal terminal CB, the second terminal of transistor M5 is coupled to the signal output terminal Gn(1), and the gate of transistor M5 is coupled to the second terminal of transistor M8; the first terminal of transistor M6 is coupled to the second power supply voltage terminal VH, the second terminal of transistor M6 is coupled to the first terminal of transistor M7, and the gate of transistor M6 is coupled to the second node B; the second terminal of transistor M7 is coupled to the first node A, and the gate of transistor M7 is coupled to the second clock signal terminal CB; the first terminal of transistor M8 is coupled to the first node A, and the gate of transistor M8 is coupled to the first power supply voltage terminal VL; the first terminal of capacitor C1 is coupled to the second terminal of transistor M8, and the second terminal of capacitor C1 is coupled to the signal output terminal Gn(1); the first terminal of capacitor C2 is coupled to the second node B, and the second terminal of capacitor C2 is coupled to the second power supply voltage terminal VH.

[0185] As shown in Figure 16, the inverter circuit N includes transistors M9-M12 and capacitor C3. The first terminal of transistor M9 is coupled to the second power supply voltage terminal VH, the second terminal of transistor M9 is coupled to the gate of transistor M12, and the gate of transistor M9 is coupled to the signal output terminal Gn(1). The first terminal of transistor M10 is coupled to the first power supply voltage terminal VL, the second terminal of transistor M10 is coupled to the gate of transistor M12, and the gate of transistor M10 is coupled to the first power supply voltage terminal VL. The first terminal of transistor M11 is coupled to the second power supply voltage terminal VH, the second terminal of transistor M11 is coupled to the signal output terminal Gn(2), and the gate of transistor M11 is coupled to the signal output terminal Gn(1). The first terminal of transistor M12 is coupled to the first power supply voltage terminal VL, and the second terminal of transistor M12 is coupled to the signal output terminal Gn(2).

[0186] For example, as shown in FIG17, the display panel further includes: a second gate drive circuit GOA2, the second gate drive circuit GOA2 including a plurality of cascaded second shift register units SR2;

[0187] The signal output terminal of the second shift register unit SR2(n) of the nth stage is coupled to the first control signal terminal G1 and the first scan signal terminal G3 of the pixel driving circuit px of the i-th row; where n and i are both positive integers.

[0188] For example, as shown in Figure 17, the signal output terminal of the (n-1)th stage second shift register unit SR2(n-1) is coupled to the first reset signal terminal R1 and the second reset signal terminal R2 of the i-th row pixel driving circuit px, and the signal output terminal of the (n+1)th stage second shift register unit SR2(n+1) is coupled to the data compensation signal terminal S of the i-th row pixel driving circuit px.

[0189] For example, in the second gate drive circuit GOA2, the input signal terminal of the first-stage second shift register unit SR2(1) is coupled to the frame trigger signal terminal, and the signal output terminal of the nth-stage second shift register unit SR2(n) is coupled to the input signal terminal of the (n+m)th-stage second shift register unit SR2(n+m), where m and n are both positive integers. For example, when m is 1, the signal output terminal of the nth-stage second shift register unit SR2(n) is coupled to the input signal terminal of the (n+1)th-stage second shift register unit SR2(n+1); when m is 2, the signal output terminal of the nth-stage second shift register unit SR2(n) is coupled to the input signal terminal of the (n+2)th-stage second shift register unit SR2(n+2).

[0190] For example, the aforementioned display panel further includes: multiple initialization signal lines, wherein the first reference voltage terminal, the third reference voltage terminal, the first initialization signal terminal, and the second initialization signal terminal of a row of pixel driving circuits are coupled to the same initialization signal line, or,

[0191] The first reference voltage terminal, the third reference voltage terminal, the first initialization signal terminal, and the second initialization signal terminal of a pixel driving circuit are coupled to the same initialization signal line.

[0192] For example, as shown in FIG18, the display panel includes the pixel driving circuit shown in FIG11. The first reference voltage terminal, the third reference voltage terminal, the first initialization signal terminal and the second initialization signal terminal of the pixel driving circuit are the same signal terminal. The first reference voltage terminal, the third reference voltage terminal, the first initialization signal terminal and the second initialization signal terminal of a row of pixel driving circuit are coupled to the initialization signal terminal Vinit through the same initialization signal line L.

[0193] This disclosure also provides a display device, including the display panel described above.

[0194] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0195] The pixel driving circuit, driving method, display panel, and display device provided in this disclosure embodiment enable the brightness of the light-emitting device to be related only to the signal and data voltage at the first reference voltage terminal and not to the power supply voltage input at the first power supply terminal when driving the light-emitting device. This avoids the influence of voltage drop on the power supply traces that transmit the power supply voltage on the brightness of the light emission. It also enables the data voltage of the current display frame to be written into the pixel driving circuit in advance during the light emission stage of the previous display frame, thereby improving the delay phenomenon of data voltage during the input process, reducing the black insertion time, avoiding flickering problems caused by excessive black insertion time, and improving the display effect.

[0196] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0197] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A pixel driving circuit, wherein, include: The power compensation circuit is configured to provide a signal from a first reference voltage terminal to a first node in response to a signal from a first control signal terminal, and to provide a signal from a second reference voltage terminal to the first node in response to a signal from a second control signal terminal. A driving transistor is coupled between the first power supply terminal and the first electrode of the light-emitting device; A compensation capacitor is coupled between the gate of the driving transistor and the first node; The data writing circuit is configured to provide a data voltage to the first terminal of the driving transistor in response to a signal at the first scan signal terminal.

2. The pixel driving circuit as described in claim 1, wherein, The power compensation circuit includes: a first transistor and a second transistor; The first terminal of the first transistor is coupled to the first reference voltage terminal, the second terminal of the first transistor is coupled to the first node, and the gate of the first transistor is coupled to the first control signal terminal. The first terminal of the second transistor is coupled to the second reference voltage terminal, the second terminal of the second transistor is coupled to the first node, and the gate of the second transistor is coupled to the second control signal terminal.

3. The pixel driving circuit as described in claim 2, wherein, The first transistor and the second transistor are of the same type, and the signal at the first control signal terminal is out of phase with the signal at the second control signal terminal.

4. The pixel driving circuit as described in claim 2, wherein, The first transistor and the second transistor are of different types, and the first control signal terminal and the second control signal terminal are the same signal terminal.

5. The pixel driving circuit according to any one of claims 1-4, wherein, The data writing circuit is coupled to the data signal terminal and is configured to provide the data voltage input to the data signal terminal to the first pole of the driving transistor in response to the signal at the first scan signal terminal.

6. The pixel driving circuit according to any one of claims 1-4, wherein, Also includes: A data compensation circuit, coupled to a data signal terminal and a second node, is configured to provide the data voltage input at the data signal terminal to the second node in response to a signal at the data compensation signal terminal. The data writing circuit is coupled to the second node and is configured to provide the data voltage of the second node to the first terminal of the driving transistor in response to a signal at the first scan signal terminal.

7. The pixel driving circuit as described in claim 6, wherein, The data compensation circuit includes: a third transistor and a first capacitor; The first terminal of the third transistor is coupled to the data signal terminal, the second terminal of the third transistor is coupled to the second node, and the gate of the third transistor is coupled to the data compensation signal terminal. The first terminal of the first capacitor is coupled to the third reference voltage terminal, and the second terminal of the first capacitor is coupled to the second node.

8. The pixel driving circuit as described in claim 7, wherein, The third reference voltage terminal is the same signal terminal as the first reference voltage terminal.

9. The pixel driving circuit according to any one of claims 1-8, wherein, Also includes: A first reset circuit is configured to provide a signal from a first initialization signal terminal to a first electrode of the light-emitting device in response to a signal from a first reset signal terminal. The second reset circuit is configured to provide a signal from the second initialization signal terminal to the gate or second electrode of the driving transistor in response to a signal from the second reset signal terminal.

10. The pixel driving circuit as described in claim 9, wherein, At least two of the first initialization signal terminal, the second initialization signal terminal, and the first reference voltage terminal are the same signal terminal.

11. The pixel driving circuit according to any one of claims 1-10, wherein, Also includes: A threshold compensation circuit is configured to turn on the second terminal and gate of the driving transistor in response to a signal at the second scan signal terminal.

12. The pixel driving circuit as described in claim 11, wherein, The first scan signal terminal and the second scan signal terminal are the same signal terminal.

13. The pixel driving circuit according to any one of claims 1-12, wherein, Also includes: A first light-emitting control circuit, coupled between the first power supply terminal and the first electrode of the driving transistor, is configured to provide the power supply voltage of the first power supply terminal to the first electrode of the driving transistor in response to a signal from the light-emitting control signal terminal.

14. The pixel driving circuit as described in claim 13, wherein, Also includes: The second light-emitting control circuit, coupled between the second terminal of the driving transistor and the first terminal of the light-emitting device, is configured to conduct the second terminal of the driving transistor and the first terminal of the light-emitting device in response to a signal from the light-emitting control signal terminal.

15. The pixel driving circuit according to any one of claims 1-14, wherein, The second control signal terminal and the light emission control signal terminal are the same signal terminal.

16. The pixel driving circuit according to any one of claims 1-15, wherein, The first scan signal terminal and the first control signal terminal are the same signal terminal; or, The second reference voltage terminal and the first power supply terminal are the same signal terminal.

17. A driving method for a pixel driving circuit as described in any one of claims 1-16, wherein, include: In the first stage, the power compensation circuit responds to the signal at the first control signal terminal and provides the signal at the first reference voltage terminal to the first node. In the second stage, the power compensation circuit responds to the signal at the first control signal terminal by providing the signal at the first reference voltage terminal to the first node; the data writing circuit responds to the signal at the first scan signal terminal by providing the data voltage to the first terminal of the driving transistor. In the third stage, the power compensation circuit responds to the signal at the second control signal terminal and provides the signal at the second reference voltage terminal to the first node. The compensation capacitor couples the voltage change value of the first node to the gate of the driving transistor; The driving transistor responds to the voltage change value and the data voltage, generates a driving current, and outputs it to the first electrode of the light-emitting device.

18. A display panel, wherein, Includes the pixel driving circuit as described in any one of claims 1-16.

19. The display panel as claimed in claim 18, wherein, Also includes: A first gate driving circuit, the first gate driving circuit including a plurality of cascaded first shift register units; Each of the first shift register units includes a gate signal generation circuit and an inverting circuit. The gate signal generation circuit is configured to output a first control signal to the first control signal terminal of the pixel driving circuit and the inverting circuit. The inverting circuit is configured to invert the first control signal and then output a second control signal to the second control signal terminal of the pixel driving circuit.

20. The display panel as claimed in claim 18, wherein, Also includes: The second gate drive circuit includes a plurality of cascaded second shift register units; The signal output terminal of the second shift register unit of the nth stage is coupled to the first control signal terminal and the first scan signal terminal of the pixel driving circuit of the i-th row; where n and i are both positive integers.

21. The display panel as claimed in claim 20, wherein, The signal output terminal of the (n-1)th stage second shift register unit is coupled to the first reset signal terminal and the second reset signal terminal of the i-th row pixel driving circuit, and the signal output terminal of the (n+1)th stage second shift register unit is coupled to the data compensation signal terminal of the i-th row pixel driving circuit.

22. The display panel according to any one of claims 18-21, wherein, Also includes: Multiple initialization signal lines, where the first reference voltage terminal, third reference voltage terminal, first initialization signal terminal, and second initialization signal terminal of a row pixel driving circuit are coupled to the same initialization signal line, or... The first reference voltage terminal, the third reference voltage terminal, the first initialization signal terminal, and the second initialization signal terminal of a pixel driving circuit are coupled to the same initialization signal line.

23. A display device, wherein, Includes the display panel as described in any one of claims 18-22.

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