Asymmetric common source inductance for reducing turn-off overvoltage in mosfet

Abstract

A circuit includes a metal oxide semiconductor field effect transistor (MOSFET) (110) having a gate, a source, and a drain. The circuit also includes a first inductor (140A) and a second inductor (140B). The first inductor has a small inductance value, and the small inductance value is smaller than the larger inductance value of the second inductor. The circuit also includes a switch (130) configured to include the first inductor in a current path shared by a gate loop and a source loop of the MOSFET when the MOSFET is on, and to include the second inductor in a current path shared by the gate loop and the source loop when the MOSFET is off.

Description

Cross-references to related applications on asymmetric common-source inductors for reducing turn-off overvoltage in MOSFETs

[0001] This patent application is a continuation of and claims priority to U.S. Patent Application No. 18 / 636,445, filed April 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This specification relates to semiconductor devices, and more specifically to transistor devices, such as metal-oxide-semiconductor field-effect transistors. Background Technology

[0003] Power transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) are used in all kinds of consumer electronics, automotive electronics, and industrial electronics systems. Representative examples of applications for these devices include inverters for power conversion in renewable energy systems and power topologies in powertrain systems for electric vehicles. These applications may involve known converter topologies or transistor configurations such as resonant inverters, full-bridge, half-bridge, asymmetric half-bridge, etc. Each of these different transistor configurations presents one or more networks consisting of high-side (HS) and low-side (LS) switches that operate complementaryly and are coupled to a common switching node. These switches can be transistors (if the switches are driven by a control voltage) or diodes (if the switches are not driven by a control voltage). Parasitic inductance (associated with the HS and LS switches and / or in the printed circuit board (PCB) used to implement the power converter) and the output capacitance (C) of the LS transistor are interdependent. oss Combinations can lead to, for example, changes in drain-to-source voltage (V). DS ) or current (I D Overshoot and / or ringing at the switching node. Such overshoot and / or ringing may cause the voltage at the switching node to exceed the breakdown voltage of the LS transistor, such as the drain-to-source breakdown voltage (BV) of an LSMOSFET. dss When BV dss If the power is exceeded, the power conversion efficiency of the power converter may be reduced and / or the transistor may be damaged or destroyed. Summary of the Invention

[0004] In a general aspect, a circuit is provided that includes a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain. The circuit also includes a first inductor, a second inductor, and a switch. The first inductor has a smaller inductance value than the larger inductance value of the second inductor. The switch is configured to include the first inductor in a current path shared by the gate and source circuits of the MOSFET when the MOSFET is turned on, and to include the second inductor in a current path shared by the gate and source circuits when the MOSFET is turned off.

[0005] In a general aspect, a circuit is provided that includes a metal-oxide-semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain. The circuit also includes a first inductor, a second inductor, a switch, and a current-limiting element, the first inductor, the second inductor, the switch, and the current-limiting element being connected in series in a source-drain current path and shared with the MOSFET's gate driver circuit. The switch is configured to close when the MOSFET is turned on, short-circuiting the second inductor and the current-limiting element, such that gate circuit current flows through the first inductor and bypasses the second inductor and the current-limiting element.

[0006] In a general aspect, one method includes positioning a first inductor and a second inductor adjacent to a source-drain current path shared with a gate driver loop associated with a MOSFET. The method also includes switching the gate loop current to flow through the first inductor when the MOSFET is turned on, and switching the gate loop current to flow through the second inductor when the MOSFET is turned off. Attached Figure Description

[0007] Figure 1 is a block diagram schematically illustrating a SiC MOSFET driver circuit in which the common-source inductor (Lcs) can switch between a smaller inductance in the MOSFET's on-state and a larger inductance in the MOSFET's off-state.

[0008] Figure 2 is a schematic circuit diagram illustrating the various parts of a driver circuit in which low-voltage auxiliary switches and resistors are used to implement an asymmetric small / large Lcs scheme for SiC MOSFETs.

[0009] Figure 3 illustrates an example circuit in which resistor R1 in the circuit of Figure 2 is replaced by a diode.

[0010] Figure 4A illustrates a plan view of an example circuit manufactured on a printed circuit board (PCB) having discrete components including power transistors assembled on the PCB using surface mount device (SMD) technology.

[0011] Figure 4B illustrates a plan view of an example circuit manufactured on a printed circuit board (PCB) having discrete components including power transistors assembled on the PCB using through-hole mounting (THM) technology.

[0012] Figure 5 shows a cross-sectional view of a semiconductor die including a co-integrated side-auxiliary MOSFET disposed adjacent to a vertical SiC MOSFET.

[0013] Figure 6 illustrates a package that includes a SiC MOSFET and an auxiliary switch fabricated on separate semiconductor dies (e.g., die A and die B, respectively).

[0014] Figure 7 illustrates the gate driver circuit coupled to the SiC MOSFET in Figure 1.

[0015] Figure 8 is a flowchart illustrating an example method for reducing turn-off overvoltage and switching power loss (e.g., turn-off power loss Eoff) in a power MOSFET.

[0016] Figure 9A illustrates a gate driver circuit for a SiC MOSFET with a first driver return path.

[0017] Figure 9B illustrates a gate driver circuit for the SiC MOSFET of Figure 9A with a second driver return path.

[0018] Figure 9C illustrates a gate driver circuit for the SiC MOSFET of Figure 3, which has a first auxiliary branch for a first driver return path and a second auxiliary branch for a second driver return path.

[0019] Figure 10A schematically illustrates a mixed-mode simulation model (TCAD-SPICE model) of a package that includes the circuit shown in Figure 2 within a dual-pulse test circuit.

[0020] Figure 10B illustrates the source-drain current, gate-to-source voltage, and drain-to-source voltage during MOSFET turn-on (corresponding to the state of the circuit shown in Figure 2).

[0021] Figure 10C illustrates the source-drain current, gate-to-source voltage, and drain-to-source voltage during MOSFET turn-off (corresponding to the state of the circuit shown in Figure 2). Detailed Implementation

[0022] This disclosure relates to circuits and devices (e.g., semiconductor devices) that can be implemented in power converters such as DC-DC power converters, power factor correction (PFC) boost converters, or three-phase inverters.

[0023] Silicon carbide (SiC) MOSFETs can be rated for applications at high voltages, such as exceeding 600 volts. The common source inductance (CSI or Lcs) is the inductance shared by the main current path and the gate driver loop in the MOSFET. Both the drain-source current and the gate-charge current of the MOSFET are carried by the Lcs. The Lcs described herein do not need to be formed from discrete or lumped inductor elements, but can be formed from distributed or parasitic inductor elements. The Lcs can vary depending on the device package (material and layout) and the device layout.

[0024] For small Lcs, SiC MOSFETs can exhibit faster turn-off and larger turn-off V. DS Overvoltage and corresponding large switching power losses (e.g., turn-off power loss Eoff). Furthermore, SiC MOSFETs with Kelvin connections (with small Lcs) can achieve avalanche conditions in hard-switching-based circuit topologies used in power converter circuits. Additionally, due to the large turn-off V that can be associated with SiC MOSFETs... DS Overvoltage testing: When tested with sequential time increments, SiC power MOSFETs exhibit small short-circuit wait times (SCWT) compared to single-event-to-fault testing.

[0025] Used to reduce the shutdown V DS Methods to reduce both overvoltage (Lcs) and turn-off power loss (Eoff) can be achieved in Si superjunction (SJ) MOSFETs by reducing the Lcs of the MOSFET. Reducing Lcs works in Si superjunction (SJ) MOSFETs, for example, to reduce overshoot and / or ringing at the switching node (e.g., in an associated power converter), while also reducing power conversion efficiency losses. Methods to reduce the Lcs for turn-on and turn-off of Si SJ MOSFETs may not be effective for SiC MOSFETs because the output charge Q of SiC MOSFETs... oss The drain-source charge can be several times smaller than the output charge of a SiSJ MOSFET (e.g., 4 to 5 times smaller), while the gate charge Q of a SiC MOSFET is much smaller. G It has roughly the same gate charge as the Si SJ MOSFET.

[0026] In a specific implementation example, based on the principles of this disclosure, an asymmetric common-source inductor (Lcs) scheme is implemented for the turn-on and turn-off of SiC MOSFETs.

[0027] In a specific implementation example, the driver circuitry associated with the SiC MOSFET may include inductor elements with different inductance values ​​(Lcs), which are interchangeably introduced into the gate-source loop of the SiC MOSFET. Gate current (Ig) G The current flows through this circuit to charge and discharge the parasitic capacitance of the SiC MOSFET during turn-on and turn-off transients. The inductor element may, for example, include a first inductor element with a smaller Lcs value and a second inductor element with a larger Lcs value. The first inductor element with the smaller Lcs value and the second inductor element with the larger Lcs value may be located in branch I. G In the current path. In an example implementation, the driver circuit may include a switch that, for example, introduces a first inductor with a small Lcs value into the gate-source loop of the SiC MOSFET when the MOSFET is in the on state, and introduces a second inductor with a larger Lcs value into the gate-source loop of the SiC MOSFET when the MOSFET is in the off state.

[0028] It should be noted that MOSFETs are voltage-controlled devices, and the gate current referred to herein is, for example, the current required to charge and discharge the parasitic capacitance during the turn-on and turn-off transients of the MOSFET.

[0029] Figure 1 is a schematic circuit diagram illustrating various parts of a driver circuit 100, in which the source-drain current (I00) is... D The common-source inductance (Lcs) in the current path can switch between a smaller inductance when the SiC MOSFET 110 is on and a larger inductance when the MOSFET is off.

[0030] As shown in Figure 1, the SiC MOSFET 110 may have a gate (G), a drain (D), and a source (S). In an example implementation, the SiC MOSFET 110 may be an N-channel power MOSFET.

[0031] As shown in Figure 1, the drain D can be coupled to the output load represented by diode 120 and output inductor (L) 122. A gate signal 101S (e.g., a rectangular pulse or square wave pulse) can be applied to the gate G through the gate resistor Rg to switch the SiC MOSFET 110 between the on and off states. The drain-to-source voltage V... DS The voltage transferred (applied) from the SiC MOSFET 110 to the output load is Vdrain-to-source.DS It can be related to the source-drain current I flowing between the drain D and the source S. D Correspondingly.

[0032] The gate signal 101S may have a rising edge RE of the turn-on MOSFET 110 and a falling edge FE of the turn-off MOSFET 110.

[0033] In an example embodiment, the driver circuit 100 may include a switch 130 (in addition to the SiC MOSFET 110 itself). Switch 130 may be configured to introduce an asymmetric inductance value (Lcs) into the gate-source loop of the SiC MOSFET. In an example embodiment, switch 130 may be closed, for example, in a first position 130A or a second position 130B. A smaller inductance (e.g., inductor 140A) may be positioned between the first position 130A and node N. In this case, node N may refer to a reference terminal of the gate driver. Furthermore, a larger inductance (e.g., inductor 140B) may be positioned between the second position 130B and node N.

[0034] The first position 130A and the second position 130B correspond to the on and off states of the SiC MOSFET 110, respectively. In the on state of the SiC MOSFET 110, the switch 130 can be closed in the first position 130A to introduce a smaller inductance (e.g., inductor 140A) into the gate-source circuit of the SiC MOSFET 110. In the off state of the SiC MOSFET 110, the switch 130 can be closed in the second position 130B to introduce a larger inductance (e.g., inductor 140B) into the gate-source circuit of the SiC MOSFET 110.

[0035] In the example implementation, for the example 650V SiC power MOSFET, the smaller inductance (e.g., inductor 140A) may be less than 0.5nH, and the larger inductance (e.g., inductor 140B) may be greater than 3.0nH.

[0036] In the example implementation, for the example 650V SiC power MOSFET, the smaller value inductance (e.g., inductor 140A) may be, for example, about 1.0nH or less (e.g., less than 0.5nH), and the larger value inductance (e.g., inductor 140B) may be, for example, in the range of 2.0nH to 10.0nH (e.g., greater than 3.0nH).

[0037] The asymmetry of the inductance value introduced in the gate-source loop can reduce turn-off overvoltage without compromising the switching power loss (e.g., turn-off power loss Eoff) of the SiCMOSFET 110.

[0038] In some example implementations, low-voltage auxiliary switches and current-limiting elements (e.g., resistors) can be used to achieve asymmetric small / large Lcs schemes during the turn-on / turn-off of SiCMOSFETs.

[0039] Figure 2 shows a circuit diagram schematically illustrating various parts of a driver circuit 200, in which low-voltage auxiliary switches and current-limiting elements (e.g., resistors) are used to implement an asymmetric small / large Lcs scheme for the SiC MOSFET 110.

[0040] In the driver circuit 200, a smaller inductor (e.g., inductor 150A) and a larger inductor (e.g., inductor 150B) are connected in series between the source S of the MOSFET 110 and node N in the main current path. When the auxiliary switch 160 is activated, the low-voltage auxiliary switch 160 can short-circuit or bypass the source-drain current I shared by the gate circuit and the power circuit. D The larger inductance in the path (e.g., inductor 150B). In an example implementation, auxiliary switch 160 may be a MOSFET with a source SA, drain DA, and gate GA. Resistor R1, extending from node N in the main current path, is connected in parallel with auxiliary switch 160. As shown in Figure 2, the source SA of auxiliary switch 160 may be connected to tap P1 between the smaller inductance (e.g., inductor 150A) and the larger inductance (e.g., inductor 150B). The drain DA of auxiliary switch 160 is connected to tap P2 between resistor R1 and gate resistor Rg. The first gate current (I) in driver circuit 200 G The return path or auxiliary branch (e.g., the first return path RT1 in Figure 7) extends from tap point P1 to tap point P2 via auxiliary switch 160. The first gate current (I...) G The current on the return path or auxiliary branch passes through the smaller-value inductor (e.g., inductor 150A) but bypasses the larger-value inductor (e.g., inductor 150B). The second gate current (I0) in the driver circuit 200... G A return path or auxiliary branch (e.g., the second return path RT2 in Figure 7 via resistor R1) extends from node N to tap point P2. Current on the second return path or auxiliary branch flows through both the smaller inductor (e.g., inductor 150A) and the larger inductor (e.g., inductor 150B). In other words, the switch is configured to open when the MOSFET is off to introduce the second inductor into the source-drain current path.

[0041] Different Lcs (e.g., Lcs = inductor 150A or Lcs = (inductor 150A + inductor 150B)) are shared between the gate circuit and the power circuit, depending on which driver return path is activated. If the driver return path is at tap P1, the voltage drop in Lcs (inductor 150A) caused by d(Id) / dt is small. If the driver return path is at node N, the voltage drop in Lcs (inductor 150Bb) caused by d(Id) / dt is small. D The voltage drop generated by dt is large. The voltage drop in Lcs has the opposite effect on the gate-source voltage (Vgs) applied to the SiC MOSFET 110 by the driver (e.g., driver signal 101S). This causes the transient response of the MOSFET to changes in Vgs to be suppressed or slowed down.

[0042] In the specific implementation example, when the SiC MOSFET is turned on, the gate-source voltage (Vgs) applied to the gate G of the SiC MOSFET 110 is determined by the voltage V across the small inductor in the first driver return path. i1 (For example, induced voltage V) i =L*di / dt) cancels out, and when the SiC MOSFET 110 is turned off, the gate-source voltage (Vgs) applied to the gate G of the SiC MOSFET 110 is equal to the voltage V on the large inductor. i2 (For example, induced voltage V) i2 =Lcs(Inductor 150A + Inductor 150B)*dI D / dt) offset.

[0043] In the configuration shown in Figure 2, the driver signal 101S, applied to the gate G of the SiC MOSFET 110 via the gate resistor Rg to turn the SiC MOSFET 110 on or off, is also applied to the gate GA of the auxiliary switch 160 to turn the auxiliary switch on or off. The auxiliary switch 160 can be turned on during the on-time of the SiC MOSFET 110 and turned off during the off-time of the SiC MOSFET 110.

[0044] In the specific implementation example, resistor R1 can be significantly larger than the on-resistance (Ron) of auxiliary switch 160. When auxiliary switch 160 is turned on, the gate current I supplied by the gate driver... G During the conduction transient, the current will flow from tap point P1 to tap point P2 through the auxiliary switch via the first return path, and the drain-source current I... D Only inductor 150A will flow. The smaller inductance of inductor 150A will be shared between the gate circuit and the power circuit. The larger inductance of inductor 150B and resistor R1 will be short-circuited or bypassed.

[0045] In the specific implementation example, resistor R1 can be significantly smaller than the turn-off resistance (Roff) of auxiliary switch 160. When auxiliary switch 160 is turned off, the gate current I... G The current flows from node N to tap P2 through resistor R1 via the second return path, and the drain-source current flows through both inductors 150A and 150B. The smaller inductance of inductor 150A and the larger inductance of inductor 150B are connected in series and are shared for the gate circuit and power circuit.

[0046] In the example implementation, for example SiC MOSFET 110 (e.g., a MOSFET rated for operation at 650V), the smaller inductance of inductor 150A may be, for example, 0.3nH or less, and the larger inductance of inductor 150A may be, for example, 1nH or more.

[0047] In some implementations, resistor R1 can be replaced by diode 170 to prevent current from flowing through a larger inductor (e.g., inductor 150A). Figure 3 shows an example circuit 300 in which resistor R1 (Figure 2) is replaced by diode 170. Using a low-voltage auxiliary switch 160 in conjunction with diode 170 to implement an asymmetric small / large Lcs scheme prevents current from circulating in reverse through the auxiliary device.

[0048] In some implementations, resistor R1 may be replaced by another low-voltage auxiliary switch MOSFET (not shown) to prevent current from flowing through a larger value inductor (e.g., inductor 150A). In some implementations, auxiliary switch 160 may be replaced by a diode (not shown) to prevent current from flowing back through the first return path.

[0049] In specific implementations of the examples, the aforementioned circuit arrangements (e.g., circuit 200 of FIG. 2 and circuit 300 of FIG. 3) can be fabricated using components mounted on a printed circuit board (PCB). For example, the components may include surface mount packages or surface mount devices (SMDs).

[0050] Figure 4A shows a plan view of an example circuit 400A fabricated on a printed circuit board (PCB) 402A. The example circuit 400A may, for example, include a SiC MOSFET SMD package 410A surface-mounted on the PCB 402A. The SiC MOSFET SMD package 410A includes a SiC MOSFET device (e.g., the SiC MOSFET 110 of Figure 2). The SiC MOSFET SMD package 410A may be a four-pin package including a gate pin G, a Kelvin pin K, a source pin S, and a drain pin D. The Kelvin pin K provides a low-impedance and low-current connection or a current-free connection to the source of the SiC MOSFET 110. Pads for the gate pin G, Kelvin pin K, and source pins (S, S) are shown on the top surface ST of the PCB 402A. A low-value inductor (e.g., the smaller inductance of inductor 150A, not shown in Figure 4A) may be a parasitic inductance (e.g., a package inductor) associated with the Kelvin pin K. The drain of the SiC MOSFET 110 can be a metal layer on the back side of the SiC MOSFET 110. In Figure 4A, the drain contact (D) is schematically shown on the back side surface SB by a square with sides indicated by dashed lines. In an example implementation, a large Lcs can be achieved in circuit 400A at the package level and / or PCB level as described below by disabling the Kelvin connection or by adding a large discrete inductor.

[0051] Example circuit 400A may also include a MOSFET SMD package 420, which includes an auxiliary MOSFET device (e.g., auxiliary switch 160 of FIG. 2), a gate driver package 430, which includes a gate signal generator (e.g., gate signal 101S), and a resistor 440 (e.g., resistor R1 of FIG. 2). In some example embodiments, resistor 440 may be replaced by a diode (e.g., diode 170 of FIG. 3).

[0052] Example circuit 400A may also include an inductor 450 with a large value (e.g., >2nH). Inductor 450 may be the larger of two asymmetric Lcs (e.g., the smaller inductance of inductor 150A and the larger inductance of inductor 150B in Figure 2), which may be introduced into the circuit to limit turn-off overvoltage in the SiC MOSFET 110. In some example implementations, as shown in Figure 4A, the large Lcs inductor 450 and resistor R1 are implemented at the PCB level. In some example implementations, as shown in Figure 4A, the inductor 450 implemented at the PCB level may be a coil.

[0053] In some military or industrial applications, components in a circuit may be subjected to severe shocks and vibrations. For such applications, through-hole mounting (THM) packages may be preferred for the components. Boards assembled with through-hole components can be robust due to the large solder joints that extend across the entire width of the board itself.

[0054] Figure 4B shows a plan view of an example circuit 400B fabricated on a printed circuit board (PCB) 402B using THM technology. The example circuit 400B may, for example, include a SiC MOSFET THM package 410B mounted on the PCB 402B. The SiC MOSFET THM package 410B includes a SiC MOSFET device (e.g., the SiC MOSFET 110 of Figure 2). The SiC MOSFET THM package 410B may be a four-lead package including a gate lead G1, a Kelvin lead K1, a source lead S1, and a drain lead D1. The Kelvin lead K1 provides a low-impedance and low-current connection to the source of the SiC MOSFET 110. In the example implementation, a large Lcs can be achieved in circuit 400B at the package level and / or PCB level by disabling the Kelvin connection or by adding a large inductor, as described below (and with reference to circuit 400A of Figure 4A above).

[0055] Similar to circuit 400A of Figure 4A, example circuit 400B may also include a MOSFET SMD package 420 (which includes the auxiliary switch 160 of Figure 2), a gate driver package 430 including a gate signal generator (e.g., gate signal 101S), and a resistor 440 (e.g., resistor R1 of Figure 2). In some example implementations, resistor 440 may be replaced by a diode (e.g., diode 170 of Figure 3).

[0056] Similar to circuit 400A in Figure 4A, example circuit 400B may also include an inductor 450 with a large value (e.g., >2nH). Inductor 450 may be the larger of two asymmetric Lcs (e.g., the smaller inductance of inductor 150B in Figure 2 and the larger inductance of inductor 150B), which may be introduced into the circuit to limit the turn-off overvoltage in the SiC MOSFET 110. In some example implementations, as shown in Figure 4B, the large Lcs inductor 450 and resistor R1 are implemented at the PCB level. In some example implementations, as shown in Figure 4B, the inductor 450 implemented at the PCB level may be a coil.

[0057] The operating characteristics of the inductors, capacitors, transistors, and resistors in the examples of Figures 1 through 4B can be determined by design and / or fabrication. That is, the corresponding Lcs and resistance values ​​suitable for a particular specific implementation can be achieved through layout and shaping, as well as through the selection of semiconductor processing parameters (e.g., doping concentration) and / or materials. While specific examples are shown and described with reference to Figures 1 through 4B, other specific implementations of inductors, capacitors, diodes, and / or resistors may be used in some specific implementations. For example, in some examples, diodes may be implemented as Zener diodes, resistors may be implemented as diffused resistors or metallic resistors, and capacitors may be implemented using low-k and / or high-k dielectrics to achieve the desired capacitance value.

[0058] In some example implementations, the circuitry implementing the asymmetric LCS scheme (e.g., circuit 400A in Figure 4A or circuit 400B in Figure 4B) may utilize co-integrated devices. For example, the circuitry implementing the asymmetric LCS scheme may utilize an auxiliary switch (e.g., auxiliary switch 160, MOSFET in Figure 2) co-integrated with the SiC MOSFET 110. The auxiliary switch (MOSFET) and the SiC MOSFET device may be co-integrated in a single semiconductor die fabricated using a common or flexible MOSFET manufacturing process.

[0059] In a specific implementation example, the auxiliary switch used in the circuit implementing the asymmetric Lcs scheme (e.g., auxiliary switch 160 similar to FIG2) can be a low-voltage side MOSFET (e.g., side MOSFET 510) integrated with the SiC MOSFET 110 shown in FIG5.

[0060] An auxiliary switch (side MOSFET 510) and a SiC MOSFET 110 can be co-integrated in a single semiconductor die using a common flexible MOSFET fabrication process. Figure 5 shows a cross-sectional view of a semiconductor die 500 including the co-integrated side MOSFET 510 disposed adjacent to the SiC MOSFET 110. The side MOSFET 510 can occupy a small surface area of ​​the semiconductor die 500 compared to the area occupied by the SiC MOSFET 110. The SiC MOSFET 110 can have a vertical structure, with the source and drain located on opposite sides of the semiconductor die. Current flows vertically in the MOSFET 110 between the opposite sides of the semiconductor die. The vertical structure may include an N- epitaxial layer (e.g., layer 500D) disposed on an N+ substrate layer (e.g., layer 500S). Layer 500S can form the drain of the SiC MOSFET 110 disposed adjacent to the MOSFET 510. A metal layer (e.g., 500M) disposed on the back side of layer 500S can form the drain contact for MOSFET 110. The lateral MOSFET can have a lateral structure, wherein the source and drain are located at the top side of the semiconductor die. In Figure 5, the lateral MOSFET 510 has a drain terminal at pad 510K and a source terminal at 510S. The lateral MOSFET 510 is a lateral MOSFET connected from pad 510K to the source of MOSFET 110. In the lateral MOSFET 510, current flows laterally (parallel to the substrate surface) through a channel at the top of region 510B controlled by gate 510G.

[0061] The Kelvin pads, gate, and source structures of the lateral MOSFETs 510 and 110 can be formed on top of an N-epitaxial layer (e.g., layer 500D). For example, the source S of the MOSFET can be an N+ doped region formed in the P-body regions 510B and 110B at the top of the N-epitaxial layer (e.g., layer 500D). The source contact pads 510S of the lateral MOSFET 510 and 110S of the MOSFET 110 can be formed of a metal layer. The metal layer can make ohmic contacts with the N+ doped regions formed in the P-body regions 510B and 110B, respectively. The Kelvin contact pad of the lateral MOSFET 510 (e.g., Kelvin contact pad 510K) can be a metal layer that makes ohmic contacts with the N+ doped region formed in the P-body region 510B.

[0062] In the example implementation, the P-body region in MOSFET 510 may be a dedicated P-well, which may be necessary to adjust the threshold voltage Vth of MOSFET 510.

[0063] The gate structure of MOSFET 510 may include a gate 510G (e.g., metal) disposed on a gate dielectric layer (e.g., dielectric layer 510O) disposed on the top surface of semiconductor die 500. The gate structure of MOSFET 110 may include a gate contact pad 110G (e.g., metal) disposed on a gate dielectric layer (e.g., dielectric layer 110O) disposed on the top surface of semiconductor die 500.

[0064] In the example implementation, the P+ doped region (e.g., region PB) can be used to form ohmic contacts between the P-body region and the source contact pads (e.g., pads 110S and 510S) in the co-integrated MOSFET 110 and MOSFET 510, and between the P-body region and the Kelvin contact pad (e.g., pad 510K).

[0065] In some example implementations, the circuitry implementing the asymmetric LCS scheme (e.g., circuit 400A in Figure 4A or circuit 400B in Figure 4B) can utilize auxiliary switches (auxiliary switch 160 in Figure 2) and SiC power MOSFETs (e.g., SiC MOSFET 110 in Figure 2) fabricated on separate semiconductor dies. The separate semiconductor dies can be individually packaged in different packages (e.g., MOSFET SMD package 420, SiC MOSFET SMD package 410A, and SiC MOSFET THM package 410B in Figures 4A and 4B).

[0066] In some implementations, the auxiliary switch and SiC MOSFET device may be fabricated on separate semiconductor dies, but are co-packaged in a single package. In other words, two semiconductor dies can be encapsulated in a single package. Figure 6 illustrates, for example, package 600, which includes a SiC MOSFET 110 and an auxiliary switch 160 fabricated on separate semiconductor dies (e.g., die A and die B, respectively). In package 600, die A, containing the SiC MOSFET 110, is disposed on a portion of leadframe pad 610. Leadframe pad 610 may be, for example, a copper sheet or copper plate. Die B, containing the auxiliary switch 160, is disposed on a conductive plate 630, which is disposed on another portion of leadframe pad 610. An insulating layer 620 separates conductive plate 630 from leadframe pad 610.

[0067] Metal terminals, including, for example, drain terminal D, source terminal S, Kelvin terminal K, and gate terminal G, may extend externally to the outside of package 600. Drain terminal D may be formed as an extension of leadframe pad 610. Source terminal S, Kelvin terminal K, and gate terminal G may be connected via wire bonding (e.g., lead 605) to corresponding contact pads on auxiliary switch 160 and SiC MOSFET 110 (not all shown or labeled in FIG. 6). The wire bonding structure and device form part of, for example, a circuit (e.g., circuit 200 of FIG. 2) for implementing an asymmetric common-source inductor (Lcs) scheme for turn-on and turn-off of the SiC MOSFET.

[0068] In a specific implementation of the example, the devices and circuits in package 600 may be encapsulated in, for example, epoxy molding compound (EMC) 602.

[0069] In the example implementation, package 600 can be used with a large value Lcs and resistor R1 implemented at the PCB level, as discussed above, for example with reference to Figure 4B.

[0070] In the example implementation, the gate driver circuit for implementing the asymmetric common-source inductor (Lcs) scheme for turning on and off the SiC MOSFET can utilize a power amplifier that accepts a low-power input from the controller IC and generates a high-current drive input for the gate of the SiC MOSFET. The gate driver can be located on-chip or as a discrete module.

[0071] Figure 7 illustrates a gate driver circuit module (e.g., gate driver circuit module 700) coupled to a SiC MOSFET 110 (Figure 1). Gate driver circuit module 700 serves as an interface between control signals (digital or analog controllers) and the SiC MOSFET. Compared to discrete gate driver solutions, integrated gate driver solutions reduce design complexity, development time, bill of materials (BOM), and board space, while improving reliability. In the example implementation shown in Figure 7, gate driver circuit module 700 may include amplifier 710 (e.g., a power amplifier that accepts a low-power input from a controller IC and generates a high-current drive input for the gate of the SiC MOSFET). Furthermore, gate driver circuit module 700 includes internal functionality (e.g., switching circuit 720) for switching between a first driver return RT1 and a second driver return RT2. The first driver return RT1 may, for example, introduce a smaller inductance (e.g., inductor 140A) into the gate-source loop of the SiC MOSFET 110. The second driver return RT2 can introduce a larger value inductor (e.g., inductor 140A connected in series with inductor 140B) into the gate-source loop of the SiC MOSFET 110. The driver output signal (e.g., signal 101S) driving the gate of the SiC MOSFET 110 is also used to drive a transistor (not shown) in the switching circuit 720 to select either the first driver return RT1 or the second driver return RT2 (in other words, selecting a small or large value inductor to match the turn-on / turn-off process of the SiC MOSFET 110).

[0072] Figure 8 illustrates an example method 800 for reducing turn-off overvoltage and switching power loss (e.g., turn-off power loss Eoff) in a power MOSFET. The power MOSFET may be, for example, a SiC power MOSFET. The power MOSFET may be rated for operation at values ​​greater than 600V. The power MOSFET may include a gate, a source, and a drain, wherein the gate controls the source-drain current (Io). D The flow of ).

[0073] Method 800 includes placing a first inductor and a second inductor alongside a main current path shared with a gate driver loop associated with the MOSFET (810). The first inductor may have an inductance value smaller than that of the second inductor. The main current path (e.g., a power path) may be a source-drain current path (e.g., I0) shared with the gate driver loop in the MOSFET. D path).

[0074] Method 800 further includes switching the gate loop current to flow through the first inductor (820) when the MOSFET is turned on; and switching the gate loop current to flow through the second inductor (830) when the MOSFET is turned off.

[0075] In method 800, setting the first inductor and the second inductor includes setting an inductor formed by distributed inductor elements or parasitic inductor elements. The parasitic inductor elements may vary depending on the package and device layout and design. In an example implementation, for a 650V SiC MOSFET, the first inductor may have a value less than 0.5nH, and the second inductor may have a value greater than 3nH.

[0076] In some example embodiments, the first inductor and / or the second inductor may include discrete inductor elements. In some example embodiments, the discrete inductor elements may be cylindrical coils.

[0077] As discussed above, the circuit arrangement for implementing the asymmetric common-source inductor (Lcs) scheme for turning on and off SiC MOSFETs (e.g., circuit 200 in Figure 2) can involve circuits constructed from discrete components, or circuits and devices co-integrated on a single die, or circuits and devices fabricated on a separate die in a common package. In all such circuits, the common operating principle is to use a first driver return path to apply a small voltage V across the inductor when the SiC MOSFET is turned on. i1 (For example, induced voltage V) i1 =Lcs (Inductance of 150A in Figure 2) * dI D / dt) cancels out the applied gate-source voltage, and uses the second driver return path to use the voltage V on the large inductor when turning off the SiC MOSFET. i2 (For example, induced voltage V) i2 =Lcs(Inductor 150A + Inductor 150B in Figure 2)*dI D / dt) cancels out the applied gate-source voltage.

[0078] In circuit 200, as shown in Figure 9A, the first driver return path RT1 allows only a small inductor, such as inductor 150A, to pass through. When the SiC MOSFET (e.g., MOSFET 110) is turned on, the first driver return path RT1 is formed between taps P1 and P2 by activating the auxiliary switch 160. R1 is greater than the on-resistance of the auxiliary switch 160. When the SiC MOSFET is turned on, the auxiliary switch 160 turns on faster due to its smaller parasitic input capacitance and lower threshold voltage; Lcs remains low.

[0079] The common-source inductor (Lcs) in the power current path (e.g., small or large Lcs) is used as a feedback element to generate the gate driver current.

[0080] In the first quadrant mode of MOSFET operation, n-channel MOSFET operation begins when a positive voltage is applied to the drain. In circuit 200, the induced voltage Vi at tap point P1 (induced by the current flowing through the larger inductor 150B) can be obtained from V... i =L*di / dt is given. The drain current (I) D During the ramp-up to the third quadrant mode of MOSFET operation, the drain-to-source voltage v in auxiliary switch 160 DS_AUX Approximately equal to -V in auxiliary switch 160 i In the third quadrant mode, the current flows in the opposite direction compared to the first quadrant operation.

[0081] In circuit 200, as shown in Figure 9B, the second driver return path RT2 sends source-drain current through a large inductor (e.g., inductor 150B (and a smaller inductor 150A in series)). The induced voltage Vi at tap point P1 (induced by the current flowing through the larger inductor 150B) can be obtained from V i =L*di / dt is given as a negative number. In the drain current (I D During the ramp-down to the first quadrant mode of MOSFET operation, the drain-to-source voltage v in auxiliary switch 160 DS_AUX Approximately equal to -V i However, in negative v DS_AUX There is no conduction through auxiliary switch 160 at this point. Auxiliary switch 160 is actually discontinuous in circuit 200. The discontinuity is depicted by the X mark placed on auxiliary switch 160 in Figure 9B.

[0082] The induced voltage Vi at tap point P1 (induced by the current flowing through the larger inductor 150B) can be obtained from V i =Lcs*dI D The negative value of / dt is given. In the drain current (I D During the ramp-down to the first quadrant mode of MOSFET operation, the drain-to-source voltage v in auxiliary switch 160 DS_AUX Approximately equal to -V i However, in negative v DS_AUX There is no conduction through auxiliary switch 160 at this point. Auxiliary switch 160 is actually discontinuous in circuit 200. The discontinuity is depicted by the X mark placed on auxiliary switch 160 in Figure 9B.

[0083] When the SiC MOSFET (e.g., MOSFET 110) is turned off, a second driver return path RT2 in circuit 200 is formed between tap point P2 and node N by disabling auxiliary switch 160. When the SiC MOSFET is turned off, auxiliary switch 160 turns off more quickly, the Kelvin pin in the SiC MOSFET (Figures 4A to 6) is disconnected, and the driver return (RT2) remains connected to the point with a larger Lcs (e.g., node N).

[0084] In another example implementation, in circuit 300, as shown in FIG9C, to implement the asymmetric Lgs scheme, the first driver return path RT1 includes a small-value inductor (e.g., inductor 150A) as a common inductor between the gate loop and the power loop. The second driver return path RT2 includes a large-value inductor (e.g., inductor 150B) as a common inductor between the gate loop and the power loop. In FIG9C, the return paths for implementing the asymmetric Lgs scheme are implemented by two auxiliary branches (e.g., auxiliary branch AB1 and auxiliary branch AB2) in the driver circuit. As shown in FIG9C, auxiliary branch AB1 extends between tap points P1 and P2, and auxiliary branch AB2 extends between tap points P3 and P4. Each auxiliary branch includes a low-voltage transistor (auxiliary switch) and a diode. For example, auxiliary branch AB1 includes a diode D1 and a MOSFET 162 with a gate G1; and auxiliary branch AB2 includes a diode D2 and a MOSFET 164 with a gate G2.

[0085] This circuit solution, based on two auxiliary branches (each containing a transistor and a diode), is a safer method to avoid current recirculation in large inductor loops. However, this solution requires circuitry (not shown) to drive the transistor gates G1 and G2.

[0086] The semiconductor industry can use technical computer-aided design (TCAD) tools to analyze the electrical characteristics and behavior of circuits implementing asymmetric small / large Lcs schemes for SiC MOSFETs (such as circuit 200 in Figure 2 or circuit 300 in Figures 9A through 9C). TCAD tools can be used to simulate and analyze the behavior of semiconductor devices and circuit elements at the device level, die level, or package level.

[0087] In the example TCAD simulation analysis, circuit 200 includes a SiC MOSFET 110 fabricated on a semiconductor die. The auxiliary switch 160 can be represented by a known process model of a commercially available 60V MOSFET device (e.g., an NTMFS4C032N T6MOSFET from Onsemi). The semiconductor die including the SiC MOSFET 110 is placed on a leadframe and encapsulated in a package (e.g., package 600 of Figure 6). The package may have leads or terminals for external connection to the gate, source, drain, and Kelvin pads of the SiC MOSFET 110 fabricated on the semiconductor die. For analysis, at the die level (e.g., V... GS DIE ), package level (e.g., V GS PCKG ) and auxiliary switch 160 (e.g., V GS AUX The gate-to-source voltage is measured at the die level (e.g., V). DS DIE ), package level (e.g., V DS PCKG ) and auxiliary switches with 160 levels (e.g., V) DS AUX ) Measure the drain-to-source voltage at point .

[0088] Figure 10A shows an example model analog circuit 1000 that can be used to analyze the behavior of the circuits described herein (e.g., circuit 200 of Figure 2). The behavior of analog circuit 1000 can be analyzed using TCAD and SPICE models.

[0089] The model simulation circuit 1000 includes a semiconductor die package 1010, which includes a SiC MOSFET 110 coupled to an auxiliary switch (e.g., auxiliary switch 160, MOSFET). The output load of the semiconductor die package 1010 is represented by a diode 120 and an RLC circuit including an inductor (L) 122. The diode 120 may be formed by a MOSFET 124 with its gate and source shorted. In Figure 10A, various MOSFETs (e.g., MOSFET 110, auxiliary switch 160 (MOSFET), and MOSFET 124) are represented by a 2D TCAD cross-sectional view. In the example embodiment, MOSFETs 110 and 124 may be 650V / 50MΩ SiC MOSFETs. The auxiliary switch 160 (MOSFET) may be, for example, a single 30V n-channel power MOSFET (e.g., an NTMFS4C032N T6 MOSFET).

[0090] In the example embodiment, the circuit components in the simulation model and the connections between various components may include inductor, resistor, and capacitor elements. These elements may include discrete (lumped) components and / or may be formed by distributed or parasitic components. In the embodiment shown in Figure 10A, multiple inductor, resistor, and capacitor elements are shown with example assigned values. The assigned values ​​may be calculated or heuristic values. In the example embodiment, the model simulation circuit 1000 may include or be coupled to a Pearson current probe 1020. The Pearson current probe 1020 may be configured to measure on / off cycles, ripple waveforms, and switching losses, etc.

[0091] Figure 10B shows the source-drain current I during MOSFET turn-on (corresponding to the state of the circuit shown in Figure 9A). D Simulated values ​​varying over time. Figure 10A also shows the gate-to-source voltage (e.g., V) at the package level. GS PCKG ) and the gate-to-source voltage at the auxiliary switch (e.g., V GS AUX ); and the drain-to-source voltage at the package level (e.g., V). DS PCKG ), and the drain-to-source voltage at the auxiliary switching stage (e.g., V DS AUX ).

[0092] Figure 10C shows the source-drain current I during MOSFET turn-off (corresponding to the state of the circuit shown in Figure 9B). D Simulated values ​​varying over time. Figure 10C also shows the gate-to-source voltage (e.g., V) at the package level. GS PCKG ) and the gate-to-source voltage at the auxiliary switch (e.g., V GS AUX ); and the drain-to-source voltage at the package level (e.g., V). DS PCKG ), and the drain-to-source voltage at the auxiliary switching stage (e.g., V DS AUX ).

[0093] As previously mentioned, compared to circuit solutions with only asymmetric Rg, the asymmetric Lcs scheme implemented in circuit 200 or 300 significantly reduces switching losses (Esw) for the same Vds max. The benefits of the asymmetric Lcs scheme can be superimposed on the scheme based on using asymmetric Rg.

[0094] The various devices and techniques described herein can be implemented using a variety of semiconductor processing and / or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing techniques associated with semiconductor substrates, including but not limited to, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0095] It should also be understood that when an element such as a layer, region, or substrate is mentioned as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is mentioned as being directly on, directly connected to, or directly coupled to another element or layer, no intermediate elements or layers are present. As used herein, “coupled to” or “coupled with” can mean electrically coupled to, electrically coupled to, physically coupled to, and / or physically coupled to.

[0096] Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to may be referred to so. The claims of this application may be amended to describe the exemplary relationships described in the specification or shown in the drawings.

[0097] As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations shown in the figures, spatially relative terms (e.g., above, on, above, below, under, beneath, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, the term adjacent may include laterally adjacent or horizontally adjacent to.

[0098] While certain features of the specific embodiments described herein have been exemplified as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any parts of the apparatus and / or methods described herein can be combined in any way, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A circuit (100), the circuit comprising: A metal-oxide-semiconductor field-effect transistor (MOSFET) (110) includes a gate, a source, and a drain; A first inductor (140A) and a second inductor (140B), the first inductor having a small inductance value smaller than the larger inductance value of the second inductor; and a switch (130) configured to include the first inductor in a current path shared by the gate and source circuits of the MOSFET when the MOSFET is turned on, and to include the second inductor in the current path shared by the gate and source circuits when the MOSFET is turned off.

2. The circuit according to claim 1, wherein the MOSFET is a silicon carbide (SiC) power MOSFET.

3. The circuit according to claim 2, wherein the smaller inductance value of the first inductor is less than 0.5nH, and the larger inductance value of the second inductor is greater than 3.0nH.

4. A circuit (200), the circuit comprising: A metal-oxide-semiconductor field-effect transistor (MOSFET) (110) includes a gate, a source, and a drain; A first inductor (140A), a second inductor (140B), and a current-limiting element (R1), wherein the first inductor, the second inductor, and the current-limiting element are connected in series in the source-drain current path and are shared with the gate driver circuit of the MOSFET; and a switch (130), which is configured to close when the MOSFET is turned on and short-circuit the second inductor and the current-limiting element, such that the gate circuit current flows through the first inductor and bypasses the second inductor and the current-limiting element.

5. The circuit of claim 4, wherein the MOSFET is a high-voltage SiC power MOSFET, and the switch is a low-voltage MOSFET connected in parallel with the second inductor and the current-limiting element.

6. The circuit of claim 4, wherein the switch is configured to open when the MOSFET is turned off to introduce the second inductor into the source-drain current path.

7. The circuit according to claim 4, wherein the current-limiting element is a resistor.

8. The circuit according to claim 4, wherein the current limiting element is a diode.

9. The circuit of claim 4, wherein the MOSFET and at least the first inductor are encapsulated in a first package, the switch is encapsulated in a second package, and the circuit is assembled on a printed circuit board (PCB), wherein the first package and the second package are mounted on the PCB.

10. The circuit of claim 9, wherein the second inductor is implemented by disabling the Kelvin connection to the MOSFET.

11. The circuit of claim 9, wherein the second inductor is implemented by adding an inductor at at least one of the package level and the PCB level.

12. The circuit of claim 4, wherein the MOSFET and the switch are co-integrated in a single semiconductor die.

13. The circuit of claim 4, wherein the MOSFET and the switch are fabricated on two separate semiconductor dies, the two separate semiconductor dies being co-packaged in a single package.

14. The circuit according to claim 4, further comprising: A gate driver circuit module coupled to the MOSFET, the gate driver circuit module including an amplifier that generates a high current drive input for the gate of the MOSFET; The switching circuit switches between a first driver return path and a second driver return path, wherein the first driver return path introduces a smaller inductor into the source-drain current path of the MOSFET, and the second driver return path introduces a larger inductor into the source-drain current path of the MOSFET.

15. A method comprising: The first and second inductors are positioned next to the source-drain current path shared with the gate driver loop associated with the MOSFET (810). When the MOSFET is turned on, the gate loop current is switched to flow through the first inductor (820); and when the MOSFET is turned off, the gate loop current is switched to flow through the second inductor (830).

16. The method of claim 15, wherein the MOSFET is a silicon carbide (SiC) power MOSFET.

17. The method of claim 16, wherein the first inductor has an inductance value of less than 0.5 nH and the second inductor has an inductance value of greater than 3.0 nH.

18. The method of claim 15, wherein setting the first inductor and the second inductor comprises setting an inductor formed of distributed inductance elements or parasitic inductance elements.

19. The method of claim 15, wherein setting the first inductor and the second inductor includes setting discrete inductor elements.

20. The method of claim 19, wherein setting the discrete inductor element includes setting a cylindrical coil.

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