Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprises a display area (AA), the display area (AA) comprises a first display area (A1) and a second display area (A2), the first display area (A1) comprises a plurality of pixel island areas (A11) and a plurality of light-transmitting areas (A12) distributed among the pixel island areas (A11); the plurality of first type sub-pixels are located in the first display area (A1), at least one first type sub-pixel in the plurality of first type sub-pixels comprises a first type pixel driving circuit (11) and a first type light emitting device (13), the plurality of first type sub-pixels form a plurality of pixel islands (Pi), each pixel island (Pi) is located in a pixel island area (A11) in the plurality of pixel island areas, and the first type light emitting device (13) is located in the first display area (A1). Each pixel island (Pi) comprises at least two sub-pixels of the first type; the pitch between adjacent pixel islands (Pi) in the first direction (D1) is smaller than the pitch between adjacent pixel islands (Pi) in the second direction (D2).

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display substrate, including: a display area and a peripheral area located around the display area, the display area including a first display area and a second display area, the second display area at least partially surrounding the first display area, and the first display area including a plurality of pixel island areas and a plurality of light-transmitting areas distributed between the pixel island areas;

[0006] A plurality of first-type sub-pixels are located in the first display area. At least one of the plurality of first-type sub-pixels includes a first-type pixel driving circuit and a first-type light-emitting device. The first-type pixel driving circuit is configured to drive the first-type light-emitting device to emit light. The plurality of first-type sub-pixels constitute a plurality of pixel islands. Each pixel island is located in one of the plurality of pixel island regions, and each pixel island includes at least two first-type sub-pixels. The spacing between adjacent pixel islands along a first direction is smaller than the spacing between adjacent pixel islands along a second direction. The first direction and the second direction intersect.

[0007] A plurality of second-type sub-pixels are located in the second display area. At least one of the plurality of second-type sub-pixels includes a second-type pixel driving circuit and a second-type light-emitting device. The second-type pixel driving circuit is configured to drive the second-type light-emitting device to emit light.

[0008] In an exemplary embodiment, the spacing between adjacent pixel islands along the first direction is equal to the spacing between two adjacent first-type pixel driving circuits within the pixel island along the first direction.

[0009] In an exemplary embodiment, the first type of pixel driving circuit includes: a capacitor and a driving transistor, wherein the capacitor includes a first plate and a second plate, and the first plate is connected to the control electrode of the driving transistor;

[0010] The maximum length of the first plate of the capacitor in the first type of pixel driving circuit along the second direction is less than the spacing between adjacent pixel islands along the second direction, but greater than the spacing between adjacent pixel islands along the first direction.

[0011] In an exemplary embodiment, the light-emitting structure includes: a substrate and a light-emitting structure layer disposed on the substrate, wherein a first type of light-emitting device is disposed on the light-emitting structure layer, the first type of light-emitting device includes: a first light-emitting device, a second light-emitting device and a third light-emitting device, the first type of light-emitting device includes: an anode, and the light-emitting structure layer includes: an anode conductive layer disposed on the substrate;

[0012] The anode conductive layer includes: a first anode of a first light-emitting device, a second anode of a second light-emitting device, and a third anode of a third light-emitting device;

[0013] The first anode and the second anode are arranged along the second direction, and are respectively arranged with the third anode along the first direction.

[0014] The area of ​​the first anode is smaller than the area of ​​the second anode, and the area of ​​the third anode is larger than the area of ​​at least one of the first anode and the second anode.

[0015] In an exemplary embodiment, the length of the third anode along the second direction is greater than the sum of the length of the first anode along the second direction and the length of the second anode along the second direction;

[0016] The distance between the second anode connected to at least one first-type pixel driving circuit in the i-th row and the first anode connected to at least one first-type pixel driving circuit in the (i+1)-th row along the second direction is greater than the length of at least one second anode along the second direction.

[0017] In an exemplary embodiment, the light-emitting structure layer further includes: a pixel definition layer located on the side of the anode conductive layer away from the substrate, the pixel definition layer including: a first anode opening exposing the first anode, a second anode opening exposing the second anode, and a third anode opening exposing the third anode;

[0018] The first type of pixel driving circuit includes: a first pixel driving circuit, a second pixel driving circuit and a third pixel driving circuit, wherein the first pixel driving circuit is electrically connected to the first anode, the second pixel driving circuit is electrically connected to the second anode, and the third pixel driving circuit is electrically connected to the third anode.

[0019] The length of the third anode opening along the second direction is greater than the sum of the length of the first anode opening along the second direction and the length of the second anode opening along the second direction;

[0020] The distance between the second anode opening of the second anode connected to the second anode of the i-th row second pixel driving circuit and the first anode opening of the first anode connected to the first anode of the (i+1)-th row first pixel driving circuit along the second direction is greater than the length of at least one second anode opening along the second direction.

[0021] In an exemplary embodiment, it further includes: a driving circuit layer located on the side of the light-emitting structure layer near the substrate, the driving circuit layer including: a light-shielding layer disposed on the substrate, the light-shielding layer including: a plurality of light-shielding structures arranged along the second direction and a light-shielding connection structure located between at least two adjacent light-shielding structures;

[0022] The i-th light-shielding connection structure is connected to the i-th light-shielding structure and the (i+1)-th light-shielding structure respectively, 1≤i≤M, where M is the total number of rows of the pixel driving circuit;

[0023] At least one of the plurality of light-shielding structures has its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of the active pattern of at least one transistor in at least one first-type pixel driving circuit.

[0024] In an exemplary embodiment, the at least one light-shielding structure includes: a first light-shielding portion, a third light-shielding portion, and a plurality of second light-shielding portions arranged along the first direction between the first light-shielding portion and the third light-shielding portion; at least one of the first light-shielding portion and the third light-shielding portion extends at least partially along the first direction;

[0025] The first light-shielding part of the i-th light-shielding structure is located on the side of the third light-shielding part of the i-th light-shielding structure away from the (i+1)-th light-shielding structure, and at least two adjacent second light-shielding parts in the same light-shielding structure are interconnected.

[0026] In an exemplary embodiment, a second opening is formed between at least two adjacent second light-shielding portions and a first light-shielding portion located in the same light-shielding structure, a third opening is formed between at least two adjacent second light-shielding portions and a third light-shielding portion located in the same light-shielding structure, and a fourth opening is provided on the second light-shielding portion.

[0027] The area of ​​the fourth opening is smaller than the area of ​​either the second opening or the third opening.

[0028] In an exemplary embodiment, the at least one of the light-shielding connection structures includes: a plurality of light-shielding connection portions arranged along the first direction, at least one of the plurality of light-shielding connection portions extending along the second direction, and adjacent light-shielding connection portions being spaced apart.

[0029] At least two adjacent light-shielding connection parts in the i-th light-shielding connection structure are respectively connected to the third light-shielding part in the i-th light-shielding structure and the first light-shielding part in the (i+1)-th light-shielding structure, and a first opening is formed between them and the third light-shielding part in the i-th light-shielding structure and the first light-shielding part in the (i+1)-th light-shielding structure.

[0030] The area of ​​the first opening is greater than the area of ​​either the second opening or the third opening.

[0031] In an exemplary embodiment, the length of at least one of the light-shielding connecting portions along the second direction is greater than the length of at least one of the first and third light-shielding portions in the light-shielding structure along the second direction.

[0032] In an exemplary embodiment, the driving structure layer further includes: a semiconductor layer disposed on the side of the light-shielding layer away from the substrate, and the first type of pixel driving circuit includes: at least one transistor, the at least one transistor including: an active pattern, a control electrode, a first electrode, and a second electrode;

[0033] The semiconductor layer includes: an active pattern of at least one transistor;

[0034] The orthographic projection of the i-th light-shielding structure on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one transistor in the i-th row of the first type pixel driving circuit on the substrate.

[0035] In an exemplary embodiment, the at least one transistor includes: a first transistor to a seventh transistor;

[0036] The orthographic projection of the first light-shielding part of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of a portion of the active pattern of the first transistor in the i-th row of the first type pixel driving circuit onto the substrate;

[0037] The orthographic projection of the second light-shielding part of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projections of the active pattern of the first transistor in the i-th row of the first type pixel driving circuit and the active patterns of the second transistor to the sixth transistor onto the substrate.

[0038] The orthographic projection of the third light-shielding part of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of the active pattern of the seventh transistor in the i-th row of the first type pixel driving circuit onto the substrate.

[0039] In an exemplary embodiment, it further includes: multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple reset signal lines, multiple second initial signal lines, multiple first light-emitting signal lines, and multiple second light-emitting signal lines, wherein the capacitor includes: a first electrode plate and a second electrode plate;

[0040] At least one of the plurality of second scan signal lines, the plurality of reset signal lines, the plurality of second initial signal lines, the plurality of first scan signal lines, the plurality of third scan signal lines, the plurality of first light emission signal lines, and the plurality of second light emission signal lines extends at least partially along the first direction;

[0041] The driving structure layer further includes: a first conductive layer, a second conductive layer and a third conductive layer, wherein the first conductive layer is located on the side of the semiconductor layer away from the substrate, the second conductive layer is located on the side of the first conductive layer away from the substrate, and the third conductive layer is located on the side of the second conductive layer away from the substrate;

[0042] The first conductive layer includes at least: the plurality of second scan signal lines, the plurality of reset signal lines, and the control electrode of at least one transistor located in at least one first type pixel driving circuit and the first plate of the capacitor;

[0043] The second conductive layer includes at least: the plurality of second initial signal lines and the second plate of the capacitor located in at least one of the first type pixel driving circuits;

[0044] The third conductive layer includes at least: the plurality of first scan signal lines, the plurality of third scan signal lines, the plurality of first light emission signal lines, the plurality of second light emission signal lines, and the first and second electrodes of the at least one transistor located in at least one first type pixel driving circuit.

[0045] In an exemplary embodiment, the orthogonal projection of at least one of the reset signal line and the second initial signal line connected to the i-th row first type pixel driving circuit on the substrate at least partially overlaps with the orthogonal projection of the third light-shielding part in the i-th light-shielding structure on the substrate.

[0046] The orthographic projections of the second scan signal line connected to the first type pixel driving circuit in the i-th row, the first scan signal line connected to the first type pixel driving circuit in the i-th row, the third scan signal line connected to the first type pixel driving circuit in the i-th row, the first light emission signal line connected to the first type pixel driving circuit in the i-th row, the second light emission signal line connected to the first type pixel driving circuit in the i-th row, the second initial signal line connected to the first type pixel driving circuit in the i-th row, and the reset signal line connected to the first type pixel driving circuit in the i-th row are arranged sequentially along the second direction.

[0047] In an exemplary embodiment, it further includes: a plurality of first initial signal lines, at least one of the plurality of first initial signal lines including: a plurality of spaced first initial connection portions and a plurality of spaced second initial connection portions;

[0048] At least one of the first initial connection portion and the second initial connection portion extends at least partially along the first direction, the plurality of spaced first initial connection portions of the first initial signal line are arranged sequentially along the first direction, and the plurality of spaced second initial connection portions of the first initial signal line are arranged sequentially along the first direction;

[0049] The orthographic projections of the plurality of spaced second initial connection portions of the first initial signal line on the substrate are alternately arranged with the orthographic projections of the plurality of spaced first initial connection portions of the first initial signal line on the substrate, and at least one first initial connection portion of the first initial signal line is connected to two second initial connection portions.

[0050] In an exemplary embodiment, the first initial connection portion is located in the second conductive layer, and the second initial connection portion is located in the third conductive layer.

[0051] In an exemplary embodiment, the orthographic projection of the first initial signal line connected to the first type pixel driving circuit in the i-th row on the substrate and the orthographic projection of the second scan signal line connected to the first type pixel driving circuit in the i-th row on the substrate on the side away from the orthographic projection of the first scan signal line connected to the first type pixel driving circuit in the i-th row on the substrate are respectively.

[0052] The orthographic projection of the first initial signal line connected to the first type pixel driving circuit in the i-th row on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part of the i-th light-shielding structure on the substrate.

[0053] In an exemplary embodiment, it further includes: a plurality of data signal lines, wherein at least one of the plurality of data signal lines includes: a plurality of spaced first data connection lines and a plurality of spaced second data connection lines;

[0054] At least one of the first data connection line and the second data connection line extends at least partially along the second direction, the plurality of spaced first data connection lines of the plurality of data signal lines are arranged sequentially along the second direction, and the plurality of spaced second data connection lines of the plurality of data signal lines are arranged sequentially along the second direction;

[0055] The orthographic projections of the plurality of spaced first data connection lines on the substrate and the orthographic projections of the plurality of spaced second data connection lines on the substrate are arranged alternately, and at least one second data connection line is connected to two first data connection lines.

[0056] In an exemplary embodiment, the first type of pixel driving circuit for at least one pixel island includes: a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit. For the same pixel island, the first data connection line of the data signal line connected to the first pixel driving circuit and the first data connection line of the data signal line connected to the third pixel driving circuit are respectively located on opposite sides of the first data connection line of the data signal line connected to the second pixel driving circuit.

[0057] The first data connection line of the data signal line connected to the second pixel driving circuit extends along the second direction, and the orthographic projection of the first data connection line of the data signal line connected to the second pixel driving circuit in the (i+1)th row on the substrate at least partially overlaps with the orthographic projection of at least one of the third light-shielding part of the i-th light-shielding structure, the first light-shielding part of the (i+1)th light-shielding structure, and the light-shielding connection part located between the i-th light-shielding structure and the (i+1)th light-shielding structure on the substrate.

[0058] The first data connection line of the data signal line connected to the first pixel driving circuit includes: a first connection portion, a second connection portion and a third connection portion. The first connection portion and the third connection portion are located on the side of the first data connection line away from the second connection portion and the data signal line connected to the second pixel driving circuit, and are arranged along the second direction. The second connection portion is connected to the first connection portion and the third connection portion respectively. At least one of the first connection portion and the third connection portion extends at least partially along the first direction, and the second connection portion extends at least partially along the second direction.

[0059] For the first data connection line of the data signal line connected to the first pixel driving circuit in the (i+1)th row, the orthographic projection of the first connection part on the substrate at least partially overlaps with the orthographic projection of the third light-shielding part of the i-th light-shielding structure on the substrate; the orthographic projection of the second connection part on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection part in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate; the orthographic projection of the third connection part on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part of the (i+1)-th light-shielding structure on the substrate.

[0060] The first data connection line of the data signal line connected to the third pixel driving circuit includes: a fourth connection part, a fifth connection part, and a sixth connection part. The fourth connection part and the sixth connection part are located on the side of the first data connection line away from the fifth connection part away from the data signal line connected to the second pixel driving circuit, and are arranged along the second direction. The fifth connection part is connected to the fourth connection part and the sixth connection part respectively. At least one of the fourth connection part and the sixth connection part extends at least partially along the first direction, and the fifth connection part extends at least partially along the second direction.

[0061] For the first data connection line of the data signal line connected to the third pixel driving circuit in the (i+1)th row, the orthographic projection of the fourth connection part on the substrate at least partially overlaps with the orthographic projection of the third light-shielding part of the i-th light-shielding structure on the substrate; the orthographic projection of the fifth connection part on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection part in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate; and the orthographic projection of the sixth connection part on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part of the (i+1)-th light-shielding structure on the substrate.

[0062] In an exemplary embodiment, the driving structure layer further includes a fourth conductive layer, the fourth conductive layer being located on the side of the third conductive layer away from the substrate;

[0063] The first data connection line is located in the third conductive layer, and the second data connection line is located in the fourth conductive layer.

[0064] In an exemplary embodiment, it further includes: a plurality of first power lines, a plurality of first power connection lines, and a plurality of second power connection lines, wherein at least one of the plurality of first power connection lines is connected to a first light-shielding part of at least one of the plurality of light-shielding structures, and at least one of the plurality of second power connection lines is connected to a third light-shielding part of at least one of the plurality of light-shielding structures.

[0065] The first power line extends along the second direction, and at least one of the first power connection line and the second power connection line extends along the first direction;

[0066] The first power lines of adjacent first-type pixel driving circuits in the same column are spaced apart and arranged along the second direction; the first power lines of adjacent first-type pixel driving circuits in the same row are spaced apart and arranged along the first direction.

[0067] The first end of the first power line connected to the first type pixel driving circuit in the i-th row is electrically connected to the first power line connected to the i-th first power line, and the second end of the first power line connected to the first type pixel driving circuit in the i-th row is electrically connected to the i-th second power line connected to the second power line.

[0068] The first power connection line and the first light-shielding part of the first light-shielding structure at least partially overlap on the substrate, and the second power connection line and the third light-shielding part of the first light-shielding structure at least partially overlap on the substrate.

[0069] In an exemplary embodiment, the plurality of first power lines, the plurality of first power connection lines, and the plurality of second power connection lines are located in the fourth conductive layer.

[0070] In an exemplary embodiment, it further includes: a plurality of power connection structures, wherein the i-th power connection structure is connected to the i-th second power connection line and the i+1-th first power connection line respectively, and is located between the i-th second power connection line and the i+1-th first power connection line;

[0071] At least one of the plurality of power connection structures includes a plurality of spaced power connection portions, the power connection portions extending along the second direction and located in the fourth conductive layer;

[0072] At least one power connection portion in the i-th power connection structure is connected to the i-th second power connection line and the i+1-th first power connection line respectively, and a fifth opening is formed between the i-th second power connection line, the i+1-th first power connection line and at least two adjacent power connection portions of the i-th power connection structure.

[0073] In an exemplary embodiment, the orthographic projection of at least one power connection portion of the i-th power connection structure onto the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection portion of the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure onto the substrate.

[0074] At least one power connection portion has its center line extending along the second direction located between the center lines of at least two of the plurality of first power lines extending along the second direction.

[0075] In an exemplary embodiment, the i-th second power connection line has a recessed portion at its edge near the i-th first power connection line.

[0076] In an exemplary embodiment, it further includes: a third anode connection electrode that is connected to the third pixel driving circuit and the third anode respectively, the third anode connection electrode being located in the fourth conductive layer;

[0077] The third anode connection electrode extends at least partially along the second direction, and the third anode connection electrode in the i-th row pixel driving circuit is at least partially located in the recess of the i-th second power connection line.

[0078] In an exemplary embodiment, the line width of at least one of the plurality of spaced power connection portions is greater than the line width of at least one of the plurality of first power lines.

[0079] In an exemplary embodiment, the light-emitting structure layer further includes: a cathode conductive layer located on the side of the anode conductive layer away from the substrate, the cathode conductive layer being provided with a plurality of cathode vias;

[0080] At least one of the plurality of cathode vias has its orthographic projection on the substrate located within the range of the orthographic projections of at least one of the first opening and the fifth opening on the substrate.

[0081] In a second aspect, this disclosure also provides a display substrate, including: a display area, the display area including at least: a first display area and a second display area, the second display area at least partially surrounding the first display area, the first display area including a plurality of pixel island areas and a plurality of light-transmitting areas distributed between the pixel island areas;

[0082] A plurality of first-type sub-pixels are located in the first display area. At least one of the plurality of first-type sub-pixels includes a first-type pixel driving circuit and a first-type light-emitting device. The first-type pixel driving circuit is configured to drive the first-type light-emitting device to emit light. The plurality of first-type sub-pixels constitute a plurality of pixel islands. Each pixel island is located in one of the plurality of pixel island areas, and each pixel island includes at least two first-type sub-pixels.

[0083] A plurality of second-type sub-pixels are located in the second display area. At least one of the plurality of second-type sub-pixels includes a second-type pixel driving circuit and a second-type light-emitting device. The second-type pixel driving circuit is configured to drive the second-type light-emitting device to emit light.

[0084] The spacing between adjacent pixel islands along the first direction is less than the maximum length of the light-transmitting area between adjacent pixel islands along the second direction, and the spacing between adjacent second-type pixel driving circuits along the second direction is less than the spacing between adjacent pixel islands along the second direction.

[0085] In an exemplary embodiment, the area of ​​the first type of pixel driving circuit located in the first display area is smaller than the area of ​​the second type of pixel driving circuit located in the second display area.

[0086] In an exemplary embodiment, the display substrate includes a substrate and a driving circuit layer and a light-emitting structure layer disposed on the substrate. The light-emitting structure layer includes a cathode conductive layer having a plurality of cathode vias. The driving circuit layer includes at least one conductive layer.

[0087] At least one of the plurality of cathode vias has an orthographic projection on the substrate that does not overlap with the orthographic projection of the at least one conductive layer on the substrate.

[0088] Thirdly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0089] In an exemplary embodiment, the device further includes a sensor located on the non-light-emitting side of the display substrate, wherein the orthographic projection of the sensor on the substrate is at least partially located on the orthographic projection of the first display area on the substrate.

[0090] In an exemplary embodiment, the system further includes a camera located on the non-light-emitting side of the display substrate, wherein the orthographic projection of the camera onto the substrate is at least partially located on the orthographic projection of the first display area onto the substrate.

[0091] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0092] Overview of the attached figures

[0093] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0094] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0095] Figure 2 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0096] Figure 3 is a timing diagram of a pixel driving circuit.

[0097] Figure 4A is a schematic diagram of the arrangement of pixel driving circuits in the display area of ​​at least one embodiment of the present disclosure;

[0098] Figure 4B is a schematic diagram of the arrangement of pixel driving circuits in the display area of ​​at least one embodiment of the present disclosure;

[0099] Figure 5 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0100] Figure 6 is a schematic cross-sectional view of the display substrate provided in an embodiment of this disclosure;

[0101] Figure 7 is a schematic diagram of the film layers of the anode conductive layer and the pixel definition layer in a display substrate provided in an exemplary embodiment;

[0102] Figure 8 is a schematic diagram of the structure of the light-shielding layer and the semiconductor layer in a display substrate provided in an exemplary embodiment;

[0103] Figure 9 is a schematic diagram of multiple film layers of a display substrate provided in an exemplary embodiment;

[0104] Figure 10 is a schematic diagram of multiple film layers of a display substrate provided in an exemplary embodiment;

[0105] Figure 11 is a schematic diagram of multiple film layers of a display substrate provided in an exemplary embodiment;

[0106] Figure 12 is a schematic diagram after the formation of the light-shielding layer pattern;

[0107] Figure 13 is a schematic diagram of the semiconductor layer pattern;

[0108] Figure 14 is a schematic diagram after the semiconductor layer pattern has been formed;

[0109] Figure 15 is a schematic diagram of the pattern of the first conductive layer;

[0110] Figure 16 is a schematic diagram after the formation of the first conductive layer pattern;

[0111] Figure 17 is a schematic diagram of the pattern of the second conductive layer;

[0112] Figure 18 is a schematic diagram after the formation of the second conductive layer pattern;

[0113] Figure 19 is a schematic diagram after the fourth insulating layer pattern is formed;

[0114] Figure 20 is a schematic diagram of the pattern of the third conductive layer;

[0115] Figure 21 is a schematic diagram after the formation of the third conductive layer pattern;

[0116] Figure 22 is a schematic diagram after the formation of the first planarization layer pattern;

[0117] Figure 23 is a schematic diagram of the pattern of the fourth conductive layer;

[0118] Figure 24 is a schematic diagram after the formation of the fourth conductive layer pattern;

[0119] Figure 25 is a schematic diagram after the formation of the second planarization layer pattern;

[0120] Figure 26 is a schematic diagram of the anode conductive layer pattern;

[0121] Figure 27 is a schematic diagram after the formation of the anode conductive layer pattern;

[0122] Figure 28 is a schematic diagram after the pixel definition layer pattern is formed;

[0123] Figure 29 is a schematic diagram after the cathode conductive layer pattern is applied;

[0124] Figure 30 is a schematic diagram after the cathode conductive layer pattern is formed;

[0125] Figure 31 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure.

[0126] Detailed Explanation

[0127] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0128] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0129] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0130] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0131] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0132] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0133] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0134] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0135] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0136] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0137] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0138] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0139] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0140] In-vehicle facial recognition systems are an advanced facial recognition technology that enables facial recognition in automotive products and is currently widely used in the automotive industry. However, older in-vehicle facial recognition systems typically have a low aperture ratio, which reduces their reliability.

[0141] The automotive products include display substrates used for display and facial recognition.

[0142] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. As shown in Figure 1, the display substrate may include a display area AA and a peripheral area BB located around the display area AA. The display area AA of the display substrate may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited in this respect.

[0143] In some examples, as shown in Figure 1, the first display area A1 can be a light-transmitting display area, or it can also be called an under-display camera (FDC) area. The second display area A2 can also be called a normal display area. For example, the orthographic projection of a sensor (such as a camera or other hardware) onto the display substrate can be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 can be circular, and the size of the orthographic projection of the sensor onto the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the sensor onto the display substrate can be less than or equal to the size of the first display area A1.

[0144] In some examples, as shown in Figure 1, the first display area A1 may be located at the top center of the display area AA. The second display area A2 may surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 may be located at other positions such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 may surround at least one side of the first display area A1.

[0145] In some examples, as shown in Figure 1, the display area AA can be a rectangle, such as a rounded rectangle. The first display area A1 can be a circle, an ellipse, or a rectangle. However, this embodiment is not limited to this. For example, the first display area A1 can be a rectangle, a semicircle, a pentagon, or other shapes.

[0146] In some examples, the display area AA can be configured with multiple sub-pixels. At least one sub-pixel can include a pixel driving circuit and a light-emitting device. The pixel driving circuit can be configured to drive the connected light-emitting device. For example, the pixel driving circuit can be configured to provide a driving current to drive the light-emitting device to emit light. The pixel driving circuit can include multiple transistors and at least one capacitor. For example, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0147] As shown in Figure 1, the sub-pixel located in the first display area is a first type pixel. At least one of the multiple first type sub-pixels includes: a first type pixel driving circuit 11 and a first type light-emitting device 13. The first type pixel driving circuit 11 is configured to drive at least one first type light-emitting device 13 to emit light.

[0148] The sub-pixel located in the second display area is a second type of sub-pixel. At least one of the multiple second type sub-pixels includes: a second type pixel driving circuit 12 and a second type light-emitting device 14. The second type pixel driving circuit 12 is configured to drive the second type light-emitting device 14 to emit light.

[0149] In an exemplary embodiment, the orthographic projection of the first type pixel driving circuit 11 on the substrate at least partially overlaps with the orthographic projection of at least one first type light-emitting device 13 on the substrate.

[0150] In an exemplary embodiment, the orthographic projection of the second type pixel driving circuit 12 on the substrate at least partially overlaps with the orthographic projection of at least one second type light-emitting device 14 on the substrate.

[0151] In some examples, at least one of the first and second type of light-emitting devices may include a current-driven device, such as a current-driven light-emitting diode (LED), a micro LED, a mini LED, an organic light-emitting diode (OLED), or a quantum dot LED (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm. For example, the light-emitting device can be an OLED, which can emit red, green, blue, or white light when driven by its corresponding pixel driving circuit. The emitted color of the light-emitting device can be determined as needed. In some examples, the light-emitting device may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting device can be electrically connected to the corresponding pixel driving circuit. However, this embodiment is not limited to this.

[0152] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0153] Figure 2 is an equivalent circuit diagram of a pixel driving circuit. The pixel driving circuit shown in Figure 2 refers to the first type of pixel driving circuit and the second type of pixel driving circuit. Figure 2 is illustrated using a 7T1C pixel driving circuit as an example. As shown in Figure 2, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 1 capacitor C. The pixel driving circuit can be connected to ten signal lines (data signal line Data, first power supply line VDD, reset signal line Reset, first scan signal line Gate1, second scan signal line Gate2, third scan signal line Gate3, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1 and second initial signal line INIT2).

[0154] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0155] In an exemplary embodiment, the first end of capacitor C is connected to the first power line VDD, and the second end of capacitor C is connected to the second node N2, that is, the second end of capacitor C is connected to the control electrode of the third transistor T3.

[0156] The control electrode of the first transistor T1 is connected to the second scan signal line Gate2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the second node N2. When a conduction-level scan signal is applied to the second scan signal line Gate2, the first transistor T1 transmits the initialization voltage of the first initial signal line INIT1 to the control electrode of the third transistor T3, thereby initializing the charge of the control electrode of the third transistor T3.

[0157] The control electrode of the second transistor T2 is connected to the third scan signal line Gate3, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the third scan signal line Gate3, the second transistor T2 causes the control electrode of the third transistor T3 to connect to its second electrode.

[0158] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0159] The control electrode of the fourth transistor T4 is connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line Gate1, the fourth transistor T4 causes the data voltage of the data signal line Data to be input to the pixel driving circuit.

[0160] The control electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device L. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the first light-emitting signal line EM1 and the second light-emitting signal line EM2, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0161] The control electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device L. When a conduction level scan signal is applied to the reset signal line Reset, the seventh transistor T7 transmits the initialization voltage of the second initial signal line INIT2 to the first electrode of the light-emitting device L, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0162] In an exemplary embodiment, the second electrode of the light-emitting device L is connected to the second power line VSS.

[0163] In an exemplary embodiment, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The second scan signal line Gate2 can be a third scan signal line Gate3 connected to at least one row of pixel driving circuits located before this display row.

[0164] Based on their characteristics, transistors can be classified into N-type transistors and P-type transistors. When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0165] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0166] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0167] In an exemplary embodiment, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 may be the same signal line or different signal lines, depending on the structure of the pixel driving circuit. This disclosure does not impose any limitations on this.

[0168] Figure 3 is a timing diagram of a pixel driving circuit. The following describes an exemplary embodiment of this disclosure through the operation of the pixel driving circuit illustrated in Figure 2. The pixel driving circuit in Figure 2 includes seven transistors (first transistor T1 to seventh transistor T7) and one capacitor. All seven transistors are P-type transistors.

[0169] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0170] In the first stage A1, also known as the reset stage, the signals of the second scan signal line Gate2, the third scan signal line Gate3, and the reset signal line Reset are low-level signals, while the signals of the first scan signal line Gate1, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. When the signal of the second scan signal line Gate2 is low, the first transistor T1 is turned on, and the signal of the first initial signal line INIT1 is provided to the second node N2 and the third node N3 to initialize (reset) them, clearing the original charge in the capacitors. When the signal of the reset signal line Reset is low, the seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is provided to the first terminal of the light-emitting device L to initialize (reset) it, clearing the original charge in the first terminal of the light-emitting device L. When the signals of the first scan signal line Gate1, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off, and the light-emitting device L does not emit light during this stage.

[0171] The second stage, A2, is called the data writing stage or threshold compensation stage. The signals of the first scan signal line Gate1 and the third scan signal line Gate3 are low-level signals, while the signals of the reset signal line Reset, the second scan signal line Gate2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. The data signal line Data outputs a data voltage. With the first scan signal line Gate1 and the third scan signal line Gate3 low-level signals, the second transistor T2 and the fourth transistor T4 are turned on. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line Data to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line Data and the threshold voltage of the third transistor T3 is charged into the second terminal of capacitor C (second node N2), resulting in a voltage of Vd - |Vth|, where Vd is the data voltage output from the data signal line Data, and Vth is the threshold voltage of the third transistor T3. The signals of the reset signal line Reset, the second scan signal line Gate2, the first light emission signal line EM1, and the second light emission signal line EM2 are high-level signals, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are disconnected.

[0172] The third stage, A3, is called the light-emitting stage. During this stage, the signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, while the signals on the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, and the reset signal line Reset are high-level signals. The low-level signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 turn on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first terminal of the light-emitting device L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device L to emit light.

[0173] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is: I = K*(Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0174] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0175] As can be seen from the derivation of the above current formula, during the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.

[0176] Figure 4A is a schematic diagram of the arrangement of pixel driving circuits in the display area according to at least one embodiment of the present disclosure, and Figure 4B is a schematic diagram of the arrangement of pixel driving circuits in the display area according to at least one embodiment of the present disclosure. Figures 4A and 4B are enlarged schematic diagrams of the dashed box L in Figure 1. As shown in Figures 4A and 4B, the multiple pixel driving circuits in the display area may include: multiple first-type pixel driving circuits 11 located in the first display area A1 and multiple second-type pixel driving circuits 12 located in the second display area A2. The multiple first-type pixel driving circuits 11 in the first display area A1 and the multiple second-type pixel driving circuits 12 in the second display area A2 can be arranged in an array along the first direction D1 and the second direction D2. Among them, the multiple pixel driving circuits arranged along the first direction D1 are a row of pixel driving circuits, and the multiple pixel driving circuits arranged along the second direction D2 are a column of pixel driving circuits. For example, the first direction D1 may be perpendicular to the second direction D2. Only the first-type pixel driving circuits and the second-type pixel driving circuits are shown in Figure 4, and the first-type light-emitting devices and the second-type light-emitting devices are not shown.

[0177] In some examples, as shown in Figures 4A and 4B, the first display area A1 may include: a plurality of pixel island areas A11 and a plurality of light-transmitting areas A12 distributed among the pixel island areas. A plurality of first-type sub-pixels 11 constitute a plurality of pixel islands, each pixel island being located in one of the plurality of pixel island areas, and each pixel island including at least two first-type sub-pixels, for example, each pixel island including three first-type sub-pixels. In some exemplary embodiments, as shown in Figures 4A and 4B, the first display area A1 may further include: a plurality of wiring areas A13.

[0178] In an exemplary embodiment, the pixel island area A11 may include: at least one row of first-type pixel driving circuits disposed on the substrate and multiple groups of first-type light-emitting devices (not shown) arranged along the first direction D1. One row of first-type pixel driving circuits may include multiple first-type pixel driving circuits 11 aligned along the first direction D1. Each group of first-type light-emitting devices may include multiple first-type light-emitting devices, for example, it may include three first-type light-emitting devices emitting different colors of light. For example, the orthographic projection of the multiple groups of first-type light-emitting devices arranged along the first direction D1 onto the substrate may be located within the orthographic projection range of one row of first-type pixel driving circuits onto the substrate.

[0179] In an exemplary embodiment, a plurality of pixel island regions A11 are arranged in an array along a first direction D1 and a second direction D2. The pixel island regions A11 can be generally rectangular. The length of the pixel island regions A11 along the first direction D1 can be greater than the length along the second direction D2.

[0180] In some examples, multiple pixel driving circuits in the display area can be connected to multiple first signal lines extending along a first direction D1 (illustrated as a single first signal line 15 in Figures 4A and 4B) and multiple second signal lines extending along a second direction D2 (illustrated as a single second signal line 16 in Figures 4A and 4B). First-type pixel driving circuits 11 within adjacent pixel island areas A11 can transmit signals along the second direction D2 via signal connection lines 17. Multiple signal connection lines 17 can be centrally arranged within the wiring area A13. In some examples, the multiple first signal lines may include multiple gate lines, such as scan lines, light emission control lines, and reset control lines. The multiple second signal lines may include multiple data lines and a first power supply line.

[0181] In some examples, the first signal line 15 passing through the first display area A1 can be connected to a row of first-type pixel driving circuits 11 in the pixel island area A11 and a corresponding row of second-type pixel driving circuits 12 in the second display area A2. The second signal line 16 passing through the first display area A1 can be connected to a column of first-type pixel driving circuits 11 in multiple sub-pixel island areas A11 and a corresponding column of second-type pixel driving circuits 12 in the second display area A2. The signal connection line 17 enables connection between the same column of first pixel circuits 11 in adjacent sub-display areas A11.

[0182] In some examples, the maximum length of the first type pixel driving circuit 11 along the second direction D2 can be less than the maximum length of the second type pixel driving circuit 12 along the second direction D2. A column of first type pixel driving circuits 11 in the pixel island area A11 can be aligned with a column of second type pixel driving circuits 12 in the second display area A2. In this way, the pixel density (PPI, Pixels Per Inch) of the first display area A1 and the pixel density of the second display area A2 can be guaranteed to be the same. Taking an automotive display device as an example, since the pixel density of automotive display devices is relatively low, usually around 200 PPI, reducing the pixel density of the first display area will affect the display effect. Therefore, ensuring that the pixel density of the first display area A1 and the second display area A2 is the same can guarantee the display effect of the first display area A1.

[0183] In some examples, as shown in Figures 4A and 4B, multiple trace areas A13 and multiple light-transmitting areas A12 are provided between adjacent pixel island areas A11. The trace areas A13 and the light-transmitting areas A12 can be arranged alternately along a first direction D1. A light-transmitting area A12 can be surrounded by two adjacent trace areas A13 and two adjacent pixel island areas A11. The light-transmitting area A12 can be approximately rectangular, and its length along the first direction D1 can be greater than its length along the second direction D2. In other examples, the traces within the trace areas A13 can be made of a transparent conductive material, allowing the light-transmitting areas separated by the trace areas to be connected, thereby improving light transmittance.

[0184] As shown in Figures 4A and 4B, the spacing W1 between adjacent pixel islands along the first direction D1 is smaller than the spacing W2 between adjacent pixel islands along the second direction D2.

[0185] In this example, by compressing the first type of pixel driving circuit 11 along the second direction D2, the horizontal space (i.e., the space along the first direction D1) in the first display area A1 can be fully utilized, and the vertical space (i.e., the space along the second direction D2) can be freed up as a light-transmitting area, thereby improving the light transmittance of the first display area A1 while ensuring the pixel density of the first display area A1.

[0186] In an exemplary embodiment, as shown in Figures 4A and 4B, the spacing W1 between adjacent pixel islands along the first direction D1 is equal to the spacing W3 between two adjacent first-type pixel driving circuits within a pixel island along the first direction D1.

[0187] The embodiments of this disclosure shown in Figures 4A and 4B provide a display substrate in which the area of ​​the first type pixel driving circuit 11 located in the first display area A1 is smaller than the area S2 of the second type pixel driving circuit located in the second display area A2.

[0188] In an exemplary embodiment, as shown in Figures 4A and 4B, the spacing W4 between adjacent second-type pixel driving circuits along the second direction D2 is smaller than the spacing W2 between adjacent pixel islands along the second direction D2.

[0189] In an exemplary embodiment, as shown in FIG4A, a row of first-type pixel driving circuits 11 can be provided in the pixel island area A11 of the first display area A1. Each row of first-type pixel driving circuits can correspond to a row of second-type pixel driving circuits in the second display area A2. Each column of first-type pixel driving circuits can correspond to a column of second-type pixel driving circuits in the second display area A2. Adjacent first-type pixel driving circuits 11 in the same column of first-type pixel driving circuits in adjacent sub-display areas A11 can achieve signal transmission along the second direction D2 through the signal connection lines 17 of the wiring area A13 (such as including multiple first data connection lines located in the third conductive layer and power connection parts located in the fourth conductive layer).

[0190] In an exemplary embodiment, as shown in FIG4B, the pixel island area A11 of the first display area A1 can be provided with two rows of first-type pixel driving circuits 11, and each row of first-type pixel driving circuits can correspond to a row of second-type pixel driving circuits in the second display area A2. Each column of first-type pixel driving circuits can correspond to a column of second-type pixel driving circuits in the second display area A2. Adjacent first-type pixel driving circuits 11 in the same column of first-type pixel driving circuits in adjacent sub-display areas A11 can achieve signal transmission along the second direction D2 through the signal connection lines 17 of the wiring area A13 (such as including multiple first data connection lines located in the third conductive layer and power connection parts located in the fourth conductive layer). In some examples, the maximum length of the light-transmitting area A12 along the second direction D2 can be greater than the maximum length of the first-type pixel driving circuit 11 along the second direction D2, and greater than the maximum length of the second-type pixel driving circuit 12 along the second direction D2. The arrangement of this example is beneficial to increasing the size of the light-transmitting area along the second direction. The remaining description of the display substrate of this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0191] In other examples, the pixel island area A11 of the first display area A1 can be configured with three rows, four rows, or more rows of first-type pixel driving circuits. By centrally configuring the first-type pixel driving circuits along the second direction D2, it is advantageous to increase the size of the light-transmitting area along the second direction.

[0192] In other examples, the first direction can be a column direction, and the second direction can be a row direction. Multiple pixel islands A11 in the first display area can be arranged sequentially along the column direction, and multiple light-transmitting areas and multiple trace areas located between adjacent pixel islands A11 can be spaced apart along the column direction. One or more columns of first-type pixel driving circuits can be arranged within a pixel island A11. The light-transmitting areas can extend along the column direction.

[0193] In an exemplary embodiment, the spacing between adjacent pixel islands along the first direction D1 is less than the maximum length of the light-transmitting area between adjacent pixel islands along the second direction D2.

[0194] Figure 5 is a structural schematic diagram of a display substrate located in the first display area according to an embodiment of the present disclosure, and Figure 6 is a cross-sectional schematic diagram of the display substrate provided in an embodiment of the present disclosure. As shown in Figures 5 and 6, Figures 5 and 6 are illustrated using a display substrate located in the first display area as an example. The first type pixel driving circuit 11 is configured to drive a first type light-emitting device to emit light. At least one first type pixel driving circuit includes: a driving transistor and a capacitor C. The capacitor includes a first electrode and a second electrode, and the first electrode is connected to the control electrode of the driving transistor. Figure 5 is an enlarged schematic diagram of two rows and three columns of first type sub-pixels in the first display area.

[0195] In some examples, as shown in Figure 6, the display area of ​​the display substrate may include at least: a substrate 10 and a driving circuit layer 20 and a light-emitting structure layer 30 sequentially disposed on the substrate 10. The driving circuit layer 20 may include at least: a first-type pixel driving circuit for a plurality of first-type sub-pixels, each first-type sub-pixel's first-type pixel driving circuit may include a plurality of transistors and at least one capacitor. The light-emitting structure layer 30 may include at least: a first-type light-emitting device for a plurality of first-type sub-pixels.

[0196] In an exemplary embodiment, a transistor may include: an active pattern, a control electrode, a first electrode, and a second electrode.

[0197] In an exemplary embodiment, the display substrate may further include an encapsulation structure layer 40 and a touch structure layer 50 disposed on the side of the light-emitting structure layer away from the substrate.

[0198] In some examples, Figure 6 illustrates a first-type sub-pixel comprising one transistor 21 and one capacitor 23. The transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor.

[0199] In some examples, the driving circuit layer 20 of the display area may include: a bottom light-shielding metal layer, a semiconductor layer, a first conductive layer (also a first gate metal layer), a second conductive layer (also a second gate metal layer), a third conductive layer (also a first source / drain metal layer) and a fourth conductive layer (also a second source / drain metal layer) disposed on the substrate 10. A first insulating layer 101 (which can be called a buffer layer) can be disposed between the bottom light-shielding metal layer and the semiconductor layer; a second insulating layer 102 (first gate insulating layer) can be disposed between the semiconductor layer and the first gate metal layer; a third insulating layer 103 (second gate insulating layer) can be disposed between the first gate metal layer and the second gate metal layer; a fourth insulating layer 104 (interlayer dielectric layer) can be disposed between the second gate metal layer and the first source / drain metal layer; a fifth insulating layer 105 (which can also be called a passivation layer) and a sixth insulating layer 106 (which can also be called a first planarization layer) can be disposed between the first source / drain metal layer and the second source / drain metal layer, the sixth insulating layer 106 being located on the side of the fifth insulating layer 105 away from the substrate 10; and a seventh insulating layer 107 (which can also be called a second planarization layer) can be disposed on the side of the second source / drain metal layer away from the substrate 10. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be inorganic insulating layers, while the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, the buffer layer can prevent harmful substances in the substrate from penetrating the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, the bottom light-shielding metal layer can be configured to at least partially cover the active layer of the transistors of the pixel driving circuit to avoid external light affecting the performance of the transistors. In other examples, the fifth insulating layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the sixth insulating layer can be provided between the first source / drain metal layer and the second source / drain metal layer.

[0200] In some examples, as shown in FIG6, the semiconductor layer of the display area may include at least the active pattern 210 of transistor 21. The active pattern 210 of transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the first gate 213 of transistor 21 and the first electrode 231 of capacitor 23. The orthographic projection of the first gate 213 of transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 10. The second gate metal layer may include at least the second electrode 232 of capacitor 23. The orthographic projections of the second electrode 232 and the first electrode 231 of capacitor 23 onto the substrate 10 may at least partially overlap, for example, they may coincide.

[0201] In some examples, as shown in Figure 6, the first source-drain metal layer of the display area may include at least a first source 211 and a first drain 212 of transistor 21. The fourth insulating layer 104 may have multiple pixel vias (e.g., including a first pixel via and a second pixel via) in the display area. The fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, and the second insulating layer 102 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The first source 211 of transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via.

[0202] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer and the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer; and the first power lines of the display area may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect.

[0203] In some examples, as shown in Figure 6, the light-emitting structure layer 30 may include a pixel definition layer 134 and multiple light-emitting devices. For example, each first type of light-emitting device may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the first type of light-emitting device can be an anode, and the first electrode 131 can be disposed on a seventh insulating layer 107 and electrically connected to a first transition electrode 241 through a third pixel via formed in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0204] In some examples, the organic light-emitting layer 132 of the first type of light-emitting device may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0205] In some examples, the light-emitting layers of different colors of Type I light-emitting devices can be different. For example, a red Type I light-emitting device includes a red light-emitting layer, a green Type I light-emitting device includes a green light-emitting layer, and a blue Type I light-emitting device includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, and the electron injection layer and electron transport layer on the other side of the light-emitting layer can also be common layers. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0206] In some examples, as shown in Figure 6, the encapsulation structure layer 40 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density, which can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to ensure that external moisture cannot enter the light-emitting device. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display substrate and relieve stress on the first and third encapsulation layers 141 and 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0207] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0208] In some examples, as shown in FIG6, the touch structure layer 50 of the display area may include, in the direction perpendicular to the display substrate, a touch buffer layer (TBL) 150, a first touch conductive layer 151, a touch interlayer insulating layer (TLD) 153, a second touch conductive layer 152, and a touch protective layer (TOC) 154 arranged sequentially. The touch buffer layer 150 and the touch interlayer insulating layer 153 may be inorganic insulating layers, and the touch protective layer 154 may be an organic insulating layer. For example, the first touch conductive layer 151 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure interconnected. The second touch conductive layer 152 may include a plurality of second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer 153. However, this embodiment is not limited in this respect. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0209] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0210] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0211] In an exemplary embodiment, FIG7 is a top view schematic diagram of the film layers of the anode conductive layer and the pixel definition layer in a display substrate provided by an exemplary embodiment. As shown in FIG7, the first type of light-emitting device includes: a first light-emitting device, a second light-emitting device and a third light-emitting device, wherein the light-emitting device includes: an anode.

[0212] In an exemplary embodiment, the light-emitting structure layer includes: an anode conductive layer, a pixel definition layer, an organic light-emitting layer, and a cathode conductive layer sequentially stacked on a substrate.

[0213] In an exemplary embodiment, the anode conductive layer includes: a first anode AN1 of a first light-emitting device, a second anode AN2 of a second light-emitting device, and a third anode AN3 of a third light-emitting device.

[0214] In an exemplary embodiment, the first anode AN1 and the second anode AN2 are arranged along the second direction D2, and are respectively arranged with the third anode AN3 along the first direction D1.

[0215] In an exemplary embodiment, the area of ​​the first anode AN1 is smaller than the area of ​​the second anode AN2, and the area of ​​the third anode AN3 is larger than the area of ​​at least one of the first anode AN1 and the second anode AN2.

[0216] In an exemplary embodiment, the length L13 of the third anode AN3 along the second direction D2 is greater than the sum of the length L11 of the first anode AN1 along the second direction D2 and the length L12 of the second anode AN2 along the second direction D2.

[0217] In an exemplary embodiment, the distance H1 between the second anode AN2 connected to at least one first-type pixel driving circuit in the i-th row and the first anode AN1 connected to at least one first-type pixel driving circuit in the i+1-th row along the second direction D2 is greater than the length L12 of at least one second anode AN2 along the second direction D2.

[0218] In an exemplary embodiment, as shown in FIG7, the pixel definition layer includes: a first anode opening AV1 exposing a first anode, a second anode opening AV2 exposing a second anode, and a third anode opening AV3 exposing a third anode.

[0219] In an exemplary embodiment, the first type of pixel driving circuit includes: a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit, wherein the first pixel driving circuit is electrically connected to a first anode, the second pixel driving circuit is electrically connected to a second anode, and the third pixel driving circuit is electrically connected to a third anode.

[0220] In an exemplary embodiment, as shown in FIG7, the length W13 of the third anode opening AV3 along the second direction D2 is greater than the sum of the length W11 of the first anode opening AV1 along the second direction D2 and the length W12 of the second anode opening AV2 along the second direction D2.

[0221] In an exemplary embodiment, as shown in FIG7, the distance H2 between the second anode opening AV2 that exposes the second anode connected to the second anode in the i-th row and the first anode opening AV1 that exposes the first anode connected to the first anode in the (i+1)-th row along the second direction D2 is greater than the length W12 of the second anode opening along the second direction D2.

[0222] Figure 8 is a schematic diagram of the structure of a light-shielding layer and a semiconductor layer in a display substrate provided by an exemplary embodiment. As shown in Figure 8, the light-shielding layer includes: a plurality of light-shielding structures arranged along the second direction D2 and a light-shielding connection structure located between at least two adjacent light-shielding structures. The i-th light-shielding connection structure is connected to the i-th light-shielding structure and the (i+1)-th light-shielding structure, respectively, 1≤i≤M, where M is the total number of rows of the pixel driving circuit.

[0223] In an exemplary embodiment, the orthographic projection of at least one of the multiple light-shielding structures onto the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor in at least one first-type pixel driving circuit onto the substrate.

[0224] In an exemplary embodiment, as shown in FIG8, at least one light-shielding structure includes: a first light-shielding part BS1, a third light-shielding part BS3, and a plurality of second light-shielding parts BS2 arranged along a first direction D1 between the first light-shielding part BS1 and the third light-shielding part BS3.

[0225] In an exemplary embodiment, the first light-shielding portion BS1 and the third light-shielding portion BS3 extend at least partially along the first direction D1.

[0226] In an exemplary embodiment, as shown in FIG8, the first light-shielding part BS1 of the i-th light-shielding structure is located on the side of the third light-shielding part BS3 of the i-th light-shielding structure away from the (i+1)-th light-shielding structure, and at least two adjacent second light-shielding parts BS2 in the same light-shielding structure are interconnected.

[0227] In an exemplary embodiment, as shown in FIG8, a second opening K2 is formed between at least two adjacent second light-shielding parts BS2 and the first light-shielding part BS1 located in the same light-shielding structure, a third opening K3 is formed between at least two adjacent second light-shielding parts BS2 and the third light-shielding part BS3 located in the same light-shielding structure, and a fourth opening K4 is provided on at least one second light-shielding part BS2.

[0228] In an exemplary embodiment, as shown in FIG8, the area of ​​the fourth opening K4 is smaller than the area of ​​one of the second opening K2 and the third opening K3.

[0229] In an exemplary embodiment, as shown in FIG8, at least one light-shielding connection structure includes: a plurality of light-shielding connection portions BSC arranged along a first direction D1, at least one light-shielding connection portion BSC extending along a second direction D2, and adjacent light-shielding connection portions BSC being spaced apart.

[0230] In an exemplary embodiment, as shown in FIG8, at least two adjacent light-shielding connecting portions BSC in the i-th light-shielding connecting structure are respectively connected to the third light-shielding portion BS3 in the i-th light-shielding structure and the first light-shielding portion BS1 in the (i+1)-th light-shielding structure, and a first opening K1 is formed between them and the third light-shielding portion BS3 in the i-th light-shielding structure and the first light-shielding portion BS1 in the (i+1)-th light-shielding structure. The first opening K1 may be located in the light-transmitting area.

[0231] In an exemplary embodiment, as shown in FIG8, the area of ​​the first opening K1 is greater than the area of ​​one of the second opening K2 and the third opening K3.

[0232] In an exemplary embodiment, as shown in FIG8, the length of at least one light-shielding connection portion BSC along the second direction D2 is greater than the length of at least one of the first light-shielding portion BS1 and the third light-shielding portion BS3 in the light-shielding structure along the second direction D2.

[0233] In an exemplary embodiment, the arrangement of the light-shielding structure and the light-shielding connection structure allows the pattern of the light-shielding layer to be a mesh structure.

[0234] In an exemplary embodiment, as shown in FIG8, the semiconductor layer includes an active pattern of at least one transistor. The orthographic projection of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor in the i-th row of the first-type pixel driving circuit onto the substrate.

[0235] In an exemplary embodiment, at least one transistor includes: a first transistor to a seventh transistor. The orthographic projection of the first light-shielding portion BS1 of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of a portion of the active pattern T11 of the first transistor located in the i-th row of the first-type pixel driving circuit onto the substrate. The orthographic projection of the second light-shielding portion BS2 of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projections of a portion of the active pattern T11 of the first transistor located in the i-th row of the first-type pixel driving circuit and the active patterns T21 of the second transistor to the active patterns T61 of the sixth transistor onto the substrate. In an exemplary embodiment, the orthographic projection of the third light-shielding portion BS3 of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of the active pattern T71 of the seventh transistor located in the i-th row of the first-type pixel driving circuit onto the substrate.

[0236] In an exemplary embodiment, the light-shielding layer blocks the active patterns of all transistors in the first type of pixel driving circuit, avoiding the influence of light illuminating the channel regions of the active patterns of all transistors, thereby improving the reliability of the pixel driving circuit.

[0237] In an exemplary embodiment, FIG9 is a schematic diagram of multiple film layers of a display substrate provided in an exemplary embodiment, and FIG10 is a schematic diagram of multiple film layers of a display substrate provided in an exemplary embodiment. As shown in FIG9 and FIG10, the display substrate further includes: multiple second scan signal lines Gate2, multiple reset signal lines Reset, multiple second initial signal lines INIT2, multiple first scan signal lines Gate1, multiple third scan signal lines Gate3, multiple first light emission signal lines EM1, and multiple second light emission signal lines EM2.

[0238] In an exemplary embodiment, as shown in Figures 9 and 10, at least one of the following signal lines extends at least partially along the first direction D1: a plurality of second scan signal lines Gate2, a plurality of reset signal lines Reset, a plurality of second initial signal lines INIT2, a plurality of first scan signal lines Gate1, a plurality of third scan signal lines Gate3, a plurality of first light emission signal lines EM1, and a plurality of second light emission signal lines EM2.

[0239] In an exemplary embodiment, the first conductive layer includes at least: a plurality of second scan signal lines Gate2, a plurality of reset signal lines Reset, and the control electrode of at least one transistor and the first plate of a capacitor located in at least one pixel driving circuit.

[0240] In an exemplary embodiment, the second conductive layer includes at least: a plurality of second initial signal lines INIT2 and a second plate of a capacitor located in at least one pixel driving circuit.

[0241] In an exemplary embodiment, the third conductive layer includes at least: a plurality of first scan signal lines Gate1, a plurality of third scan signal lines Gate3, a plurality of first light-emitting signal lines EM1, a plurality of second light-emitting signal lines EM2, a first light-shielding connection electrode, a second light-shielding connection electrode, and a first electrode and a second electrode located at at least one transistor of at least one first type pixel driving circuit.

[0242] In an exemplary embodiment, as shown in Figures 9 and 10, the orthographic projection of at least one of the reset signal line Reset and the second initial signal line INIT2 connected to the first type pixel driving circuit in the i-th row on the substrate at least partially overlaps with the orthographic projection of the third light-shielding part BS3 in the i-th light-shielding structure on the substrate.

[0243] In an exemplary embodiment, as shown in Figures 9 and 10, the orthographic projections of the second scan signal line Gate2 connected to the first type pixel driving circuit in the i-th row, the first scan signal line Gate1 connected to the first type pixel driving circuit in the i-th row, the third scan signal line Gate3 connected to the first type pixel driving circuit in the i-th row, the first light emission signal line EM1 connected to the first type pixel driving circuit in the i-th row, the second light emission signal line EM2 connected to the first type pixel driving circuit in the i-th row, the second initial signal line INIT2 connected to the first type pixel driving circuit in the i-th row, and the reset signal line Reset connected to the first type pixel driving circuit in the i-th row are arranged sequentially along the second direction D2.

[0244] In an exemplary embodiment, as shown in FIG10, the display substrate further includes: a plurality of first initial signal lines INIT1, wherein at least one of the plurality of first initial signal lines INIT1 includes: a plurality of spaced first initial connection portions CL1 and a plurality of spaced second initial connection portions CL2.

[0245] In an exemplary embodiment, as shown in FIG10, at least one of the first initial connection portion CL1 and the second initial connection portion CL2 extends at least partially along the first direction D1, and a plurality of first initial connection portions CL1 arranged at intervals along the first direction D1 are arranged sequentially along the first direction D1, and a plurality of second initial connection portions CL2 arranged at intervals along the first initial signal line are arranged sequentially along the first direction D1.

[0246] In an exemplary embodiment, as shown in FIG10, the orthographic projections of the plurality of spaced second initial connection portions CL2 of the first initial signal line INIT1 on the substrate are alternately arranged with the orthographic projections of the plurality of spaced first initial connection portions CL1 of the first initial signal line INIT1 on the substrate, and at least one first initial connection portion CL1 of the first initial signal line INIT1 is connected to two second initial connection portions CL2.

[0247] In an exemplary embodiment, as shown in FIG10, the first initial connection portion CL1 is located in the second conductive layer, and the second initial connection portion CL2 is located in the third conductive layer.

[0248] In an exemplary embodiment, as shown in FIG10, the orthographic projection of the first initial signal line INIT1 connected to the first type pixel driving circuit in the i-th row on the substrate and the orthographic projection of the second scan signal line Gate2 connected to the first type pixel driving circuit in the i-th row on the substrate are on the side away from the orthographic projection of the first scan signal line Gate1 connected to the first type pixel driving circuit in the i-th row on the substrate.

[0249] In an exemplary embodiment, as shown in FIG10, the orthographic projection of the first initial signal line connected to the first type pixel driving circuit in the i-th row on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part of the i-th light-shielding structure on the substrate.

[0250] In an exemplary embodiment, as shown in FIG9, the display substrate may further include: a plurality of data signal lines. At least one of the plurality of data signal lines includes: a plurality of spaced-apart first data connection lines Data1 and a plurality of spaced-apart second data connection lines Data2.

[0251] In an exemplary embodiment, as shown in Figures 9 and 10, the first data connection line Data1 and the second data connection line extend at least partially along the second direction D2. The multiple spaced first data connection lines Data1 are arranged sequentially along the second direction D2, and the multiple spaced second data connection lines Data2 are arranged sequentially along the second direction D2. The orthographic projections of the multiple spaced first data connection lines Data1 on the substrate and the orthographic projections of the multiple spaced second data connection lines Data2 on the substrate are arranged alternately, and at least one second data connection line Data2 is connected to two first data connection lines Data1.

[0252] In an exemplary embodiment, the first type of pixel driving circuit for at least one pixel island includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit. The different pixel driving circuits are configured to drive first type light-emitting devices of different colors to emit light.

[0253] In an exemplary embodiment, as shown in FIG10, for the same pixel island, the first data connection line Data1-1 of the data signal line connected to the first pixel driving circuit and the first data connection line Data1-3 of the data signal line connected to the third pixel driving circuit are respectively located on both sides of the first data connection line Data1-2 of the data signal line connected to the second pixel driving circuit. FIG10 is illustrated using an example of a pixel island including three first-type pixel driving circuits.

[0254] In an exemplary embodiment, as shown in FIG10, the first data connection line Data1-2 of the data signal line connected to the second pixel driving circuit extends along the second direction D2, and the orthographic projection of the first data connection line Data1-2 of the data signal line connected to the second pixel driving circuit in the (i+1)th row on the substrate at least partially overlaps with the orthographic projection of at least one of the third light-shielding part BS3 of the i-th light-shielding structure, the first light-shielding part BS1 of the (i+1)-th light-shielding structure, and the light-shielding connection structure BSC located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate.

[0255] In an exemplary embodiment, as shown in FIG10, the first data connection line Data1-1 of the data signal line connected to the first pixel driving circuit includes: a first connection portion 31, a second connection portion 32 and a third connection portion 33. The first connection portion 31 and the third connection portion 33 are located on the side of the first data connection line away from the second connection portion 32 away from the data signal line connected to the second pixel driving circuit, and are arranged along the second direction D2. The second connection portion 32 is connected to the first connection portion 31 and the third connection portion 33 respectively. At least one of the first connection portion 31 and the third connection portion 33 extends at least partially along the first direction D1, and the second connection portion 32 extends at least partially along the second direction D2.

[0256] In an exemplary embodiment, as shown in FIG10, for the first data connection line Data1-1 of the data signal line connected to the first pixel driving circuit in the (i+1)th row, the orthographic projection of the first connection part 31 on the substrate at least partially overlaps with the orthographic projection of the third light-shielding part BS3 of the i-th light-shielding structure on the substrate, the orthographic projection of the second connection part 32 on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection part BSC in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate, and the orthographic projection of the third connection part 33 on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part BS1 of the (i+1)-th light-shielding structure on the substrate.

[0257] In an exemplary embodiment, as shown in FIG10, the first data connection line Data1-3 of the data signal line connected to the third pixel driving circuit includes a fourth connection portion 41, a fifth connection portion 42, and a sixth connection portion 43. The fourth connection portion 41 and the sixth connection portion 43 are located on the side of the first data connection line Data1-2 away from the fifth connection portion 42 and are arranged along the second direction D2. The fifth connection portion 42 is connected to the fourth connection portion 41 and the sixth connection portion 43 respectively. At least one of the fourth connection portion 41 and the sixth connection portion 43 extends at least partially along the first direction D1, and the fifth connection portion 42 extends at least partially along the second direction D2.

[0258] In an exemplary embodiment, as shown in FIG10, for the first data connection line Data1-3 of the data signal line connected to the third pixel driving circuit of the (i+1)th row, the orthographic projection of the fourth connection part 41 on the substrate at least partially overlaps with the orthographic projection of the third light-shielding part BS3 of the i-th light-shielding structure on the substrate, the orthographic projection of the fifth connection part 42 on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection part BSC in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate, and the orthographic projection of the sixth connection part 43 on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part BS1 of the (i+1)-th light-shielding structure on the substrate.

[0259] In an exemplary embodiment, as shown in FIG10, the first data connection line Data1 is located in the third conductive layer, and the second data connection line Data1 is located in the fourth conductive layer.

[0260] In an exemplary embodiment, as shown in FIG9, the display substrate further includes: a plurality of first power lines VDD, a plurality of first power connection lines VL1, and a plurality of second power connection lines VL2; the first power lines VDD extend along a second direction D2, and at least one of the first power connection lines VL1 and the second power connection lines VL2 extends along a first direction D1.

[0261] In an exemplary embodiment, as shown in FIG9, at least one of the plurality of first power lines VDD, the first power connection line VL1, is connected to the first light-shielding part of at least one of the plurality of light-shielding structures.

[0262] In an exemplary embodiment, as shown in FIG9, at least one of the plurality of second power connection lines VL2 is connected to the third light-shielding part of at least one of the plurality of light-shielding structures.

[0263] In an exemplary embodiment, the first power line VDD, the first power connection line VL1, and the multiple second power connection lines may be located in the fourth conductive layer.

[0264] In an exemplary embodiment, as shown in FIG9, the first power lines VDD connected to the first type of pixel driving circuits located in the same column are spaced apart and arranged along the second direction D2, and the first power lines VDD connected to the first type of pixel driving circuits located in the same row are spaced apart and arranged along the first direction D1.

[0265] In an exemplary embodiment, as shown in FIG9, the first end of the plurality of first power lines VDD connected to the first type pixel driving circuit in the i-th row is electrically connected to the i-th first power connection line VL1, and the second end of the plurality of first power lines VDD connected to the first type pixel driving circuit in the i-th row is electrically connected to the i-th second power connection line VL2.

[0266] In an exemplary embodiment, as shown in FIG9, the orthographic projection of the i-th first power connection line VL1 and the first light-shielding part of the i-th light-shielding structure on the substrate at least partially overlaps, and the orthographic projection of the i-th second power connection line VL2 and the third light-shielding part of the i-th light-shielding structure on the substrate at least partially overlaps.

[0267] In an exemplary embodiment, as shown in FIG9, the display substrate may further include: a plurality of power connection structures, wherein the i-th power connection structure is connected to the i-th second power connection line and the i+1-th first power connection line respectively, and is located between the i-th second power connection line and the i+1-th first power connection line.

[0268] In an exemplary embodiment, as shown in FIG9, at least one of the plurality of power connection structures includes a plurality of spaced-apart power connection portions VCL. The power connection portions VCL extend along a second direction D2.

[0269] In an exemplary embodiment, as shown in FIG9, at least one power connection portion VCL located in the i-th second power connection line VL2 and the i-th power connection structure is connected to the i-th second power connection line VL2 and the (i+1)-th first power connection line VL1, respectively, and a fifth opening K5 is formed between the i-th second power connection line VL2, the (i+1)-th first power connection line VL1 and at least two adjacent power connection portions VCL in the i-th power connection structure.

[0270] In an exemplary embodiment, as shown in FIG9, the orthographic projection of at least one power connection portion VCL in the i-th power connection structure onto the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection portion in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure onto the substrate.

[0271] In an exemplary embodiment, as shown in FIG9, the center line of at least one power connection VCL extending along the second direction D2 is located between the center lines of at least two of the plurality of first power lines VDD extending along the second direction D2.

[0272] In an exemplary embodiment, as shown in FIG9, multiple first power lines VDD, multiple first power connection lines VL1, multiple second power connection lines VL2, and multiple power connection structures can form a mesh structure to ensure that the first power lines connected to at least one sub-pixel are interconnected, thereby improving the display uniformity of the display substrate.

[0273] In an exemplary embodiment, as shown in FIG9, the i-th second power connection line VL2 is provided with a recessed portion H near the edge of the i-th first power connection line VL1.

[0274] In an exemplary embodiment, as shown in FIG9, the display substrate further includes a third anode connection electrode AL3 located in the driving structure layer and connected to the third pixel driving circuit and the third anode respectively. The third anode connection electrode AL3 is located in the fourth conductive layer; the third anode connection electrode AL3 extends at least partially along the second direction D2, and a recessed portion H is provided on the edge of the i-th second power connection line VL2 near the i-th first power connection line VL1, and at least a portion of the third anode connection electrode AL3 in the i-th row pixel driving circuit is located in the recessed portion.

[0275] In an exemplary embodiment, as shown in FIG9, the line width of the power connection portion VCL among the plurality of spaced power connection portions is greater than the line width of the first power line VDD among the plurality of first power lines.

[0276] Figure 11 is a schematic diagram of multiple film layers of a display substrate provided in an exemplary embodiment. As shown in Figure 11, the cathode conductive layer includes: at least one cathode EN of a light-emitting device, and the cathode conductive layer is further provided with multiple cathode vias EV. The multiple cathode vias EV are located in the light-transmitting area.

[0277] In an exemplary embodiment, the cathodes of multiple light-emitting devices are interconnected or can be spaced apart; this disclosure does not limit this in any way.

[0278] In an exemplary embodiment, the orthographic projection of at least one of the plurality of cathode vias EVs onto the substrate is within the range of the orthographic projections of at least one of the first openings K1 and the fifth opening K5 onto the substrate.

[0279] In an exemplary embodiment, the length of the first opening or the fifth opening along the second direction can be 40 to 50 micrometers. Specifically, the length of the first opening or the fifth opening along the second direction can be 48 micrometers.

[0280] In an exemplary embodiment, the length of the first opening or the fifth opening along the second direction can be 110 micrometers to 120 micrometers. Specifically, the length of the first opening or the fifth opening along the second direction can be 118 micrometers.

[0281] The display substrate provided in this embodiment makes full use of the space in the first direction and leaves a large space in the second direction (such as the first opening or the fifth opening) to form a light-transmitting area, which greatly improves the transmittance of the display substrate.

[0282] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0283] Figures 12 to 30 are schematic diagrams illustrating the fabrication process of a display substrate according to an exemplary embodiment. Figures 12 to 30 are illustrated using a two-row, three-column first-type pixel driving circuit as an example. The fabrication process of a display substrate located in a first display area according to an exemplary embodiment may include:

[0284] In an exemplary embodiment, at least one transistor includes an active pattern, a gate electrode, a first electrode, and a second electrode.

[0285] (1) Forming a light-shielding layer pattern. In an exemplary embodiment, forming a light-shielding layer pattern includes: depositing a light-shielding film on a substrate, and patterning the light-shielding film through a patterning process to form a light-shielding layer pattern, as shown in FIG12. FIG12 is a schematic diagram after forming the light-shielding layer pattern.

[0286] In an exemplary embodiment, as shown in FIG12, the light-shielding layer pattern may include: a plurality of light-shielding structures arranged along the second direction D2 and a light-shielding connection structure located between at least two adjacent light-shielding structures.

[0287] In an exemplary embodiment, at least one light-shielding structure includes: a first light-shielding portion BS1, a third light-shielding portion BS3, and a plurality of second light-shielding portions BS2 arranged along a first direction D1 between the first light-shielding portion BS1 and the third light-shielding portion BS3. At least two adjacent second light-shielding portions BS2 within the same light-shielding structure are interconnected.

[0288] In an exemplary embodiment, the first light-shielding part BS1 of the i-th light-shielding structure is located on the side of the third light-shielding part BS3 of the i-th light-shielding structure away from the (i+1)-th light-shielding structure, 1≤i≤M, where M is the total number of rows of the first type of pixel driving circuit.

[0289] In an exemplary embodiment, a second opening K2 is formed between at least two adjacent second light-shielding portions BS2 and the first light-shielding portion BS1 located in the same light-shielding structure.

[0290] In an exemplary embodiment, the shape of the second opening K2 can be rectangular, circular, or polygonal. For example, the shape of the second opening K2 can be a polygon.

[0291] In an exemplary embodiment, a third opening K3 is formed between at least two adjacent second light-shielding portions BS2 and third light-shielding portions BS3 located in the same light-shielding structure.

[0292] In an exemplary embodiment, the shape of the third opening K3 can be rectangular, circular, or polygonal. For example, the shape of the third opening K3 can be a polygon.

[0293] In an exemplary embodiment, at least one second light-shielding portion BS2 is provided with a fourth opening K4.

[0294] In an exemplary embodiment, the shape of the fourth opening K4 can be rectangular, circular, or polygonal. For example, the shape of the fourth opening K4 can be rectangular.

[0295] In an exemplary embodiment, the area of ​​the fourth opening K4 is smaller than the area of ​​one of the second opening K2 and the third opening K3.

[0296] In an exemplary embodiment, the shape of the first light-shielding portion BS1 can be a line shape extending along the first direction D1.

[0297] In an exemplary embodiment, the main outline of the second light-shielding part BS2 can be square.

[0298] In an exemplary embodiment, the shape of the third light-shielding portion BS3 can be a line shape extending along the first direction D1.

[0299] In an exemplary embodiment, at least one light-shielding connection structure includes: a plurality of light-shielding connection portions BSC arranged along a first direction D1, with adjacent light-shielding connection portions BSC spaced apart.

[0300] In an exemplary embodiment, at least two adjacent light-shielding connection parts in the i-th light-shielding connection structure are respectively connected to the third light-shielding part BS3 in the i-th light-shielding structure and the first light-shielding part BS1 in the (i+1)-th light-shielding structure, and a first opening K1 is formed between them and the third light-shielding part BS3 in the i-th light-shielding structure and the first light-shielding part BS1 in the (i+1)-th light-shielding structure.

[0301] In an exemplary embodiment, the shape of the first opening K1 can be rectangular, circular, or polygonal. For example, the shape of the first opening K1 can be rectangular.

[0302] In an exemplary embodiment, the area of ​​the first opening K1 is greater than the area of ​​one of the second opening K2 and the third opening K3.

[0303] In an exemplary embodiment, the shape of the light-shielding connector BSC can be a strip shape extending along the second direction D2.

[0304] In an exemplary embodiment, the light-shielding layer pattern may be a mesh structure.

[0305] In an exemplary embodiment, the length of at least one light-shielding connection portion BSC along the second direction D2 is greater than the length of at least one of the first and third light-shielding portions in the light-shielding structure along the second direction D2.

[0306] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film on a substrate, and patterning the first insulating film and the semiconductor film by a patterning process to form a first insulating layer pattern and a semiconductor layer pattern formed on the first insulating layer pattern, as shown in Figures 13 and 14. Figure 13 is a schematic diagram of the semiconductor layer pattern, and Figure 14 is a schematic diagram after the semiconductor layer pattern is formed.

[0307] In an exemplary embodiment, the semiconductor layer pattern may include: active patterns T11 to T71 of the first transistor located in at least one first type pixel driving circuit.

[0308] In an exemplary embodiment, the active patterns T11 of the first transistor to T71 of the seventh transistor are an integral structure that is interconnected.

[0309] In an exemplary embodiment, in the first direction D1, the active pattern T21 of the second transistor and the active pattern T61 of the sixth transistor may be on the same side of the active pattern T31 of the third transistor T3. The active pattern T41 of the fourth transistor and the active pattern T51 of the fifth transistor may be on the same side of the active pattern T31 of the third transistor T3. The active pattern T21 of the second transistor and the active pattern T41 of the fourth transistor may be on different sides of the active pattern T31 of the third transistor T3. In the second direction D2, the active pattern T11 of the first transistor, the active pattern T21 of the second transistor, and the active pattern T41 of the fourth transistor in the i-th row of sub-pixels may be on the side of the active pattern T31 of the third transistor T3 closer to the (i - 1)-th row of sub-pixels. The active pattern T51 of the fifth transistor, the active pattern T61 of the sixth transistor, and the active pattern T71 of the seventh transistor in the i-th row of sub-pixels may be on the side of the active pattern T31 of the third transistor T3 closer to the (i + 1)-th row of sub-pixels.

[0310] In an exemplary embodiment, the shape of the active pattern T11 of the first transistor may be in the shape of "┐", the shape of the active pattern T21 of the second transistor may be in the shape of "n", the shape of the active pattern T31 of the third transistor T3 may be in the shape of an inverted "Ω", the active patterns T41 of the fourth transistor and T61 of the sixth transistor may be in the shape of "I", the active pattern T51 of the fifth transistor may be in the shape of "┘", and the active pattern T71 of the seventh transistor may be in the shape of "—".

[0311] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the second region T11-2 of the active pattern T11 of the first transistor may serve as the first region T21-1 of the active pattern T21 of the second transistor. The first region T31-1 of the active pattern T31 of the third transistor T3 may simultaneously serve as the second region T41-2 of the active pattern T41 of the fourth transistor and the second region T51-2 of the active pattern T51 of the fifth transistor. The second region T31-2 of the active pattern T31 of the third transistor T3 may simultaneously serve as the second region T21-2 of the active pattern T21 of the second transistor and the first region T61-1 of the active pattern T61 of the sixth transistor. The second region T61-2 of the active pattern T61 of the sixth transistor may serve as the second region T71-2 of the active pattern T71 of the seventh transistor. The first regions T11-1 of the active pattern T11 of the first transistor, T41-1 of the active pattern T41 of the fourth transistor, T51-1 of the active pattern T51 of the fifth transistor, and T71-1 of the active pattern of the seventh transistor may be separately provided.

[0312] In an exemplary embodiment, the orthographic projection of the i-th light-shielding structure on the substrate at least partially overlaps with the orthographic projection of the active pattern of at least one transistor in the i-th row of the first type pixel driving circuit on the substrate.

[0313] In an exemplary embodiment, the orthographic projection of the second light-shielding portion of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projections of a portion of the active pattern of the first transistor located in the i-th row of the first type pixel driving circuit and the active patterns of the second transistor to the sixth transistor onto the substrate.

[0314] In an exemplary embodiment, the orthographic projection of the first light-shielding portion of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of another portion of the active pattern of the first transistor located in the i-th row of the first type pixel driving circuit onto the substrate.

[0315] In an exemplary embodiment, the orthographic projection of the third light-shielding portion of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of the active pattern of the seventh transistor located in the i-th row of the first type pixel driving circuit onto the substrate.

[0316] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second insulating film and the first conductive film using a patterning process to form a second insulating layer pattern and a first conductive layer pattern located on the second insulating layer, as shown in Figures 15 and 16, wherein Figure 15 is a schematic diagram of the first conductive layer pattern, and Figure 16 is a schematic diagram after the formation of the first conductive layer pattern. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0317] In an exemplary embodiment, the first conductive layer pattern may include: a second scan signal line Gate2, a reset signal line Reset, and the control electrode T12 of the first transistor to the control electrode T72 of the seventh transistor in at least one first type pixel driving circuit and the first plate C1 of the capacitor.

[0318] In an exemplary embodiment, the first plate C1 of the capacitor can be rectangular in shape, with chamfered corners. The orthographic projection of the first plate C1 onto the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor onto the substrate. In an exemplary embodiment, the first plate C1 of the capacitor can also serve as the control electrode T32 of the third transistor T3.

[0319] In an exemplary embodiment, the reset signal line Reset can be a line shape in which the main body extends along the first direction D1. The reset signal line Reset connected to the first type pixel driving circuit in the i-th row can be located on the side of the first plate C1 of the capacitor in the i-th row of the first type pixel driving circuit, close to the side of the (i+1)-th row of the first type pixel driving circuit. The reset signal line Reset is provided with the control electrode T72 of the seventh transistor. The first end of the control electrode T72 of the seventh transistor is connected to the reset signal line Reset, and the second end of the control electrode T72 of the seventh transistor extends toward the first plate C1 of the capacitor (which is also the control electrode T32 of the third transistor).

[0320] In an exemplary embodiment, the orthographic projection of the reset signal line Reset connected to the first type pixel driving circuit in the i-th row onto the substrate at least partially overlaps with the orthographic projection of the third light-shielding part in the i-th light-shielding structure onto the substrate.

[0321] In an exemplary embodiment, the shape of the second scan signal line Gate2 can be a line shape in which the main body extends along the first direction D1. The second scan signal line Gate2 connected to the first type pixel driving circuit in the i-th row can be located on the side of the first plate C1 of the capacitor in the i-th row of the first type pixel driving circuit (which is also the control electrode T32 of the third transistor) away from the (i+1)-th row of the first type pixel driving circuit. The second scan signal line Gate2 connected to the first type pixel driving circuit is provided with a gate block Gate2-1. The first end of the gate block Gate2-1 is connected to the second scan signal line Gate2, and the second end of the gate block Gate2-1 extends toward the next column of the first type pixel driving circuit. The area where the second scan signal line Gate2 and the gate block Gate2-1 overlap with the active pattern of the first transistor in the first type pixel driving circuit serves as the control electrode of the first transistor T1 in the dual-gate structure.

[0322] In an exemplary embodiment, the orthographic projection of the second scan signal line Gate2 connected to the first type pixel driving circuit in the i-th row on the substrate is located between the orthographic projection of the first light-shielding part of the i-th light-shielding structure on the substrate and the orthographic projection of the third light-shielding part of the i-th light-shielding structure on the substrate.

[0323] In an exemplary embodiment, the control electrode T22 of the second transistor is separately configured and located on the side of the second scan signal line Gate2 connected to the first type of pixel driving circuit, close to the control electrode T32 of the third transistor (which is also the first plate C1 of the capacitor). The control electrode T22 of the second transistor can be shaped like an "n". The shaped "n" shape of the control electrode T22 of the second transistor allows the second transistor to be a dual-gate structure.

[0324] In an exemplary embodiment, the control electrode T42 of the fourth transistor is separately disposed and located on the side of the second scan signal line Gate2 connected to the first type of pixel driving circuit, close to the control electrode T32 of the third transistor (which is also the first plate C1 of the capacitor). The shape of the control electrode T42 of the fourth transistor can be a strip shape extending along the first direction D1.

[0325] In an exemplary embodiment, the control electrode T52 of the fifth transistor is separately disposed and located on the side away from the control electrode T32 of the third transistor (which is also the first plate C1 of the capacitor) and connected to the second scan signal line Gate2 of the first type pixel driving circuit. The control electrode T52 of the fifth transistor may be in the shape of a "┘".

[0326] In an exemplary embodiment, the control electrode T62 of the sixth transistor is separately disposed and located on the side away from the control electrode T32 of the third transistor (which is also the first plate C1 of the capacitor) and connected to the second scan signal line Gate2 of the first type pixel driving circuit. The control electrode T62 of the sixth transistor can be a strip extending along the first direction D1.

[0327] In an exemplary embodiment, the control electrode T12 of the first transistor is disposed across the active pattern of the first transistor, the control electrode T22 of the second transistor is disposed across the active pattern of the second transistor, the control electrode T32 of the third transistor T3 is disposed across the active pattern of the third transistor T3, the control electrode T42 of the fourth transistor is disposed across the active pattern of the fourth transistor, the control electrode T52 of the fifth transistor is disposed across the active pattern of the fifth transistor, the control electrode T62 of the sixth transistor is disposed across the active pattern of the sixth transistor, and the control electrode T72 of the seventh transistor is disposed across the active pattern of the seventh transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0328] In an exemplary embodiment, the process further includes a conductor-enhancing process. The conductor-enhancing process involves, after forming the first conductive layer pattern, using the semiconductor layer in the control electrode shielding region of the multiple transistors (i.e., the region where the semiconductor layer overlaps with the control electrode) as the channel region of the transistor, and processing the semiconductor layer in the region not shielded by the first conductive layer into a conductor-enhancing layer. The first region of the active pattern of the third transistor (which is also the second region of the active pattern of the fourth transistor and the second region of the active pattern of the fifth transistor) can serve as the first electrode T33 of the third transistor (which is also the second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor), and the second region of the active pattern of the third transistor (which is also the second region of the active pattern of the second transistor and the first region of the active pattern of the sixth transistor) can serve as the second electrode T34 of the third transistor (which is also the second electrode T24 of the second transistor and the first electrode T63 of the sixth transistor).

[0329] In an exemplary embodiment, the second scan signal line Gate2 and the reset signal line Reset can be designed with equal width or non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0330] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the third insulating film and the second conductive film using a patterning process to form a third insulating layer pattern and a second conductive layer pattern located on the third insulating layer, as shown in Figures 17 and 18. Figure 17 is a schematic diagram of the second conductive layer pattern, and Figure 18 is a schematic diagram after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0331] In an exemplary embodiment, the second conductive layer pattern includes at least: a second initial signal line INIT2, a plurality of spaced first initial connection portions CL1 of the first initial signal line, and a second plate C2 of a capacitor located in at least one first type pixel driving circuit.

[0332] In an exemplary embodiment, the main outline of the second plate C2 of the capacitor can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second plate C2 on the substrate at least partially overlaps with the orthographic projection of the first plate of the capacitor on the substrate. An opening K is provided on the second plate C2 of the capacitor. The opening K can be rectangular and can be located in the middle of the second plate C2, so that the second plate C2 of the capacitor forms a ring structure. The opening K exposes the third insulating layer covering the first plate of the capacitor, and the orthographic projection of the first plate on the substrate includes the orthographic projection of the opening on the substrate.

[0333] In an exemplary embodiment, the shape of the second initial signal line INIT2 can be a line shape in which the main body extends along the first direction D1.

[0334] In an exemplary embodiment, the orthographic projection of the second initial signal line INIT2 connected to the first type pixel driving circuit in the i-th row on the substrate at least partially overlaps with the orthographic projection of the third light-shielding portion of the i-th light-shielding structure on the substrate. The orthographic projection of the second initial signal line INIT2 connected to the first type pixel driving circuit in the i-th row on the substrate is located between the orthographic projection of the reset signal line connected to the first type pixel driving circuit in the i-th row on the substrate and the orthographic projection of the second scan signal line connected to the first type pixel driving circuit in the i-th row on the substrate.

[0335] In an exemplary embodiment, a plurality of first initial connection portions CL1, which are spaced apart, are arranged sequentially along a first direction D1, and the shape of the first initial connection portion CL1 can be a strip shape extending along the first direction D1.

[0336] In an exemplary embodiment, the orthographic projection of the first initial connection portion CL1, which is a plurality of spaced first initial signal lines connected to the first type pixel driving circuit in the i-th row, onto the substrate at least partially overlaps with the orthographic projection of the first light-shielding portion of the i-th light-shielding structure onto the substrate.

[0337] (5) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer pattern covering the second conductive layer. The fourth insulating layer pattern has a plurality of vias, as shown in FIG19, FIG19 being a schematic diagram after the fourth insulating layer pattern is formed.

[0338] In an exemplary embodiment, the fourth insulating layer pattern is provided with a plurality of vias, including at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0339] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the orthographic projection range of the first region of the active pattern of the first transistor onto the substrate. The third and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the active pattern of the first transistor. The first via V1 is configured to allow the second initial connection portion (which is also the first pole of the first transistor) of the subsequently formed first initial signal line to be connected to the first region of the active pattern of the first transistor through the via.

[0340] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the second region of the active pattern of the first transistor (which is also the first region of the active pattern of the second transistor) onto the substrate. The third insulating layer and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor (which is also the first region of the active pattern of the second transistor). The second via V2 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor) to be connected to the second region of the active pattern of the first transistor (which is also the first region of the active pattern of the second transistor) through the via.

[0341] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the orthographic projection of the first region of the active pattern of the fourth transistor onto the substrate. The third insulating layer and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor. The third via V3 is configured to allow the first data connection line (which is also the first pole of the fourth transistor) of the subsequently formed data signal line to be connected to the first region of the active pattern of the fourth transistor through the via.

[0342] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the orthographic projection of the first region of the active pattern of the fifth transistor onto the substrate. The third and second insulating layers within the fourth via V4 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor. The fourth via V4 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0343] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) onto the substrate. The third and second insulating layers within the fifth via V5 are etched away, exposing the surface of the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor). The fifth via V5 is configured to allow the second electrode of the subsequently formed sixth transistor (which is also the second electrode of the seventh transistor) to be connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through the via.

[0344] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the orthographic projection of the first region of the active pattern of the seventh transistor onto the substrate. The third and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor. The sixth via V6 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the first region of the active pattern of the seventh transistor through the via.

[0345] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is within the range of the orthographic projection of the first light-shielding portion of the light-shielding structure on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the seventh via V7 are etched away, exposing the surface of the first light-shielding portion of the light-shielding structure. The seventh via V7 is configured to allow the subsequently formed first light-shielding connection electrode to be connected to the first light-shielding portion of the light-shielding structure through the via.

[0346] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the third light-shielding portion of the light-shielding structure on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer in the eighth via V8 are etched away, exposing the surface of the third light-shielding portion of the light-shielding structure. The eighth via V8 is configured to allow the subsequently formed second light-shielding connection electrode to be connected to the third light-shielding portion of the light-shielding structure through the via.

[0347] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate is within the range of the orthogonal projection of the control electrode of the second transistor onto the substrate. The third insulating layer within the ninth via V9 is etched away, exposing the surface of the control electrode of the second transistor. The ninth via V9 is configured to allow the subsequently formed third scan signal line to be connected to the control electrode of the second transistor through the via.

[0348] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the opening onto the substrate. The third insulating layer within the tenth via V10 is etched away, exposing the surface of the first electrode plate of the capacitor (which is also the control electrode of the third transistor). The tenth via V10 is configured to allow the second electrode of the subsequently formed first transistor (which is also the first electrode of the second transistor) to be connected to the first electrode plate of the capacitor (which is also the control electrode of the third transistor) through the via.

[0349] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the control electrode of the fourth transistor onto the substrate. The third insulating layer within the eleventh via V11 is etched away, exposing the surface of the control electrode of the fourth transistor. The eleventh via V11 is configured to allow the subsequently formed first scan signal line to be connected to the control electrode of the fourth transistor through the via.

[0350] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the substrate is within the range of the orthogonal projection of the control electrode of the fifth transistor onto the substrate. The third insulating layer within the twelfth via V12 is etched away, exposing the surface of the control electrode of the fifth transistor. The twelfth via V12 is configured to allow the subsequently formed first light-emitting signal line to be connected to the control electrode of the fifth transistor through the via.

[0351] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the control electrode of the sixth transistor on the substrate. The third insulating layer within the thirteenth via V13 is etched away, exposing the surface of the control electrode of the sixth transistor. The thirteenth via V13 is configured to allow the subsequently formed second light-emitting signal line to be connected to the control electrode of the sixth transistor through the via.

[0352] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the first initial connection portion of the first initial signal line on the substrate. The fourteenth via V14 exposes the surface of the first initial connection portion of the first initial signal line. The fourteenth via V14 is configured to allow the second initial connection portion of the subsequently formed first initial signal line (which is also the first pole of the first transistor) to be connected to the first initial connection portion of the first initial signal line through the via.

[0353] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the second plate of the capacitor on the substrate. The fifteenth via V15 exposes the surface of the second plate of the capacitor. The fifteenth via V15 is configured to allow the first electrode of the subsequently formed fifth transistor to be connected to the second plate of the capacitor through the via.

[0354] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the second initial signal line on the substrate. The sixteenth via V16 exposes the surface of the second initial signal line. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed seventh transistor to be connected to the second initial signal line through the via.

[0355] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer pattern disposed on a fourth insulating layer, as shown in Figures 20 and 21. Figure 20 is a schematic diagram of the third conductive layer pattern, and Figure 21 is a schematic diagram after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0356] In an exemplary embodiment, the third conductive layer pattern may include at least: a first scan signal line Gate1, a third scan signal line Gate3, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a plurality of spaced second initial connection portions CL2 of the first initial signal line, a plurality of spaced first data connection lines Data1 of the data signal line, a first light-shielding connection electrode SC1, a second light-shielding connection electrode SC2, and a first electrode T13 of a first transistor, a second electrode T14 of a first transistor, a first electrode T23 of a second transistor, a first electrode T43 of a fourth transistor, a first electrode T53 of a fifth transistor, a second electrode T64 of a sixth transistor, and a first electrode T73 and a second electrode T74 of a seventh transistor located in at least one pixel driving circuit.

[0357] In an exemplary embodiment, the first scan signal line Gate1, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 are arranged sequentially along the second direction D2.

[0358] In an exemplary embodiment, the orthographic projections of the first scan signal line Gate1 and the third scan signal line Gate3 connected to the i-th row pixel driving circuit on the substrate are located on the side of the first plate of the capacitor of the i-th row pixel driving circuit away from the (i+1)-th row pixel driving circuit. The orthographic projections of the first light emission signal line EM1 and the second light emission signal line EM2 connected to the i-th row pixel driving circuit on the substrate are located on the side of the first plate of the capacitor of the i-th row pixel driving circuit closer to the (i+1)-th row pixel driving circuit.

[0359] In an exemplary embodiment, the orthographic projection of the second scan signal line on the substrate is located on the side where the orthographic projection of the first scan signal line Gate1 on the substrate is far from the orthographic projection of the third scan signal line Gate3 on the substrate. The orthographic projection of the reset signal line on the substrate is located on the side where the orthographic projection of the second light-emitting signal line EM2 on the substrate is far from the orthographic projection of the first light-emitting signal line EM1 on the substrate.

[0360] In an exemplary embodiment, a plurality of spaced second initial connection portions CL2 of the first initial signal line are arranged sequentially along the first direction D1, and their orthographic projections on the substrate alternate with the orthographic projections of the plurality of spaced first initial connection portions of the first initial signal line on the substrate. At least one first initial connection portion of the first initial signal line is connected to two adjacent second initial connection portions. The second initial connection portion CL2 can serve as the first electrode T13 of the first transistor.

[0361] In an exemplary embodiment, at least one second initial connection portion CL2 is electrically connected to the first region of the active pattern of the first transistor through a first via, and is electrically connected to the two connected first initial connection portions through a fourteenth via.

[0362] In an exemplary embodiment, the shape of the first scan signal line Gate1 can be a line shape in which the main body extends along the first direction D1. The first scan signal line Gate1 is connected to the control electrode of the fourth transistor through an eleventh via.

[0363] In an exemplary embodiment, the third scan signal line Gate3 can be a line shape in which the main body extends along the first direction D1. The third scan signal line Gate3 is connected to the control electrode of the second transistor through a ninth via.

[0364] In an exemplary embodiment, the shape of the first light-emitting signal line EM1 can be a line shape in which the main body extends along the first direction D1. The first light-emitting signal line EM1 is connected to the control electrode of the fifth transistor through the twelfth via.

[0365] In an exemplary embodiment, the shape of the second light-emitting signal line EM2 can be a line shape in which the main body extends along the first direction D1. The second light-emitting signal line EM2 is connected to the control electrode of the sixth transistor through a thirteenth via.

[0366] In an exemplary embodiment, the orthographic projection of at least one first light-shielding connection electrode SC1 on the substrate at least partially overlaps with the orthographic projection of the first light-shielding portion of at least one light-shielding structure on the substrate. The shape of the first light-shielding connection electrode SC1 may be a strip extending along the first direction D1. The first light-shielding connection electrode SC1 is connected to the first light-shielding portion of the light-shielding structure through a seventh through-hole.

[0367] In an exemplary embodiment, the orthographic projection of at least one second light-shielding connection electrode SC2 on the substrate at least partially overlaps with the orthographic projection of the third light-shielding portion of at least one light-shielding structure on the substrate. The shape of the second light-shielding connection electrode SC2 may be a strip extending along the first direction D1. The second light-shielding connection electrode SC2 is connected to the third light-shielding portion of the light-shielding structure through an eighth through-hole.

[0368] In an exemplary embodiment, the second electrode T14 of the first transistor and the first electrode T23 of the second transistor are integrally formed. The integral structure of the second electrode T14 and the first electrode T23 of the first transistor has a zigzag shape. The second electrode T14 of the first transistor (which is also the first electrode T23 of the second transistor) is connected to the second region of the active pattern of the first transistor (which is also the first region of the active pattern of the second transistor) through a second via, and is connected to the first plate of the capacitor (which is also the control electrode of the third transistor) through a tenth via.

[0369] In an exemplary embodiment, the first electrode T53 of the fifth transistor is provided separately. The first electrode T53 of the fifth transistor can be block-shaped. The first electrode T53 of the fifth transistor is connected to the second region of the active pattern of the fifth transistor through a fourth via, and is connected to the second plate of the capacitor through a fifteenth via.

[0370] In an exemplary embodiment, the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor are an integral structure. The shape of the integral structure of the second electrode T64 of the sixth transistor and the second electrode T74 of the seventh transistor extends along the first direction D1. The second electrode T64 of the sixth transistor (which is also the second electrode T74 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor (which is also the second region of the active pattern of the seventh transistor) through a fifth via.

[0371] In an exemplary embodiment, the first electrode T73 of the seventh transistor is provided separately. The shape of the first electrode T73 of the seventh transistor can be a strip extending along the first direction D1. The first electrode T73 of the seventh transistor is connected to the first region of the active pattern of the seventh transistor through a sixth via, and is connected to the second initial signal line through a sixteen-via.

[0372] In an exemplary embodiment, at least one first data connection line Data1 of the data signal line is electrically connected to a pixel driving circuit. A plurality of spaced-apart first data connection lines Data1 are arranged sequentially along a second direction D2. At least a portion of the first data connection lines Data1 extends along the second direction D2. The first data connection lines Data1 can serve as the first electrode T43 of a fourth transistor. At least one first data connection line of the data signal line (which is also the first electrode of the fourth transistor) is connected to a first region of the active pattern of the fourth transistor via a third via.

[0373] In an exemplary embodiment, a first type of pixel driving circuit located on at least one pixel island includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit. The first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit located on the same pixel island are arranged sequentially along a first direction D1.

[0374] In an exemplary embodiment, for the same sub-pixel, the first data connection line Data1-1 of the data signal line connected to the first pixel driving circuit and the first data connection line Data1-3 of the data signal line connected to the third pixel driving circuit are located on both sides of the first data connection line Data1-2 of the data signal line connected to the second pixel driving circuit.

[0375] In an exemplary embodiment, the first data connection line Data1-2 of the data signal line connected to the second pixel driving circuit is a strip extending along the second direction D2.

[0376] In an exemplary embodiment, the orthographic projection of the first data connection line Data1-2 of the data signal line connected to the second pixel driving circuit of the (i+1)th row on the substrate at least partially overlaps with the orthographic projection of the third light-shielding part of the i-th light-shielding structure, the first light-shielding part of the (i+1)th light-shielding structure, and at least one light-shielding connection part of the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)th light-shielding structure on the substrate.

[0377] In an exemplary embodiment, the first data connection line Data1-1 of the data signal line connected to the first pixel driving circuit includes: a first connection part 31, a second connection part 32 and a third connection part 33.

[0378] In an exemplary embodiment, the first connection portion 31 and the third connection portion 33 are located on the side of the second connection portion 32 away from the data signal line Data1-2 connected to the second pixel driving circuit, and are arranged along the second direction D2. The second connection portion 32 is connected to the first connection portion 31 and the third connection portion 33 respectively, and at least one of the first connection portion 31 and the third connection portion 33 extends at least partially along the first direction D1, and the second connection portion 32 extends at least partially along the second direction D2.

[0379] In an exemplary embodiment, for the first data connection line of the data signal line connected to the first pixel driving circuit in the (i+1)th row, the orthographic projection of the first connection portion 31 on the substrate at least partially overlaps with the orthographic projection of the third light-shielding portion of the i-th light-shielding structure on the substrate, the orthographic projection of the second connection portion 32 on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection portion in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate, and the orthographic projection of the third connection portion 33 on the substrate at least partially overlaps with the orthographic projection of the first light-shielding portion of the (i+1)-th light-shielding structure on the substrate.

[0380] In an exemplary embodiment, the first data connection line Data1-3 of the data signal line connected to the third pixel driving circuit includes a fourth connection part 41, a fifth connection part 42, and a sixth connection part 43.

[0381] In an exemplary embodiment, the fourth connection portion 41 and the sixth connection portion 43 are located on the side of the fifth connection portion 42 away from the first data connection line Data1-2 of the data signal line connected to the second pixel driving circuit, and are arranged along the second direction D2. The fifth connection portion 42 is connected to the fourth connection portion 41 and the sixth connection portion 43 respectively, at least one of the fourth connection portion 41 and the sixth connection portion 43 extends at least partially along the first direction D1, and the fifth connection portion 42 extends at least partially along the second direction D2.

[0382] In an exemplary embodiment, for the first data connection line of the data signal line connected to the third pixel driving circuit in the (i+1)th row, the orthographic projection of the fourth connection portion 41 on the substrate at least partially overlaps with the orthographic projection of the third light-shielding portion of the i-th light-shielding structure on the substrate, the orthographic projection of the fifth connection portion 42 on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection portion in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate, and the orthographic projection of the sixth connection portion 43 on the substrate at least partially overlaps with the orthographic projection of the first light-shielding portion of the (i+1)-th light-shielding structure on the substrate.

[0383] In an exemplary embodiment, the first scan signal line Gate1, the third scan signal line Gate3, the first light emission signal line EM1, and the second light emission signal line EM2 can be designed with equal width or with non-equal width, and can be straight lines or broken lines. This not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This disclosure does not limit the scope of the invention.

[0384] (7) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and using a patterning process to pattern the first planarization film and the fifth insulating film to form a fifth insulating layer covering the third conductive layer pattern and a first planarization layer disposed on the fifth insulating layer. The first planarization layer is provided with a plurality of vias, as shown in FIG22, FIG22 being a schematic diagram after the formation of the first planarization layer pattern.

[0385] In an exemplary embodiment, the plurality of vias on the first planarization layer pattern include at least: seventeenth via V17 to twenty-first via V21.

[0386] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the range of the orthographic projection of the first data connection line of the data signal line (which is also the first electrode of the fourth transistor) onto the substrate. The fifth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the first data connection line of the data signal line (which is also the first electrode of the fourth transistor). The seventeenth via V17 is configured to connect the via to the first data connection line of the data signal line (which is also the first electrode of the fourth transistor) of the subsequently formed second data connection line of the data signal line.

[0387] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate. The fifth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the first electrode of the fifth transistor for the data signal line. The eighteenth via V18 is configured to connect the via to the first electrode of the fifth transistor for the subsequently formed first power line.

[0388] In an exemplary embodiment, the orthogonal projection of the nineteenth via V19 onto the substrate is within the range of the orthogonal projection of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) onto the substrate. The fifth insulating layer within the nineteenth via V19 is etched away, exposing the surface of the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor). The nineteenth via V19 is configured to connect the via to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) of the subsequently formed anode connection electrode.

[0389] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the substrate is within the range of the orthographic projection of the first light-shielding connection electrode on the substrate. The fifth insulating layer within the twentieth via V20 is etched away, exposing the surface of the first light-shielding connection electrode. The twentieth via V20 is configured to connect the via to the first light-shielding connection electrode for a subsequently formed first power connection line.

[0390] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the second light-shielding connection electrode on the substrate. The fifth insulating layer within the 21st via V21 is etched away, exposing the surface of the second light-shielding connection electrode. The 21st via V21 is configured to connect the via to the second light-shielding connection electrode for the subsequently formed first power connection line.

[0391] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern disposed on a fourth insulating layer, as shown in Figures 23 and 24. Figure 23 is a schematic diagram of the fourth conductive layer pattern, and Figure 24 is a schematic diagram after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0392] In an exemplary embodiment, the fourth conductive layer pattern includes at least: a plurality of spaced second data connection lines Data2, a first power line VDD, a first power connection line VL1, a second power connection line VL2, a power connection structure, and an anode connection electrode AL located in at least one pixel driving circuit.

[0393] In an exemplary embodiment, the anode connection electrode AL of at least one pixel driving circuit is connected to the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) through the nineteenth via.

[0394] In an exemplary embodiment, the anode connection electrode AL of at least one pixel driving circuit includes: a first anode connection electrode AL1 located in the first pixel driving circuit, a second anode connection electrode AL2 located in the second pixel driving circuit, and a third anode connection electrode AL3 located in the third pixel driving circuit.

[0395] In an exemplary embodiment, the first anode connecting electrode AL1 and the second anode connecting electrode AL2 are strip-shaped extending along the second direction D2.

[0396] In an exemplary embodiment, the third anode connecting electrode AL3 is in the shape of a strip that extends at least partially along the second direction D2.

[0397] In an exemplary embodiment, a plurality of spaced second data connection lines Data2 of the data signal line are arranged sequentially along the second direction D2, and their orthographic projections on the substrate are alternately arranged with the orthographic projections of the plurality of spaced first data connection lines of the data signal line on the substrate. At least one second data connection line of the data signal line is connected to two first data connection lines.

[0398] In an exemplary embodiment, the second data connection line Data2 of the data signal line can be a strip extending along the second direction D2, and is connected to two first data connection lines that are connected to the second data connection line Data2 of the data signal line through the seventeenth via.

[0399] In an exemplary embodiment, the first power lines VDD connected to the first type of pixel driving circuits located in the same column are spaced apart and arranged along the second direction D2, and the first power lines VDD connected to the first type of pixel driving circuits located in the same row are spaced apart and arranged along the first direction D1.

[0400] In an exemplary embodiment, the first power line VDD can be a strip extending along the second direction D2. The first power line VDD is connected to the first terminal of the fifth transistor through the eighteenth via.

[0401] In an exemplary embodiment, at least one of the first power connection line VL1 and the second power connection line VL2 extends along a first direction D1. The i-th first power connection line is connected to the first light-shielding connection electrode through a twentieth via, and the i-th second power connection line is connected to the second light-shielding connection electrode through a twenty-first via.

[0402] In an exemplary embodiment, the first ends of the plurality of first power lines VDD connected to the first type pixel driving circuit in the i-th row are electrically connected to the i-th first power connection line VL1(i), and the second ends of the plurality of first power lines VDD connected to the first type pixel driving circuit in the i-th row are electrically connected to the i-th second power connection line. A sixth opening K6 is formed between at least two adjacent first power lines VDD connected to the first type pixel driving circuit in the i-th row and the i-th first power connection line VL1(i) and the i-th second power connection line.

[0403] In an exemplary embodiment, the orthographic projection of the first power connection line and the first light-shielding part of the first light-shielding structure on the substrate at least partially overlaps, and the orthographic projection of the second power connection line and the third light-shielding part of the first light-shielding structure on the substrate at least partially overlaps.

[0404] In an exemplary embodiment, a second data connection line, consisting of at least one anode connection electrode and at least one data signal line, is located between first power lines connecting two adjacent pixel driving circuits in the same row.

[0405] In an exemplary embodiment, at least one power connection structure includes a plurality of spaced power connection portions VCL. At least one power connection portion in the power connection structure located between the i-th second power connection line and the i+1-th first power connection line is connected to the i-th second power connection line and the i+1-th first power connection line, respectively. A fifth opening K5 located in the light-transmitting area is formed between the i-th second power connection line VL2, the i+1-th first power connection line VL1, and at least two adjacent power connection portions VCL located between the i-th second power connection line and the i+1-th first power connection line.

[0406] In an exemplary embodiment, the orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the fifth opening K5 on the substrate.

[0407] In an exemplary embodiment, the orthographic projection of at least one power connection portion VCL in the power structure located between the i-th second power connection line and the (i+1)-th first power connection line on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection portion in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate.

[0408] In an exemplary embodiment, the center line of at least one power connection portion extending along the second direction D2 is located between the center lines of at least two first power lines extending along the second direction D2.

[0409] In an exemplary embodiment, the i-th second power connection line VL2 has a recessed portion H near the edge of the i-th first power connection line VL1, and the third anode connection electrode AL3 in the i-th row pixel driving circuit is at least partially located in the recessed portion H.

[0410] In an exemplary embodiment, at least one virtual straight line extending along the second direction D2 passes through the i-th second power connection line and the third anode connection electrode in the i-th row pixel driving circuit.

[0411] In an exemplary embodiment, the shape of the power connection portion VCL can be a strip extending along the second direction D2.

[0412] In an exemplary embodiment, the line width of the power connection portion VCL is greater than the line width of the first power line VDD.

[0413] (9) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering the pattern of the fourth conductive layer, wherein a plurality of vias are provided on the second planarization layer. Figure 25 is a schematic diagram after the formation of the second planarization layer pattern.

[0414] In an exemplary embodiment, the second planarization layer pattern may include at least: a twenty-second via V22, a twenty-third via V23, and a twenty-fourth via V24.

[0415] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the first anode connection electrode on the substrate, exposing the surface of the first anode connection electrode. The 22nd via V22 is configured to allow the anode of the subsequently formed first light-emitting device to be connected to the first anode connection electrode through the via.

[0416] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the second anode connection electrode on the substrate, exposing the surface of the second anode connection electrode. The 23rd via V23 is configured to allow the anode of the subsequently formed second light-emitting device to be connected to the second anode connection electrode through the via.

[0417] In an exemplary embodiment, the orthogonal projection of the 24th via V24 on the substrate is within the range of the orthogonal projection of the third anode connection electrode on the substrate, exposing the surface of the third anode connection electrode. The 24th via V24 is configured to allow the anode of the subsequently formed third light-emitting device to be connected to the third anode connection electrode through the via.

[0418] At this point, the driving circuit layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include: a first type of pixel driving circuit, which is connected to a reset signal line, a first scan signal line, a second scan signal line, a third scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial signal line, a data signal line, and a first power supply line. In a plane perpendicular to the display substrate, the driving circuit layer may be disposed on the substrate.

[0419] The driving circuit layer may include, sequentially disposed on a substrate, a light-shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planarization layer, a fourth conductive layer, and a second planarization layer. The light-shielding layer may include a light-shielding structure. The semiconductor layer may include at least one active pattern of a transistor. The first conductive layer may include at least one control electrode of a transistor, a first electrode of a capacitor, a second scan signal line, and a reset signal line. The second conductive layer may include at least a second electrode of a capacitor, a first initial connection portion of a first initial signal line, and a second initial signal line. The third conductive layer may include at least: first and second electrodes of multiple transistors, a first initial connection portion of the first initial signal line, a first data connection line of a data signal line, a first scan signal line, a third scan signal line, a first light-emitting signal line, and a third light-emitting signal line. The fourth conductive layer may include at least: a second data connection line of the data signal line, a first power line, a first power connection line, a second power connection line, a power connection electrode, and an anode connection electrode.

[0420] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0421] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0422] In an exemplary embodiment, the first, second, third, fourth, and fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer, the second and third insulating layers can be called gate insulating (GI) layers, the fourth insulating layer can be called an interlayer insulating (ILD) layer, and the fifth insulating layer can be called a passivation (PVX) layer.

[0423] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of organic materials, such as resin.

[0424] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0425] (10) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern includes: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern. Figure 26 is a schematic diagram of the anode conductive layer pattern, and Figure 27 is a schematic diagram after the anode conductive layer pattern is formed.

[0426] In an exemplary embodiment, the anode conductive layer pattern may include at least: anodes of a plurality of first-type light-emitting devices, the anodes of the plurality of first-type light-emitting devices including: a first anode AN1 of a first light-emitting device located on at least one pixel island, a second anode AN2 of a second light-emitting device, and a third anode AN3 of a third light-emitting device.

[0427] In an exemplary embodiment, the first anode AN1 and the second anode AN2 are arranged along the second direction D2, and are respectively arranged with the third anode AN3 along the first direction D1.

[0428] In an exemplary embodiment, the area of ​​the first anode AN1 is smaller than the area of ​​the second anode AN2.

[0429] In an exemplary embodiment, the area of ​​the third anode AN3 is greater than the area of ​​at least one of the first anode AN1 and the second anode AN2.

[0430] In an exemplary embodiment, the length of the third anode AN3 along the second direction D2 is greater than the sum of the lengths of the first anode AN1 along the second direction D2 and the second anode AN2 along the second direction D2.

[0431] In an exemplary embodiment, the distance between the second anode AN2 connected to the second pixel driving circuit in the i-th row and the first anode AN1 connected to the first pixel driving circuit in the (i+1)-th row along the second direction D2 is greater than the length of the second anode AN2 along the second direction D2.

[0432] In an exemplary embodiment, the first anode AN1 may include a first anode body portion and a first anode connecting portion connected to each other. The shape of the first anode body portion may be rectangular, and the corners of the rectangle may be provided with rounded chamfers. The shape of the first anode connecting portion may be strip-shaped, and the first anode connecting portion is connected to the first anode connecting electrode through a twenty-second through-hole. The orthographic projection of the first anode on the substrate is at least partially located within the orthographic projection range of the sixth opening on the substrate.

[0433] In an exemplary embodiment, the second anode AN2 may include a second anode body portion and a second anode connecting portion connected to each other. The shape of the second anode body portion may be rectangular, and the corners of the rectangle may be provided with rounded chamfers. The shape of the second anode connecting portion may be strip-shaped, and the second anode connecting portion is connected to the second anode connecting electrode through a twenty-third through-hole. At least a portion of the orthographic projection of the second anode AN2 on the substrate is located within the orthographic projection range of the sixth opening on the substrate.

[0434] In an exemplary embodiment, the sixth opening where the orthographic projection of the first anode connected to the adjacent first pixel driving circuits in the same row is located on the substrate, and the sixth opening where the orthographic projection of the second anode connected to the second pixel driving circuits on the substrate is located on the substrate, is the same opening.

[0435] In an exemplary embodiment, the third anode may include a third anode body portion and a third anode connecting portion connected to each other. The third anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers. The third anode connecting portion may be strip-shaped, and the third anode connecting portion is connected to the third anode connecting electrode through a twenty-fourth via. At least a portion of the orthographic projection of the third anode onto the substrate is located within the orthographic projection range of the sixth opening onto the substrate. The sixth opening where the orthographic projection of at least one of the first and second anodes located in the same sub-pixel is located is a different opening from the sixth opening where the orthographic projection of the third anode is located.

[0436] (11) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern includes: depositing a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer pattern that exposes the anode layer pattern. As shown in FIG28, FIG28 is a schematic diagram after forming the pixel definition layer pattern.

[0437] In an exemplary embodiment, the pixel definition layer pattern includes at least: a first anode opening AV1, a second anode opening AV2, and a third anode opening AV3.

[0438] In an exemplary embodiment, the orthographic projection of the first anode opening AV1 on the substrate is within the range of the orthographic projection of the first anode on the substrate, exposing the surface of the first anode. The first anode opening AV1 is configured to allow the organic light-emitting layer of the subsequently formed first light-emitting device to be connected to the first anode through the via.

[0439] In an exemplary embodiment, the orthographic projection of the second anode opening AV2 on the substrate is within the range of the orthographic projection of the second anode on the substrate, exposing the surface of the second anode. The second anode opening AV2 is configured to allow the organic light-emitting layer of the subsequently formed second light-emitting device to be connected to the second anode through the via.

[0440] In an exemplary embodiment, the orthographic projection of the third anode opening AV3 on the substrate is within the range of the orthographic projection of the third anode on the substrate, exposing the surface of the third anode. The third anode opening AV3 is configured to allow the organic light-emitting layer of the subsequently formed third light-emitting device to be connected to the third anode through the via.

[0441] In an exemplary embodiment, the length of the third anode opening AV3 along the second direction D2 is greater than the sum of the lengths of the first anode opening AV1 along the second direction D2 and the lengths of the second anode opening AV2 along the second direction D2.

[0442] In an exemplary embodiment, a plurality of first anode openings AV1 and a plurality of second anode openings AV2 are arranged along a second direction D2. The plurality of first anode openings AV1 and the plurality of second anode openings AV2 are alternately arranged.

[0443] In an exemplary embodiment, the distance between the second anode opening AV2 that exposes the second anode connected to the second anode in the i-th row of the second pixel driving circuit and the first anode opening AV1 that exposes the first anode connected to the first anode in the (i+1)-th row of the first pixel driving circuit along the second direction D2 is greater than the length of the second anode opening AV2 along the second direction D2.

[0444] (12) Forming a cathode conductive layer pattern. In an exemplary embodiment, forming a cathode conductive layer pattern includes: coating an organic light-emitting material on a substrate on which the aforementioned pattern is formed; patterning the organic light-emitting material using a patterning process to form an organic structure layer pattern; depositing a cathode conductive film on the substrate on which the organic material layer pattern is formed; and patterning the cathode conductive film using a patterning process to form a cathode conductive layer pattern. Figure 29 is a schematic diagram after the cathode conductive layer pattern is formed, and Figure 30 is a schematic diagram after the cathode conductive layer pattern is formed.

[0445] In an exemplary embodiment, the cathode conductive layer pattern includes at least: a cathode of at least one light-emitting device, and the cathode conductive layer is further provided with a plurality of cathode vias EV.

[0446] In an exemplary embodiment, the cathode of at least one light-emitting device includes: a first cathode EN1 of a first light-emitting device, a second cathode EN2 of a second light-emitting device, and a third cathode EN3 of a third light-emitting device. The cathodes of at least one light-emitting device are interconnected or can be disposed separately.

[0447] In an exemplary embodiment, the orthographic projection of at least one cathode via on the substrate is located within the orthographic projection range of one of the first and fifth openings on the substrate.

[0448] In an exemplary embodiment, the organic structure layer pattern may include at least: an organic light-emitting layer of a light-emitting device.

[0449] In an exemplary embodiment, the anode conductive layer may be made of a transparent conductive material, such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO).

[0450] In an exemplary embodiment, the cathode conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or conductive alloy materials such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0451] In an exemplary embodiment, the display device may further include an encapsulation structure layer and a touch structure layer located on the side of the light-emitting structure layer away from the substrate.

[0452] In an exemplary embodiment, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0453] In an exemplary embodiment, the touch structure layer may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0454] This disclosure also provides a display device. Figure 31 is a schematic diagram of the structure of the display device provided in this disclosure. As shown in Figure 31, the display device includes: the display substrate 100 provided in any of the foregoing embodiments; the implementation principle and effects will not be repeated here.

[0455] In an exemplary embodiment, the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0456] In an exemplary embodiment, as shown in FIG31, the display device may further include: a sensor 200, the sensor 200 being located on the non-light-emitting side of the display substrate 100, and the orthographic projection of the sensor 200 on the substrate being at least partially located on the orthographic projection of the first display area on the substrate. Exemplarily, the sensor 200 may be located within the first display area A1.

[0457] In an exemplary embodiment, the sensor may be a camera located on the non-light-emitting side of the display substrate, and the orthographic projection of the camera onto the substrate is at least partially located on the orthographic projection of the first display area onto the substrate. Exemplarily, the camera may be located within the first display area.

[0458] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0459] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0460] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The display area includes a first display area and a second display area, wherein the second display area at least partially surrounds the first display area, and the first display area includes a plurality of pixel island areas and a plurality of light-transmitting areas distributed between the pixel island areas. A plurality of first-type sub-pixels are located in the first display area. At least one of the plurality of first-type sub-pixels includes a first-type pixel driving circuit and a first-type light-emitting device. The first-type pixel driving circuit is configured to drive the first-type light-emitting device to emit light. The plurality of first-type sub-pixels constitute a plurality of pixel islands. Each pixel island is located in one of the plurality of pixel island areas, and each pixel island includes at least two first-type sub-pixels. The spacing between adjacent pixel islands along the first direction is smaller than the spacing between adjacent pixel islands along the second direction, and the first direction and the second direction intersect. A plurality of second-type sub-pixels are located in the second display area. At least one of the plurality of second-type sub-pixels includes a second-type pixel driving circuit and a second-type light-emitting device. The second-type pixel driving circuit is configured to drive the second-type light-emitting device to emit light.

2. The display substrate according to claim 1, wherein, The spacing between adjacent pixel islands along the first direction is equal to the spacing between two adjacent first-type pixel driving circuits within the pixel island along the first direction.

3. The display substrate according to claim 1, wherein, The first type of pixel driving circuit includes: a capacitor and a driving transistor, wherein the capacitor includes a first plate and a second plate, and the first plate is connected to the control electrode of the driving transistor; The maximum length of the first plate of the capacitor in the first type of pixel driving circuit along the second direction is less than the spacing between adjacent pixel islands along the second direction, but greater than the spacing between adjacent pixel islands along the first direction.

4. The display substrate according to claim 1, comprising: A substrate and a light-emitting structure layer disposed on the substrate, wherein a first type of light-emitting device is disposed on the light-emitting structure layer, the first type of light-emitting device includes: a first light-emitting device, a second light-emitting device and a third light-emitting device, the first type of light-emitting device includes: an anode, and the light-emitting structure layer includes: an anode conductive layer disposed on the substrate; The anode conductive layer includes: a first anode of a first light-emitting device, a second anode of a second light-emitting device, and a third anode of a third light-emitting device; The first anode and the second anode are arranged along the second direction, and are respectively arranged with the third anode along the first direction; The area of ​​the first anode is smaller than the area of ​​the second anode, and the area of ​​the third anode is larger than the area of ​​at least one of the first anode and the second anode.

5. The display substrate according to claim 4, wherein, The length of the third anode along the second direction is greater than the sum of the length of the first anode along the second direction and the length of the second anode along the second direction; The distance between the second anode connected to at least one first-type pixel driving circuit in the i-th row and the first anode connected to at least one first-type pixel driving circuit in the (i+1)-th row along the second direction is greater than the length of at least one second anode along the second direction.

6. The display substrate according to claim 4, wherein, The light-emitting structure layer further includes a pixel definition layer located on the side of the anode conductive layer away from the substrate, the pixel definition layer including a first anode opening exposing the first anode, a second anode opening exposing the second anode, and a third anode opening exposing the third anode; The first type of pixel driving circuit includes: a first pixel driving circuit, a second pixel driving circuit and a third pixel driving circuit, wherein the first pixel driving circuit is electrically connected to the first anode, the second pixel driving circuit is electrically connected to the second anode, and the third pixel driving circuit is electrically connected to the third anode. The length of the third anode opening along the second direction is greater than the sum of the length of the first anode opening along the second direction and the length of the second anode opening along the second direction; The distance between the second anode opening of the second anode connected to the second anode of the i-th row second pixel driving circuit and the first anode opening of the first anode connected to the first anode of the (i+1)-th row first pixel driving circuit along the second direction is greater than the length of at least one second anode opening along the second direction.

7. The display substrate according to claim 6, further comprising: The driving circuit layer located on the side of the light-emitting structure layer near the substrate includes: a light-shielding layer disposed on the substrate, the light-shielding layer including: a plurality of light-shielding structures arranged along the second direction and a light-shielding connection structure located between at least two adjacent light-shielding structures; The i-th light-shielding connection structure is connected to the i-th light-shielding structure and the (i+1)-th light-shielding structure respectively, 1≤i≤M, where M is the total number of rows of the pixel driving circuit; At least one of the plurality of light-shielding structures has its orthographic projection on the substrate at least partially overlaps with the orthographic projection on the substrate of the active pattern of at least one transistor in at least one first-type pixel driving circuit.

8. The display substrate according to claim 7, wherein, The at least one light-shielding structure includes: a first light-shielding part, a third light-shielding part, and a plurality of second light-shielding parts arranged along the first direction between the first light-shielding part and the third light-shielding part; at least one of the first light-shielding part and the third light-shielding part extends at least partially along the first direction; The first light-shielding part of the i-th light-shielding structure is located on the side of the third light-shielding part of the i-th light-shielding structure away from the (i+1)-th light-shielding structure, and at least two adjacent second light-shielding parts in the same light-shielding structure are interconnected.

9. The display substrate according to claim 8, wherein, A second opening is formed between at least two adjacent second light-shielding parts and a first light-shielding part located in the same light-shielding structure; a third opening is formed between at least two adjacent second light-shielding parts and a third light-shielding part located in the same light-shielding structure; and a fourth opening is provided on the second light-shielding part. The area of ​​the fourth opening is smaller than the area of ​​either the second opening or the third opening.

10. The display substrate according to claim 9, wherein, The at least one of the light-shielding connection structures includes: a plurality of light-shielding connection portions arranged along the first direction, wherein at least one of the plurality of light-shielding connection portions extends along the second direction, and adjacent light-shielding connection portions are spaced apart. At least two adjacent light-shielding connection parts in the i-th light-shielding connection structure are respectively connected to the third light-shielding part in the i-th light-shielding structure and the first light-shielding part in the (i+1)-th light-shielding structure, and a first opening is formed between them and the third light-shielding part in the i-th light-shielding structure and the first light-shielding part in the (i+1)-th light-shielding structure. The area of ​​the first opening is greater than the area of ​​either the second opening or the third opening.

11. The display substrate according to claim 10, wherein, The length of at least one of the light-shielding connecting portions along the second direction is greater than the length of at least one of the first and third light-shielding portions in the light-shielding structure along the second direction.

12. The display substrate according to claim 10, wherein, The driving structure layer further includes: a semiconductor layer disposed on the side of the light-shielding layer away from the substrate; the first type of pixel driving circuit includes: at least one transistor, the at least one transistor including: an active pattern, a control electrode, a first electrode, and a second electrode; The semiconductor layer includes: an active pattern of at least one transistor; The orthographic projection of the i-th light-shielding structure on the substrate at least partially overlaps with the orthographic projection of the active pattern of the at least one transistor in the i-th row of the first type pixel driving circuit on the substrate.

13. The display substrate according to claim 12, wherein, The at least one transistor includes: a first transistor to a seventh transistor; The orthographic projection of the first light-shielding part of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of a portion of the active pattern of the first transistor in the i-th row of the first type pixel driving circuit onto the substrate; The orthographic projection of the second light-shielding part of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projections of the active pattern of the first transistor in the i-th row of the first type pixel driving circuit and the active patterns of the second transistor to the sixth transistor onto the substrate. The orthographic projection of the third light-shielding part of the i-th light-shielding structure onto the substrate at least partially overlaps with the orthographic projection of the active pattern of the seventh transistor in the i-th row of the first type pixel driving circuit onto the substrate.

14. The display substrate according to claim 12, further comprising: The capacitor comprises multiple first scan signal lines, multiple second scan signal lines, multiple third scan signal lines, multiple reset signal lines, multiple second initial signal lines, multiple first light-emitting signal lines, and multiple second light-emitting signal lines, and the capacitor includes: a first electrode and a second electrode. At least one of the plurality of second scan signal lines, the plurality of reset signal lines, the plurality of second initial signal lines, the plurality of first scan signal lines, the plurality of third scan signal lines, the plurality of first light emission signal lines, and the plurality of second light emission signal lines extends at least partially along the first direction; The driving structure layer further includes: a first conductive layer, a second conductive layer and a third conductive layer, wherein the first conductive layer is located on the side of the semiconductor layer away from the substrate, the second conductive layer is located on the side of the first conductive layer away from the substrate, and the third conductive layer is located on the side of the second conductive layer away from the substrate; The first conductive layer includes at least: the plurality of second scan signal lines, the plurality of reset signal lines, and the control electrode of at least one transistor located in at least one first type pixel driving circuit and the first plate of the capacitor; The second conductive layer includes at least: the plurality of second initial signal lines and the second plate of the capacitor located in at least one of the first type pixel driving circuits; The third conductive layer includes at least: the plurality of first scan signal lines, the plurality of third scan signal lines, the plurality of first light emission signal lines, the plurality of second light emission signal lines, and the first and second electrodes of the at least one transistor located in at least one first type pixel driving circuit.

15. The display substrate according to claim 14, wherein, At least one of the reset signal lines and the second initial signal lines connected to the first type pixel driving circuit in the i-th row, when projected onto the substrate, at least partially overlaps with the projected onto the substrate of the third light-shielding part in the i-th light-shielding structure. The orthographic projections of the second scan signal line connected to the first type pixel driving circuit in the i-th row, the first scan signal line connected to the first type pixel driving circuit in the i-th row, the third scan signal line connected to the first type pixel driving circuit in the i-th row, the first light emission signal line connected to the first type pixel driving circuit in the i-th row, the second light emission signal line connected to the first type pixel driving circuit in the i-th row, the second initial signal line connected to the first type pixel driving circuit in the i-th row, and the reset signal line connected to the first type pixel driving circuit in the i-th row are arranged sequentially along the second direction.

16. The display substrate according to claim 15, further comprising: Multiple first initial signal lines, at least one of the multiple first initial signal lines includes: multiple spaced first initial connection portions and multiple spaced second initial connection portions; At least one of the first initial connection portion and the second initial connection portion extends at least partially along the first direction, the plurality of spaced first initial connection portions of the first initial signal line are arranged sequentially along the first direction, and the plurality of spaced second initial connection portions of the first initial signal line are arranged sequentially along the first direction; The orthographic projections of the plurality of spaced second initial connection portions of the first initial signal line on the substrate are alternately arranged with the orthographic projections of the plurality of spaced first initial connection portions of the first initial signal line on the substrate, and at least one first initial connection portion of the first initial signal line is connected to two second initial connection portions.

17. The display substrate according to claim 16, wherein, The first initial connection portion is located in the second conductive layer, and the second initial connection portion is located in the third conductive layer.

18. The display substrate according to claim 16, wherein, The orthographic projection of the first initial signal line connected to the first type pixel driving circuit in the i-th row on the substrate and the orthographic projection of the second scan signal line connected to the first type pixel driving circuit in the i-th row on the substrate on the side away from the orthographic projection of the first scan signal line connected to the first type pixel driving circuit in the i-th row on the substrate. The orthographic projection of the first initial signal line connected to the first type pixel driving circuit in the i-th row on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part of the i-th light-shielding structure on the substrate.

19. The display substrate according to claim 16, further comprising: Multiple data signal lines, wherein at least one of the multiple data signal lines includes: multiple spaced first data connection lines and multiple spaced second data connection lines; At least one of the first data connection line and the second data connection line extends at least partially along the second direction, the plurality of spaced first data connection lines of the plurality of data signal lines are arranged sequentially along the second direction, and the plurality of spaced second data connection lines of the plurality of data signal lines are arranged sequentially along the second direction; The orthographic projections of the plurality of spaced first data connection lines on the substrate and the orthographic projections of the plurality of spaced second data connection lines on the substrate are arranged alternately, and at least one second data connection line is connected to two first data connection lines.

20. The display substrate according to claim 19, wherein, The first type of pixel driving circuit for at least one pixel island includes: a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit. For the same pixel island, the first data connection line of the data signal line connected by the first pixel driving circuit and the first data connection line of the data signal line connected by the third pixel driving circuit are respectively located on opposite sides of the first data connection line of the data signal line connected by the second pixel driving circuit. The first data connection line of the data signal line connected to the second pixel driving circuit extends along the second direction, and the orthographic projection of the first data connection line of the data signal line connected to the second pixel driving circuit in the (i+1)th row on the substrate at least partially overlaps with the orthographic projection of at least one of the third light-shielding part of the i-th light-shielding structure, the first light-shielding part of the (i+1)th light-shielding structure, and the light-shielding connection part located between the i-th light-shielding structure and the (i+1)th light-shielding structure on the substrate. The first data connection line of the data signal line connected to the first pixel driving circuit includes: a first connection portion, a second connection portion and a third connection portion. The first connection portion and the third connection portion are located on the side of the first data connection line away from the second connection portion and the data signal line connected to the second pixel driving circuit, and are arranged along the second direction. The second connection portion is connected to the first connection portion and the third connection portion respectively. At least one of the first connection portion and the third connection portion extends at least partially along the first direction, and the second connection portion extends at least partially along the second direction. For the first data connection line of the data signal line connected to the first pixel driving circuit in the (i+1)th row, the orthographic projection of the first connection part on the substrate at least partially overlaps with the orthographic projection of the third light-shielding part of the i-th light-shielding structure on the substrate; the orthographic projection of the second connection part on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection part in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate; the orthographic projection of the third connection part on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part of the (i+1)-th light-shielding structure on the substrate. The first data connection line of the data signal line connected to the third pixel driving circuit includes: a fourth connection part, a fifth connection part, and a sixth connection part. The fourth connection part and the sixth connection part are located on the side of the first data connection line away from the fifth connection part away from the data signal line connected to the second pixel driving circuit, and are arranged along the second direction. The fifth connection part is connected to the fourth connection part and the sixth connection part respectively. At least one of the fourth connection part and the sixth connection part extends at least partially along the first direction, and the fifth connection part extends at least partially along the second direction. For the first data connection line of the data signal line connected to the third pixel driving circuit in the (i+1)th row, the orthographic projection of the fourth connection part on the substrate at least partially overlaps with the orthographic projection of the third light-shielding part of the i-th light-shielding structure on the substrate; the orthographic projection of the fifth connection part on the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection part in the light-shielding connection structure located between the i-th light-shielding structure and the (i+1)-th light-shielding structure on the substrate; and the orthographic projection of the sixth connection part on the substrate at least partially overlaps with the orthographic projection of the first light-shielding part of the (i+1)-th light-shielding structure on the substrate.

21. The display substrate according to claim 19, wherein, The driving structure layer further includes: a fourth conductive layer, the fourth conductive layer being located on the side of the third conductive layer away from the substrate; The first data connection line is located in the third conductive layer, and the second data connection line is located in the fourth conductive layer.

22. The display substrate according to claim 21, further comprising: Multiple first power lines, multiple first power connection lines, and multiple second power connection lines, wherein at least one of the multiple first power connection lines is connected to a first light-shielding part of at least one of the multiple light-shielding structures, and at least one of the multiple second power connection lines is connected to a third light-shielding part of at least one of the multiple light-shielding structures. The first power line extends along the second direction, and at least one of the first power connection line and the second power connection line extends along the first direction. The first power lines of adjacent first-type pixel driving circuits in the same column are spaced apart and arranged along the second direction; the first power lines of adjacent first-type pixel driving circuits in the same row are spaced apart and arranged along the first direction. The first end of the first power line connected to the first type pixel driving circuit in the i-th row is electrically connected to the first power line connected to the i-th first power line, and the second end of the first power line connected to the first type pixel driving circuit in the i-th row is electrically connected to the i-th second power line connected to the second power line. The first power connection line and the first light-shielding part of the first light-shielding structure at least partially overlap on the substrate, and the second power connection line and the third light-shielding part of the first light-shielding structure at least partially overlap on the substrate.

23. The display substrate according to claim 22, wherein, The plurality of first power lines, the plurality of first power connection lines, and the plurality of second power connection lines are located in the fourth conductive layer.

24. The display substrate according to claim 21, further comprising: Multiple power connection structures, wherein the i-th power connection structure is connected to the i-th second power connection line and the i+1-th first power connection line respectively, and is located between the i-th second power connection line and the i+1-th first power connection line; At least one of the plurality of power connection structures includes a plurality of spaced power connection portions, the power connection portions extending along the second direction and located in the fourth conductive layer; At least one power connection portion in the i-th power connection structure is connected to the i-th second power connection line and the i+1-th first power connection line respectively, and a fifth opening is formed between the i-th second power connection line, the i+1-th first power connection line and at least two adjacent power connection portions of the i-th power connection structure.

25. The display substrate according to claim 24, wherein, The orthographic projection of at least one power connection portion in the i-th power connection structure onto the substrate at least partially overlaps with the orthographic projection of at least one light-shielding connection portion in the light-shielding connection structure located between the i-th and i+1-th light-shielding structures onto the substrate. At least one power connection portion has its center line extending along the second direction located between the center lines of at least two of the plurality of first power lines extending along the second direction.

26. The display substrate according to claim 22, wherein, The i-th second power connection line has a recessed portion near the edge of the i-th first power connection line.

27. The display substrate according to claim 26, further comprising: A third anode connection electrode is connected to the third pixel driving circuit and the third anode respectively, and the third anode connection electrode is located in the fourth conductive layer; The third anode connection electrode extends at least partially along the second direction, and the third anode connection electrode in the i-th row pixel driving circuit is at least partially located in the recess of the i-th second power connection line.

28. The display substrate according to claim 24, wherein, At least one of the multiple spaced power connection portions has a line width greater than the line width of at least one of the multiple first power lines.

29. The display substrate according to claim 24, wherein, The light-emitting structure layer further includes: a cathode conductive layer located on the side of the anode conductive layer away from the substrate, wherein the cathode conductive layer is provided with a plurality of cathode vias; At least one of the plurality of cathode vias has its orthographic projection on the substrate located within the range of the orthographic projections of at least one of the first opening and the fifth opening on the substrate.

30. A display substrate, comprising: The display area includes at least a first display area and a second display area, wherein the second display area at least partially surrounds the first display area, and the first display area includes a plurality of pixel island areas and a plurality of light-transmitting areas distributed between the pixel island areas. A plurality of first-type sub-pixels are located in the first display area. At least one of the plurality of first-type sub-pixels includes a first-type pixel driving circuit and a first-type light-emitting device. The first-type pixel driving circuit is configured to drive the first-type light-emitting device to emit light. The plurality of first-type sub-pixels constitute a plurality of pixel islands. Each pixel island is located in one of the plurality of pixel island areas, and each pixel island includes at least two first-type sub-pixels. A plurality of second-type sub-pixels are located in the second display area. At least one of the plurality of second-type sub-pixels includes a second-type pixel driving circuit and a second-type light-emitting device. The second-type pixel driving circuit is configured to drive the second-type light-emitting device to emit light. The spacing between adjacent pixel islands along the first direction is less than the maximum length of the light-transmitting area between adjacent pixel islands along the second direction, and the spacing between adjacent second-type pixel driving circuits along the second direction is less than the spacing between adjacent pixel islands along the second direction.

31. The display substrate according to claim 30, wherein, The area of ​​the first type of pixel driving circuit located in the first display area is smaller than the area of ​​the second type of pixel driving circuit located in the second display area.

32. The display substrate according to claim 30, wherein, The display substrate includes a substrate and a driving circuit layer and a light-emitting structure layer disposed on the substrate. The light-emitting structure layer includes a cathode conductive layer and a plurality of cathode vias. The driving circuit layer includes at least one conductive layer. At least one of the plurality of cathode vias has an orthographic projection on the substrate that does not overlap with the orthographic projection of the at least one conductive layer on the substrate.

33. A display device, comprising: The display substrate as described in any one of claims 1 to 32.

34. The display device according to claim 33, further comprising: A sensor located on the non-light-emitting side of the display substrate, wherein the orthographic projection of the sensor on the substrate is at least partially located on the orthographic projection of the first display area on the substrate.

35. The display device according to claim 33, further comprising: A camera is located on the non-light-emitting side of the display substrate, and the orthographic projection of the camera on the substrate is at least partially located on the orthographic projection of the first display area on the substrate.

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