Interposer connection structure based on wire bonding

Abstract

In one aspect, an integrated circuit (IC) package includes: a base structure; an IC component disposed on the base structure; a plurality of interposer connection structures disposed on the base structure; and an interposer structure disposed over the IC component and the plurality of interposer connection structures. The plurality of interposer connection structures are configured to connect the base structure and the interposer structure. Each of the plurality of interposer connection structures includes a bond ball portion connected to the base structure, and a bond wire portion coupled to the bond ball portion and extending toward the interposer structure. A width of the bonding ball portion is greater than a width of the bonding wire portion.

Description

Intermediate layer connection structure based on wire bonding Technical Field

[0001] This disclosure relates generally to an integrated circuit (IC) package, and more specifically to an IC package including an interposer interconnect structure formed based on a wire bonding process. Background Technology

[0002] IC technology has made significant strides in improving computing power through the miniaturization of electronic components. An IC chip or IC die may include a set of circuitry integrated thereon. In some embodiments, an IC device can be formed by incorporating and protecting one or more IC chips or dies within an IC package, wherein various power and signal nodes of the one or more IC chips are electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in one or more packaging substrates of the IC package. Unless otherwise stated, the term "substrate" in this disclosure refers to a packaging substrate used to encapsulate one or more IC chips, which is different from the semiconductor substrate used to form the IC chips.

[0003] Various packaging technologies are found in many electronic devices, including processors, servers, radio frequency (RF) ICs, and so on. Advanced packaging and processing technologies enable the realization of complex devices such as multi-die devices and system-on-a-chip (SoC) devices, which may include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., Wi-Fi, Bluetooth, and other communications), etc.

[0004] For example, a PoP (PoS) packaging method can correspond to vertically combining discrete logic components and / or memory chips or dies to reduce the size of IC devices. In some examples, the PoP packaging method can be used in conjunction with a molded embedded package (MEP) packaging method, which may be referred to as a molded embedded stacked package (MEP) packaging method. In some examples, in an IC package formed based on a PoP packaging method and / or a MEP packaging method, each chip can be mounted on a corresponding substrate, and an interposer can be used to couple different substrates to the chips mounted thereon.

[0005] In some examples, an interposer may be disposed above a package substrate, on which an IC component may be mounted. The interposer and the package substrate may be connected via multiple interposer connection structures. The horizontal dimension of the IC package may be determined based on the pitch of the multiple interposer connection structures and the count of the multiple interposer connection structures. Furthermore, the thickness of the IC component that can be placed between the interposer and the package substrate may be limited by the height of the multiple interposer connection structures. In some examples, there may be challenges in configuring the interposer connection structures with a reduced pitch to reduce the horizontal dimension of the IC package and an increased height to accommodate IC components with considerable thickness.

[0006] Therefore, there is a need for improved interposer connection structures for IC packages and their manufacturing methods to address the aforementioned issues. Summary of the Invention

[0007] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0008] In one aspect, an integrated circuit (IC) package includes: a base structure; an IC assembly disposed on the base structure; a plurality of interposer connection structures disposed on the base structure; and an interposer structure disposed above the IC assembly and the plurality of interposer connection structures, wherein the plurality of interposer connection structures are configured to connect the base structure and the interposer structure, and wherein each of the plurality of interposer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the interposer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

[0009] In one aspect, a method of manufacturing an integrated circuit (IC) package includes: disposing an IC component on a base structure; disposing a plurality of interposer connection structures on the base structure; and disposing an interposer structure above the IC component and the plurality of interposer connection structures, wherein the plurality of interposer connection structures are configured to connect the base structure and the interposer structure, and wherein each of the plurality of interposer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the interposer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

[0010] In one aspect, an electronic device includes an integrated circuit (IC) package comprising: a base structure; an IC assembly disposed on the base structure; a plurality of interposer connection structures disposed on the base structure; and an interposer structure disposed above the IC assembly and the plurality of interposer connection structures, wherein the plurality of interposer connection structures are configured to connect the base structure and the interposer structure, and wherein each of the plurality of interposer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the interposer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

[0011] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0012] The accompanying drawings are provided to help describe various aspects of this disclosure, and are provided for illustrative purposes only and not to limit the aspects.

[0013] Figure 1 is a cross-sectional view of an integrated circuit (IC) package according to various aspects of the present disclosure.

[0014] Figures 2A to 2D illustrate portions of examples of IC packages according to various aspects of this disclosure.

[0015] Figures 3A to 3F illustrate the structure at various stages of manufacturing an IC package according to various aspects of this disclosure.

[0016] Figures 4A to 4H illustrate the structure at various stages of manufacturing an IC package according to various aspects of this disclosure.

[0017] Figures 5A to 5F illustrate the structure at various stages of manufacturing an IC package according to various aspects of this disclosure.

[0018] Figures 6A to 6D illustrate the structure at various stages of manufacturing an IC package according to various aspects of this disclosure.

[0019] Figure 7 illustrates a method for manufacturing an IC package according to various aspects of this disclosure.

[0020] Figure 8 illustrates a mobile device according to various aspects of this disclosure.

[0021] Figure 9 illustrates various electronic devices that can be incorporated into an IC package as described herein, according to various aspects of this disclosure.

[0022] By convention, features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0023] Various aspects of this disclosure are provided in the following description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Furthermore, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0024] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0025] In some of the described example implementations, instances are identified where the various component structures and operational parts are derived from known conventional techniques and subsequently arranged according to one or more aspects. In such instances, the internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary aspects disclosed herein.

[0026] The terminology used herein is for descriptive purposes only and is not intended to be limiting. As used herein, the singular forms “a,” “some,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including” as used herein indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, terms such as “generally” and “overall” indicate that the examples provided are not intended to be limited to precise numerical values ​​or geometries and include normal variations due to manufacturing tolerances and variations, material variations, and other design considerations.

[0027] As described above, various aspects generally relate to an integrated circuit (IC) package including an interposer connection structure formed based on a wire bonding process. In some aspects, the wire bonding-based interposer connection structure may have a reduced pitch to reduce the horizontal dimensions of the IC package and / or increase the count per unit area of ​​the interposer connection structure. In some aspects, the wire bonding-based interposer connection structure may have a greater height-to-pitch ratio than other solutions (e.g., copper core balls or copper-plated pillars) to accommodate thicker IC components between the interposer structure and the base structure of the IC package. Furthermore, the wire bonding-based interposer connection structure may be less expensive to manufacture than other alternative implementations based on copper core balls or copper-plated pillars.

[0028] Figure 1 is a cross-sectional view of an IC package 100 according to various aspects of the present disclosure. In some aspects, Figure 1 is a simplified cross-sectional view of the IC package 100, and certain details and components of the IC package 100 may be simplified or omitted in Figure 1.

[0029] In some aspects, as shown in Figure 1, the IC package 100 may be based on a PoP (Programmable on Port) packaging method. The IC package 100 may include a first package portion 110 above a second package portion 130, wherein an interposer structure 150 couples the first package portion 110 to the second package portion 130.

[0030] The first package portion 110 may include a first base structure 112 (e.g., a package substrate) and a first package terminal 114 (e.g., a solder bump or copper pillar bump) electrically coupling the first base structure 112 to an interposer structure 150. In some aspects, the first package terminal 114 may also be configured to mechanically couple the first base structure 112 to the interposer structure 150. The first package portion 110 may include a first IC chip 120 mounted on the first base structure 112 via a first IC terminal 122 (e.g., a solder bump or copper pillar bump). In some aspects, the first package portion 110 may also include a first molding compound portion 118 disposed on the first base structure 112 and covering the first IC chip 120. In some aspects, the first molding compound portion 118 may surround only the first IC terminal 122 without covering the first IC chip 120. In some aspects, the first package portion 110 may not include the first molding compound portion 118. In some respects, the first IC terminal 122, the first molding compound portion 118, or both may be configured to mechanically couple the first IC chip 120 to the first base structure 112.

[0031] The second package portion 130 may include a second base structure 132 (e.g., a package substrate) and second package terminals 134 (e.g., solder bumps or copper pillar bumps) for electrically coupling the IC package 100 to an external component (such as a circuit board). The second package portion 130 may include a second IC chip 140 mounted on the second base structure 132 via second IC terminals 142 (e.g., solder bumps or copper pillar bumps). The second package portion 130 may include an interposer connection structure 136 electrically coupling the second base structure 132 to an interposer structure 150.

[0032] In some aspects, the second package portion 130 may further include a second molding compound portion 138 disposed on the second base structure 132 and covering the second IC chip 140. In some aspects, the second molding compound portion 138 may surround the interposer connection structure 136. In some aspects, the second molding compound portion 138 may only surround the second IC terminal 142 without covering the second IC chip 140 and / or without surrounding the interposer connection structure 136. In some aspects, the second package portion 130 may not include the second molding compound portion 138.

[0033] In some aspects, the second IC terminal 142, the second molding compound portion 138, or both may be configured to mechanically couple the second IC chip 140 to the second base structure 132. In some aspects, the interposer connection structure 136, the second molding compound portion 138, or both may be configured to mechanically couple the second base structure 132 to the interposer structure 150.

[0034] As used herein, the interposer structure 150 is configured to electrically couple base structures 112 and 132, and in some respects couples IC chips 120 and 140 via base structures 112 and 132 and additional components (e.g., other IC chips, active components such as discrete transistors or operational amplifiers, and / or passive components such as resistors, capacitors, and / or inductors) optionally formed on or embedded in base structures 112 and / or 132.

[0035] In some aspects, the interposer connection structure 136 may include copper core balls or copper-plated pillars. However, these specific implementation examples of the interposer connection structure 136 may not be suitable for meeting both pitch and height requirements of some applications.

[0036] It should be understood that the configurations and descriptions illustrated herein are merely for illustrating the various aspects disclosed herein. Therefore, the foregoing illustrative examples should not be construed as limiting the various aspects disclosed and claimed herein.

[0037] Figure 2A illustrates a portion of a first IC package example 200A according to various aspects of the present disclosure. As shown in Figure 2A, the first IC package example 200A may include a package portion 210 and an interposer structure 240. In some aspects, the package portion 210 may correspond to the second package portion 130 in Figure 1, and the interposer structure 240 may correspond to the interposer structure 150 in Figure 1. In some aspects, certain details and components of the first IC package example 200A may be simplified or omitted in Figure 2A.

[0038] As shown in FIG2A, the package portion 210 may include a base structure 212 and an IC assembly 220 disposed on the base structure 212. The IC assembly 220 may be mounted on the base structure 212 via IC terminals 222 (e.g., solder bumps or copper pillar bumps). Furthermore, the first IC package example 200A may include package terminals 214 (e.g., multiple solder bumps or copper pillar bumps) located below the base structure 212 and configured to connect the IC package 200A to external components (e.g., a circuit board). In some aspects, the base structure 212 may be a package substrate in which conductive structures are formed. In some aspects, the package substrate may be formed by attaching one or more patterned conductive layers to a substrate core, the substrate core including resin and reinforcing components (e.g., glass fibers) embedded therein. In some aspects, the package substrate may have a coreless configuration.

[0039] In some aspects, IC component 220 may be an IC chip, or it may be a component having its own packaging substrate and an IC chip mounted on the packaging substrate of the component. Furthermore, an interposer structure 240 may be disposed above IC component 220 and base structure 212. In some aspects, the interposer structure may include a package in which conductive structures are formed.

[0040] The first IC package example 200A also includes a plurality of interposer connection structures 230 disposed on a base structure 212. In some aspects, the plurality of interposer connection structures 230 may be configured to connect the base structure 212 and an interposer structure 240. In some aspects, as shown in the enlarged view of the example interposer connection structure 230, each of the plurality of interposer connection structures 230 may include a bonding ball portion 232 connected to the base structure 212, and a bonding line portion 234 coupled to the bonding ball portion 232 and extending toward the interposer structure 240. In some aspects, the lower end of each interposer connection structure may be connected to a corresponding conductive pad of the base structure 212, and the upper end of each interposer connection structure may be connected to a corresponding conductive pad of the interposer structure 240. In some aspects, each of the plurality of interposer connection structures 230 may further include connecting the upper end of the corresponding bonding line portion 234 to a solder portion 236 of the interposer structure 240.

[0041] In some aspects, the interposer connection structure 230 is formed based on a wire bonding process. In some aspects, the width W1 of the bonding ball portion 232 may be greater than the width W2 of the bonding wire portion 234. In some aspects, the bonding ball portion 232 and the bonding wire portion 234 of each of the plurality of interposer connection structures 230 may form a bonding wire post and may include metal. In some aspects, the metal includes copper, aluminum, gold, or combinations thereof.

[0042] In some aspects, the first IC package example 200A may also include a molding compound portion 216 that is located between the base structure 212 and the interposer structure 240 and at least surrounds a portion of the bonding ball portion 232 and the bonding line portion 234 of the plurality of interposer connection structures 230. In some aspects, the molding compound portion 216 may contact the upper surface of the base structure 212 and the lower surface of the interposer structure 240.

[0043] In some aspects, the multiple interposer connection structures 230 may have a pitch P equal to or less than 150 micrometers (µm). In some aspects, the multiple interposer connection structures 230 may have a pitch P ranging from 100µm to 150µm. In some aspects, the distance D between the upper surface of the base structure 212 and the lower surface of the interposer structure 240 may be greater than 200µm.

[0044] In some respects, compared to IC package 100, the plurality of interposer connection structures 230 in the first IC package example 200A can be fabricated based on a wire bonding process, which can have a tighter pitch and a greater distance between the base structure 212 and the interposer structure 240 compared to other alternative embodiments based on copper core balls or plated copper pillars. Therefore, the plurality of interposer connection structures 230 based on the wire bonding process can help reduce package size (e.g., horizontal dimension) and / or increase the number of interposer connection structures. Using the plurality of interposer connection structures 230 based on the wire bonding process, thicker IC components can be placed in IC packages with a low interposer connection pitch. Furthermore, the manufacturing cost of the wire bonding process-based interposer connection structures 230 can be lower than that of other alternative embodiments based on copper core balls or plated copper pillars.

[0045] Figure 2B illustrates a portion of a second IC package example 200B according to various aspects of the present disclosure. As shown in Figure 2B, the second IC package example 200B may include a package portion 250 and an interposer structure 260. In some aspects, the package portion 250 may correspond to the second package portion 130 in Figure 1, and the interposer structure 260 may correspond to the interposer structure 150 in Figure 1. In some aspects, certain details and components of the second IC package example 200B may be simplified or omitted in Figure 2B.

[0046] In some respects, the second IC package example 200B can be considered a variation of the first IC package example 200A. Therefore, components in FIG2B that are the same as or similar to those in FIG2A are given the same reference numerals or labels, and their detailed descriptions may be omitted.

[0047] As shown in Figure 2B, the package portion 250 may include a base structure 252 on which the IC component 220 may be disposed. In this example, the base structure 252 may include a redistribution layer, which may be a metallized structure and may be implemented using conductive structure layers that are finer and more complex than the conductive structure layers in the package substrate. In some aspects, the redistribution layer may be formed by constructing conductive structure layers by laminating and patterning conductive layers one after another. Furthermore, the interposer structure 260 may include the redistribution layer.

[0048] In some aspects, each of the plurality of interposer connection structures 230' may include at least the bonding post portion shown in the enlarged view of FIG. 2A, which may include a corresponding bonding ball portion 232 and a corresponding bonding line portion 234. In some aspects, the upper end of the corresponding bonding line portion of each of the plurality of interposer connection structures 230' may be connected to the interposer structure 260, because the conductive structure of the interposer structure 260 may be formed directly on the upper end of the bonding line portion. In some aspects, the second IC package example 200B may be used in a redistributed layer PoP packaging process.

[0049] In some aspects, compared to the first IC package example 200A, the interposer structure 260 including the redistribution layer can be formed directly on the upper end of the plurality of interposer connection structures 230', and the solder portion 236 can be omitted. In some aspects, the interposer structure 260 including the redistribution layer can allow even tighter pitch P than solder bonding examples (e.g., the first IC package example 200A having an interposer structure 240 including a package substrate and connected by solder portions 236). Therefore, the plurality of interposer connection structures 230' can have a pitch P equal to or less than 150µm or even equal to or less than 100µm. In some aspects, the distance D between the upper surface of the base structure 252 and the lower surface of the interposer structure 260 can be greater than 200µm.

[0050] Figure 2C illustrates a portion of a third IC package example 200C according to various aspects of the present disclosure. As shown in Figure 2C, the third IC package example 200C may include a package portion 270 and an interposer structure 260. In some aspects, the package portion 270 may correspond to the second package portion 130 in Figure 1, and the interposer structure 260 may correspond to the interposer structure 150 in Figure 1. In some aspects, certain details and components of the third IC package example 200C may be simplified or omitted in Figure 2C.

[0051] In some respects, the third IC package example 200C can be considered a variation of the first IC package example 200A and the second IC package example 200B. Therefore, components in FIG2C that are the same as or similar to those in FIG2A and FIG2B are given the same reference numerals or labels, and their detailed descriptions may be omitted.

[0052] As shown in Figure 2C, the package portion 270 may include a base structure 212 on which the IC component 220 may be disposed. In this example, the base structure 212 may be a package substrate in which conductive structures are formed. Compared to the first IC package example 200A, the interposer structure 260 of the third IC package example 200C may be a redistribution layer. In some aspects, the upper end of the corresponding bonding line portion of each of the plurality of interposer connection structures 230' may be connected to the interposer structure 260. In some aspects, the second IC package example 200B may be used in a MEP process with a redistribution layer on top.

[0053] In some aspects, compared to the first IC package example 200A, the interposer structure 260 including the redistribution layer can be directly formed on the upper end of the plurality of interposer connection structures 230', and the solder portion 236 can be omitted. In some aspects, the interposer structure 260 including the redistribution layer can allow even tighter pitch P, as described with reference to FIG. 2B. Therefore, the plurality of interposer connection structures 230' can have a pitch P equal to or less than 150µm or even equal to or less than 100µm. In some aspects, the distance D between the upper surface of the base structure 212 and the lower surface of the interposer structure 260 can be greater than 200µm.

[0054] Figure 2D illustrates a portion of a fourth IC package example 200D according to various aspects of the present disclosure. As shown in Figure 2D, the fourth IC package example 200D may include a package portion 280 and an interposer structure 240. In some aspects, the package portion 280 may correspond to the second package portion 130 in Figure 1, and the interposer structure 240 may correspond to the interposer structure 150 in Figure 1. In some aspects, certain details and components of the fourth IC package example 200D may be simplified or omitted in Figure 2D.

[0055] In some respects, the fourth IC package example 200D can be considered a variation of the first IC package example 200A. Therefore, components in FIG2D that are the same as or similar to those in FIG2A are given the same reference numerals or labels, and their detailed descriptions may be omitted.

[0056] As shown in Figure 2D, the package portion 280 may include a molding compound portion 218 that does not cover the upper surface of the IC component 220. The package portion 280 may also include a thermal interface material layer 282 between the upper surface of the IC component 220 and the interposer structure 240. In some aspects, a gap may exist between the molding compound portion 218 and the lower surface of the interposer structure 240 due to the insertion of the thermal interface material layer 282.

[0057] In some aspects, the thermal interface material layer 282 may include a material with a thermal conductivity equal to or greater than 3 W / mK. In some aspects, the thermal interface material layer 282 may include a material with a thermal conductivity in the range of 3 W / mK to 10 W / mK. In some aspects, the fourth IC package example 200D may be used in a MEP packaging process and may further reduce the pitch P and improve heat dissipation of the IC component 220.

[0058] In some aspects, the multiple interposer connection structures 230 may have a pitch P equal to or less than 150 µm. In some aspects, the multiple interposer connection structures 230 may have a pitch P ranging from 100 µm to 150 µm. In some aspects, the distance D between the upper surface of the base structure 212 and the lower surface of the interposer structure 240 may be greater than 200 µm.

[0059] In some aspects, the base structure 212 or base structure 252 in Figures 2A to 2D may be depicted as a non-limiting example. In some aspects, the base structure for any of the IC package examples 200A to 200D may include a package substrate, a redistribution layer, or a combination thereof. In some aspects, the interposer connection structures 230 or 230' in Figures 2A to 2D may reduce the horizontal dimension of the IC package or increase the count per unit area of ​​the interposer connection structures. In some aspects, the interposer connection structures 230 or 230' in Figures 2A to 2D may be manufactured based on a wire bonding process, which may be less expensive than processes based on copper core balls or copper-plated pillars.

[0060] In some respects, the interposer connection structure 230 or 230' in Figures 2A to 2D can be used to connect two substrates, two redistribution layers, or a substrate and a redistribution layer in MEP process, PoP packaging process, MEP-PoP process, redistribution layer PoP packaging process, side-by-side packaging process, die-to-wafer fusion packaging process, split die packaging process, multi-die packaging process, multi-chip module (MCM) packaging process, system-in-package (SiP) packaging process, or packaging process based on a combination of the above.

[0061] Figures 3A to 3F illustrate the structure of various stages in manufacturing an IC package (such as the first IC package example 200A in Figure 2A) according to various aspects of this disclosure. Components illustrated in Figures 3A to 3F that are the same as or similar to those in Figure 2A are given the same reference numerals, and their detailed descriptions may be omitted.

[0062] As shown in Figure 3A, structure 300A can be formed by mounting IC component 220 on base structure 212. In some aspects, IC component 220 can be mounted on base structure 212 via IC terminals 222 (e.g., solder bumps or copper pillar bumps). In some aspects, IC component 220 can be an IC chip, or an assembly having a packaging substrate and an IC chip mounted on the packaging substrate. In some aspects, base structure 212, as shown in Figure 3A, can be a packaging substrate. In some examples, base structure 212 can be a redistribution layer. In some aspects, base structure 212 at this stage can be in the form of a portion of a wafer, strip, or panel, on which one or more other base structures for one or more other IC packages are also provided. In some aspects, base structure 212 can be a separate base structure for forming an IC package.

[0063] As shown in Figure 3B, structure 300B can be formed based on forming a plurality of bonding posts 310 on the upper surface of base structure 212. The plurality of bonding posts 310 will form the basis for forming a plurality of intermediate layer connection structures 230 in a later stage. In some aspects, as shown in the enlarged view of the example bonding posts, each bonding post may include a bonding ball portion 232 connected to base structure 212, and a bonding line portion 234 coupled to the bonding ball portion 232 and extending upward. In some aspects, the lower end of each bonding post may be connected to a corresponding conductive pad of base structure 212. In some aspects, the width W1 of the bonding ball portion 232 may be greater than the width W2 of the bonding line portion 234. In some aspects, the plurality of bonding posts 310 may have a pitch P equal to or less than 150µm or equal to or less than 100µm. In some aspects, the pitch P may be in the range of 100µm to 150µm. In some aspects, the plurality of bonding posts 310 may be formed based on a wire bonding process utilizing bonding lines comprising metal. In some respects, the metal may include copper, aluminum, gold, or combinations thereof.

[0064] As shown in Figure 3C, structure 300C can be formed based on forming solder portions 236 on the lower surface of the interposer structure 240. In Figure 3C, the interposer structure 240 is depicted as being in an upside-down position compared to the interposer structure 240 depicted in Figure 2A. In some aspects, the solder portions 236 can be formed by paste-printing solder material onto the lower surface of the interposer structure 240.

[0065] As shown in Figure 3D, structure 300D can be formed by attaching structure 300C to structure 300B, wherein solder portion 236 can bond bonding posts 310 to interposer structure 240. The combination of solder portion 236 and bonding posts 310 can form multiple interposer connection structures 230. Therefore, interposer structure 240 can be disposed above IC component 220 and multiple interposer connection structures 230. Furthermore, the multiple interposer connection structures 230 can be configured to connect base structure 212 and interposer structure 240. In some aspects, the distance D between the upper surface of base structure 212 and the lower surface of interposer structure 240 can be greater than 200µm.

[0066] As shown in Figure 3E, structure 300E can be formed based on structure 300D by forming a molding compound portion 216 on base structure 212 and at least around a portion of the bonding ball portion and bonding line portion of the plurality of intermediate layer connection structures 230. In some aspects, the molding compound portion 216 may be in contact with the upper surface of base structure 212 and the lower surface of intermediate layer structure 240.

[0067] As shown in Figure 3F, structure 300F can be formed based on structure 300E by forming a plurality of package terminals 214 (e.g., a plurality of solder bumps or copper pillar bumps) under base structure 212, wherein the plurality of package terminals 214 are configured to connect the resulting IC package (e.g., first IC package example 200A) to external components (e.g., circuit board). Furthermore, since base structure 212 in Figures 3A to 3E is part of a wafer, strip, or panel, structure 300F may be further formed based on performing a dicing process to separate structure 300F from one or more other base structures for one or more other IC packages. In some aspects, structure 300F may correspond to first IC package example 200A.

[0068] Figures 4A to 4H illustrate the structures at various stages of manufacturing an IC package (such as the second IC package example 200B in Figure 2B) according to various aspects of this disclosure. Components illustrated in Figures 4A to 4H that are the same as or similar to those in Figure 2B are given the same reference numerals, and their detailed descriptions may be omitted.

[0069] As shown in Figure 4A, structure 400A can be formed by mounting IC component 220 on base structure 252. In some aspects, IC component 220 can be mounted on base structure 212 via IC terminals 222 (e.g., solder bumps or copper pillar bumps). In some aspects, IC component 220 can be an IC chip, or an assembly having a package substrate and an IC chip mounted on the package substrate. In some aspects, base structure 252, as shown in Figure 4A, can be a redistribution layer formed on carrier 402. In some examples, base structure 252 can be a package substrate. In some aspects, base structure 252 at this stage, together with carrier 402, can be in the form of part of a wafer, strip, or panel, on which one or more other base structures for one or more other IC packages are also provided. In some aspects, base structure 252 can be a separate base structure for forming an IC package.

[0070] As shown in Figure 4B, structure 400B can be formed based on the formation of a plurality of bonding posts 410 on the upper surface of base structure 252. The plurality of bonding posts 410 will form the basis for the formation of a plurality of intermediate layer connection structures 230' in a later stage. In some aspects, each of the plurality of bonding posts 410 may include a bonding ball portion 232 connected to base structure 252, and a bonding line portion 234 coupled to the bonding ball portion 232 and extending upward, as similarly illustrated with reference to Figure 3B. In some aspects, the plurality of bonding posts 410 may have a pitch P equal to or less than 150 µm. In some aspects, the pitch P may be equal to or less than 100 µm because the subsequently formed intermediate layer structure 260 may be a redistribution layer. In some aspects, the plurality of bonding posts 410 may be formed based on a wire bonding process utilizing bonding lines comprising metal. In some aspects, the metal may include copper, aluminum, gold, or combinations thereof.

[0071] As shown in Figure 4C, structure 400C can be formed based on structure 400B by forming a molding compound portion 420 on base structure 252 and covering IC component 220 and bonding post 410.

[0072] As shown in Figure 4D, structure 400D can be formed based on structure 400C by polishing the molding compound portion 420 to expose the upper end of the bonding line portion of the bonding post 410. In some aspects, the bonding post 410 may be a plurality of intermediate layer connection structures 230' having exposed upper ends, and the polished molding compound portion 420 may be a molding compound portion 216.

[0073] As shown in Figure 4E, structure 400E can be formed based on structure 400D by disposing an interposer structure 260 above IC component 220 and multiple interposer connection structures 230'. In some aspects, the interposer structure 260 may be a redistributed layer formed after polishing on the upper end of the molding compound portion 216 and the bonding line portion of the multiple interposer connection structures 230'. In some aspects, the distance D between the upper surface of base structure 252 and the lower surface of interposer structure 260 may be greater than 200µm.

[0074] As shown in Figure 4F, structure 400F can be formed based on structure 400E by forming another carrier 404 on intermediate layer structure 260 and removing the carrier 402 below base structure 252.

[0075] As shown in Figure 4G, structure 400G can be formed based on structure 400F by forming a plurality of package terminals 214 (e.g., a plurality of solder bumps or copper pillar bumps) under base structure 252, wherein the plurality of package terminals 214 are configured to connect the resulting IC package (e.g., second IC package example 200B) to external components (e.g., circuit board).

[0076] As shown in Figure 4H, structure 400H can be formed based on structure 400G by removing carrier 404. Furthermore, since the base structure 252 in Figures 4A to 4G is part of a wafer, strip, or panel, structure 400H can be further formed by performing a dicing process to separate structure 400H from one or more other base structures used for one or more other IC packages. In some aspects, structure 400H may correspond to a second IC package example 200B.

[0077] Figures 5A to 5F illustrate the structures at various stages of manufacturing an IC package (such as the third IC package example 200C in Figure 2C) according to various aspects of this disclosure. Components illustrated in Figures 5A to 5F that are the same as or similar to those in Figure 2C are given the same reference numerals, and their detailed descriptions may be omitted.

[0078] As shown in Figure 5A, structure 500A can be formed by mounting IC component 220 on base structure 212. In some aspects, IC component 220 can be mounted on base structure 212 via IC terminals 222 (e.g., solder bumps or copper pillar bumps). In some aspects, IC component 220 can be an IC chip, or an assembly having a packaging substrate and an IC chip mounted on the packaging substrate. In some aspects, base structure 212, as shown in Figure 5A, can be a packaging substrate. In some examples, base structure 212 can be a redistribution layer. In some aspects, base structure 212 at this stage can be in the form of a portion of a wafer, strip, or panel, on which one or more other base structures for one or more other IC packages are also provided. In some aspects, base structure 212 can be a separate base structure for forming an IC package.

[0079] As shown in FIG. 5B, structure 500B can be formed based on forming a plurality of bonding posts 510 on the upper surface of the base substrate 212. The plurality of bonding posts 510 will form the basis for forming a plurality of interposer connection structures 230' in a later stage. In some aspects, each of the plurality of bonding posts 510 may include a bonding ball portion 232 connected to the base structure 212, and a bonding line portion 234 coupled to the bonding ball portion 232 and extending upward, as similarly illustrated with reference to FIG. 3B. In some aspects, the plurality of bonding posts 510 may have a pitch P equal to or less than 150 µm. In some aspects, the pitch P may be equal to or less than 100 µm because the subsequently formed interposer structure 260 may be a redistribution layer. In some aspects, the plurality of bonding posts 510 may be formed based on a wire bonding process utilizing bonding lines comprising metal. In some aspects, the metal may include copper, aluminum, gold, or combinations thereof.

[0080] As shown in Figure 5C, structure 500C can be formed based on structure 500B by forming a molding compound portion 520 on base structure 212 and covering IC component 220 and bonding post 510.

[0081] As shown in Figure 5D, structure 500D can be formed based on structure 500C by polishing the molding compound portion 520 to expose the upper end of the bonding line portion of the bonding post 510. In some aspects, the bonding post 510 may be a plurality of intermediate layer connection structures 230' having exposed upper ends, and the polished molding compound portion 520 may be a molding compound portion 216.

[0082] As shown in Figure 5E, structure 500E can be formed based on structure 500D by disposing an interposer structure 260 above IC component 220 and multiple interposer connection structures 230'. In some aspects, the interposer structure 260 may be a redistributed layer formed after polishing on the upper end of the molding compound portion 216 and the bonding line portion of the multiple interposer connection structures 230'. In some aspects, the distance D between the upper surface of the base structure 212 and the lower surface of the interposer structure 260 may be greater than 200µm.

[0083] As shown in Figure 5F, structure 500F can be formed based on structure 500E by forming a plurality of package terminals 214 (e.g., a plurality of solder bumps or copper pillar bumps) under base structure 212, wherein the plurality of package terminals 214 are configured to connect the resulting IC package (e.g., third IC package example 200C) to external components (e.g., circuit boards). Furthermore, since base structure 212 in Figures 5A to 5E is part of a wafer, strip, or panel, structure 500F can be further formed by performing a dicing process to separate structure 500F from one or more other base structures for one or more other IC packages. In some aspects, structure 500F may correspond to third IC package example 200C.

[0084] Figures 6A to 6D, together with Figures 5A to 5D, illustrate the structures at various stages of manufacturing an IC package (such as the fourth IC package example 200D in Figure 2D) according to various aspects of this disclosure. Components illustrated in Figures 6A to 6D that are the same as or similar to those in Figures 2C and 5A to 5D are given the same reference numerals, and their detailed descriptions may be omitted.

[0085] As shown in Figure 6A, polishing for forming structure 500D can further expose the upper surface of IC component 220. After polishing, a thermal interface material layer 282 can be disposed on the upper surface of IC component 220. In some aspects, the thermal interface material layer 282 may include a material with a thermal conductivity equal to or greater than 3 W / mK. In some aspects, the thermal interface material layer 282 may include a material with a thermal conductivity in the range of 3 W / mK to 10 W / mK.

[0086] As shown in Figure 6B, structure 600B can be formed based on forming solder portions 236 on the lower surface of the interposer structure 240. In Figure 6B, the interposer structure 240 is depicted as being in an upside-down position compared to the interposer structure 240 depicted in Figure 2D. In some aspects, the solder portions 236 can be formed by paste-printing solder material onto the lower surface of the interposer structure 240.

[0087] As shown in Figure 6C, structure 600C can be formed by attaching structure 600B to structure 600A, wherein solder portions 236 can bond bonding posts 510 to interposer structure 240. Combinations of solder portions 236 bonding bonding posts 510 can form multiple interposer connection structures 230. Therefore, interposer structure 240 can be disposed above IC assembly 220 and multiple interposer connection structures 230. Furthermore, the multiple interposer connection structures 230 can be configured to connect base structure 212 and interposer structure 240. In some aspects, the distance D between the upper surface of base structure 212 and the lower surface of interposer structure 240 can be greater than 200µm. In some aspects, a gap can exist between molding compound portion 218 and the lower surface of interposer structure 240 due to thermal interface material layer 282.

[0088] As shown in Figure 6D, structure 600D can be formed based on structure 600C by forming a plurality of package terminals 214 (e.g., a plurality of solder bumps or copper pillar bumps) under base structure 212, wherein the plurality of package terminals 214 are configured to connect the resulting IC package (e.g., fourth IC package example 200D) to external components (e.g., circuit boards). Furthermore, since base structure 212 in Figures 6A to 6C is part of a wafer, strip, or panel, structure 600D can be further formed by performing a dicing process to separate structure 600D from one or more other base structures for one or more other IC packages. In some aspects, structure 600D may correspond to fourth IC package example 200D.

[0089] Figure 7 illustrates a method 700 for manufacturing IC packages (such as IC package examples 200A, 200B, 200C and / or 200D) according to various aspects of this disclosure. In some aspects, Figures 3A to 3F, 4A to 4H, 5A to 5F and 6A to 6D may depict portions of IC package examples at different manufacturing stages according to method 700.

[0090] At operation 710, an IC component (e.g., IC component 220) may be disposed on a base structure (e.g., base structure 212 or base structure 252). In some aspects, IC component 220 may be an IC chip, or an assembly having a packaging substrate and an IC chip mounted on the packaging substrate. In some aspects, the base structure may be a packaging substrate (e.g., base structure 212) or a redistribution layer (e.g., base structure 252). In some aspects, operation 710 may correspond to the stages depicted in Figures 3A, 4A, and 5A.

[0091] At operation 720, multiple interposer connection structures (e.g., multiple interposer connection structures 230 or multiple interposer connection structures 230') may be disposed on the base structure. In some aspects, disposing of multiple interposer connection structures may include, for each of the multiple interposer connection structures, forming a corresponding bonding ball portion and a corresponding bonding line portion based on a wire bonding process utilizing bonding lines comprising metal (e.g., disposing bonding line posts 310, 410, or 510 in Figures 3B, 4B, and 5B). In some aspects, the metal includes copper, aluminum, gold, or combinations thereof.

[0092] In some aspects, the multiple interposer layer connection structure may have a pitch equal to or less than 150 µm. In other aspects, the multiple interposer layer connection structure may have a pitch equal to or less than 100 µm.

[0093] At operation 730, an interposer structure (e.g., interposer structure 240 or interposer structure 260) may be disposed above the IC component and the plurality of interposer connection structures. In some aspects, the plurality of interposer connection structures are configured to connect the base structure and the interposer structure. In some aspects, each of the plurality of interposer connection structures may include a bonding ball portion connected to the base structure and a bonding line portion coupled to the bonding ball portion and extending toward the interposer structure. In some aspects, for each of the plurality of interposer connection structures, the width of the bonding ball portion may be greater than the width of the bonding line portion.

[0094] In some respects, the distance between the upper surface of the base structure and the lower surface of the intermediate layer structure can be greater than 200µm.

[0095] In some aspects, method 700 may further include forming a molding compound portion on the base structure and at least around a portion of the bonding ball portion and bonding line portion of the plurality of intermediate layer connection structures. In some aspects, method 700 may further include polishing the molding compound portion to expose the upper ends of the bonding line portions of the plurality of intermediate layer connection structures.

[0096] In some respects, polishing can expose the upper surface of the IC component, and method 700 may also include setting a thermal interface material layer on the upper surface of the IC component after polishing.

[0097] In some aspects, the interposer structure may be a package substrate (e.g., interposer structure 240 in Figures 2A and 2D). In some aspects, setting the interposer structure may include: forming solder portions on the lower surface of the interposer structure; and bonding the upper ends of bonding line portions of the interposer structure to a plurality of interposer connection structures based on the solder portions.

[0098] In some aspects, the interposer structure may be a redistribution layer (e.g., interposer structure 260 in Figures 2B and 2C). In some aspects, method 700 may also include forming a redistribution layer on the upper end of the molding compound portion and the bonding line portion of the plurality of interposer connection structures after polishing.

[0099] In some aspects, after operation 730, method 700 may further include forming a plurality of solder bumps or copper pillar bumps beneath the base structure. In some aspects, the plurality of solder bumps or copper pillar bumps may be configured to connect the IC package to a circuit board.

[0100] The technical advantages of method 700 correspond to the manufacture of integrated circuit (IC) packages including interposer interconnect structures formed using wire bonding processes. In some aspects, wire bonding-based interposer interconnect structures can reduce the horizontal dimensions of the IC package and / or increase the count per unit area of ​​the interposer interconnect structure. In some aspects, wire bonding-based interposer interconnect structures can have a greater height-to-pitch ratio than other solutions (e.g., copper core balls or copper-plated pillars) to accommodate thicker IC components between the interposer structure and the base structure of the IC package. Furthermore, the manufacturing cost of wire bonding-based interposer interconnect structures can be lower than other alternative implementations based on copper core balls or copper-plated pillars.

[0101] Figure 8 illustrates a mobile device 800 according to various aspects of this disclosure. In some aspects, the mobile device 800 may be implemented by including an IC device based on the IC package disclosed herein.

[0102] In some aspects, the mobile device 800 can be configured as a wireless communication device. As shown, the mobile device 800 includes a processor 801. The processor 801 is communicatively coupled to a memory 832 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 800 also includes a display 828 and a display controller 826, wherein the display controller 826 is coupled to the processor 801 and the display 828. The mobile device 800 may include an input device 830 (e.g., a physical or virtual keyboard), a power supply 844 (e.g., a battery), a speaker 836, a microphone 838, and a wireless antenna 842. In some aspects, the power supply 844 may directly or indirectly provide the power supply voltage for operating some or all of the components of the mobile device 800.

[0103] In some aspects, FIG8 may include a decoder / decoder (codec) 834 (e.g., an audio and / or speech codec) coupled to processor 801; a speaker 836 and a microphone 838 coupled to codec 834; and a wireless circuit 840 (which may include a modem, RF circuitry, filters, etc.) coupled to wireless antenna 842 and to processor 801.

[0104] In some aspects, one or more of the processor 801 (e.g., SOC, application processor (AP)), display controller 826, memory 832, codec 834, and wireless circuit 840 (e.g., baseband interface) include IC devices packaged as IC packages according to the various aspects described in this disclosure.

[0105] It should be noted that although Figure 8 depicts a mobile device 800, similar architectures can be used to implement devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0106] Figure 9 illustrates various electronic devices 910, 920 and 930 that can be incorporated into IC devices 912, 922 and 932 according to various aspects of the present disclosure, which can be packaged as IC packages described herein.

[0107] For example, mobile phone device 910, laptop computer device 920, and fixed-location terminal device 930 can each generally be considered as user equipment (UE) and may include one or more IC devices (such as IC devices 912, 922, and 932) and a power supply for providing a supply voltage to power the IC devices. IC devices 912, 922, and 932 may, for example, correspond to IC devices packaged as IC packages having a package substrate manufactured based on the examples described above with reference to Figures 2A to 6D.

[0108] The devices 910, 920, and 930 illustrated in Figure 9 are merely non-limiting examples. Other electronic devices may also feature IC devices including a package substrate as described in this disclosure, including but not limited to a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, access points, base stations, or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0109] It should be understood that the various aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices as described and / or understood by those skilled in the art. For example, in one aspect, the apparatus may include components for performing the various functions discussed above. It should be understood that the foregoing aspects are provided by way of example only, and the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0110] One or more of the components, processes, features, and / or functions illustrated in Figures 1 through 9 may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. In some embodiments, Figures 1 through 9 and the corresponding descriptions may be used to manufacture, create, provide, and / or produce integrated equipment. In some embodiments, the equipment may include dies, integrated devices, die packages, ICs, device packages, IC packages, wafers, semiconductor devices, system-in-package (SiP), system-on-a-chip (SoC), stacked-package (PoP) devices, etc.

[0111] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein expressly include these combinations unless expressly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0112] Specific implementation examples are described in the following numbered clauses: Clause 1. An integrated circuit (IC) package comprising: a base structure; an IC assembly disposed on the base structure; a plurality of interposer connection structures disposed on the base structure; and an interposer structure disposed above the IC assembly and the plurality of interposer connection structures, wherein the plurality of interposer connection structures are configured to connect the base structure and the interposer structure, and wherein each of the plurality of interposer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the interposer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

[0113] Clause 2. The IC package according to Clause 1, wherein: the bonding ball portion and the bonding line portion of each of the plurality of interposer connection structures comprise metal.

[0114] Clause 3. The IC package as described in Clause 2, wherein: the metal comprises copper, aluminum, gold, or a combination thereof.

[0115] Clause 4. An IC package according to any one of Clauses 1 to 3, wherein: the plurality of interposer interconnects have a pitch of 150 micrometers (µm) or less.

[0116] Clause 5. The IC package according to Clause 4, wherein: the plurality of interposer connection structures have a pitch equal to or less than 100µm.

[0117] Clause 6. An IC package according to any one of Clauses 1 to 5, wherein: the distance between the upper surface of the base structure and the lower surface of the interposer structure is greater than 200 micrometers (µm).

[0118] Clause 7. An IC package according to any one of Clauses 1 to 6, wherein: each of the plurality of interposer connection structures further includes a solder portion connecting the upper end of the corresponding bonding wire portion to the interposer structure.

[0119] Clause 8. An IC package according to any one of Clauses 1 to 7, the IC package further comprising: a molding compound portion between the base structure and the interposer structure and at least around a portion of the bonding ball portion and the bonding line portion of the plurality of interposer connection structures.

[0120] Clause 9. The IC package according to Clause 8, the IC package further comprising: a thermal interface material layer between the upper surface of the IC component and the interposer structure.

[0121] Clause 10. An IC package according to any one of Clauses 1 to 6, wherein: the interposer structure includes a redistribution layer, and the upper end of the corresponding bonding line portion of each of the plurality of interposer connection structures is connected to the interposer structure.

[0122] Clause 11. An IC package according to any one of Clauses 1 to 10, wherein: the base structure comprises a package substrate or a redistribution layer.

[0123] Clause 12. An IC package according to any one of Clauses 1 to 11, the IC package further comprising: a plurality of solder bumps or copper pillar bumps, the plurality of solder bumps or copper pillar bumps being below the base structure and configured to connect the IC package to a circuit board.

[0124] Clause 13. An IC package according to any one of Clauses 1 to 12, wherein: the IC component is an IC chip, or an assembly having a package substrate and the IC chip mounted on the package substrate.

[0125] Clause 14. A method of manufacturing an integrated circuit (IC) package, the method comprising: disposing an IC component on a base structure; disposing a plurality of interposer connection structures on the base structure; and disposing an interposer structure over the IC component and the plurality of interposer connection structures, wherein the plurality of interposer connection structures are configured to connect the base structure and the interposer structure, and wherein each of the plurality of interposer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the interposer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

[0126] Clause 15. The method according to Clause 14, wherein: setting the plurality of interposer connection structures includes: for each of the plurality of interposer connection structures, forming the corresponding bonding ball portion and the corresponding bonding line portion based on a wire bonding process utilizing bonding lines including metal.

[0127] Clause 16. The method according to Clause 15, wherein: the metal includes copper, aluminum, gold, or combinations thereof.

[0128] Clause 17. The method according to any one of Clauses 14 to 16, wherein: the plurality of interposer layer connection structures have a pitch equal to or less than 150 micrometers (µm).

[0129] Clause 18. The method according to any one of Clauses 14 to 17, wherein: the distance between the upper surface of the base structure and the lower surface of the intermediate layer structure is greater than 200 micrometers (µm).

[0130] Clause 19. The method according to any one of Clauses 14 to 18, wherein: setting the interposer structure comprises: forming a solder portion on the lower surface of the interposer structure; and joining the upper ends of the bonding line portions of the interposer structure to the plurality of interposer connection structures based on the solder portion.

[0131] Clause 20. The method according to any one of Clauses 14 to 18, the method further comprising: forming a molding compound portion on the base structure and at least around a portion of the bonding ball portion and the bonding line portion of the plurality of intermediate layer connection structures.

[0132] Clause 21. The method according to Clause 20, the method further comprising: polishing the molding compound portion to expose the upper end of the bonding line portion of the plurality of intermediate layer connection structures.

[0133] Clause 22. The method according to Clause 21, the method further comprising: depositing a thermal interface material layer on the upper surface of the IC assembly after the polishing, wherein the polishing exposes the upper surface of the IC assembly.

[0134] Clause 23. The method according to any one of Clauses 21 to 22, the method further comprising: forming a redistribution layer on the upper end of the molding compound portion and the bonding line portion of the plurality of intermediate layer connection structures after the polishing.

[0135] Clause 24. The method according to any one of Clauses 14 to 23, the method further comprising: forming a plurality of solder bumps or copper pillar bumps below the base structure, the plurality of solder bumps or copper pillar bumps being configured to connect the IC package to a circuit board.

[0136] Clause 25. An electronic device comprising: an integrated circuit (IC) package, the IC package including: a base structure; an IC assembly disposed on the base structure; a plurality of interposer connection structures disposed on the base structure; and an interposer structure disposed above the IC assembly and the plurality of interposer connection structures, wherein the plurality of interposer connection structures are configured to connect the base structure and the interposer structure, and wherein each of the plurality of interposer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the interposer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

[0137] Clause 26. The electronic device according to Clause 25, wherein: the bonding ball portion and the bonding line portion of each of the plurality of interposer connection structures comprise metal, and the metal comprises copper, aluminum, gold, or combinations thereof.

[0138] Clause 27. An electronic device according to any one of Clauses 25 to 26, wherein: the plurality of interposer connection structures have a pitch equal to or less than 150 micrometers (µm), and the distance between the upper surface of the base structure and the lower surface of the interposer structure is greater than 200µm.

[0139] Clause 28. An electronic device according to any one of Clauses 25 to 27, wherein: the interposer structure includes a package substrate, and each of the plurality of interposer connection structures further includes a solder portion connecting the upper end of the corresponding bonding line portion to the interposer structure.

[0140] Clause 29. An electronic device according to any one of Clauses 25 to 27, wherein: the intermediary layer structure includes a redistribution layer, and the upper end of the corresponding bonding line portion of each of the plurality of intermediary layer connection structures is connected to the intermediary layer structure.

[0141] Clause 30. An electronic device pursuant to any one of Clauses 25 to 29, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

[0142] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0143] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application; however, such implementation decisions should not be construed as departing from the scope of this disclosure.

[0144] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic units, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0145] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0146] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0147] Furthermore, as used herein, the terms “set,” “group,” etc., are intended to include one or more of the elements. Additionally, as used herein, the terms “having,” “comprising,” “including,” etc., do not exclude the presence of one or more additional elements (e.g., element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless otherwise explicitly stated. Moreover, as used herein, the term “or” is intended to be open-ended when used in a series and may be used interchangeably with “and / or” unless otherwise explicitly stated (e.g., if used in conjunction with “any” or “only one”), or these alternatives are mutually exclusive (e.g., “one or more” should not be interpreted as “one and more”). Furthermore, although components, functions, actions, and instructions may be described or claimed in the singular form, the plural form may also be considered unless explicitly stated as limited to the singular. Therefore, as used herein, the articles “a,” “an,” “the,” and “the” are intended to include one or more of the elements. Additionally, as used herein, the terms “at least one” and “one or more” include performing or being able to perform “one” component, function, action, or instruction of the described or claimed functionality, and also include performing or being able to perform “two or more” components, functions, actions, or instructions of the described or claimed functionality in combination.

[0148] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. For example, the functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, no component, function, action, or instruction described or claimed herein should be construed as critical or essential unless expressly stated otherwise.

Claims

1. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: Base structure; IC components are disposed on the base structure; Multiple intermediate layer connection structures are disposed on the base structure; An intermediary layer structure is disposed above the IC component and the plurality of intermediary layer connection structures, wherein the plurality of intermediary layer connection structures are configured to connect the base structure and the intermediary layer structure, and wherein each of the plurality of intermediary layer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the intermediary layer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

2. The IC package according to claim 1, wherein: The bonding ball portion and the bonding line portion of each of the plurality of intermediary layer connection structures comprise metal.

3. The IC package according to claim 2, wherein: The metal includes copper, aluminum, gold, or combinations thereof.

4. The IC package according to claim 1, wherein: The multiple intermediate layer connection structures have a pitch of 150 micrometers (µm) or less.

5. The IC package according to claim 4, wherein: The multiple intermediate layer connection structures have a pitch of 100µm or less.

6. The IC package according to claim 1, wherein: The distance between the upper surface of the base structure and the lower surface of the intermediate layer structure is greater than 200 micrometers (µm).

7. The IC package according to claim 1, wherein: Each of the plurality of interposer connection structures further includes a solder portion connecting the upper end of the corresponding bonding line portion to the interposer structure.

8. The IC package according to claim 1, further comprising: A molding compound portion, the molding compound portion being between the base structure and the intermediate layer structure and at least surrounding a portion of the bonding ball portion and the bonding line portion of the plurality of intermediate layer connection structures.

9. The IC package according to claim 8, further comprising: A thermal interface material layer is provided between the upper surface of the IC component and the interposer structure.

10. The IC package according to claim 1, wherein: The intermediary layer structure includes a redistribution layer, and the upper end of the corresponding bonding line portion of each of the plurality of intermediary layer connection structures is connected to the intermediary layer structure.

11. The IC package according to claim 1, wherein: The base structure includes a packaging substrate or a redistribution layer.

12. The IC package according to claim 1, further comprising: Multiple solder bumps or copper pillar bumps are located below the base structure and are configured to connect the IC package to a circuit board.

13. The IC package according to claim 1, wherein: The IC component is an IC chip, or an assembly having a packaging substrate and the IC chip mounted on the packaging substrate.

14. A method for manufacturing an integrated circuit (IC) package, the method comprising: The IC components are mounted on the base structure; Multiple intermediate layer connection structures are disposed on the base structure; An intermediary layer structure is disposed above the IC component and the plurality of intermediary layer connection structures, wherein the plurality of intermediary layer connection structures are configured to connect the base structure and the intermediary layer structure, and wherein each of the plurality of intermediary layer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the intermediary layer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

15. The method of claim 14, wherein: The provision of the plurality of intermediary layer connection structures includes: for each of the plurality of intermediary layer connection structures, forming the corresponding bonding ball portion and the corresponding bonding line portion based on a wire bonding process utilizing bonding lines including metal.

16. The method of claim 15, wherein: The metal includes copper, aluminum, gold, or combinations thereof.

17. The method of claim 14, wherein: The multiple intermediate layer connection structures have a pitch of 150 micrometers (µm) or less.

18. The method of claim 14, wherein: The distance between the upper surface of the base structure and the lower surface of the intermediate layer structure is greater than 200 micrometers (µm).

19. The method of claim 14, wherein: The provisioning of the interposer structure includes: forming a solder portion on the lower surface of the interposer structure; and joining the upper ends of the bonding line portions of the interposer structure to the plurality of interposer connection structures based on the solder portion.

20. The method of claim 14, further comprising: A molding compound portion is formed on the base structure and at least around a portion of the bonding ball portion and the bonding line portion of the plurality of intermediate layer connection structures.

21. The method according to claim 20, further comprising: Polish the molded compound portion to expose the upper end of the bonding line portion of the plurality of intermediate layer connection structures.

22. The method according to claim 21, further comprising: A thermal interface material layer is applied to the upper surface of the IC assembly after polishing, wherein the polishing exposes the upper surface of the IC assembly.

23. The method according to claim 21, further comprising: A redistribution layer is formed on the upper end of the molding compound portion and the bonding line portion of the plurality of intermediate layer connection structures after polishing.

24. The method according to claim 14, further comprising: Multiple solder bumps or copper pillar bumps are formed below the base structure, and the multiple solder bumps or copper pillar bumps are configured to connect the IC package to the circuit board.

25. An electronic device, the electronic device comprising: An integrated circuit (IC) package includes: a base structure; an IC assembly disposed on the base structure; a plurality of interposer connection structures disposed on the base structure; and an interposer structure disposed above the IC assembly and the plurality of interposer connection structures, wherein the plurality of interposer connection structures are configured to connect the base structure and the interposer structure, and wherein each of the plurality of interposer connection structures includes: a bonding ball portion connected to the base structure, and a bonding line portion coupled to the bonding ball portion and extending toward the interposer structure, wherein the width of the bonding ball portion is greater than the width of the bonding line portion.

26. The electronic device according to claim 25, wherein: The bonding ball portion and the bonding line portion of each of the plurality of intermediary layer connection structures comprise metal, and the metal comprises copper, aluminum, gold, or a combination thereof.

27. The electronic device according to claim 25, wherein: The plurality of intermediate layer connection structures have a pitch of 150 micrometers (µm) or less, and the distance between the upper surface of the base structure and the lower surface of the intermediate layer structure is greater than 200µm.

28. The electronic device according to claim 25, wherein: The interposer structure includes a packaging substrate; and each of the plurality of interposer connection structures further includes a solder portion connecting the upper end of the corresponding bonding line portion to the interposer structure.

29. The electronic device according to claim 25, wherein: The intermediary layer structure includes a redistribution layer, and the upper end of the corresponding bonding line portion of each of the plurality of intermediary layer connection structures is connected to the intermediary layer structure.

30. The electronic device of claim 25, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

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