Integrated circuit device including thermal interposer

Abstract

A device includes a die including a set of contacts coupled to a first side of the die. The die also includes an active circuit coupled to the set of contacts. The device also includes a thermal interposer (TIL) adjacent to the first side of the die. The TIL includes a thermally conductive material having one or more through-holes (THVs) aligned with one or more first contacts of the set of contacts. The device also includes a set of electrically conductive connections coupled to the one or more first contacts and extending through the THVs.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to jointly owned U.S. non-provisional patent application No. 18 / 538,738, filed on December 13, 2023, the contents of which are expressly incorporated herein by reference in their entirety. Technical Field

[0003] Various features are involved in integrated circuit devices. Background Technology

[0004] Electrical connections exist at every level of a system hierarchy. This hierarchy includes the interconnections of active devices at the lowest system level, all the way up to the system-level interconnections at the highest level. For example, interconnect layers connect different devices on an integrated circuit. As integrated circuits become more complex, more interconnect layers are used to provide electrical connections between devices. Recently, due to the sheer number of interconnected devices in modern electronics, the number of interconnect layers in a circuit has substantially increased. The increasing number of interconnect layers to support the growing number of devices involves more complex processes.

[0005] Existing mobile application devices require small form factor, low cost, tight power budgets, and high electrical performance. Mobile packaging designs have evolved to meet these diverse goals, enabling mobile applications that support multimedia enhancements. However, when one or more dies are housed within a small form factor, these mobile applications are susceptible to overheating issues. In particular, system performance may degrade, making high-speed computing difficult due to limited heat dissipation. Summary of the Invention

[0006] Various features are involved in integrated circuit devices.

[0007] One example provides a device including a die. The die includes a set of contacts coupled to a first side of the die. The die also includes active circuitry coupled to the set of contacts. The device further includes a thermally conductive interlayer (TIL) adjacent to the first side of the die. The TIL includes a thermally conductive material having one or more through-holes (THVs) aligned with one or more of the first contacts in the set of contacts. The device also includes a set of conductive connections coupled to the one or more first contacts and extending through the THVs.

[0008] Another example provides a manufacturing method comprising forming a thermally conductive interlayer (TIL) of a thermally conductive material having one or more through-holes (THVs). The method further comprises forming a set of conductive connectors coupled to one or more first contacts of a die. The die includes a set of contacts coupled to a first side of the die. The die includes active circuitry coupled to the set of contacts. The set of contacts includes one or more first contacts. The method further comprises attaching the TIL to the die using the set of conductive connectors extending through the one or more THVs to couple to the one or more first contacts.

[0009] Another example provides a device including a first chiplet. The first chiplet includes a first set of contacts coupled to a first side of the first chiplet. The first chiplet also includes first active circuitry coupled to the first set of contacts. The device includes a first thermally conductive layer (TIL) adjacent to the first side of the first chiplet. The first TIL includes a first thermally conductive material having one or more first through-holes (THVs) aligned with one or more of the first contacts in the first set. The device also includes a first set of conductive connections coupled to the one or more first contacts and extending through the first THV. The device further includes a packaging substrate including a set of substrate contacts. One or more of the first substrate contacts in the set are coupled to the first set of conductive connections. Attached Figure Description

[0010] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0011] Figure 1A A cross-sectional profile of an exemplary integrated circuit (IC) device including a thermal interposer (TIL) is illustrated.

[0012] Figure 1B Examples Figure 1A A top cross-sectional view of an example and exemplary IC device for TIL.

[0013] Figure 2A A cross-sectional profile of an exemplary IC device including TIL is shown.

[0014] Figure 2B Examples Figure 2A A top cross-sectional view of an example and exemplary IC device for TIL.

[0015] Figure 3A A cross-sectional profile of an exemplary IC device including TIL is shown.

[0016] Figure 3B Examples Figure 3AA top view of an exemplary IC device.

[0017] Figure 4A A cross-sectional profile of an exemplary IC device including TIL is shown.

[0018] Figure 4B Examples Figure 4A A top cross-sectional view of an example and exemplary IC device for TIL.

[0019] Figure 5A A cross-sectional profile of an exemplary IC device including TIL is shown.

[0020] Figure 5B Examples Figure 5A A top cross-sectional view of an example and exemplary IC device for TIL.

[0021] Figure 6A A cross-sectional profile of an exemplary IC device including TIL is shown.

[0022] Figure 6B Examples Figure 6A A top view of a portion of an example and exemplary IC device of TIL.

[0023] Figure 7 An example of TIL and a cross-sectional top view of a portion of an exemplary IC device including TIL are shown.

[0024] Figure 8A Exemplary process stages for manufacturing an exemplary IC device including a TIL are illustrated.

[0025] Figure 8B Exemplary process stages for manufacturing an exemplary IC device including a TIL are illustrated.

[0026] Figure 8C Exemplary process stages for manufacturing an exemplary IC device including a TIL are illustrated.

[0027] Figure 8D Exemplary process stages for manufacturing an exemplary IC device including a TIL are illustrated.

[0028] Figure 8E Exemplary process stages for manufacturing an exemplary IC device including a TIL are illustrated.

[0029] Figure 9 An exemplary flowchart illustrating a method for manufacturing an exemplary IC device including a TIL is shown.

[0030] Figure 10Examples are given of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0031] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0032] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a,” “an,” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optional plural form (as indicated by “(multiple)”), unless the aspect relating to multiples of features is being described.

[0033] In some accompanying figures, multiple instances of a particular type of feature are used. Although these features are physically and / or logically different, the same reference numerals are used for each feature, and these different instances are distinguished by adding letters to the reference numerals. When features are referred to herein as a group or a type (e.g., when a specific feature among these features is not mentioned), reference numerals are used without distinguishing letters. However, when a specific feature of multiple features of the same type is referred to herein, reference numerals are used with distinguishing letters. For example, reference... Figure 2A The figure illustrates several hotspots, which are associated with reference numerals 108A and 108B. When referring to a specific hotspot among these hotspots (such as hotspot 108A), the distinguishing letter "A" is used. However, when referring to any individual hotspot among these hotspots or when referring to these hotspots as a group, reference numeral 108 is used without the distinguishing letter.

[0034] As used herein, the term “comprising” may be used interchangeably with “including”. As used herein, “exemplary” indicates an example, specific implementation, and / or aspect, and should not be construed as restrictive or indicating a preference or preferred implementation. As used herein, ordinal terms used to modify elements (such as structures, components, operations, etc.) (e.g., “first,” “second,” “third,” etc.) do not in themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using ordinal terms). As used herein, the term “set” refers to one or more specific elements among specific elements, while the term “multiple” refers to multiple (e.g., two or more) specific elements.

[0035] Improvements in manufacturing technology and the demand for lower-cost and more capable electronic devices have led to increased complexity in ICs. Typically, more complex ICs have more complex interconnect schemes to enable interaction between ICs within a device. Due to the sheer number of interconnected devices in today's state-of-the-art mobile applications, the number of interconnect layers in the circuitry has also increased substantially.

[0036] These interconnects include back-end process (BEOL) interconnect layers, which can refer to conductive interconnect layers used for electrical coupling to front-end process (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, where lower BEOL interconnect levels typically use a thinner metal layer than upper BEOL interconnect levels. BEOL interconnect layers can be electrically coupled to middle-end process (MOL) interconnect layers, which interconnect to the IC's FEOL active devices.

[0037] Existing mobile application devices require small form factor, low cost, tight power budgets, and high electrical performance. Mobile packaging designs have evolved to meet these diverse objectives, enabling multimedia-enhanced mobile applications. For example, fan-out (FO) wafer-level packaging (WLP), or FO-WLP process technology, is an evolution of packaging technologies useful for mobile applications. This chip-first FO-WLP process technology solution provides flexibility for fan-in and fan-out connections from the die to the package ball. Furthermore, this solution offers a significant reduction in the height of the first-level interconnect between the die and package ball for mobile application devices. However, these mobile applications are susceptible to overheating issues when one or more dies are arranged within a small form factor.

[0038] Stacked die and chiplet architecture solutions are becoming increasingly common as product lines exhibit significant yield improvements in the power performance area (PPA). Various aspects of this disclosure provide an IC device with TIL (Total Power Area) to provide improved thermal dissipation, thereby enhancing computing performance.

[0039] As used herein, the term "layer" includes films and is not construed as indicating vertical or horizontal thickness unless otherwise stated. As used herein, the term "chiplet" can refer to a block of integrated circuits, a block of functional circuitry, or other similar circuitry specifically designed to work with one or more other chiplets to form a larger, more complex chiplet architecture.

[0040] 3D integrated circuits (3D ICs) consist of a set of stacked and interconnected dies. Generally speaking, 3D IC architectures can achieve higher performance, increased functionality, lower power consumption, and / or smaller footprint compared to providing the same circuitry in a monolithic die or in a two-dimensional (2D) IC structure.

[0041] Various aspects of this disclosure relate to IC devices that use TIL (Transfer Inlet / Outlet) to provide improved heat dissipation. In some aspects of this disclosure, the TIL is disposed in a space adjacent to the hot spots of the die. Having a TIL can improve performance and increase the component lifespan of the IC device.

[0042] Exemplary IC device including thermal interposer

[0043] Figure 1A A cross-sectional profile of a device 100 (e.g., an exemplary IC device) including a thermal interposer (TIL) 114 is illustrated. Figure 1B An example of TIL 114 and a cross-sectional top view of device 100 are shown.

[0044] Device 100 includes die 102. Die 102 may include integrated circuits, such as multiple transistors and / or other circuit elements arranged and interconnected to form logic cells, memory cells, etc. Components of the integrated circuit may be formed in and / or on a semiconductor substrate. Different embodiments may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finFETs, gate-all-around FETs, or a mixture of transistor types. In certain aspects, die 102 may include a complementary metal-oxide-semiconductor (CMOS) chip, a power amplifier, a low-noise amplifier (LNA), a switch, a filter, or a combination thereof. In some embodiments, front-end process (FEOL) technology may be used to fabricate the integrated circuit in and / or on the semiconductor substrate.

[0045] Die 102 includes a set of contacts 116 coupled to side 150 of die 102. In a particular embodiment, die 102 includes active circuitry coupled to contacts 116. The active circuitry includes, for example, processing logic blocks (e.g., transistor blocks), memory blocks, etc. Device 100 includes a thermally conductive interphase (TIL) 114 adjacent to side 150 of die 102. In a particular embodiment, TIL 114 is positioned adjacent to hot spots 108 of die 102 and dissipates heat from die 102. TIL 114 includes a thermally conductive material having one or more through-holes (THVs) 140. In a particular embodiment, the thermally conductive material includes alumina ceramic, aluminum nitride, silicon carbide (SiC), or combinations thereof. THV 140 is aligned with one or more contacts in contacts 116. Device 100 includes a set of conductive connections (CCs) 142 coupled to at least some of the contacts in contacts 116. For example, one or more CC 142s are coupled to the corresponding contact 116 and extend through THV 140. CC 142s may be conductive, thermally conductive, or both.

[0046] exist Figure 1B In this example, each THV in THV 140 is illustrated as having a substantially circular cross-section. In other examples, THV 140 may have cross-sections of different shapes. For illustration, at least one THV in THV 140 may have a substantially circular cross-section, a substantially elliptical cross-section, a substantially square cross-section, or a combination thereof, as referenced. Figure 6B Further description.

[0047] Device 100 also includes a substrate 110 (e.g., a package substrate) that includes a set of contacts 120 coupled to a side 152 of substrate 110. One or more contacts 120 are coupled to corresponding conductive interconnects 142. For example, each contact 120 is coupled to a corresponding CC 142 via a conductive interconnect (CI) 122 and a pad 118. Thus, the circuitry of die 102 is electrically connected to substrate 110 via a conductive path including contacts 116, CC 142, pad 118, CI 122, and contacts 120. In a particular embodiment, die 102 corresponds to a chiplet separated from substrate 110 by a TIL 114.

[0048] In some embodiments, die 102 includes input / output (I / O) circuitry, and one or more of the CCs 142 are connected to the I / O circuitry to provide a data path between die 102 and a second device coupled to substrate 110. As an exemplary example, the second device may include a dynamic random access memory (DRAM) chip (or chiplet). In this exemplary example, the I / O circuitry of die 102 may include, or correspond to, interface circuitry (e.g., serializer / deserializer (SerDes) circuitry, double data rate (DDR) type DRAM bus interface circuitry), memory buffers, and / or other circuitry facilitating interaction between the active circuitry of die 102 and the DRAM. In some embodiments, the I / O circuitry may be connected to other devices that complement or replace the second device. For example, the I / O circuitry may interact with one or more other devices on a printed circuit board via one or more CCs 142.

[0049] In a particular embodiment, one or more of contact 116, CC 142, pad 118, CI 122, or contact 120 comprises a conductive material, such as copper, tin, aluminum, silver, gold, lead, bismuth, or combinations thereof. In a particular embodiment, one or more of contact 116, CC 142, pad 118, CI 122, or contact 120 may comprise a conductive material not included in another of contact 116, CC 142, pad 118, CI 122, or contact 120. In a particular embodiment, one or more of contact 116, CC 142, pad 118, CI 122, or contact 120 comprises a thermally conductive material. For example, one or more of contact 116, CC 142, pad 118, CI 122, or contact 120 are used for electrical signal propagation, heat propagation, or both.

[0050] In a particular embodiment, CC 142 corresponds to a copper pillar, CI 122 corresponds to a solder bump, and contacts 116, 120, and 118 correspond to metal pads. The pillars, bumps, and pads serve as illustrative examples of the shapes of components of device 100 (e.g., CC 142, CI 122, contacts 116, 120, and pads 118). In other examples, one or more components of device 100 (e.g., CC 142, CI 122, contacts 116, 120, or pads 118) may have different shapes, such as pillars, pads, bumps, balls, traces, etc.

[0051] exist Figure 1A In this configuration, TIL 114 has a height of 124 (e.g., 40 to 80 micrometers) between the die 102 and the substrate 110. Figure 1BIn this configuration, the distance between the first contact 116 and the next contact 116 corresponds to the contact spacing 132. The distance between the first edge of contact 116 and the opposite edge of contact 116 corresponds to the contact size 130.

[0052] In some embodiments, device 100 includes a thermal interface material (TIM) 144 located between CC 142 and TIL 114. For example, TIM 144 corresponds to a thermally conductive gap filler, which may be referred to as a thermal gap filler (TFG). In certain embodiments, TIM 144 may comprise silver-tin (AgSn) solder paste, silicone, polyurethane, or both. In a particular aspect, TIM 144 is used to fill the gap between TIL 114 and CC 142 (extending through TIL 114) to provide efficient thermal conduction from TIL 114 to CI 122, which enables further heat dissipation via CC 142.

[0053] In some embodiments, device 100 includes an adhesive 112 located between TIL 114 and die 102. In certain aspects, adhesive 112 corresponds to a light-definable adhesive or dry film adhesive. In some embodiments, device 100 includes a molding compound (MC) 104 that at least partially encapsulates die 102, contact 116, adhesive 112, CC 142, TIL 114, TIM 144, or combinations thereof. In some embodiments, device 100 includes an MC 106 that at least partially encapsulates pad 118, CI 122, contact 120, substrate 110, or combinations thereof. In examples, MC 104, MC 106, or both comprise epoxy, silicone, polyimide, alumina, or combinations thereof.

[0054] In a specific aspect, one or more CCs in CC 142 (e.g., heat pipes) provide a primary path for heat dissipation, which is improved by TIL 114. TIL 114 improves the overall thermal conductivity to dissipate heat from die 102 compared to using only molding compounds (e.g., MC 104, MC 106, or both) for heat dissipation. In a specific aspect, having TIL 114 reduces the temperature rise of device 100 (e.g., a reduction of 16 degrees Celsius) compared to using only molding compounds for heat dissipation. In a specific embodiment, the thermally conductive material of TIL 114 has a first thermal conductivity (e.g., 36 W / mK) that is greater than the second thermal conductivity of MC 104 (e.g., 1.3 W / mK), the third thermal conductivity of MC 106, or both. Therefore, TIL 114 improves heat dissipation and achieves higher computing performance within the small form factor of device 100.

[0055] Figure 2AA cross-sectional profile view of a device 200 (e.g., an exemplary IC device) including TIL 114A and TIL 114B is shown, and Figure 2B Examples of TIL 114A and TIL 114B are shown, as well as Figure 2A A top view of the cross-section of device 200.

[0056] Figure 2A The device 200 includes the same as the one mentioned above. Figure 1A and Figure 1B Many components and features are identical to those described above. These components and features are physically and operationally similar to those referenced above. Figure 1A and Figure 1B The described components and features are the same, and in Figure 2A and Figure 2B The same reference numerals are used to denote them. In some specific embodiments, device 200 includes... Figure 1A and Figure 1B Device 100 has all the same features and components as device 200; however, for the sake of simplification and to highlight the differences between device 100 and device 200, Figure 2A and Figure 2B The text has been omitted (or not marked with figure labels). Figure 1A and Figure 1B Some components and features are illustrated in the figures. The omission of such features and reference numerals should not be construed as meaning that... Figure 2A and Figure 2B The features and components are limited to those specifically stated below. For example, although Figure 2A The active circuitry of die 102 is not shown, but die 102 may include active circuitry, as shown in reference. Figure 1A and Figure 1B As described.

[0057] exist Figure 1A and Figure 1B In the example illustrated, device 100 includes die 102, wherein a single TIL 114 is adjacent to a single portion of die 102 (e.g., corresponding to hot spot 108). Figure 2A and Figure 2B In the example illustrated, device 200 includes a die 102 having a TIL 114A adjacent to a first portion of the die 102 (e.g., corresponding to hotspot 108A) and a TIL 114B adjacent to a second portion of the die 102 (e.g., corresponding to hotspot 108B). It should be noted that... Figure 2A and Figure 2BThe device 200 illustrated herein, comprising two TILs 114 adjacent to two portions of die 102, is merely an example. In other examples, without departing from the scope of this disclosure, device 200 may include more than two TILs 114 adjacent to corresponding portions of die 102.

[0058] exist Figure 2A In this embodiment, device 200 includes a redistribution layer (RDL) 208 located on side 150 of die 102. RDL 208 electrically connects contacts 116 of die 102 to pads 216 on CC 142. For example, contacts 116 are connected to one or more pads 216 via RDL 208. Pads 216 are connected to contacts 120 on side 152 of substrate 110 via CC 142, pads 118, and CI 122. In a particular embodiment, substrate 110 includes metal traces 210 to electrically connect the various contacts 120 to each other, to one or more other dies of device 200, to one or more other devices, or combinations thereof. In a particular aspect, device 200 includes an adhesive 112 located between portions of RDL 208 and portions of TILs 114A and 114B.

[0059] Figure 3A A cross-sectional profile view of a device 300 (e.g., an exemplary stacked IC device) including TIL 114A and TIL 114B is illustrated, and Figure 3B Examples Figure 3A A top view of device 300. Device 300 includes components as described above. Figures 1A to 2B Many components and features are identical to those described herein. Such components and features are physically and operationally identical to those described above and are designated using the same reference numerals. In some specific embodiments, device 300 includes components and features identical to those described herein. Figure 1A and Figure 1B Device 100 and / or Figure 2A and Figure 2B Device 200 has the same features and components as device 100; however, for the sake of simplification and to highlight the differences between devices 100, 200 and 300, Figure 3A and Figure 3B Some such components and features have been omitted (or not labeled with reference numerals). The omission of such features and reference numerals should not be construed as meaning that... Figure 3A and Figure 3B The features and components are limited to those specifically indicated below.

[0060] exist Figure 1A and Figure 2A In the example illustrated, one or more TIL 114s are located between die 102 and substrate 110. Figure 3A and Figure 3B In the example illustrated, one or more additional dies 306 are located between one or more TIL 114s and the substrate 110. For example, die 306A is located between TIL 114A and the substrate 110, and die 306B is located between TIL 114B and the substrate 110. In a particular embodiment, one or more CC 342s extend through the TIL 114, and one or more through-silicon vias (TSVs) 308 extend through the die 306. In a particular embodiment, TIL 114A is adjacent to a first portion of die 102 corresponding to hot spot 108A, and TIL 114B is adjacent to a second portion of die 102 corresponding to hot spot 108B. CC 342s, TSVs 308s, one or more pads 318, or combinations thereof, contain various conductive materials such as copper, tin, aluminum, silver, gold, lead, bismuth, or combinations thereof. In a particular embodiment, at least one of CC 342, TSV 308, or pad 318 comprises a first conductive material not included in the other of CC 342, TSV 308, or pad 318. In a particular embodiment, one or more of CC 342, TSV 308, or pad 318 comprises a thermally conductive material. For example, one or more of CC 342, TSV 308, or pad 318 are used for electrical signal propagation, heat propagation, or both.

[0061] The substrate 110 includes a contact 120 located on a side 152 of the substrate 110. (See reference...) Figure 1A As described, contact 120 is electrically connected to pad 118 via CI 122. A first subset of pad 118 is electrically connected to a first subset of contact 116 via CC 142. A second subset of pad 118 is electrically connected to pad 318 via TSV 308, and pad 318 is electrically connected to a second subset of contact 116 via CC 342. For example, pad 118 is electrically connected to contact 116 via CC 142 extending through MC 104. As another example, pad 118 is electrically connected to pad 318 via TSV 308 extending through die 306A. Pad 318 is electrically connected to contact 116 via CC 342 extending through TIL 114A. As yet another example, pad 118 is electrically connected to pad 318 via TSV 308 extending through die 306B. Pad 318 is electrically connected to contact 116 via CC 342, which extends through TIL 114B.

[0062] exist Figure 3B In the diagram, contact 116 is illustrated as having the same contact size. Figure 3AIn the first subset of contacts 116 located on CC 142, the first contact size is different from (e.g., larger than) the second contact size of the second subset of contacts 116 located on CC 342. In a particular embodiment, device 300 includes a TIM 304 located between heat sink 302 and die 102. TIM 304 is adjacent to the side of die 102 opposite to side 150. Heat sink 302 is configured to provide additional heat dissipation for die 102 of device 300.

[0063] In a particular embodiment, die 306A corresponds to a first high-bandwidth memory (HBM) module, and die 306B corresponds to a second HBM module. The first HBM module (e.g., die 306A) includes a first set of conductive connections (e.g., including a first TSV 308) extending through the first HBM module and aligned with a first set of CC 342 extending through TIL 114A to a first set of contacts 116. The second HBM module (e.g., die 306B) includes a second set of conductive connections (e.g., including a second TSV 308) extending through the second HBM module and aligned with a second set of CC 342 extending through TIL 114B to a second set of contacts 116.

[0064] In some implementations, die 102 is a first chiplet, die 306A is a second chiplet, and die 306B is a third chiplet, and the first, second, and third chiplets are designed to operate in combination with each other. For illustration, in some implementations, the active circuitry of the first chiplet / die 102 includes one or more first functional circuit blocks, the circuitry of the second chiplet / die 306A includes one or more second functional circuit blocks, and the circuitry of the third chiplet / die 306B includes one or more third functional circuit blocks, wherein one or more first functional circuit blocks, one or more second functional circuit blocks, one or more third functional circuit blocks, or combinations thereof, are operationally interdependent.

[0065] Using chiplets arranged and interconnected as a 3D stacked IC to form device 300 offers various benefits compared to providing the same functional circuitry in a single monolithic chip. For example, each chiplet is smaller than a monolithic die containing all the same functional circuitry blocks. Since yield losses in IC manufacturing tend to increase with die size, using smaller dies can reduce yield losses in the IC manufacturing process (i.e., increase yield). Another benefit is that chiplets can be manufactured in different locations and / or by different manufacturers, and in some cases, using different manufacturing technologies (e.g., different manufacturing technology nodes). As an example, one die of a chiplet-based integrated device (e.g., die 102 of device 300) may include components (e.g., interconnects, transistors, etc.) having a first minimum size, and another die of a chiplet-based integrated device (e.g., die 306A of device 300) may include components (e.g., interconnects, transistors, etc.) having a second minimum size, where the second minimum size is larger than the first minimum size. In contrast, all circuitry on a monolithic die is manufactured using the same manufacturing technology and equipment. Therefore, when manufacturing a monolithic die, the entire die may be subject to the most stringent manufacturing constraints of the most complex components of the monolithic die. In contrast, when using chiplets, different chiplets can be manufactured using different manufacturing technologies (e.g., different manufacturing technology nodes), and only one or more chiplets containing the most complex components are subject to the most stringent manufacturing constraints. In this arrangement, chiplets manufactured using cheaper and / or higher-yield manufacturing technologies can be integrated with chiplets manufactured using more expensive and / or lower-yield manufacturing technologies to form an IC (e.g., device 300), resulting in overall savings. Furthermore, in some cases, the design of chiplets can change as technology improves. Chiplet stacking allows the integration of such new chiplet designs with older chiplet designs to form stacked IC devices, which increases manufacturing flexibility and reduces design costs.

[0066] Figure 4A A cross-sectional profile view of a device 400 (e.g., an exemplary IC device) including TIL 114A and TIL 114B is shown, and Figure 4B Examples of TIL 114A and TIL 114B are shown, as well as Figure 4A A top view of the cross-section of device 400.

[0067] Device 400 includes the same as described above. Figures 1A to 3B Many components and features are identical to those described herein. Such components and features are physically and operationally identical to those described above and are designated using the same reference numerals. In some specific embodiments, device 400 includes components and features identical to those described herein. Figure 1A and Figure 1B Device 100 Figure 2A and Figure 2B Device 200 and / or Figure 3A and Figure 3B Device 300 has the same features and components as device 100; however, for the sake of simplification and to highlight the differences between devices 100, 200, 300 and 400, Figure 4A and Figure 4B Some such components and features have been omitted (or not labeled with reference numerals). The omission of such features and reference numerals should not be construed as meaning that... Figure 4A and Figure 4B The features and components are limited to those specifically indicated below.

[0068] exist Figure 4A and Figure 4B In the example illustrated herein, device 400 includes a plurality of dies 102 and TILs 114 adjacent to one or more of the dies 102. For example, device 400 includes dies 102A, dies 102B, and dies 102C. Device 400 also includes TIL 114A adjacent to one side of die 102A and TIL 114B adjacent to one side of die 102C. It should be understood that device 400 including three dies is provided as an illustrative example, and in other examples, device 400 may include fewer than or more than three dies 102.

[0069] In a particular embodiment, device 400 includes an RDL 208 located between die 102 and TIL 114 and / or MC 104. RDL 208 electrically connects contacts 116 of die 102 to pads 216 of CC 142. In an example, a first set of CC 142 extends from first set of pads 216 to first set of pads 118. The first set of pads 216 is electrically connected via a first portion of RDL 208 to a first set of contacts 116 coupled to a first side of die 102A. The first set of contacts 116 is electrically connected to a first active circuit of die 102A. Device 400 includes a TIL 114A adjacent to the first side of die 102A. TIL 114A includes one or more first THV 140s extending through TIL 114A and aligned with the first set of contacts 116. A subset of the first set of CC 142 extends through one or more first THV 140s of TIL 114A.

[0070] In another example, the second set of CC 142 extends from the second set of pads 216 to the second set of pads 118. The second set of pads 216 is electrically connected via a second portion of RDL 208 to the second set of contacts 116 coupled to the first side of die 102B. The second set of contacts 116 is electrically connected to the second active circuitry of die 102B. The second set of CC 142 extends through MC 104 and does not extend through any TIL.

[0071] In yet another example, a third set of CCs 142 extends from a third set of pads 216 to a third set of pads 118. The third set of pads 216 is electrically connected via a third portion of RDL 208 to a third set of contacts 116 coupled to a first side of die 102C. The third set of contacts 116 is electrically connected to a third active circuit of die 102C. TIL 114B includes one or more second THVs 140 extending through TIL 114B and aligned with the third set of contacts 116. A subset of the third set of CCs 142 extends through one or more of the second THVs 140 of TIL 114B.

[0072] Pad 118 is electrically connected to metal trace 210 of substrate 110 via CI 122 and contact 120, as referenced. Figure 2A As described. In the example, the first group of contacts 120 is electrically connected to the first group CC 142, the second group of contacts 120 is electrically connected to the second group CC 142, and the third group of contacts 120 is electrically connected to the third group CC 142.

[0073] In some implementations, die 102A is a first chiplet, die 102B is a second chiplet, and die 102C is a third chiplet, and the first, second, and third chiplets are designed to operate in combination with each other. For illustration, in some implementations, the active circuitry of the first chiplet / die 102A includes one or more first functional circuit blocks, the circuitry of the second chiplet / die 102B includes one or more second functional circuit blocks, and the circuitry of the third chiplet / die 102C includes one or more third functional circuit blocks, wherein the one or more first functional circuit blocks, the one or more second functional circuit blocks, the one or more third functional circuit blocks, or combinations thereof, are operationally interdependent.

[0074] Die 102A (e.g., a first chiplet) is separated from substrate 110 by TIL 114A, and die 102C (e.g., a third chiplet) is separated from substrate 110 by TIL 114B. In a particular embodiment, die 102A includes a system-on-chip (SOC) device, die 102B includes an LNA, a switch, or both, and die 102C includes a radio frequency power amplifier (RF-PA). In a particular aspect, overheating may degrade the performance of die 102A (e.g., the SOC device) and die 102C (e.g., the RF-PA). The improved heat dissipation provided by TIL 114A and TIL 114B improves the performance of die 102A and die 102C. In a particular aspect, TIL 114 increases the lifetime of one or more components of device 400. For example, TIL 114B increases the high-temperature operating lifetime (HTOL) of the RF-PA (e.g., a gallium arsenide (GaAs) power amplifier). In an exemplary example, having TIL 114B can double the HTOL of the RF-PA.

[0075] exist Figure 4B In this example, TIL 114A and TIL 114B are illustrated as having THV 140, which have the same size corresponding to (e.g., greater than or equal to) the contact size 130 and a distance corresponding to (e.g., less than or equal to) the contact pitch 132. In other examples, TIL 114B has a second THV 140, which have a different size, shape, pitch, or combination thereof from the first THV 140 of TIL 114A, to accommodate the second contact size 130, second contact pitch 132, and second contact shape of the third set of contacts 116 of die 102C, which are different from the first contact size 130, first contact pitch 132, and / or first contact shape of the first set of contacts 116 of die 102A.

[0076] Figure 5A A cross-sectional profile view of a device 500 (e.g., an exemplary IC device) including TIL 114 is shown, and Figure 5B Examples of TIL 114 and Figure 5A A top view of the cross-section of device 500.

[0077] Device 500 includes the same as the one mentioned above. Figures 1A to 4B Many components and features are identical to those described above. Such components and features are physically and operationally identical to those described above and are designated using the same reference numerals. In some specific embodiments, device 500 includes components and features identical to those described above. Figure 1A and Figure 1B Device 100 Figure 2Aand Figure 2B Device 200, Figure 3A and Figure 3B Device 300 and / or Figure 4A and Figure 4B Device 400 has the same features and components as all other devices; however, for the sake of simplification and to highlight the differences between devices 100, 200, 300, 400, and 500, Figure 5A and Figure 5B Some such components and features have been omitted (or not labeled with reference numerals). The omission of such features and reference numerals should not be construed as meaning that... Figure 5A and Figure 5B The features and components are limited to those specifically indicated below.

[0078] exist Figure 5A and Figure 5B In the example illustrated, device 500 includes a heat rod 502 extending through TIL 114 and THV 540. For example, one or more CCs in CCs 142 correspond to the heat rod 502 extending through TIL 114 and THV 540. The heat rod 502 is configured to dissipate additional heat from device 500. In a particular aspect, one or more CCs in CCs 142 extending through TIL 114 and THV 140 are connected to the I / O circuitry of die 102 to provide a data path between die 102 and a second device coupled to substrate 110.

[0079] In a particular embodiment, device 500 includes a TIM 144 located between heat rod 502 and TIL 114. In a particular aspect, device 500 includes a TIM 144 located between TIL 114 and a subset of CC 142 extending through TIL 114.

[0080] exist Figure 5BIn this embodiment, example 550 of TIL 114 includes a THV 540 having a shape corresponding to (e.g., matching) the shape of the heating rod 502 and a size corresponding to (e.g., greater than or equal to) the size of the heating rod 502. Example 552 of TIL 114 includes THV 540 and also includes one or more THVs 140 having a shape corresponding to (e.g., matching) the shape of the contact 116 and a size corresponding to (e.g., greater than or equal to) the size of the contact 116. In a particular embodiment, the heating rod 502 has a non-circular cross-section, and the THV 540 has a non-circular cross-section adapted to the cross-section of the heating rod 502. For example, the heating rod 502 has a first elliptical cross-section, and the THV 540 has a second elliptical cross-section large enough to accommodate (e.g., fit) the first elliptical cross-section and the TIM 144. A top cross-sectional view of device 500 includes example 550 of TIL 114. In another embodiment, device 500 may include example 552 of TIL 114.

[0081] Figure 6A A cross-sectional profile view of a device 600 (e.g., an exemplary IC device) including TIL 114 is shown, and Figure 6B Examples of TIL 114 and Figure 6A A top view of a portion of device 600.

[0082] Device 600 includes the same as the one mentioned above. Figures 1A to 5B Many components and features are identical to those described herein. Such components and features are physically and operationally identical to those described above and are designated using the same reference numerals. In some specific embodiments, device 600 includes components and features identical to those described herein. Figure 1A and Figure 1B Device 100 Figure 2A and Figure 2B Device 200, Figure 3A and Figure 3B Device 300, Figure 4A and Figure 4B Device 400 and / or Figure 5A and Figure 5B Device 500 has the same features and components as all other devices; however, for the sake of simplification and to highlight the differences between devices 100, 200, 300, 400, 500, and 600, Figure 6A and Figure 6B Some such components and features have been omitted (or not labeled with reference numerals). The omission of such features and reference numerals should not be construed as meaning that... Figure 6A and Figure 6BThe features and components are limited to those specifically indicated below.

[0083] exist Figure 5A and Figure 5B In the example illustrated, device 500 includes a hotspot 502 offset from a hotspot 108 of die 102. For example, hotspot 108 corresponds to a portion of die 102 adjacent to a portion of CC 142 that is not a hotspot 502. Figure 6A and Figure 6B In the example illustrated, the end of the heat pipe 502 is adjacent to a portion of the wick 102 corresponding to the hot spot 108. Figure 6B In this example 652 of TIL 114, there are THV 540 and one or more THV 140, which have a shape corresponding to (e.g., matching) the shape of contact 116 and a size corresponding to (e.g., greater than or equal to) the size of contact 116. A cross-sectional top view of device 600 includes example 652 of TIL 114.

[0084] Figure 7 An example of TIL 114 and a cross-sectional top view of a portion of a device 700 (e.g., an exemplary IC device) including TIL 114 are illustrated. TIL 114 includes THV 140, which has a shape corresponding to (e.g., matching) the shape of contact 116 and a size corresponding to (e.g., greater than or equal to) the size of contact 116. The cross-sectional top view of a portion of device 700 includes TIM 144 located between contact 116 and TIL 114.

[0085] Although Figures 1A to 7 Each of these examples illustrates an IC device comprising one or more dies and one or more TIL 114s, but the IC devices disclosed herein can be integrated with or included within a wide variety of other devices. For example, the devices disclosed herein comprising one or more dies and one or more TIL 114s may include components such as power management integrated circuits (PMICs), application processors, modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. In such devices, the die or chiplet may operate as any component (or combination of these components) of these components that include active circuitry.

[0086] Exemplary process for manufacturing integrated circuit devices including thermal dielectric layers

[0087] In some specific implementations, manufacturing an IC device (such as any of the devices 100, 200, 300, 400, 500, 600, or 700) involves several processes. Figures 8A to 8E Examples are provided or manufactured as per the reference. Figures 1A to 7 The exemplary process stages of an IC device comprising at least one TIL described in any of the above. In some specific implementations, Figures 8A to 8E The process can be used to provide (e.g., during manufacturing). Figures 1A to 7 One or more of the following devices: 100, 200, 300, 400, 500, 600 or 700.

[0088] It should be noted that Figures 8A to 8E The process steps may be combined to simplify and / or clarify the steps for providing or manufacturing an integrated device. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more processes may be substituted or replaced without departing from the scope of this disclosure. In the following description, reference is made to various exemplary stages of the process steps, which are... Figures 8A to 8E The numbers (using circled numbers) are numbered.

[0089] Figure 8A Phase 1 illustrates TIL 114. In a particular embodiment, TIL 114 comprises alumina ceramic. Phase 2 illustrates the state after THV 140 and THV 540 are formed in TIL 114. For example, drilling can be used to form THV 140 and 540. In a particular example, laser ablation is used to form THV 140 and 540. Phase 3 illustrates the state after adhesive 112 is applied to side 802 of TIL 114. In a particular example, a deposition process, spin coating process, or similar process can be used to apply adhesive 112. In a particular aspect, adhesive 112 may be light-defined.

[0090] Figure 8B Phase 4 illustrates the state after the pre-packaged die 804 is aligned with the TIL 114. For example, the pre-packaged die 804 includes a die 102 having contacts 116 located on side 150 of the die 102. (See reference...) Figure 1A As described, contact 116 is electrically connected to CC 142. A first subset of contact 116 is electrically connected to a first CC 142 aligned with one or more TILs 114, and a second subset of contact 116 is electrically connected to a second CC 142 that extends through MC 104 and does not need to be aligned with any TIL.

[0091] The first CC 142 is aligned with the THV 140 of TIL 114. In the illustrated embodiment, CC 142 includes a heat pipe 502 adjacent to a portion of the die 102 corresponding to the hot spot 108, as referenced. Figure 6A As described. The heat pipe 502 is aligned with the THV 540. Stage 5 illustrates the state after the pre-encapsulated die 804 is attached to the TIL 114 using adhesive 112.

[0092] Figure 8C Stage 6 illustrates the state after TIM 144 has been applied to fill the gap between the thermally conductive materials CC 142 and TIL 114. In certain examples, TIM 144 may be applied using a deposition process, spin coating process, or similar process, and may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners. In certain aspects, TIM 144 comprises solder paste. In certain aspects, TIM 144 comprises silver, tin, or both.

[0093] Phase 7 illustrates the state after MC 104 is disposed on die 102 and between CC 142 and TIL 114 to form a pre-packaged die 804. In a particular example, MC 104 may be applied using a deposition process, spin coating process, or similar process, and may subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners.

[0094] Figure 8D Stage 8 illustrates the state after a material removal process is applied to pre-packaged die 804 to form pre-packaged die 806. For example, a material removal process is performed to remove at least a portion of MC 104, TIM 144, CC 142, or a combination thereof to expose the surfaces of CC 142, hot rod 502, TIM 144, TIL 114, or a combination thereof. The material removal process may include grinding operations, patterning operations, etching processes, drilling operations, laser ablation operations, other targeted material removal operations, or combinations thereof. After performing the material removal process, TIL 114 has a height of 124 (e.g., 40 micrometers to 80 micrometers).

[0095] Phase 9 illustrates the state after pads 118 and CI 122 are formed on the pre-packaged die 806 to form the pre-packaged die 808. For example, pads 118 and CI 122 may include electrical connections (e.g., microbumps, conductive pads, or pillars) to form an electrical connection with contacts 116 of die 102 via CC 142. Pads 118 and CI 122 may be formed using one or more plating processes and one or more patterning processes. In a particular embodiment, CI 122 corresponds to solder bumps (e.g., a grid or array of solder bumps) formed on pads 118 located on CC 142.

[0096] Figure 8E Stage 10 illustrates the state after the pre-packaged die 808 and the package substrate 810 are aligned. In this example, the package substrate 810 includes contacts 120 located on the surface of substrate 110. In a particular embodiment, substrate 110 includes metal traces 210 electrically connected to the contacts 120, as referenced. Figure 2A As described. One or more contacts 120 are aligned with corresponding CI 122. In a particular embodiment, heat is applied to CI 122 before or after alignment with the contacts 120.

[0097] Stage 11 illustrates the state after the pre-packaged die 808 is attached to the package substrate 810 and MC 106 is deposited. For example, heating / reflowing can be performed on CI 122 to electrically connect CI 122 to contact 120. MC 106 is disposed on MC 104 and TIL 114 and between the surfaces of pad 118, CI 122, and contact 120. In a particular example, MC 106 can be applied using a deposition process, spin coating process, or similar process, and can subsequently be cured or hardened by exposure to light, heat, and / or chemical hardeners.

[0098] Following stage 11 in Figure 8, the formation of device 600 (e.g., a packaged IC device) is completed. However, in some specific implementations, one or more similar operations may be performed to form... Figures 1A to 5B One of devices 100, 200, 300, 400, or 500. In a particular embodiment, CC 142 has the same size excluding the heat pipe 502, or a combination of both, as referenced. Figure 1A Device 100 is described. In a particular embodiment, during phase 4, the pre-packaged die 804 is aligned with multiple TILs (such as TIL 114A and TIL 114B), as referenced. Figure 2A The device 200 is described. In some embodiments, the pre-packaged die 804 may include an RDL 208 located between the contact 116 and CC 142, as referenced. Figure 2AThe device 200 is described.

[0099] In some implementation schemes, such as reference Figure 3A As described in device 300, a first subset of contact 116 is electrically connected to CC 342, which extends through one or more TILs 114, and a second subset of contact 116 is electrically connected to CC 142, which extends through MC 104. During phase 4, CC 342 is aligned with TILs 114A and 114B, and CC 142 does not need to be aligned with any TIL. After phase 5, pads 318 are formed on CC 342. TSV 308 of die 306A is electrically connected to the corresponding pads 318 on TIL 114A, and TSV 308 of die 306B is electrically connected to the corresponding pads 318 on TIL 114B. In a particular embodiment, manufacturing proceeds to phase 9. During phase 9, pads 118 are formed on CC 142 and TSV 308, and CI 122 is formed on pads 118. In a particular implementation, after stage 11, TIM 304 is deposited on die 102, and heat sink 302 is attached to TIM 304, as referenced. Figure 3A The device 300 is described.

[0100] In certain implementations, multiple pre-packaged dies are aligned with multiple TILs. For example, during Phase 4, a subset of the electrical connections of CC142 to die 102A is aligned with the THV 140 of TIL 114A, and another subset of the electrical connections of CC142 to die 102C is aligned with the THV 140 of TIL 114B, as referenced. Figure 4A The device 400 is described. In a particular embodiment, the heat pipe 502 is offset from the hot spot 108, as referenced. Figure 5A The device 500 is described.

[0101] Exemplary flowchart of a method for manufacturing an integrated device including a thermal interposer.

[0102] In some specific implementations, manufacturing IC devices involves several processes. Figure 9 An exemplary flowchart illustrating a method 900 for providing or manufacturing an IC device including a thermally insulating layer is shown. In some specific implementations, Figure 9 Method 900 can be used to provide or manufacture Figures 1A to 7 Any device in the 100, 200, 300, 400, 500, 600 or 700 series.

[0103] It should be noted that Figure 9 Method 900 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated devices. In some implementations, the order of the processes may be changed or modified.

[0104] Method 900 includes forming a thermally conductive interlayer (TIL) at frame 902, comprising one or more through-holes (THVs) of thermally conductive material. For example, Figure 8A Phase 2 illustrates and describes an example of forming a TIL 114, which includes a thermally conductive material having one or more THV 140, one or more THV 540, or a combination thereof.

[0105] Method 900 includes forming a set of conductive connections at block 904 to one or more first contacts of a die, the die including a set of contacts coupled to a first side of the die, wherein the die includes active circuitry coupled to the set of contacts, and wherein the set of contacts includes one or more first contacts. For example, Figure 8B Phase 4 illustrates and describes an example of a pre-packaged die 804 including a CC 142 coupled to contact 116. Die 102 includes contact 116 coupled to side 150 of die 102. Die 102 includes active circuitry coupled to contact 116. One or more plating processes and one or more patterning processes may be used to form contact 116 on die 102, form CC 142 on contact 116, or a combination thereof.

[0106] Method 900 includes attaching the TIL to the die at frame 906 using a set of conductive connectors extending through one or more THVs to couple to one or more first contacts. For example, Figure 8B Phase 5 illustrates and describes an example of attaching TIL 114 to die 102 using adhesive 112. A first subset of CC 142 extends through THV 140 of TIL 114 to couple to a first subset of contacts 116.

[0107] Exemplary electronic devices

[0108] Figure 10 Examples of various electronic devices include or are integrated with any of devices 100, 200, 300, 400, 500, 600, or 700. For example, mobile phone device 1002, laptop computer device 1004, fixed-location terminal device 1006, wearable device 1008, or vehicle 1010 (e.g., automotive or aerospace equipment) may include device 1000. Device 1000 may include any of the devices 100, 200, 300, 400, 500, 600, or 700 described herein. Figure 10The devices 1002, 1004, 1006, and 1008 illustrated herein, as well as vehicle 1010, are merely exemplary. Other electronic devices may also feature device 1000, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0109] Figure 1 to Figure 10 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that Figures 1 to... Figure 10 The corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some specific embodiments, Figures 1 to... Figure 10 The descriptions and their corresponding information can be used to manufacture, create, provide, and / or produce equipment and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0110] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0111] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning can refer to an object that partially or completely encloses another object. The terms “top” and “bottom” are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. Values ​​from about X to XX can refer to values ​​between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X".For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "Multiple" components can include all possible components or only some of all possible components. For example, if a device comprises ten components, the term "multiple components" can refer to all ten components or only some of those ten components.

[0112] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0113] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0114] Further examples are described below to facilitate understanding of this disclosure.

[0115] According to Example 1, a device includes a die comprising: a set of contacts coupled to a first side of the die; and active circuitry coupled to the set of contacts. The device further includes a thermally conductive interlayer (TIL) adjacent to the first side of the die, the TIL comprising one or more through-holes (THVs) having aligned with one or more of the first contacts. The device also includes a set of conductive connectors coupled to the one or more first contacts and extending through the THVs.

[0116] Example 2 includes the device according to Example 1, and the device further includes a packaging substrate including a second set of contacts, wherein one or more second contacts in the second set of contacts are coupled to the set of conductive connectors.

[0117] Example 3 includes a device according to Example 1 or Example 2, wherein at least one of the one or more THVs has an elliptical cross-section.

[0118] Example 4 includes the device according to Example 3, wherein at least one of the conductive connectors in the set of conductive connectors corresponds to a non-circular heat rod extending through the at least one THV having the elliptical cross-section.

[0119] Example 5 includes a device according to any one of Examples 1 to 4, wherein at least one of the one or more THVs has a substantially circular cross-section.

[0120] Example 6 includes a device according to any one of Examples 1 to 5, wherein at least one of the conductive connectors in the group of conductive connectors comprises copper.

[0121] Example 7 includes a device according to any one of Examples 1 to 6, wherein the thermally conductive material comprises alumina ceramic.

[0122] Example 8 includes a device according to any one of Examples 1 to 7, wherein the thermally conductive material comprises aluminum nitride.

[0123] Example 9 includes a device according to any one of Examples 1 to 8, wherein the thermally conductive material comprises silicon carbide (SiC).

[0124] Example 10 includes a device according to any one of Examples 1 to 9, wherein the die corresponds to a small chip separated from the packaging substrate by the TIL.

[0125] Example 11 includes the device according to Example 10, and the device further includes a second chip separated from the package substrate by a second TIL.

[0126] Example 12 includes a device according to any one of Examples 1 to 11, wherein the TIL dissipates heat from the die.

[0127] Example 13 includes a device according to any one of Examples 1 to 12, and the device further includes: a heat sink; and a thermal interface material (TIM) adjacent to a second side of the die opposite to the first side, wherein the TIM is located between the heat sink and the die.

[0128] Example 14 includes a device according to any one of Examples 1 to 13, and the device further includes a high bandwidth memory (HBM) module, the high bandwidth memory (HBM) module including a set of second conductive connections extending through the HBM module and aligned with the set of conductive connections.

[0129] According to Example 15, a manufacturing method includes: forming a thermally conductive interlayer (TIL) comprising a thermally conductive material having one or more through-holes (THVs); forming a set of conductive connectors coupled to one or more first contacts of a die, the die including a set of contacts coupled to a first side of the die, wherein the die includes active circuitry coupled to the set of contacts, and wherein the set of contacts includes the one or more first contacts; and attaching the TIL to the die using the set of conductive connectors extending through the one or more THVs to couple to the one or more first contacts.

[0130] Example 16 includes the method according to Example 15, and the method further includes filling the gap between the set of conductive connectors and the thermally conductive material.

[0131] Example 17 includes the method according to Example 15 or Example 16, and the method further includes forming solder bumps on the set of conductive connectors; and electrically connecting one or more second contacts of the package substrate to the solder bumps.

[0132] Example 18 includes the method according to any one of Examples 15 to 17, wherein at least one of the one or more THVs has an elliptical cross-section.

[0133] Example 19 includes the method according to Example 18, wherein at least one of the conductive connectors in the set of conductive connectors corresponds to a non-circular heat rod extending through the at least one THV having the elliptical cross-section.

[0134] Example 20 includes the method according to any one of Examples 15 to 19, wherein at least one of the one or more THVs has a substantially circular cross-section.

[0135] Example 21 includes the method according to any one of Examples 15 to 20, wherein at least one of the conductive connectors in the set of conductive connectors comprises copper.

[0136] Example 22 includes the method according to any one of Examples 15 to 21, wherein the thermally conductive material comprises alumina ceramic.

[0137] Example 23 includes the method according to any one of Examples 15 to 22, wherein the thermally conductive material comprises aluminum nitride.

[0138] Example 24 includes the method according to any one of Examples 15 to 23, wherein the thermally conductive material comprises silicon carbide (SiC).

[0139] Example 25 includes the method according to any one of Examples 15 to 24, wherein the die corresponds to a small chip separated from the packaging substrate by the TIL.

[0140] Example 26 includes the method according to any one of Examples 15 to 25, wherein the TIL dissipates heat from the die.

[0141] According to Example 27, a device includes a first chiplet, the first chiplet comprising: a first set of contacts coupled to a first side of the first chiplet; and a first active circuit coupled to the first set of contacts. The device further includes a first thermal interposer (TIL) adjacent to the first side of the first chiplet, the first TIL including a first thermally conductive material having one or more first through-holes (THVs) aligned with one or more of the first contacts in the first set. The device also includes a first set of conductive connectors coupled to the one or more first contacts and extending through the first THV. The device further includes a packaging substrate including a set of substrate contacts, one or more of the first substrate contacts being coupled to the first set of conductive connectors.

[0142] Example 28 includes the device according to Example 27, and the device further includes a second chiplet, the second chiplet including: a second set of contacts coupled to a second side of the second chiplet; and a second active circuit coupled to the second set of contacts. The device also includes a second TIL adjacent to the second side of the second chiplet, the second TIL including a second thermally conductive material having one or more second THVs aligned with one or more second contacts in the second set of contacts. The device further includes a second set of conductive connections coupled to the one or more second contacts and extending through the second THV, one or more second substrate contacts in the set of substrate contacts being coupled to the second set of conductive connections.

[0143] Example 29 includes a device according to Example 27 or Example 28, wherein the first THV of the one or more first THVs has an elliptical cross-section.

[0144] Example 30 includes the device according to Example 29, wherein a first conductive connector in the first set of conductive connectors corresponds to a non-circular hot rod extending through the first THV.

[0145] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A device, the device comprising: The die includes: A set of contacts, said set of contacts being coupled to a first side of the die; and An active circuit, the active circuit being coupled to the set of contacts; A thermal interlayer (TIL) adjacent to the first side of the die, the TIL comprising a thermally conductive material having one or more through-holes (THVs) aligned with one or more first contacts in the set of contacts; and A set of conductive connectors, said set of conductive connectors being coupled to said one or more first contacts and extending through said THV.

2. The device of claim 1, further comprising a packaging substrate, the packaging substrate including a second set of contacts, wherein one or more second contacts in the second set of contacts are coupled to the set of conductive connectors.

3. The device according to claim 1, wherein at least one of the one or more THVs has an elliptical cross-section.

4. The device of claim 3, wherein at least one of the conductive connectors corresponds to a non-circular heat rod extending through the at least one THV having the elliptical cross-section.

5. The device of claim 1, wherein at least one of the one or more THVs has a substantially circular cross-section.

6. The device according to claim 1, wherein at least one of the conductive connectors in the group of conductive connectors comprises copper.

7. The device according to claim 1, wherein the thermally conductive material comprises alumina ceramic.

8. The device according to claim 1, wherein the thermally conductive material comprises aluminum nitride.

9. The device according to claim 1, wherein the thermally conductive material comprises silicon carbide (SiC).

10. The device of claim 1, wherein the die corresponds to a small chip separated from the packaging substrate by the TIL.

11. The device of claim 10, further comprising a second chip separated from the packaging substrate by a second TIL.

12. The device of claim 1, wherein the TIL dissipates heat from the die.

13. The device according to claim 1, further comprising: heat sink; and A thermal interface material (TIM) is adjacent to a second side of the die opposite to the first side, wherein the TIM is located between the heat sink and the die.

14. The device of claim 1, further comprising a high-bandwidth memory (HBM) module, the high-bandwidth memory (HBM) module including a set of second conductive connectors extending through the HBM module and aligned with the set of conductive connectors.

15. A manufacturing method, the manufacturing method comprising: A thermally conductive interlayer (TIL) is formed, comprising one or more through-holes (THVs). A set of conductive connectors is formed to one or more first contacts of a die, the die including a set of contacts coupled to a first side of the die, wherein the die includes an active circuit coupled to the set of contacts, and wherein the set of contacts includes the one or more first contacts; as well as The TIL is attached to the die using a set of conductive connectors that extend through the one or more THVs to couple to the one or more first contacts.

16. The method of claim 15, further comprising filling the gap between the set of conductive connectors and the thermally conductive material.

17. The method according to claim 15, further comprising: Solder bumps are formed on the set of conductive connectors; as well as One or more second contacts of the packaging substrate are electrically connected to the solder bumps.

18. The method of claim 15, wherein at least one of the one or more THVs has an elliptical cross-section.

19. The method of claim 18, wherein at least one of the conductive connectors corresponds to a non-circular heat rod extending through the at least one THV having the elliptical cross-section.

20. The method of claim 15, wherein at least one of the one or more THVs has a substantially circular cross-section.

21. The method of claim 15, wherein at least one of the conductive connectors in the group of conductive connectors comprises copper.

22. The method of claim 15, wherein the thermally conductive material comprises alumina ceramic.

23. The method of claim 15, wherein the thermally conductive material comprises aluminum nitride.

24. The method of claim 15, wherein the thermally conductive material comprises silicon carbide (SiC).

25. The method of claim 15, wherein the die corresponds to a small chip separated from the packaging substrate by the TIL.

26. The method of claim 15, wherein the TIL dissipates heat from the die.

27. A device, the device comprising: The first small chip, the first small chip comprising: The first set of contacts is coupled to the first side of the first small chip; and A first active circuit is coupled to the first set of contacts; A first thermal interposer (TIL) is adjacent to the first side of the first chiplet, and the first TIL includes a first thermally conductive material having one or more first through-holes (THVs) aligned with one or more first contacts in the first set of contacts. A first set of conductive connectors, the first set of conductive connectors being coupled to the one or more first contacts and extending through the first THV; and The packaging substrate includes a set of substrate contacts, one or more first substrate contacts of the set of substrate contacts being coupled to the first set of conductive connectors.

28. The device of claim 27, further comprising: The second small chip includes: The second set of contacts is coupled to the second side of the second small chip; and A second active circuit is coupled to the second set of contacts; The second TIL, adjacent to the second side of the second chiplet, includes a second thermally conductive material having one or more second THVs aligned with one or more second contacts in the second set of contacts; and A second set of conductive connectors, the second set of conductive connectors being coupled to the one or more second contacts and extending through the second THV, one or more of the one set of substrate contacts being coupled to the second set of conductive connectors.

29. The device of claim 27, wherein the first THV of the one or more first THVs has an elliptical cross-section.

30. The device of claim 29, wherein the first conductive connector in the first group of conductive connectors corresponds to a non-circular hot rod extending through the first THV.

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