Trap characterization method and device of SiC MOSFET device based on body diode

Abstract

The embodiment of the invention provides a trap characterization method and device for a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device based on a body diode, and the method comprises the steps: 1, connecting the SiC MOSFET device in a constant-temperature environment through test equipment; step 2, grid electrode filling voltage and drain electrode voltage are applied to the SiC MOSFET device through test equipment, and trap filling is carried out on the SiC MOSFET device; 3, applying a grid test voltage and a body diode test current in a trap release stage through test equipment, and measuring a transient response curve of the body diode voltage; 4, repeating the steps 1-3, and obtaining a plurality of transient voltage curves at different temperatures; and step 5, carrying out fitting processing on the plurality of transient voltage curves, extracting a time constant spectrum of a trap, and calculating a trap energy level by adopting an Arrhenius formula based on the time constant spectrum of the trap so as to carry out trap characterization.

Description

Technical Field

[0001] This document relates to the field of semiconductor device technology, and in particular to a trap characterization method and apparatus for SiC MOSFET devices based on a body diode. Background Technology

[0002] Silicon carbide (SiC) materials possess advantages such as a large bandgap, high electron mobility, and high thermal conductivity, making them a focal point in fields like new energy and power electronics. However, due to the presence of carbon, the gate oxide layer and SiC / SiO2 interface in the device structure exhibit surface dangling bonds, carbon cluster-related defects, and near-interface oxide defects (NITs), leading to defect trapping problems. Compared to traditional Si / SiO2 interface states, the interface state density of SiC MOSFETs can be one to two orders of magnitude higher. The trapped charges in these interface states reduce the channel carrier density and create charged centers, resulting in low channel carrier mobility, only 5% of the bulk mobility. Furthermore, defect traps in the gate dielectric can cause increased gate leakage current and unstable threshold voltage, significantly limiting the application and development of SiC MOSFET devices.

[0003] Currently, characterization methods for SiC MOSFET trap effects mainly include high- and low-frequency CV testing, conductivity methods, pulse transfer characteristic testing, noise characteristic testing, and time-domain curve testing. Among these, high- and low-frequency CV testing is a commonly used interface state density (Dit) testing method. It only provides information on the interface trapped charge density, not the trapping cross-section. Furthermore, it requires the fabrication of additional SiC MOSFET capacitors. Low-frequency noise testing (LFN), random telegraph noise, and 1 / f noise can be used to obtain the energy levels of traps within SiC MOSFETs; however, these noise characteristic tests struggle to eliminate errors caused by intrinsic noise and cannot comprehensively analyze the trap location and physical origin. In traditional transient time-domain curve testing, the additional gate voltage applied during the trap release phase affects oxide layer trap release, thus reducing the accuracy of trap energy level extraction. Summary of the Invention

[0004] The purpose of this invention is to provide a trap characterization method and apparatus for SiC MOSFET devices based on a body diode, in order to solve the above-mentioned problems in the prior art.

[0005] This invention provides a trap characterization method for SiC MOSFET devices based on a body diode, comprising: Step 1: Connect the SiC MOSFET device placed in a constant temperature environment using the test equipment; Step 2: Apply gate fill voltage and drain voltage to the SiC MOSFET device using a testing device to perform trap filling on the SiC MOSFET device; Step 3: Apply the gate test voltage and body diode test current to the trap release phase using the test equipment, and measure the transient response curve of the body diode voltage; Step 4: Repeat steps 1-3 to obtain multiple transient voltage curves at different temperatures; Step 5: Fit the multiple transient voltage curves, extract the time constant spectrum of the trap, and use the Arrhenius formula to calculate the trap energy level based on the time constant spectrum of the trap to characterize the trap.

[0006] This invention provides a trap characterization device for a SiC MOSFET device based on a body diode, comprising: Temperature control equipment is used to provide a constant temperature environment for SiC MOSFET devices; The testing equipment is used to connect to a SiC MOSFET device placed in a constant temperature environment, apply gate fill voltage and drain voltage to the SiC MOSFET device, and perform trap filling on the SiC MOSFET device; during the trap release phase, apply gate test voltage and body diode test current, measure the transient response curve of the body diode voltage, and obtain multiple transient voltage curves at different temperatures; The calculation module is used to fit the multiple transient voltage curves, extract the time constant spectrum of the trap, and use the Arrhenius formula to calculate the trap energy level based on the time constant spectrum of the trap to characterize the trap.

[0007] This invention proposes a trap parameter testing method based on the body diode voltage drop response for SiC MOSFET trap characterization. Based on the SiC MOSFET body effect, the trap time constant and energy level information are obtained by evaluating the trap release of the SiC MOSFET device after the gate fill voltage is removed. This enables accurate, non-destructive, and in-situ characterization of the trap parameters inside the SiC MOSFET, providing a basis for analyzing the trap effect of SiC MOSFET under different stress conditions. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a flowchart of a trap characterization method for a SiC MOSFET device based on a body diode, according to an embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the principle of SiC MOSFET trap testing according to an embodiment of the present invention. Figure 3 This is a detailed flowchart of the trap characterization method for SiC MOSFET devices based on body diodes according to an embodiment of the present invention; Figure 4 This is a timing diagram of the SiC MOSFET trap test according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the measured time constant and trap energy level according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a trap characterization device for a SiC MOSFET device based on a body diode, according to an embodiment of the present invention. Detailed Implementation

[0010] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0011] Method Implementation Examples According to embodiments of the present invention, a trap characterization method for SiC MOSFET devices based on a body diode is provided. Figure 1 This is a flowchart of a trap characterization method for a SiC MOSFET device based on a body diode, according to an embodiment of the present invention. Figure 1 As shown, the trap characterization method for SiC MOSFET devices based on body diodes according to embodiments of the present invention specifically includes: Step 101: Connect the SiC MOSFET device placed in a constant temperature environment using a test device; the temperature range of the constant temperature environment is 30°C to 80°C.

[0012] Step 102 involves applying gate fill voltage and drain voltage to the SiC MOSFET device using a testing device to perform trap filling; specifically including: By applying gate fill voltage and drain voltage to the SiC MOSFET device using testing equipment, trap filling is performed on the SiC MOSFET device, wherein the gate fill voltage V... GSF The range is -30 V to 30 V, and the fill time t f The range is from 1 s to 500 s.

[0013] Step 103: Applying a gate test voltage and a body diode test current during the trap release phase using a test device, and measuring the transient response curve of the body diode voltage; specifically including: By applying a gate test voltage and a body diode test current during the trap release phase using a test device, the transient response curve of the body diode voltage is measured, wherein the gate test voltage V... GSM The range is -30 V to 0 V, and the body diode test current I SD The range is from 1 mA to 100 mA, and the test time t for the trap release phase is... m The range is from 10 s to 1000 s, and the minimum sampling accuracy of the transient response curve is 10 ms.

[0014] Step 104: Repeat steps 101-103 to obtain multiple transient voltage curves at different temperatures; specifically including: Obtain multiple transient voltage curves at different temperatures, where the number of temperature points N ≥ 5.

[0015] Step 105 involves fitting the multiple transient voltage curves to extract the time constant spectrum of the traps, and then using the Arrhenius formula to calculate the trap energy levels based on the time constant spectrum to characterize the traps. Specifically, this includes: The multiple transient voltage curves are subjected to noise reduction using exponential or polynomial fitting methods, and the time constant spectrum of the traps is extracted in a semi-logarithmic coordinate system through differential operations. The abscissa of the Arrhenius formula is ln(T) 2 The ordinate is 1 / kT, where T is temperature, τ is time constant, and k is Boltzmann constant. The trap energy level Ea is obtained by linearly fitting the slope using the Arrhenius formula, and Ea ranges from 0.01 eV to 1 eV.

[0016] The technical solutions described above in the embodiments of the present invention will be explained in detail below.

[0017] Existing methods such as high- and low-frequency CV testing, conductivity methods, and pulse transfer characteristic testing are insufficient for accurate, in-situ characterization of trap parameters in SiC MOSFET devices. This invention proposes a trap parameter characterization method based on the SiC MOSFET body diode effect. Based on the SiC MOSFET body effect, the method extracts parameters such as the trap time constant and energy level of the SiC MOSFET device by analyzing the transient voltage drop response curve of the body diode after removing the gate fill voltage. By combining the filling conditions and filling mechanisms under different gate voltage biases, the trap information of the SiC MOSFET is accurately extracted.

[0018] When a constant reverse current ISD is applied to a SiC MOSFET, the source potential is higher than the drain potential, and current flows from the source to the drain. Due to the significant body effect phenomenon in SiC MOSFETs, the source-drain current ISD passes through both the device channel and the body diode simultaneously. The device body diode voltage VSD is simultaneously affected by the gate voltage VGS and the threshold voltage VTH. When the gate voltage VGS is fixed, the transient response of the body diode voltage VSD can reflect the change in the threshold voltage VTH, thereby enabling the analysis and extraction of trap information from the SiC MOSFET. Compared to traditional transient time-domain curve testing methods, since no additional gate voltage needs to be applied during the trap release period to obtain the source-drain current ISD versus time curve, the influence of additional gate voltage on the gate oxide trap during the testing process is avoided, improving the accuracy of oxide trap energy level extraction.

[0019] like Figure 2 and Figure 3 As shown in the figure, the specific implementation process of the trap characterization method based on the transient voltage response of SiC MOSFET body diode proposed in the embodiment of the invention is as follows: S1. Set the temperature of the constant temperature test chamber to T0. In this step, T0 should be set within the range of 30℃ ≤ T ≤ 40℃ to evaluate the change in the body diode voltage drop of the device under test (DUT) over time at room temperature. Then, place the SiC MOSFET device under test in the center of the constant temperature test chamber and connect it to the corresponding interface of the B1500 semiconductor parameter analyzer via an aging holder. Trap testing of the DUT can be completed using existing testing equipment; the operation is simple and convenient, requiring no additional complex testing platform.

[0020] S2. Place the device under test on a constant temperature test chamber at a temperature of T and keep it stationary for td minutes, where the stationary time ranges from td to 20 minutes, to ensure that the temperature of the device under test is consistent with the set temperature T of the constant temperature test chamber.

[0021] S3. Set the test conditions for the semiconductor parameter analyzer B1500. During the trap filling phase, apply a gate filling voltage VGF to the SiC MOSFET under test to achieve carrier trapping of the gate dielectric and filling of the SiC / SiO2 interface states. The range of VGF is -30 V ≤ VGF ≤ 30 V, and the drain voltage is 0 V. The time for which the gate filling voltage VGF is applied is tf. The range of the filling time tf is 1 s ≤ tf ≤ 500 s. During the trap release phase, apply a gate test voltage VGSM and a body diode test current ISD to the SiC MOSFET under test. The range of the gate test voltage VGSM is -30 V ≤ VGSM ≤ 0 V, and the range of the body diode test current ISD is 1 mA ≤ ISD ≤ 100 mA, ensuring that the applied power does not generate additional temperature rise as much as possible. Obtain the change of the body diode voltage VSD of the device under test over time in logarithmic form until the body diode voltage stabilizes. The test time is tm, and this curve is the response curve corresponding to the trap release process. The test time tm can be set to 10 s≤tm≤1000 s depending on the device under test and the test temperature. The minimum sampling accuracy of the transient curve changing with time can reach 10 ms.

[0022] S4. Set the temperature of the constant temperature test chamber to T1, where T1 > T0. Repeat steps two to four to obtain N transient voltage curves VSD(t) of the body diode of the SiC MOSFET device at different temperatures, where N ≥ 5.

[0023] S5. Based on the acquired transient voltage response curve VSD(t), the original curve is fitted and denoised using an e-exponential fitting or polynomial fitting method, and the time constant spectrum of the trap is extracted in a semi-logarithmic coordinate system by dV / d(logt).

[0024] S6. Based on S1 to S5, the trap parameters of SiC MOSFET devices under different temperature conditions were obtained. Based on the time constants of the SiC MOSFET traps under multiple temperature conditions, the Arrhenius formula can be used to plot the Arrhenius diagram. The horizontal axis of the Arrhenius diagram is ln(T²τ), where T is the temperature condition and τ is the trap time constant, which ranges from 10 ms ≤ τ ≤ 1000 s. The vertical axis of the Arrhenius diagram is 1 / kT, where k is the Boltzmann constant and T is the temperature condition. A linear fit is performed on the data in the Arrhenius diagram, and the slope is the trap energy level Ea, where the trap energy level ranges from 0.01 eV ≤ Ea ≤ 1 eV.

[0025] The technical solutions of the embodiments of the present invention will be described in more detail below with reference to the accompanying drawings and specific implementation methods.

[0026] Taking an N-channel SiC MOSFET device as an example, the connection diagram of the trap testing device involved in this embodiment of the invention is as follows: Figure 2 As shown, the system includes the SiC MOSFET device under test 101, a constant temperature test chamber 102, a high-temperature test cable 104, and a semiconductor parameter tester 103. The trap testing process of the parties involved in this embodiment of the invention is as follows: Figure 3 As shown, the specific implementation method is as follows: Step 1: Place the SiC MOSFET device in the constant temperature test chamber, connect it to the corresponding interface of the semiconductor parameter instrument B1500 through the high temperature test cable, and set the temperature of the constant temperature test chamber T0 to 30℃.

[0027] Step 2: Place the device under test in a constant temperature test chamber for 20 minutes to ensure that the temperature of the device under test is consistent with that of the constant temperature test chamber.

[0028] Step 3: Set the test conditions for the B1505A semiconductor parameter tester: Set the gate fill voltage VGF to -20V, drain voltage to 0V, and fill time tf to 30s; set the gate test voltage VGSM to 0V, and the body diode test current ISD to 10mA to ensure the device does not generate heat; set the test time tm to 300s and collect the drain-source voltage VDS over time. The test timing is as follows: Figure 4 As shown.

[0029] Step 4: Set the temperature of the constant temperature test chamber to 40℃, 50℃, 60℃, 70℃ and 80℃ respectively, and repeat steps 2 to 4 to obtain 6 transient voltage curves VSD(t) of the body diode of SiC MOSFET device at different temperatures.

[0030] Step 5: Fit the six transient voltage curves VSD(t) collected using a polynomial method, and extract the time constant spectrum of the trap energy level of the SiC MOSFET device in a semi-logarithmic coordinate system using dV / d(logt).

[0031] Step 6: Based on the Arrhenius equation, the time constant of the trap energy level of the SiC MOSFET device is fitted, and its trap energy level Ea is found to be 0.38 eV. Figure 5 As shown.

[0032] In summary, by utilizing the technical solutions of the embodiments of the present invention, accurate, non-destructive, and in-situ characterization of the internal trap parameters of SiC MOSFETs can be achieved, providing a foundation for analyzing the trap effect of SiC MOSFETs under different stress conditions.

[0033] Device Examples According to embodiments of the present invention, a trap characterization device for SiC MOSFET devices based on a body diode is provided. Figure 6 This is a schematic diagram of a trap characterization device for a SiC MOSFET device based on a body diode, according to an embodiment of the present invention. Figure 6 As shown, the trap characterization device for a SiC MOSFET device based on a body diode according to an embodiment of the present invention specifically includes: Temperature control equipment 60 is used to provide a constant temperature environment for SiC MOSFET devices; Test equipment 62 is used to connect to a SiC MOSFET device placed in a constant temperature environment, apply gate fill voltage and drain voltage to the SiC MOSFET device, and perform trap filling on the SiC MOSFET device; during the trap release phase, apply gate test voltage and body diode test current, measure the transient response curve of the body diode voltage, and obtain multiple transient voltage curves at different temperatures; The calculation module 64 is used to fit the multiple transient voltage curves, extract the time constant spectrum of the trap, and use the Arrhenius formula to calculate the trap energy level based on the time constant spectrum of the trap to characterize the trap.

[0034] The embodiments of the present invention are device embodiments corresponding to the above method embodiments. The specific operation of each module can be understood with reference to the description of the method embodiments, and will not be repeated here.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A trap characterization method for SiC MOSFET devices based on a body diode, characterized in that, include: Step 1: Connect the SiC MOSFET device placed in a constant temperature environment using the test equipment; Step 2: Apply gate fill voltage and drain voltage to the SiC MOSFET device using a testing device to perform trap filling on the SiC MOSFET device; Step 3: Apply the gate test voltage and body diode test current to the trap release phase using the test equipment, and measure the transient response curve of the body diode voltage; Step 4: Repeat steps 1-3 to obtain multiple transient voltage curves at different temperatures; Step 5: Fit the multiple transient voltage curves, extract the time constant spectrum of the trap, and use the Arrhenius formula to calculate the trap energy level based on the time constant spectrum of the trap to characterize the trap.

2. The method according to claim 1, characterized in that, The temperature range of the constant temperature environment is 30°C to 80°C.

3. The method according to claim 1, characterized in that, The trap filling process for the SiC MOSFET device involves applying gate fill voltage and drain voltage to the SiC MOSFET device using testing equipment, specifically including: By applying gate fill voltage and drain voltage to the SiC MOSFET device using testing equipment, trap filling is performed on the SiC MOSFET device, wherein the gate fill voltage V... GSF The range is -30 V to 30 V, and the fill time t f The range is from 1 s to 500 s.

4. The method according to claim 1, characterized in that, The transient response curve of the body diode voltage is measured by applying a gate test voltage and a body diode test current during the trap release phase using a test device. Specifically, this includes: By applying a gate test voltage and a body diode test current during the trap release phase using a test device, the transient response curve of the body diode voltage is measured, wherein the gate test voltage V... GSM The range is -30 V to 0 V, and the body diode test current I SD The range is from 1 mA to 100 mA, and the test time t for the trap release phase is... m The range is from 10 s to 1000 s, and the minimum sampling accuracy of the transient response curve is 10 ms.

5. The method according to claim 1, characterized in that, Obtaining multiple transient voltage curves at different temperatures specifically includes: Obtain multiple transient voltage curves at different temperatures, where the number of temperature points N ≥ 5.

6. The method according to claim 1, characterized in that, The process of fitting the multiple transient voltage curves and extracting the time constant spectrum of the traps specifically includes: The multiple transient voltage curves are subjected to noise reduction using exponential or polynomial fitting methods, and the time constant spectrum of the traps is extracted in a semi-logarithmic coordinate system through differential operations.

7. The method according to claim 1, characterized in that, The abscissa of the Arrhenius formula is ln(T) 2 τ), with the ordinate being 1 / kT, where T is the temperature, τ is the time constant, and k is the Boltzmann constant.

8. The method according to claim 7, characterized in that, Traps are characterized by calculating trap energy levels using the Arrhenius formula, specifically including: The trap energy level Ea was obtained by linearly fitting the slope using the Arrhenius formula. The range of Ea is from 0.01 eV to 1 eV.

9. A trap characterization device for a SiC MOSFET device based on a body diode, characterized in that, include: Temperature control equipment is used to provide a constant temperature environment for SiC MOSFET devices; The testing equipment is used to connect to a SiC MOSFET device placed in a constant temperature environment, apply gate fill voltage and drain voltage to the SiC MOSFET device, and perform trap filling on the SiC MOSFET device; during the trap release phase, apply gate test voltage and body diode test current, measure the transient response curve of the body diode voltage, and obtain multiple transient voltage curves at different temperatures; The calculation module is used to fit the multiple transient voltage curves, extract the time constant spectrum of the trap, and use the Arrhenius formula to calculate the trap energy level based on the time constant spectrum of the trap to characterize the trap.

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