Small step pitch wafer test method and system

Abstract

The invention discloses a small-step-pitch wafer testing method and system, and relates to the technical field of semiconductor testing. The method comprises the following steps: acquiring an original step size of a to-be-tested wafer chip; dividing at least two adjacent chips into virtual test units according to the original step size and a minimum step threshold preset by the test equipment, so that the step of the virtual test units is not less than the minimum step threshold; controlling the test equipment to step according to the step pitch of the virtual test unit, and testing each chip in the virtual test unit; according to a preset coding rule, coding the test result of each chip in the virtual test unit into a combined identification value and recording the combined identification value to the wafer atlas; and decoding the combined identification value according to a decoding rule to restore the test result of each chip. According to the invention, the problem that the testing equipment is limited by mechanical stepping precision and cannot test a micro-size chip is solved, the equipment updating cost is reduced, and accurate testing and data recording of a small-step product are realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to a small-pitch wafer testing method and system. Background Technology

[0002] With the rapid development of semiconductor process technology, in order to reduce the manufacturing cost of a single chip and improve wafer utilization, the design size of integrated circuit chips is showing an increasingly miniaturized trend. In the semiconductor back-end process, wafer testing is a crucial step. It utilizes a probe station to carry the wafer and move it stepwise, bringing the probes on the probe card into contact with the chip's pads, allowing the testing machine to perform functional and electrical parameter tests on the chip. In conventional testing procedures, the step distance of the probe station is usually set to match the physical size of the chip, so that chips can be tested one by one or in parallel.

[0003] When the chip size on the wafer under test is smaller than the minimum step size limit in the X or Y direction, the probe station cannot set effective stepping parameters, causing the equipment to fail to perform normal stepping movement or to fail to accurately align with the next chip under test. The traditional industry solution to this problem is usually to replace old equipment with probe stations of higher precision. This approach not only incurs high equipment procurement costs, significantly increasing chip production costs, but also leaves a large number of existing old probe stations idle, resulting in significant resource waste. Furthermore, when attempting to use existing equipment to perform parallel testing across multiple small chips in a single step, data recording becomes a challenge. Standard wafer mapping is typically based on a single coordinate system, meaning that one logical coordinate point can only record one test result. When multiple small chips are combined into one test position, existing testing systems cannot simultaneously record and distinguish the independent test states of these chips at the same coordinate point. This leads to data confusion or loss, making it difficult for subsequent dicing and packaging processes to accurately identify good and defective products. Therefore, there is an urgent need for a technical solution that can achieve precise testing of small-sized chips and accurately reproduce the test data of each chip while being compatible with existing low-precision stepping probe stations. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a small-pitch wafer testing method and system, which can overcome the hardware bottleneck that testing equipment cannot test micro-sized chips due to limitations in mechanical stepping accuracy (such as minimum step pitch limitations).

[0005] In a first aspect, embodiments of this application provide a small-pitch wafer testing method.

[0006] A small-pitch wafer testing method according to an embodiment of this application includes: obtaining the original pitch size of chips on a wafer to be tested; dividing at least two adjacent chips into virtual test units according to the original pitch size and a minimum pitch threshold preset by the testing equipment, wherein the pitch of the virtual test units is not less than the minimum pitch threshold; controlling the testing equipment to step according to the pitch of the virtual test units and testing each chip in the virtual test units to obtain the test results of each chip; encoding the test results of each chip in the virtual test units into a combined identifier value according to a preset encoding rule, and recording the combined identifier value in a wafer map; decoding the combined identifier value in the wafer map according to a decoding rule corresponding to the encoding rule to restore the test results of each chip.

[0007] The small-pitch wafer testing method according to the embodiments of this application has at least the following beneficial effects: The small-pitch wafer testing method obtains the original pitch size of the chips on the wafer to be tested, and divides at least two adjacent chips into virtual test units according to the minimum pitch threshold preset by the testing equipment. This ensures that the overall pitch of the virtual test unit is not less than the minimum pitch threshold of the equipment, thereby controlling the testing equipment to move in steps based on virtual test units. This mechanism effectively breaks through the hardware bottleneck of existing probe stations and other testing equipment, which cannot test micro-sized chips due to mechanical stepping accuracy limitations (such as minimum pitch limitations). It allows for the testing of small-pitch products using existing equipment without the need to purchase expensive new high-precision equipment, reducing equipment upgrade costs and improving the utilization and versatility of existing equipment. Furthermore, for cases where a virtual test unit contains multiple chips, the small-pitch wafer testing method encodes the test results of each chip into a unique combined identifier value using preset encoding rules and records it in the wafer map. The original results are then restored through decoding. This data processing method solves the technical problem that traditional wafer mapping cannot distinguish and record the test status of multiple independent chips at a single logical coordinate point. Without changing the existing test machine and wafer mapping standard data format, it realizes the recording and traceability of the test results of each small-sized chip in parallel testing, ensuring the accuracy of identifying good and defective products in subsequent dicing and packaging processes.

[0008] According to some embodiments of the first aspect of this application, obtaining the original step size of the chip on the wafer to be tested includes: obtaining a first original step size of the chip in a first direction; obtaining a second original step size of the chip in a second direction; wherein the second direction is perpendicular to the first direction.

[0009] According to some embodiments of the first aspect of this application, dividing at least two adjacent chips into virtual test units based on the original step size and a minimum step threshold preset by the test equipment includes: when the first original step size is less than the minimum step threshold, determining a first combination number in the first direction such that the product of the first original step size and the first combination number is not less than the minimum step threshold; when the second original step size is less than the minimum step threshold, determining a second combination number in the second direction such that the product of the second original step size and the second combination number is not less than the minimum step threshold; and dividing adjacent chips into the same virtual test unit based on the first combination number and the second combination number.

[0010] According to some embodiments of the first aspect of this application, the step of testing each chip in the virtual test unit and obtaining test results for each chip includes: simultaneously contacting all the chips in the virtual test unit through a probe card, wherein the probe card includes probe groups corresponding to all the chips in the virtual test unit; and performing parallel tests on all the chips in the virtual test unit through multiple test channels of a test machine to obtain the test results for each chip.

[0011] According to some embodiments of the first aspect of this application, encoding the test results of each chip in the virtual test unit into a combined identifier value according to a preset encoding rule includes: performing numerical conversion on the test results of each chip in the virtual test unit to obtain a state value corresponding to each chip; assigning corresponding encoding parameters to each chip in the virtual test unit; and performing calculations based on the state values ​​of all chips in the virtual test unit and the corresponding encoding parameters to obtain the combined identifier value.

[0012] According to some embodiments of the first aspect of this application, the encoding parameter is a binary bit position; The step of calculating the combined identifier value based on the state values ​​of all the chips in the virtual test unit and the corresponding encoding parameters includes: shifting the state value corresponding to each chip to the corresponding binary bit position; and summing the shifted state values ​​to obtain the combined identifier value.

[0013] According to some embodiments of the first aspect of this application, the step of performing numerical conversion on the test results of each chip in the virtual test unit to obtain the state value corresponding to each chip includes: subtracting a first preset value from the test results of each chip to obtain the state value corresponding to each chip; The process of summing the shifted state values ​​to obtain the combined identifier value further includes adding a second preset value to the summation result to obtain the final combined identifier value.

[0014] According to some embodiments of the first aspect of this application, the step of decoding the combined identifier value in the wafer map according to the decoding rule corresponding to the encoding rule to restore the test results of each chip includes: subtracting the combined identifier value from the second preset value to obtain a decoding intermediate value; performing binary conversion on the decoding intermediate value to obtain a decoding binary value; performing masking operation on the decoding binary value according to the encoding parameters corresponding to each chip to obtain the state value of each chip; and adding the first preset value to the state value corresponding to each chip to obtain the test result corresponding to each chip.

[0015] According to some embodiments of the first aspect of this application, the encoding rules adopt a lookup table mapping method; The step of encoding the test results of each chip in the virtual test unit into a combined identifier value according to a preset encoding rule includes: establishing a mapping table between test result combinations and the combined identifier values, wherein the mapping table records all possible combinations of the test results of each chip in the virtual test unit and their corresponding combined identifier values; obtaining the test results of each chip in the virtual test unit to form the test result combination; and searching for the combined identifier value corresponding to the test result combination in the mapping table.

[0016] Secondly, embodiments of this application provide a small-pitch wafer testing system.

[0017] A small-pitch wafer testing system according to an embodiment of this application includes: a probe station for carrying a wafer to be tested and performing stepping movement; a probe card installed on the probe station, including multiple test positions, each test position corresponding to a virtual test unit, and each test position containing a probe group corresponding to all chips in the virtual test unit; a tester electrically connected to the probe card, used to perform parallel testing on multiple chips in the virtual test unit through multiple test channels; and a calculation module for obtaining the original stepping size of the chips on the wafer to be tested, and dividing at least two adjacent chips into one virtual test unit when the original stepping size is less than a preset minimum stepping threshold of the test equipment. The virtual test unit's step size is greater than or equal to the preset minimum step size threshold; the test control module controls the probe station to move in steps according to the virtual test unit's step size, and controls the test machine to perform parallel tests on multiple chips contained in the same virtual test unit to obtain the test results of each chip; the data encoding module uses a preset encoding rule to encode the test results of each chip in the same virtual test unit into a combined identifier value, and records the combined identifier value in the wafer map; the data restoration module decodes the combined identifier value in the wafer map according to the decoding rule corresponding to the encoding rule, and restores the test results of each chip. Attached Figure Description

[0018] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 This is a schematic diagram of the main process of the small-pitch wafer testing method in the embodiment; Figure 2 This is a flowchart illustrating how to obtain the original pitch dimensions of the chips on a wafer under test, as an example. Figure 3 This is a flowchart illustrating how at least two adjacent chips are divided into virtual test units, as an example. Figure 4 This is a flowchart illustrating the testing of each chip within the virtual test unit as an example. Figure 5 This is a flowchart illustrating how the test results of each chip within a virtual test unit are encoded into a combined identifier value, as an example. Figure 6 This is a flowchart illustrating how calculations are performed based on the status values ​​and corresponding encoding parameters of all chips within the virtual test unit to obtain the combined identifier value. Figure 7 This is a flowchart illustrating the decoding of combined identifier values ​​in a wafer pattern, as an example. Figure 8 This is a flowchart illustrating how a combined identifier value is determined based on a mapping table, as an example. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0022] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0023] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0024] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent is obtained first. Furthermore, the collection, use, and processing of this data comply with relevant laws, regulations, and standards. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user is obtained through pop-ups or redirection to confirmation pages. Only after obtaining the user's separate permission or consent is the necessary user-related data required for the proper functioning of these embodiments acquired.

[0025] Firstly, embodiments of this application provide a small-pitch wafer testing method. This small-pitch wafer testing method is mainly applicable to semiconductor wafer testing, particularly for situations where the size of a single chip is smaller than the minimum stepping accuracy of the testing equipment (such as a probe station).

[0026] like Figure 1 As shown, the small-pitch wafer testing method in this embodiment includes, but is not limited to, steps S100 to S500: S100: Obtain the original pitch size of the chip on the wafer to be tested; S200. Based on the original step size and the minimum step threshold preset by the test equipment, divide at least two adjacent chips into virtual test units, wherein the step size of the virtual test unit is not less than the minimum step threshold. S300: Control the test equipment to step according to the step size of the virtual test unit, and test each chip in the virtual test unit to obtain the test results of each chip. S400. According to the preset encoding rules, the test results of each chip in the virtual test unit are encoded into a combined identifier value, and the combined identifier value is recorded in the wafer map. S500: According to the decoding rules corresponding to the encoding rules, decode the combined identifier values ​​in the wafer map to restore the test results of each chip.

[0027] In step S100, the system first needs to read the relevant specification data of the wafer to be tested. This can typically be obtained by reading the header information of the wafer map file or by inputting parameters through the user interface. The so-called raw step size refers to the physical size of a single chip on the wafer before any assembly, typically including the width in the X direction and the width in the Y direction. This size determines the amount of displacement required for the probe station to move each time to align with the next chip, ideally.

[0028] In step S200, the system compares the acquired original step size with the hardware limitations of the test equipment. The minimum step size threshold preset by the test equipment (e.g., 300µm) is the lower limit for the equipment to perform stable and precise stepping movements. If the original step size is less than this threshold, the system executes "virtual grouping" logic. For example, the system logically bundles two or more adjacent chips as a whole, which is called a "virtual test unit". The principle of division is that the size of the combined virtual test unit in the stepping direction (i.e., the step size of the virtual test unit) must be greater than or equal to the minimum step size threshold of the equipment. Through this division, the physical step size that was originally too small for the equipment is converted into an effective step size that meets the equipment requirements, thereby enabling older equipment to test small-sized chips.

[0029] In step S300, after determining the size of the virtual test unit, it is configured as the actual stepping parameters of the probe station. During testing, the probe station no longer moves in units of individual chips, but rather moves in large steps according to the step size of the virtual test unit. In conjunction with this, the probe card used, through its pin design, can simultaneously contact the pads of all chips contained within a virtual test unit. Once the probe pins make good contact, the tester simultaneously sends excitation signals to each chip within the unit through parallel test channels (Site) and reads the feedback, thereby obtaining independent test results for each chip (e.g., Bin 1 indicates a good chip, Bin X indicates various types of defects).

[0030] In step S400, traditional probe stations and wafer mapping typically assume that one physical coordinate point (X, Y) corresponds to only one test result (Bin value). Direct recording would lead to data conflicts (i.e., it's impossible to simultaneously record chip A as good and chip B as defective at the same coordinate point). However, in this embodiment, one step of the probe station (i.e., one coordinate point on the map) actually covers multiple physical chips. To avoid data loss, this step introduces an "encoding" mechanism. The system uses preset encoding rules to perform calculations or mappings on the test results of multiple chips within the same virtual test unit. The core of this encoding rule lies in uniqueness and reversibility; that is, different combinations of chip test results should correspond to a unique numerical value (i.e., a combination identifier value).

[0031] For example, the test result status (e.g., good / defective) of multiple chips can be converted into numerical values, and a "combined identifier value" that can represent the status of all chips within the unit can be generated through mathematical operations (e.g., weighted summation, bitwise operations) or table lookup mapping. Finally, the system writes the combined identifier value to the corresponding virtual test unit coordinate position in the wafer map.

[0032] In step S500, this step typically occurs in a subsequent process after wafer testing (e.g., during wafer dicing or packaging). Subsequent equipment (such as a die sorter) reads the wafer map containing the recorded "combination identifier values." The equipment uses a decoding rule that is the reverse of step S400 to parse the combination identifier value recorded at each coordinate point in the map. Through decoding, the system can reconstruct the specific test results of the original multiple chips within the virtual test unit from a single combination identifier value. Based on the reconstructed results, subsequent equipment can accurately identify which chips in which physical locations are good and which are defective, thus achieving precise sorting or rejection.

[0033] like Figure 2 As shown, in some embodiments, step S100 further includes, but is not limited to, steps S110 to S120: S110: Obtain the first original step distance of the chip in the first direction; S120: Obtain the second original step distance of the chip in the second direction.

[0034] In steps S110 and S120, the system acquires the first original step size (denoted as Size_x) of the chip in a first direction (e.g., the horizontal X-axis direction) and the second original step size (denoted as Size_y) in a second direction (usually the Y-axis direction perpendicular to the X-axis). These two directions are perpendicular to each other and together define the physical rectangular region of a single chip. This acquisition can be done by reading the header information from a wafer map file or by manual input by an operator through a human-machine interface.

[0035] After obtaining the above dimensions, the system executes the grouping logic in step S200, such as... Figure 3 As shown, in some embodiments, step S200 further includes, but is not limited to, steps S210 to S230. The core objective of this process is to find the smallest integer multiple such that the combined size meets device constraints.

[0036] S210. When the first original step distance is less than the minimum step distance threshold, determine the first combination number in the first direction, such that the product of the first original step distance and the first combination number is not less than the minimum step distance threshold. S220. When the second original step size is less than the minimum step size threshold, determine the second combination number in the second direction, such that the product of the second original step size and the second combination number is not less than the minimum step size threshold. S230. Based on the number of the first combination and the number of the second combination, adjacent chips are divided into the same virtual test unit.

[0037] In step S210, the system determines whether the first original step size meets the minimum step size threshold (denoted as Limit) of the test equipment. If Size_x ≥ Limit, it means that no combination is needed in the X direction, and the number of the first combination ( N_x This can be set to 1. If Size_x < Limit, the system calculates the number of the first combination. N_x The specific calculation logic can be as follows: divide the minimum step size threshold by the first original step size, and round the result up, or start from the integer 2 and search incrementally until the formula is satisfied: Size_x × N_ x ≥Limit, where, N_x It is a positive integer. At this point, the system determines that it needs to be moved in the first direction. N_x Each chip is considered as a group.

[0038] In step S220, the system performs the same judgment and calculation for the second direction. If Size_y ≥ Limit, it means that no combination is needed in the Y direction, and the number of combinations in the second direction is ( N_y The value can be set to 1. If Size_y < Limit, the system calculates the number of the second combination. N_y This makes Size_y× N_y ≥Limit, where, N_y It is a positive integer.

[0039] In step S230, the system calculates... N_x and N_y This involves constructing virtual test cells. This means that a virtual test cell physically covers the entire wafer array. N_x Row (or column) × N_y A rectangular area comprising columns (or rows). The total number of chips contained within this virtual test unit is... N_x × N_y .

[0040] After determining the structure of the virtual test unit, the system began performing physical contact and electrical tests, such as... Figure 4 As shown, in some embodiments, step S300 further includes, but is not limited to, steps S310 to S320: S310. Simultaneously contact all chips in the virtual test unit through a probe card, wherein the probe card contains probe groups corresponding to all chips in the virtual test unit; S320 performs parallel tests on all chips within the virtual test unit through multiple test channels of the test machine, and obtains the test results of each chip.

[0041] Step S310 primarily involves the physical interaction between the probe card and the wafer. To accommodate the virtual test units defined in the preceding steps, the probe card requires specific design or configuration. For example, a physical test position (typically called a Site) on the probe card no longer corresponds solely to the pad layout of a single chip, but rather includes a probe array capable of covering all chip pads within the entire virtual test unit. For instance, if the virtual test unit consists of two adjacent chips (Chip A and Chip B), the corresponding test position on the probe card will include "Probe Group A" and "Probe Group B." When the probe station drives the wafer carrier to lift in the Z-axis direction to perform a probe insertion action, these multiple probe groups on the probe card will simultaneously contact the input / output pads of all chips (Chip A and Chip B) within the virtual test unit. This design ensures that a physical connection path to all sub-chips within the virtual test unit is established in a single mechanical contact action.

[0042] Step S320 primarily involves signal interaction with the test machine. The test machine is electrically connected to the probe card via cables and interfaces. The test machine is internally configured with multiple independent test channels or test resources. Under the control of the test program, these test channels are assigned to various chips within the virtual test unit. Specifically, although the probe station treats the virtual test unit as a "one-step" object, the test machine performs parallel testing at the electrical level. The test machine simultaneously sends excitation signals (such as voltage, current, or digital vectors) to each chip within the virtual test unit through its independent channels and receives feedback signals from each chip in parallel. In this way, the system can acquire the independent test results of each chip within the virtual test unit (e.g., Chip A is Pass, Chip B is Fail) within the same time period. These independent test results are temporarily stored in the test machine's memory or cache as the basic input data for data encoding in the subsequent step S400. This parallel architecture not only solves the step size limitation problem but also maximizes the resource utilization of the test machine and avoids the time loss caused by serial testing.

[0043] Understandably, step S400 (i.e., encoding the test results of each chip within the virtual test unit into a combined identifier value according to preset encoding rules) is the core step in realizing "recording multi-chip data at a single coordinate point". To ensure the uniqueness and reversibility of the encoding, this process may include three stages: data numerical conversion, parameter allocation, and computational synthesis. Figure 5 As shown, in some embodiments, step S400 includes, but is not limited to, steps S410 to S430: S410. Perform numerical conversion on the test results of each chip in the virtual test unit to obtain the corresponding state value of each chip; S420: Assign corresponding encoding parameters to each chip in the virtual test unit; S430: Calculate the combined identifier value based on the status values ​​and corresponding encoding parameters of all chips in the virtual test unit.

[0044] In step S410, the raw test results (Raw Bin Data) output by the testing machine are typically user-defined or follow specific industry standards. For example, some products define Bin 1 as a pass, Bin 7 as an electrical defect, and Bin 9 as an appearance defect; while other products may define Bin 5 as a pass. This diversity and dispersion of raw data is not conducive to subsequent unified encoding operations. Step S410 performs "data normalization" or "state mapping" processing. The system has a preset transformation rule (or mapping function) to convert the complex raw test results into standardized "state values".

[0045] For example, in scenarios where only yield is a concern, all Bin values ​​representing acceptable results (e.g., Bin 1) can be mapped to a state value "0" (or "1"), and all Bin values ​​representing unacceptable results (e.g., Bin 2-9) can be mapped to a state value "1" (or "0"). This method simplifies diverse test results into binary states, facilitating efficient subsequent binary encoding. If specific defect type information needs to be retained, segmented mapping can be used. For example, acceptable products are mapped to 0, electrical defects to 1, and leakage defects to 2. Simple arithmetic operations can also be used, such as subtracting a fixed base from the original Bin value, thus converting Bin 1 to 0 and Bin 2 to 1. Through the above numerical conversions, the test result of each chip is transformed into a state value that is easy to perform mathematical calculations (…). Si ).

[0046] In step S420, since a virtual test unit contains multiple chips, and these chips have a fixed arrangement order in physical space (e.g., 2x2 arrangement or 1x3 arrangement), in order to distinguish which state value belongs to which chip in physical location during decoding, it is necessary to introduce encoding parameters that represent position information. Pi This encoding parameter defines the "weight" or "position" of each chip in the combined identifier value. The system assigns a unique encoding parameter to each chip within the unit according to a preset scanning order (e.g., left to right, top to bottom, or serpentine scan). For example, in a virtual test unit containing two chips (left chip A, right chip B): left chip A is assigned encoding parameter P0; right chip B is assigned encoding parameter P1. The specific form of these parameters depends on the subsequent computational logic (e.g., ...). Pi It can be a weighting factor of 10. i It can also be the number of bits shifted in binary.i ).

[0047] In step S430, after obtaining the standardized state value ( Si ) and encoding parameters representing the location ( Pi Afterwards, the system performs aggregation operations to generate unique combined identifier values. The core logic of the operation is to construct a mathematical expression that ensures a one-to-one correspondence between the input state sequence and the output combined identifier value. The operation formula can be expressed as: Combined identifier value = F ((S1,P1) , (S2,P2) , (S3,P3) , ...(Sn,Pn)) in, F This refers to the preset aggregation operation rules. For example, F A weighted summation method can be used to calculate the state value of each chip. Si According to its encoding parameters Pi Perform the transformation, then accumulate the results.

[0048] Understandably, to maximize the utilization of computer data storage characteristics and simplify computational logic, encoding parameters can be specifically defined as binary bit positions. This means that each chip within the virtual test unit will correspond to a specific bit (or bits) in the target binary number. The system assigns binary weights sequentially based on the physical arrangement of the chips within the virtual test unit (e.g., from left to right, from bottom to top). For example, for a virtual test unit containing N chips: the first chip (position 1) is assigned to the 0th bit (i.e., bit 20); the second chip (position 2) is assigned to the 1st bit (i.e., bit 21); and so on, up to the Nth chip (position N) being assigned to the (N-1)th bit (i.e., 2N-1)th bit. This allocation method establishes a direct mapping from spatial position to digital bit width. Correspondingly, as... Figure 6 As shown, in some embodiments, step S430 further includes, but is not limited to, steps S431 to S432: S431. Shift the state value of each chip to the corresponding binary bit position; S432. Summate the shifted state values ​​to obtain the combined identifier value.

[0049] In step S431, prior to this step, preferably, the numerical conversion in step S410 has normalized the chip's test results into binary state values ​​(e.g., 0 represents a good product, 1 represents a defective product). The system performs a left shift operation on each chip. Assume the state value of a certain chip is... Si Its allocated bit position is k (i.e., the first) k If the bit is specified, the operation logic is as follows: Value after shift = Si << k Or equivalent to arithmetic operations: Value after shift = Si ×2 k Through this step, state values ​​that might originally have the same value (both being 1) are assigned different "weights" because of their different bit positions. For example, a "1" in bit 0 represents the value 1, while a "1" in bit 2 represents the value 4.

[0050] In step S432, the system accumulates the values ​​obtained by shifting all the chips (in binary logic, when there is no carry overlap between the state values, the summation operation is equivalent to the "bitwise OR" operation).

[0051] Combined identifier value =

[0052] For example, suppose a virtual test unit contains three horizontally arranged chips (Chip A, Chip B, Chip C), and the tester's preset minimum step size threshold requires that these three chips be tested as a single unit.

[0053] 1) Input data (test results): Chip A (left): Test result Bin 1 (good); Chip B (Medium): Test result Bin 7 (Defective product); Chip C (right): Test result Bin 1 (good).

[0054] 2) Numerical conversion (step S410): Let the rule be: Bin 1 → state value 0; Bin 7 → state value 1; Therefore: SA=0, SB=1, SC=0; 3) Parameter allocation (step S420): Chip A corresponds to the 0th bit in binary (PA=0); Chip B corresponds to the first bit in binary (PB=1); Chip C corresponds to the second bit in binary (PC=2).

[0055] 4) Shifting and Summation (Steps S431-S432): Chip A's contribution: 0 0 = 0; Chip B's contribution: 1 1 = 2 (i.e., binary 010); Chip C's contribution: 0 2 = 0; The combined identifier value = 0 + 2 + 0 = 2.

[0056] 5) Results Recording: The system records the value 2 at the corresponding coordinates of the wafer map. When decoding later, the value "2" is converted to binary, which is 010. Based on the bit position definition, it can be deduced that the middle chip (bit 1 is 1) is defective, and the chips on the left and right sides (bits 0 and 2 are 0) are good.

[0057] By employing the method described in this embodiment, regardless of the number of chips contained within the virtual test unit, as long as the binary bit width of the combined identifier value is sufficient (for example, a 16-bit integer can store the states of 16 chips), the test results of all chips can be accurately and losslessly recorded using a single decimal value. This solves the problem of "insufficient coordinate points" in small-step testing.

[0058] Understandably, in standard wafer testing industry specifications, test results are typically represented by positive integers (e.g., Bin1 represents a good product), and the wafer map usually retains the value "0" to indicate "no wafer location" or "test skipped." Directly applying the aforementioned binary encoding may result in a situation where "all good cells result in 0," leading to map recognition errors. In some embodiments, step S410 includes, but is not limited to, step S411: S411. Subtract the first preset value from the test results of each chip to obtain the corresponding status value of each chip.

[0059] In step S411, the aim is to convert the industry-standard test results into a reference state value suitable for binary bit operations. Typically, wafer testing defines Bin 1 as a pass. To utilize binary characteristics, we want a pass to represent "0" in a summation operation (i.e., without changing the values ​​of other bits), while a defective product represents "1" or another value. Therefore, a first preset value is set equal to the original Bin value of a pass (e.g., 1). For a pass (original Bin 1): 1 1=0, this state value "0" does not contribute numerically in subsequent shifts and summations. For defective products (e.g., original Bin 2): 2 1=1, and this state value "1" will occupy a specific binary bit in subsequent calculations. By subtracting the first preset value, a normalized mapping of the test result to the "zero baseline" is achieved.

[0060] Understandably, the system uses the normalized state values ​​(0 or 1, etc.) and the shift and summation logic in the above embodiments to calculate an "intermediate calculation result". It should be noted that if all chips in a virtual test unit are good, then the state values ​​of all chips are 0, and the calculated "intermediate calculation result" will also be 0. In many Map formats, writing 0 is considered invalid data, leading to the loss of good data. Therefore, in some embodiments, after step S432, there is also, but is not limited to, step S433: S433. Add the result of the summation operation to the second preset value to obtain the final combined identifier value.

[0061] In step S433, to avoid the aforementioned "zero-value trap," the system superimposes a fixed second preset value onto the intermediate calculation result. The selection of this second preset value should meet the following condition: ensuring that even if all samples are good, the final result will not be 0 after adding this value. It is recommended to set a relatively large value (e.g., 100, 200, or 0x8000) so that the final combined identifier value is clearly distinguishable from the ordinary original Bin value in terms of numerical range, making it easier for subsequent data processing personnel to intuitively identify this area as "coded data."

[0062] Understandably, the decoding process strictly follows the inverse logic of the encoding process, for example, such as... Figure 7 As shown, in some embodiments, step S500 further includes, but is not limited to, steps S510 to S540: S510. Subtract the second preset value from the combined identifier value to obtain the decoding intermediate value; S520. Convert the intermediate decoded value into binary to obtain the decoded binary value; S530. Based on the encoding parameters corresponding to each chip, perform masking operations on the decoded binary values ​​to obtain the status values ​​of each chip. S540: Add the first preset value to the status value corresponding to each chip to obtain the test result corresponding to each chip.

[0063] In step S510, the reading device first loads the wafer map and reads the combined identifier value at specific coordinates. To eliminate the offset introduced during the encoding stage to avoid "zero values," the system first subtracts a pre-agreed second preset value from the read value. Assume the read combined identifier value is 102, and the second preset value is 100. The system calculates: 102 100 = 2. The value "2" here is the intermediate value for decoding, which contains the original state combination information of all chips in this virtual test unit.

[0064] In step S520, since the core logic of the encoding is based on binary bit positions, the decoding system needs to convert the decimal intermediate value into binary form for bit-by-bit analysis. Example: Converting the decimal value "2" to binary yields 0010.

[0065] In step S530, the system retrieves the configuration information of the virtual test unit and obtains the encoding parameters (i.e., binary bit positions) corresponding to each chip. These parameters are used to generate a corresponding mask, which is then bitwise ANDed with the decoded binary value to extract the value at a specific bit position.

[0066] Example: Extract the status of chip A (corresponding to bit 0): Generate mask: 1 0 = binary 0001; Mask operation: (0010) AND (0001) = 0; Result: The state value of chip A is 0.

[0067] Extract the status of chip B (corresponding to bit 1): Generate mask: 1 1 = binary 00101.

[0068] Mask operation: (0010) AND (0010) = non-zero value (or normalized to 1 by right shift).

[0069] Result: The state value of chip B is 1.

[0070] Through masking operations, the system successfully separated the mixed data into independent state values.

[0071] In step S540, to reconstruct the original Bin values ​​that conform to industry standards, the system adds the extracted status values ​​to the first preset value subtracted during encoding. Example: The first preset value is set to 1 (i.e., the good product benchmark). Chip A (left): Status value 0 + 1 = Bin1 (determined as good); Chip B (right): Status value 1 + 1 = Bin2 (determined as defective). Thus, the system successfully and accurately reconstructs the test results of each of the two chips in the virtual test unit from a single value "102". Subsequent equipment (such as a chip picker) can then control the nozzle to pick up only chip A on the left and discard chip B on the right, based on the reconstructed results.

[0072] Understandably, in step S400, data compression and restoration can also be achieved by establishing a preset mapping table. This method offers greater flexibility and configuration freedom for situations with many test result types or discontinuous Bin value definitions (e.g., Bin 1, Bin 5, Bin 99). Figure 8 As shown, in some embodiments, step S400 includes, but is not limited to, steps S440 to S460: S440. Establish a mapping table between test result combinations and combination identifier values. The mapping table records all possible combinations of test results of each chip in the virtual test unit and their corresponding combination identifier values. S450: Obtain the test results of each chip in the virtual test unit and form a test result combination; S460. Find the combination identifier value corresponding to the combination of test results in the mapping table.

[0073] In the S440, the system first constructs a mapping table (or dictionary / hash table) in the controller's storage unit. This mapping table enumerates all possible combinations of chip test results within the virtual test unit and assigns a unique index value (i.e., combination identifier value) to each combination. Assume a virtual test unit contains N chips, and each chip has M possible test result states (e.g., good, open / short circuit failure, leakage failure). The system generates all possible combinations (MN in total) and establishes the key-value pair relationship as shown below: Example table structure (assuming the cell contains 2 chips: chip A and chip B): Key combination: [Result from Chip A, Result from Chip B] Map value: Combined identifier value (Map ID) Example of specific content: Combination 1: [Bin 1 (Good), Bin 1 (Good)] → Mapped to ID200 Combination 2: [Bin 1 (Good), Bin 7 (Bad)] → Mapped to ID201 Combination 3: [Bin 7 (Poor), Bin 1 (Good)] → Mapped to ID202 Combination 4: [Bin 7 (Poor), Bin 7 (Poor)] → Mapped to ID203 In step S450, after the test machine completes the parallel testing of the current virtual test unit, the system collects the actual test results of each chip in the unit. For example, the system detects that chip A on the left is Bin 1 and chip B on the right is Bin 7. The system combines these two data into a sequence or vector according to the spatial arrangement order (physical position) of the chips: [Bin 1, Bin7].

[0074] In step S460, the system uses the previously generated sequence [Bin 1, Bin 7] as the lookup key to search the mapping table established in step S240. After matching the corresponding entry, the system reads its associated value (i.e., ID201). Subsequently, the system writes the value 201 into the coordinate position corresponding to the current virtual test unit in the wafer map.

[0075] Secondly, embodiments of this application provide a small-pitch wafer testing system.

[0076] The small-step wafer testing system of this embodiment comprises two main components: a hardware execution unit and a control processing unit. The hardware execution unit includes a probe station, a probe card, and a testing machine. The probe station is a device used to hold the wafer under test and perform mechanical movements. In this system, the probe station receives instructions from the test control module and executes movements along the X, Y, and Z axes. Unlike traditional systems, the probe station in this embodiment does not use the size of a single chip as the step unit, but rather the size of a "virtual test unit." For example, if a single chip is 150µm in size, and the virtual test unit contains two horizontally adjacent chips, then the X-axis step distance of the probe station is set to 300µm. This large step size avoids accuracy errors or alarm shutdowns caused by excessively small step sizes (less than 300µm).

[0077] The probe card is the physical interface connecting the tester and the wafer, and is mounted on the probe station. The probe card in this embodiment employs a special pin design. Test site correspondence: Each test site on the probe card does not correspond to a single physical chip, but rather to a virtual test unit. Probe group structure: Within each test site, there is a probe group corresponding to all the chips within that virtual test unit. For example, if a virtual test unit consists of two chips (chip A and chip B), then one test site on the probe card simultaneously has a first group of probes for contacting the pads of chip A and a second group of probes for contacting the pads of chip B. This allows the probe card to simultaneously connect the circuitry of multiple physical chips in a single probe insertion operation.

[0078] The test machine is electrically connected to the probe card via a test head. The test machine is equipped with multiple independent hardware test channels. During testing, the test machine utilizes its multi-channel parallel testing capability to simultaneously send stimulus signals to multiple chips within the virtual test unit and acquire response data through different pins of the probe card. For the test machine, it is simply performing routine parallel testing and is unaware of underlying step size limitations, ensuring system compatibility with mainstream test machine models.

[0079] The coordinated operation of the aforementioned hardware devices is achieved by a control processing unit (typically an industrial computer integrated into the testing machine or a standalone workstation) running corresponding software modules. In this embodiment, the control processing unit includes: a calculation module, a test control module, a data encoding module, and a data restoration module.

[0080] The calculation module is primarily used in the test program setup phase. It reads the wafer pattern or CAD data input by the user to obtain the original chip pitch size. This module has built-in comparison logic; when it detects that the original pitch size (e.g., 120µm) is less than the test equipment's preset minimum pitch threshold (e.g., 300µm), it automatically triggers the cell partitioning algorithm. It calculates the number of chips that need to be aggregated in the X or Y direction, defines multiple adjacent chips as a virtual test cell, and generates a corrected step pattern to ensure that the new pitch size meets the equipment requirements.

[0081] The test control module is the system's command center. During test execution, it sends corrected stepping instructions (based on the coordinates of the virtual test cells) to the probe station and a test start signal to the test machine. It ensures that once the probe station is in position, the test machine can complete the test of all chips at that location.

[0082] Once the test machine completes the test of a virtual test unit and obtains the raw results from multiple chips, the data encoding module immediately intervenes. It uses preset encoding rules (such as binary bit shifting operations or lookup table mapping) to compress this set of raw results into a unique combined identifier value. Subsequently, the module calls the system's drawing interface to write this unique value to the coordinate point corresponding to the current virtual test unit in the wafer map.

[0083] The data restoration module can exist as a standalone data processing software or be integrated into the subsequent sorting equipment control system. It stores decoding algorithms (such as reverse bitwise operations or reverse lookup tables) corresponding to the encoding rules. When the system imports the wafer map generated by this testing system, the data restoration module automatically parses the combined identifier value of each coordinate point, restoring it to the original test results of multiple chips, thereby generating a physical mapping map that can accurately guide chip sorting.

[0084] Through the organic combination of the above modules, the small-pitch wafer testing system in this embodiment achieves efficient and low-cost testing of ultra-small-pitch wafers without upgrading the expensive high-precision probe station hardware, simply by improving the probe card design and data flow control logic.

[0085] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application. Furthermore, unless otherwise specified, the embodiments and features described in the embodiments of this application can be combined with each other.

Claims

1. A method for testing small-pitch wafers, characterized in that, include: Obtain the original step size of the chip on the wafer under test; Based on the original step size and the minimum step threshold preset by the test equipment, at least two adjacent chips are divided into virtual test units, wherein the step size of the virtual test unit is not less than the minimum step threshold. The test equipment is controlled to step according to the step size of the virtual test unit, and each chip in the virtual test unit is tested to obtain the test results of each chip. According to the preset encoding rules, the test results of each chip in the virtual test unit are encoded into a combined identifier value, and the combined identifier value is recorded in the wafer map. According to the decoding rules corresponding to the encoding rules, the combined identifier values ​​in the wafer map are decoded to restore the test results of each chip.

2. The small-pitch wafer testing method according to claim 1, characterized in that, The process of obtaining the original step size of the chip on the wafer under test includes: Obtain the first original step distance of the chip in the first direction; Obtain the second original step size of the chip in the second direction; The second direction is perpendicular to the first direction.

3. The small-pitch wafer testing method according to claim 2, characterized in that, The step of dividing at least two adjacent chips into virtual test units based on the original step size and the minimum step threshold preset by the test equipment includes: When the first original step size is less than the minimum step size threshold, the first combination number in the first direction is determined such that the product of the first original step size and the first combination number is not less than the minimum step size threshold. When the second original step size is less than the minimum step size threshold, determine the second combination number in the second direction, such that the product of the second original step size and the second combination number is not less than the minimum step size threshold. Based on the first combination quantity and the second combination quantity, adjacent chips are divided into the same virtual test unit.

4. The small-pitch wafer testing method according to claim 1, characterized in that, The step of testing each chip within the virtual test unit and obtaining the test results for each chip includes: All the chips in the virtual test unit are simultaneously contacted by a probe card, wherein the probe card contains a probe group corresponding to all the chips in the virtual test unit; The tester performs parallel tests on all chips within the virtual test unit using multiple test channels to obtain the test results for each chip.

5. The small-pitch wafer testing method according to claim 1, characterized in that, The step of encoding the test results of each chip in the virtual test unit into a combined identifier value according to a preset encoding rule includes: The test results of each chip in the virtual test unit are numerically converted to obtain the state value corresponding to each chip; Assign corresponding encoding parameters to each chip within the virtual test unit; The combined identifier value is obtained by performing calculations based on the status values ​​of all the chips in the virtual test unit and the corresponding encoding parameters.

6. The small-pitch wafer testing method according to claim 5, characterized in that, The encoding parameters are binary bit positions; The step of calculating the combined identifier value based on the state values ​​of all the chips in the virtual test unit and the corresponding encoding parameters includes: Shift the state value corresponding to each chip to the corresponding binary bit position; The combined identifier value is obtained by summing the shifted state values.

7. The small-pitch wafer testing method according to claim 6, characterized in that, The step of converting the test results of each chip within the virtual test unit into numerical values ​​to obtain the state value corresponding to each chip includes: Subtract the first preset value from the test results of each chip to obtain the state value corresponding to each chip; The process of summing the shifted state values ​​to obtain the combined identifier value further includes: The result of the summation operation is added to the second preset value to obtain the final combined identifier value.

8. The small-pitch wafer testing method according to claim 7, characterized in that, The step of decoding the combined identifier value in the wafer map according to the decoding rule corresponding to the encoding rule, and restoring the test results of each chip, includes: Subtract the second preset value from the combined identifier value to obtain the decoding intermediate value; The intermediate decoded value is converted into binary to obtain the decoded binary value; Based on the encoding parameters corresponding to each chip, a mask operation is performed on the decoded binary value to obtain the state value of each chip; The test result corresponding to each chip is obtained by adding the state value corresponding to each chip to the first preset value.

9. The small-pitch wafer testing method according to claim 1, characterized in that, The encoding rules adopt a lookup table mapping method; The step of encoding the test results of each chip in the virtual test unit into a combined identifier value according to a preset encoding rule includes: A mapping table is established between test result combinations and the combination identifier values. The mapping table records all possible combinations of test results of each chip in the virtual test unit and their corresponding combination identifier values. The test results of each chip in the virtual test unit are obtained to form the test result combination; The combination identifier value corresponding to the combination of test results is found in the mapping table.

10. A small-pitch wafer testing system, characterized in that, include: A probe station is used to hold the wafer to be tested and perform stepping movements. A probe card, installed on the probe station, includes multiple test positions, each test position corresponds to a virtual test unit, and each test position contains a probe group corresponding to all chips in the virtual test unit; The tester, electrically connected to the probe card, is used to perform parallel tests on multiple chips within the virtual test unit through multiple test channels; The calculation module is used to obtain the original step size of the chip on the wafer to be tested, and when the original step size is less than the preset minimum step size threshold of the test equipment, divide at least two adjacent chips into a virtual test unit, such that the step size of the virtual test unit is greater than or equal to the preset minimum step size threshold. The test control module is used to control the probe station to move in steps according to the step size of the virtual test unit, and to control the test machine to perform parallel tests on multiple chips contained in the same virtual test unit to obtain the test results of each chip. The data encoding module is used to encode the test results of each chip in the same virtual test unit into a combined identifier value using a preset encoding rule, and record the combined identifier value to the wafer map. The data restoration module is used to decode the combined identifier values ​​in the wafer map according to the decoding rules corresponding to the encoding rules, and restore the test results of each chip.

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