Core particle, test control method, chip and electronic equipment
By incorporating a scan isolation circuit, including a first scan chain and a multiplexer, into the chip, the problem of inaccurate chip interconnect interface connection testing is solved, achieving accuracy and reliability in chip internal and interconnect testing, and reducing testing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2024-10-30
- Publication Date
- 2026-05-05
AI Technical Summary
Existing technologies cannot effectively test whether the interconnect interfaces between chips are normal, resulting in inaccurate chip testing, which may lead to overall chip defects and increase manufacturing costs.
A scan isolation circuit is set in the chip, including a first scan chain and a multiplexer. Test data is registered through a first test trigger, and the multiplexer is used to select output test data in different modes to realize internal scan test and interconnection test of the chip, thereby avoiding interference between chips.
It enables accurate testing of chips, avoids interference between chips, improves the accuracy and reliability of chip testing, and reduces testing costs.
Smart Images
Figure CN121978513A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, specifically to a chip, a test control method, a chip, and an electronic device. Background Technology
[0002] Packaging technology interconnects multiple chips to form a chip, serving as a crucial means to improve chip performance and integrate functions, and is therefore widely used in chip manufacturing. To ensure the performance of chips using packaging technology, the chips need to be tested. Therefore, providing a technical solution to achieve accurate chip testing has become a pressing technical problem for those skilled in the art. Summary of the Invention
[0003] In view of this, embodiments of this application provide a chip, a test control method, a chip, and an electronic device, which can achieve accurate testing of the chip.
[0004] To achieve the above objectives, the embodiments of this application provide the following technical solutions.
[0005] In a first aspect, embodiments of this application provide a chip, including a scanning isolation circuit; the scanning isolation circuit includes:
[0006] The first scan chain includes a plurality of first triggers, the plurality of first triggers including at least one first functional trigger and a first test trigger. The first functional trigger is connected to a chip interconnect interface and receives chip interconnect data transmitted by the chip interconnect interface. The chip communicates with interconnected chip through the chip interconnect interface. The first test trigger is used to store test data of the chip.
[0007] A first multiplexer is connected to the chip interconnect interface and the output of the first test trigger. It is used to select the output of chip interconnect data transmitted by the chip interconnect interface in the chip's functional mode, and to select the output of the test data corresponding to the first test trigger in the chip's internal scan test mode.
[0008] Optionally, the plurality of first triggers are used to transmit the test data of the internal scanning test of the core through a shift operation in the internal scanning test mode of the core, until it is transmitted to the first test trigger.
[0009] In this configuration, the output of one of the plurality of first triggers is connected to the scan input of the next first trigger to transmit the test data of the chip internal scan test to the next first trigger; the chip test data includes the test data of the chip internal scan test.
[0010] Optionally, the chip further includes: an internal logic module; the internal logic module is connected to the output of the first functional trigger and the output of the first multiplexer;
[0011] The internal logic module is used to receive the chip interconnect data transmitted by the first functional trigger and the chip interconnect data output by the first multiplexer in the chip's functional mode; and to receive the chip internal scan test data output by the first multiplexer in the chip's internal scan test mode.
[0012] Optionally, the data input terminal of the first test trigger is connected to the chip interconnect interface, and is used to receive the chip interconnect test data transmitted by the chip interconnect interface in the chip interconnect test mode; the chip interconnect test data is shifted and output through the output terminal of the first test trigger to output the chip interconnect test result.
[0013] Optionally, the scan isolation circuit further includes: a second scan chain; the second scan chain includes a plurality of second flip-flops, the plurality of second flip-flops including at least one second functional flip-flop and a second test flip-flop;
[0014] The second functional trigger connects to the chip interconnect interface and transmits chip interconnect data to the chip interconnect interface;
[0015] The second test trigger is used at least to store test data for the chip interconnect test.
[0016] Optionally, the plurality of second triggers are used to pass the test data of the chip interconnect test step by step through a shift operation until it is passed to the second test trigger; wherein, the output terminal of the previous second trigger is connected to the scan input terminal of the next second trigger to pass the test data of the chip interconnect test to the next second trigger.
[0017] Optionally, the scan isolation circuit further includes: a second multiplexer; the second multiplexer is connected to the second test trigger and the internal logic module of the chip, and is used to select and output the chip interconnect data transmitted by the internal logic module and transmit it to the chip interconnect interface in the functional mode of the chip, and to select and output the test data of the chip interconnect test stored in the second test trigger and transmit it to the chip interconnect interface in the chip interconnect test mode.
[0018] Optionally, the first test trigger is also used to store isolated data, wherein the isolated data is passed step by step through the plurality of first triggers by a shift operation until it is passed to the first test trigger;
[0019] The first multiplexer is also used to respond to the isolation control signal and select the isolated data stored in the first test trigger for output to isolate the chip interconnect interface.
[0020] Optionally, the first multiplexer, in response to an isolation control signal, selects data stored in the first test trigger register for output to isolate the chip interconnect interface, including:
[0021] When the result of the chip interconnect test indicates that the interconnect between the chip and the interconnect chip has failed, the isolation data stored in the first test trigger is selected for output to isolate the chip interconnect interface.
[0022] Optionally, the core chip further includes a control circuit; the control circuit includes:
[0023] An OR gate unit is connected to the control terminal of the first multiplexer and is used to provide the isolation control signal to the first multiplexer.
[0024] Optionally, the control circuit further includes:
[0025] The first test storage unit is used to provide at least the first test information;
[0026] The second test storage unit is used to provide at least the second test information;
[0027] The third multiplexer is used to select target test information from the first test information provided by the first test storage unit and the second test information provided by the second test storage unit; and to form test data of the chip based on the selected target test information; wherein the formed test data of the chip is divided into test data of chip internal scan test and test data of chip interconnect test.
[0028] Optionally, the OR gate unit is also connected to the first test storage unit and the second test storage unit to generate the isolation signal; and the OR gate unit also generates a selection signal for the third multiplexer and transmits it to the control terminal of the third multiplexer to control the third multiplexer to select the target test information from the first test information and the second test information.
[0029] Optionally, the first test storage unit is a static test storage unit, and the information stored in the static test storage unit is fixed; the second test storage unit is a dynamic test storage unit, and the information stored in the dynamic test storage unit is dynamically adjustable.
[0030] The first test information includes first test data, a first source selection signal, and first isolation data, wherein the first source selection signal is a selection signal stored in the first test storage unit for selecting the input source of the scan isolation circuit;
[0031] The second test information includes second test data, a second source selection signal, and a second isolation signal, wherein the second source selection signal is a selection signal stored in the second test storage unit for selecting the input source of the scan isolation circuit.
[0032] Optionally, the chip further includes a clock circuit, the clock circuit comprising:
[0033] Internal clock unit, used to provide the chip's internal clock signal;
[0034] The clock signal switching unit is used to switch the internal clock signal provided by the internal clock unit;
[0035] A fourth multiplexer is used to select a target clock signal from the internal clock signal and the clock signal provided by the interconnect chip, as the clock signal used by the first scan chain and / or the second scan chain in the chip.
[0036] Secondly, embodiments of this application provide a test control method applied to the core chip described in the first aspect above, the method comprising:
[0037] Detect the current mode of the core chip;
[0038] In the current mode of the core-particle functional mode, the core-particle interconnect data transmitted by the core-particle interconnect interface is selected for output. The core-particle communicates with the interconnected core-particle through the core-particle interconnect interface.
[0039] In the current mode of the chip's internal scan test mode, select to output the test data registered corresponding to the first test trigger of the chip; wherein, the first test trigger is a trigger set for chip testing in the first scan chain of the chip.
[0040] Thirdly, embodiments of this application provide a chip including a plurality of chips, wherein the chips are as described in the first aspect above.
[0041] Fourthly, embodiments of this application provide an electronic device including the chip described in the third aspect above.
[0042] This application provides a chip, a test control method, a chip, and an electronic device. The chip includes a scan isolation circuit. The scan isolation circuit includes: a first scan chain, including a plurality of first flip-flops, the plurality of first flip-flops including at least one first functional flip-flop and a first test flip-flop. The first functional flip-flop is connected to a chip interconnect interface and receives chip interconnect data transmitted by the chip interconnect interface. The chip communicates with interconnected chips through the chip interconnect interface. The first test flip-flop is used to store test data of the chip; a first multiplexer, the first multiplexer being connected to the chip interconnect interface and the output terminal of the first test flip-flop, used to select the output of the chip interconnect data transmitted by the chip interconnect interface in the functional mode of the chip, and to select the output of the test data corresponding to the first test flip-flop in the internal scan test mode of the chip.
[0043] As can be seen, the chip provided in this application embodiment sets up a scan isolation circuit, sets up a test-dedicated first test trigger in the scan chain to register test data, and selects to output the corresponding registered test data in the scan test scenario inside the chip based on the first multiplexer, thereby avoiding interference from other chips to the chip under test and realizing accurate testing of the chip. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0045] Figure 1 This is an example diagram of a chip using 2D packaging technology;
[0046] Figure 2 This is an example diagram of a chip using 2.5D packaging technology;
[0047] Figure 3 This is an example diagram of a chip using 3D packaging technology;
[0048] Figure 4 This is an example diagram of scan isolation for inter-module isolation;
[0049] Figures 5 to 6 Example diagram of optional core structure provided in the embodiments of this application;
[0050] Figure 7 Example diagram of the interconnection structure of the chip provided in the embodiments of this application;
[0051] Figure 8An optional flowchart of the test control method provided in the embodiments of this application. Detailed Implementation
[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0053] In modern electronics manufacturing, chip packaging is a crucial step. Chip packaging involves encapsulating a semiconductor die—an integrated circuit manufactured on a silicon wafer—in a protective casing to facilitate circuit connections, heat dissipation, and physical installation in electronic devices. Chip packaging technology not only protects integrated circuits from physical damage and environmental influences but also provides an interface for electrical connections to external circuits.
[0054] The chip can be packaged using technologies such as 2D packaging, 2.5D packaging, and 3D packaging. This invention does not limit the packaging technology used in the chip. For example, Figure 1 Example diagram of a chip using 2D packaging technology, such as Figure 1 As shown, 2D packaging technology is a packaging technology that bonds multiple chips, such as chip 111 and chip 112, to a substrate 113 and connects the multiple chips through wires inside the substrate 113. Figure 2 Here is an example diagram of a chip using 2.5D packaging technology, such as... Figure 2 As shown, 2.5D packaging technology is a packaging technology that bonds multiple chips, such as chip 121 and chip 122, to an interposer 123 (including but not limited to a silicon interposer, a glass interposer, or an organic interposer) between the chip and the packaging substrate 124, and connects the multiple chips through wires on the interposer 123. Figure 3 Example diagram of a chip using 3D packaging technology, such as Figure 3 As shown, 3D packaging technology stacks multiple chips vertically and connects them via vertical interconnect technology. These chips can be categorized as: a master chip 131 and at least one slave chip 132 located on top of the master chip 131; wherein the slave chip 132 is located above the master chip, and all chips above the master chip except the one at the bottom can be referred to as slave chips; combined with... Figure 3 As shown, in the chip, the main chip can be connected to the chip's packaging substrate 133 so as to communicate with peripherals (external devices) through the peripheral interface provided on the packaging substrate.
[0055] Understandably, interconnections between chips typically require specific methods for electrical connection. For example, in chips using 2D / 2.5D packaging technology, the interconnect interfaces of multiple chips can be bonded to the substrate, thereby achieving chip interconnection through wires within the substrate. Similarly, in chips using 3D packaging technology, multiple chips can be interconnected using vertical interconnection technology, such as TSV (Through Silicon Via) technology, and the interconnect interfaces can correspondingly be TSV interfaces. Specifically, for chips using 3D packaging technology, each slave chip can be connected to the next layer of chips via a TSV interface. For example, a master chip can be connected to the slave chips on the layer above it via a TSV interface. Furthermore, the master chip and the packaging substrate can also be connected via a TSV interface.
[0056] However, if any chip involved in the packaging process has a defect or abnormality, it may cause the entire chip to have a defect or abnormality, and in severe cases, even lead to the entire chip being discarded, thus increasing the chip's manufacturing cost. Therefore, it is necessary to test the chips involved in the packaging process. Among these defects and abnormalities, chip defects or abnormalities may be caused by chip damage during the chip manufacturing process, or by chip damage caused by the packaging steps during the packaging process.
[0057] Currently, testing of packaged chips can be achieved based on DFT (Design for Test). DFT refers to adding various additional logic to the original chip design to improve the chip's testability without changing its functional design, thereby simplifying the testing process and making the chip easier to test. Testability includes two aspects: controllability and observability.
[0058] One way to test a chip is through a scan isolation chain design, which tests different sub-modules within a single chip to check for defects or anomalies in each functional module. Scan isolation chains are an implementation of Discrete Functional Theory (DFT) used to control and isolate test signals between different modules or sub-modules. This implementation enhances chip testability by making logic inputs controllable and logic outputs observable during sub-module design. For example, during internal module testing, inputs can be controlled via an input isolation chain, and outputs can be observed via an output isolation chain; conversely, during inter-module testing, outputs can be controlled via an output isolation chain, and inputs can be observed via an input isolation chain, achieving a hierarchical structural design.
[0059] To make it easier to understand, let's take inter-module testing as an example. Figure 4 This is an example diagram of scan isolation for inter-module isolation. For example... Figure 4As shown, taking the test between module 210 and module 220 as an example, module 210 includes an input isolation chain 211, a core chain 212, and an output isolation chain 213; module 220 includes an input isolation chain 221, a core chain 222, and an output isolation chain 223; wherein, the core chain is the scan chain inside the core logic, and the core chain works together with the input isolation chain and the output isolation chain to realize a hierarchical test structure.
[0060] exist Figure 4 As shown, when testing between modules 210 and 220, all output terminals can be controlled through output isolation chain 213, and input terminals can be observed through input isolation chain 221.
[0061] The aforementioned testing method based on scan isolation technology can test each sub-module within a chip and between sub-modules, thereby testing whether there are defects or anomalies in the modules within a single chip. However, chip testing involves not only individual chips but also the connections between chips, i.e., the connections formed between chips through interconnect interfaces. The aforementioned scan isolation technology cannot test the connections between chips, that is, it cannot test whether the connections of the interconnect interfaces between chips are normal. When there is a problem with the chip interconnection, for example, if one chip malfunctions, it cannot be controlled and isolated by the aforementioned scan isolation technology, thus failing to shield the affected chip from the influence of the failed chip on other normal chips, affecting the accurate testing of the chips.
[0062] Based on this, embodiments of this application provide an improved chip testing scheme that can perform internal testing of each chip in the chip while avoiding interference between chips, thereby achieving accurate testing of the chips.
[0063] refer to Figures 5 to 6 , Figures 5 to 6 This is an example diagram of an optional structure of a chip provided in an embodiment of this application. The chip 300 includes a scan isolation circuit (Die Wrapper chain); the scan isolation circuit may include:
[0064] The first scan chain 310 includes a plurality of first triggers, the plurality of first triggers including at least one first functional trigger 311 and a first test trigger 312. The first functional trigger is connected to the chip interconnect interface 302 and receives chip interconnect data transmitted by the chip interconnect interface. The chip communicates with interconnected chip through the chip interconnect interface. The first test trigger is used to store the test data of the chip.
[0065] The first multiplexer 320 is connected to the chip interconnect interface and the output terminal Q of the first test trigger 312. It is used to select the output of the chip interconnect data transmitted by the chip interconnect interface in the chip's functional mode, and to select the output of the test data corresponding to the first test trigger in the chip's internal scan test mode.
[0066] In this embodiment of the application, the first scan chain connects multiple first flip-flops in the scan isolation circuit to form a "chain" that can be accessed through an interconnection interface. The multiple first flip-flops can be registers. By connecting multiple first flip-flops together, registers with different storage capabilities and functions can be constructed, such as shift registers, which can perform left or right shift operations on a bit-by-bit basis.
[0067] The first trigger may include at least one first functional trigger and a first test trigger, as shown in the reference. Figures 5 to 6 This application embodiment uses two first functional triggers 311 as an example for illustration. The two first functional triggers 311 can be connected to the chip interconnect interface respectively. The chip 300 can be configured with multiple chip interconnect interfaces, with one first functional trigger connected to one interconnect interface. This allows communication with the interconnected chip through the chip interconnect interface, and the reception of chip interconnect data transmitted through the chip interconnect interface. In this embodiment, the first test trigger 312 is a scan isolation register (Die wrapper cell), which can serve as a dedicated control trigger for chip testing. It is activated during chip testing to store chip test data; the test data comes from the scan chain input signal SI (scan in) provided by the scan test circuit.
[0068] The first multiplexer 320 is connected to both the chip interconnect interface and the output terminal Q of the first test trigger 312. In different scenarios, the first multiplexer can control the selection of outputting chip interconnect data transmitted by the chip interconnect interface or test data corresponding to the first test trigger. Specifically, in the chip's functional mode, the chip interconnect data transmitted by the chip interconnect interface can be selected to be output; in the chip's internal scan test mode, the test data corresponding to the first test trigger can be selected to be output.
[0069] Below, refer to Figures 5 to 6 This application provides a detailed description of the internal scanning test of the core, based on the core structure provided.
[0070] In an optional implementation, the plurality of first triggers are used to pass the test data of the chip internal scan test step by step through a shift operation in the chip internal scan test mode until it is passed to the first test trigger 312; wherein, the output terminal Q of the previous first trigger is connected to the scan input terminal SI of the next first trigger to pass the test data of the chip internal scan test to the next first trigger; the test data of the chip includes the test data of the chip internal scan test.
[0071] In this embodiment, the plurality of first flip-flops are connected in sequence to realize the function of a shift register. In the internal scanning test mode of the chip, the test data of the internal scanning test of the chip can be transferred between the plurality of first flip-flops through shift operation until it is transferred to the first test flip-flop dedicated to chip testing. The first multiplexer 320 selects and outputs the test data registered in the first test flip-flop 312.
[0072] Furthermore, continue to refer to Figures 5 to 6 The core 300 further includes an internal logic module 330, which is connected to the output Q of the first functional trigger 311 and the output of the first multiplexer 320.
[0073] The internal logic module of the chip is the foundation for the chip to implement various functions. In the functional mode of the chip, the internal logic module 330 can receive the chip interconnect data transmitted by the first functional trigger 311 and the chip interconnect data output by the first multiplexer 320. In the internal scan test mode of the chip, the internal logic module 330 can receive the test data of the chip internal scan test output by the first multiplexer 302 to verify the functional correctness of the internal logic module.
[0074] In other words, in the embodiment of this application, in the chip internal scanning test mode, the chip internal logic module is designed to implement specific functions, such as data processing and signal control. By providing the test data output by the first multiplexer to the chip internal logic module, the internal logic module receives the test data of the chip internal scanning test and performs internal testing. This can check whether the internal logic module correctly implements the specific function according to the design requirements, thereby realizing the chip internal scanning test function.
[0075] Furthermore, as an optional implementation, the chip structure provided in this application embodiment can also realize chip interconnection testing, that is, testing whether the connection of the interconnection interface between chips is normal. Figure 7 This is an example diagram of the interconnection structure of the chip provided in the embodiments of this application, wherein, Figure 7The chip interconnect structure shown may include chip 710 and chip 720, which may be any two chips connected in the package structure. Both chip 710 and chip 720 contain the same scanning isolation circuit.
[0076] It should be noted that the scanning isolation circuit provided in this application embodiment is applicable to interconnection testing between any two connected chips in any of the above-mentioned packaging technologies, including 2D packaging, 2.5D packaging and 3D packaging technologies.
[0077] In an optional embodiment, the data input terminal D of the first test trigger 312 is connected to the chip interconnect interface, which can be used to receive the chip interconnect test data transmitted by the chip interconnect interface in the chip interconnect test mode; the chip interconnect test data is shifted and output through the output terminal Q of the first test trigger 312 to output the chip interconnect test result.
[0078] Understandably, in the chip interconnect test mode, the first test trigger of each chip acts as a receiver, used to receive chip interconnect test data transmitted through the chip interconnect interface for chip interconnect testing. The test data for chip interconnect testing only needs to be output by shifting the output terminal Q of the first test trigger. By checking whether the data transmitted and output by the chip interconnect interface is output normally and whether it meets the expected value, the connection between the interconnect interface between the two chips can be verified as normal.
[0079] Below, refer to Figures 5 to 7 The chip interconnection test is described in detail in conjunction with the chip structure provided in this application.
[0080] Accordingly, in the optional implementation, refer to Figure 5 or Figure 6 The scan isolation circuit further includes: a second scan chain 340; the second scan chain includes a plurality of second flip-flops, the plurality of second flip-flops including at least one second functional flip-flop 341 and a second test flip-flop 342; the second functional flip-flop is connected to the chip interconnect interface and transmits chip interconnect data to the chip interconnect interface; the second test flip-flop is at least used to store test data of chip interconnect test.
[0081] The second trigger may include at least one second functional trigger and a second test trigger, as shown in the reference. Figures 5 to 7This application embodiment uses two second functional triggers 341 as an example for illustration. The two second functional triggers 341 can be connected to the chip interconnect interface respectively. The chip 710 can be configured with multiple chip interconnect interfaces, and one second functional trigger connects to one interconnect interface. This allows communication with the interconnect chip through the chip interconnect interface, transmitting chip interconnect data to the chip interconnect interface. In this embodiment, the second test trigger 342 is a scan isolation register (Die wrapper cell), which can be used as a dedicated observation trigger for chip testing. It is activated during chip interconnect testing to capture data transmitted from the chip to the interconnect chip; that is, the second test trigger can be used to store test data for chip interconnect testing. The test data comes from the scan chain input signal SI (scan in) provided by the scan test circuit.
[0082] In an optional example, the plurality of second triggers are used to pass the test data of the chip interconnect test step by step through a shift operation until it is passed to the second test trigger; wherein, the output terminal Q of the previous second trigger is connected to the scan input terminal SI of the next second trigger to pass the test data of the chip interconnect test to the next second trigger.
[0083] In this embodiment, the multiple second flip-flops connected in sequence can realize the function of a shift register. In the chip interconnection test mode, the test data of the chip interconnection test can be transferred between multiple second flip-flops through shift operation until it is transferred to the second test flip-flop 342 dedicated to chip testing.
[0084] Furthermore, continue to refer to Figures 5 to 7 The scan isolation circuit further includes a second multiplexer 350; the second multiplexer is connected to the second test trigger 342 and the internal logic module 360 of the chip, and is used to select the output of the chip interconnect data transmitted by the internal logic module 360 and transmit it to the chip interconnect interface in the chip functional mode, and to select the output of the chip interconnect test data registered by the second test trigger 342 and transmit it to the chip interconnect interface in the chip interconnect test mode.
[0085] In this embodiment, the second multiplexer 350 is simultaneously connected to the chip interconnect interface and the output terminal Q of the second test trigger 342. In different scenarios, the second multiplexer can control the selection and output of the chip interconnect data transmitted by the internal logic module 360 or the chip interconnect test data registered in the second test trigger 342. Specifically, in the chip's functional mode, the chip interconnect data transmitted by the internal logic module 360 can be selected and transmitted to the chip interconnect interface; while in the chip's interconnect test mode, the chip interconnect test data registered in the second test trigger 342 can be selected and transmitted to the chip interconnect interface.
[0086] Combination Figure 7 In other words, in the chip interconnect test mode, the second multiplexer 350 of chip 710 selects and outputs the chip interconnect test data stored in the second test trigger 342 and transmits it to the chip interconnect interface; then the first test trigger 312 of chip 720, which is interconnected with chip 710, acts as the receiving end and receives the chip interconnect test data through the chip interconnect interface. The chip interconnect test data only needs to be output by Q shifting the output of the first test trigger of chip 720. Then, by checking whether the data transmitted and output by the chip interconnect interface can be output normally and whether it meets the expected value, the connection between the two chips is verified to be normal, thereby realizing the chip interconnect test.
[0087] As can be seen in the embodiments of this application, both the first test trigger and the second test trigger utilize the functions of multiplexed triggers. Specifically, a first test trigger dedicated to testing is added to the first functional trigger, and a second test trigger dedicated to testing is added to the second functional trigger. Combined with the use of the first multiplexer and the second multiplexer, the chip can achieve internal scanning testing and interconnection testing between chips while implementing the functional mode, thus saving testing costs.
[0088] In other embodiments, for scenarios where functional triggers cannot be reused as test triggers, a dedicated DFT isolation register (scan wrapper cell) can be selected to implement the chip testing function.
[0089] Furthermore, the first test trigger in this application embodiment can also be used to store isolated data, wherein the isolated data is passed step by step through the plurality of first triggers by a shift operation until it is passed to the first test trigger;
[0090] In this embodiment of the application, after the chip interconnect test is completed, if the chip interconnect test result is that the interconnect between chips fails, it may lead to an uncertain state due to the floating interconnect interface. Therefore, the first test trigger in this embodiment of the application can also store isolation data, which is passed through multiple first triggers step by step through shift operation until it is passed to the first test trigger.
[0091] Correspondingly, the first multiplexer can also be used to respond to the isolation control signal, select the isolation data stored in the first test trigger for output, so as to isolate the chip interconnect interface.
[0092] Specifically, when the result of the chip interconnect test is that the interconnect between the chip and the interconnect chip fails, the isolation data stored in the first test trigger is selected for output to isolate the chip interconnect interface.
[0093] In other words, when the interconnect test fails, in order to avoid the uncertainty caused by the interconnect interface being left floating, the first multiplexer receives and responds to the isolation control signal. It can select the isolation data stored in the first test trigger for output, thereby isolating the uncertainty signal caused by the interconnect interface being left floating. This avoids the interference of the failed or shut-down core to other cores under test, and achieves accurate testing of the core.
[0094] Continue to refer to Figure 5 Furthermore, the chip in this embodiment also includes a control circuit for providing test information. The control circuit may include an OR gate unit connected to the control terminal of the first multiplexer 320, for providing the isolation control signal to the first multiplexer. When the chip interconnect fails, the isolation control signal can be provided to the first multiplexer through the OR gate unit to isolate the chip interconnect interface.
[0095] In an optional implementation, the control circuit further includes: a first test storage unit 370 for providing at least first test information; and a second test storage unit 380 for providing at least second test information.
[0096] The first test storage unit 370 is a static test storage unit, and the information stored in the static test storage unit is fixed. The first test information includes first test data, a first source selection signal, and first isolation data. The first source selection signal is a selection signal stored in the first test storage unit for selecting the input source of the scan isolation circuit.
[0097] In an optional example, refer to Figure 5The first test storage unit 370 can be an OTP (one-time programmable) storage unit. OTP is used to store test data that does not need to be changed after manufacturing / completion is completed, and has a certain degree of security and anti-tampering capability.
[0098] The second test storage unit is a dynamic test storage unit, and the information stored in the dynamic test storage unit is dynamically adjustable; the second test information includes second test data, a second source selection signal, and a second isolation signal, wherein the second source selection signal is a selection signal stored in the second test storage unit for selecting the input source of the scan isolation circuit.
[0099] In an optional example, refer to Figure 5 The second test storage unit 380 can be a Scan Controller for a scan test circuit, used to store dynamically adjustable test data that can be adjusted according to test requirements.
[0100] In other embodiments, the test storage unit that provides a signal source for the scan isolation circuit can also be a JTAG (Joint Test Access Group) network, or other structures or combinations thereof that can provide a scan isolation input source.
[0101] In the embodiments of this application, both the first test storage unit and the second test storage unit store control signals for controlling whether the scan isolation circuit is enabled. For example, before the chip interconnection, each chip enables the scan isolation circuit to isolate the chip for internal scan testing; after the chip interconnection, the scan isolation circuits of all chips under test are enabled simultaneously to test the interconnection interface between chips.
[0102] Furthermore, during the chip testing process, the first test information provides a first source selection signal and corresponding first test data, and the second test information provides a second source selection signal and corresponding second test data. The third multiplexer 390 can then select and output the test information provided by the two test storage units.
[0103] Specifically, the control circuit further includes a third multiplexer 390, used to select target test information from the first test information provided by the first test storage unit and the second test information provided by the second test storage unit; and to form test data of the chip based on the selected target test information; wherein the formed test data of the chip can be divided into test data of chip internal scanning test and test data of chip interconnection test.
[0104] In an optional implementation, the OR gate unit connects the first test storage unit and the second test storage unit to generate an isolation signal; the OR gate unit also generates a selection signal for the third multiplexer 390 and transmits it to the control terminal of the third multiplexer to control the third multiplexer to select the corresponding target test information from the first test information and the second test information.
[0105] In an optional example, in the chip internal scan test mode, the third multiplexer can select the first test storage unit, such as the first test information provided by the Scan Controller of the scan test circuit; in the chip interconnect test mode, if the interconnect test result is that the interconnect chip fails, the third multiplexer can select the second test storage unit, such as the data stored in the OTP, to isolate the chip.
[0106] In a further optional implementation, refer to Figure 6 The chip also includes a clock circuit, which includes: an internal clock unit 411 for providing an internal clock signal for the chip; and a clock signal switching unit 412 for switching the internal clock signal provided by the internal clock unit; wherein the internal clock unit obtains the internal clock signal through a test pin 301.
[0107] In a specific example, the internal clock unit can be a phase-locked loop (PLL), and the clock signal switching unit can be an on-chip clock controller (OCC) used to switch the internal clock signal provided by the PLL with the clock signal provided by other devices (such as interconnect chips) according to actual needs.
[0108] Furthermore, the clock circuit is also provided with a fourth multiplexer 420, which is used to select a target clock signal from the internal clock signal and the clock signal provided by the interconnect chip, as the clock signal used by the first scan chain and / or the second scan chain in the chip (shown as test_clk).
[0109] In the chip-internal scanning test, the internal clock signal can be selected as the target clock signal. In the chip interconnect test, taking a chip using 3D packaging technology as an example, if the interconnect chip is the main chip, the clock signal provided by the interconnect chip is selected; if the chip is the main chip, the internal clock signal is selected. (Refer to...) Figure 7Assuming that chip 710 and chip 720 are two connected chips (including master chip and slave chip) in a chip using 3D packaging technology, then when performing interconnection tests between chips, the fourth multiplexer 420 always selects the clock signal provided by the master chip as the test clock (shown as test_clk) of the scan isolation circuit including the first scan chain 310 and the second scan chain 340, to ensure clock synchronization and stability.
[0110] In a further optional implementation, based on the chip provided in the embodiments of this application, the embodiments of this application also provide a test control method applied to the chip described in the foregoing embodiments. In an optional implementation, Figure 8 An optional flowchart of the test control method provided in an embodiment of this application. (Refer to...) Figure 8 The method may include the following steps:
[0111] Step S801: Detect the current mode of the core chip;
[0112] Step S802: In the current mode of the chip functional mode, select the chip interconnect data transmitted by the chip interconnect interface to be output. The chip communicates with the interconnect chip through the chip interconnect interface.
[0113] Step S803: In the current mode of the chip's internal scan test mode, select and output the test data corresponding to the first test trigger of the chip; wherein, the first test trigger is a trigger set for chip testing in the first scan chain of the chip.
[0114] It should be noted that the optional and extended implementations of the test control method provided in this application can be referred to in conjunction with the descriptions in the corresponding sections above, and will not be elaborated here.
[0115] In a further optional implementation, this application embodiment also provides a chip including a plurality of chips, wherein the chips are as described in the foregoing embodiments.
[0116] In a further optional implementation, embodiments of this application also provide an electronic device, such as a server device or a terminal device, including the chip described in the foregoing embodiments.
[0117] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.
[0118] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A core element, characterized in that, Includes a scan isolation circuit; the scan isolation circuit includes: The first scan chain includes a plurality of first triggers, the plurality of first triggers including at least one first functional trigger and a first test trigger. The first functional trigger is connected to a chip interconnect interface and receives chip interconnect data transmitted by the chip interconnect interface. The chip communicates with interconnected chip through the chip interconnect interface. The first test trigger is used to store test data of the chip. A first multiplexer is connected to the chip interconnect interface and the output of the first test trigger. It is used to select the output of chip interconnect data transmitted by the chip interconnect interface in the chip's functional mode, and to select the output of the test data corresponding to the first test trigger in the chip's internal scan test mode.
2. The core chip according to claim 1, characterized in that, The plurality of first triggers are used to transmit the test data of the internal scanning test of the core through a shift operation in the internal scanning test mode of the core, until it is transmitted to the first test trigger. In this configuration, the output of one of the plurality of first triggers is connected to the scan input of the next first trigger to transmit the test data of the chip internal scan test to the next first trigger; the chip test data includes the test data of the chip internal scan test.
3. The core element according to claim 2, characterized in that, The chip also includes: an internal logic module; the internal logic module is connected to the output of the first functional trigger and the output of the first multiplexer; The internal logic module is used to receive the chip interconnect data transmitted by the first functional trigger and the chip interconnect data output by the first multiplexer in the chip's functional mode; and to receive the chip internal scan test data output by the first multiplexer in the chip's internal scan test mode.
4. The core chip according to claim 1, characterized in that, The data input terminal of the first test trigger is connected to the chip interconnect interface, and is used to receive the chip interconnect test data transmitted by the chip interconnect interface in the chip interconnect test mode; the chip interconnect test data is shifted and output through the output terminal of the first test trigger to output the chip interconnect test result.
5. The core chip according to any one of claims 1-4, characterized in that, The scan isolation circuit further includes: a second scan chain; the second scan chain includes a plurality of second flip-flops, the plurality of second flip-flops including at least one second functional flip-flop and a second test flip-flop; The second functional trigger connects to the chip interconnect interface and transmits chip interconnect data to the chip interconnect interface; The second test trigger is used at least to store test data for the chip interconnect test.
6. The core element according to claim 5, characterized in that, The plurality of second triggers are used to pass the test data of the chip interconnect test step by step through a shift operation until it is passed to the second test trigger; wherein, the output terminal of the previous second trigger is connected to the scan input terminal of the next second trigger to pass the test data of the chip interconnect test to the next second trigger.
7. The core chip according to claim 6, characterized in that, The scan isolation circuit further includes: a second multiplexer; the second multiplexer is connected to the second test trigger and the internal logic module of the chip, and is used to select the chip interconnect data transmitted by the internal logic module and transmit it to the chip interconnect interface in the functional mode of the chip, and to select the test data of the chip interconnect test stored in the second test trigger and transmit it to the chip interconnect interface in the chip interconnect test mode.
8. The core element according to claim 1, characterized in that, The first test trigger is also used to store isolated data, wherein the isolated data is passed step by step through the plurality of first triggers by a shift operation until it is passed to the first test trigger; The first multiplexer is also used to respond to the isolation control signal and select the isolated data stored in the first test trigger for output to isolate the chip interconnect interface.
9. The core chip according to claim 8, characterized in that, The first multiplexer, in response to an isolation control signal, selects data stored in the first test trigger register for output to isolate the chip interconnect interface, including: When the result of the chip interconnect test indicates that the interconnect between the chip and the interconnect chip has failed, the isolation data stored in the first test trigger is selected for output to isolate the chip interconnect interface.
10. The core according to claim 9, characterized in that, The core also includes a control circuit; the control circuit includes: An OR gate unit is connected to the control terminal of the first multiplexer and is used to provide the isolation control signal to the first multiplexer.
11. The core according to claim 10, characterized in that, The control circuit also includes: The first test storage unit is used to provide at least the first test information; The second test storage unit is used to provide at least the second test information; The third multiplexer is used to select target test information from the first test information provided by the first test storage unit and the second test information provided by the second test storage unit; and to form test data of the chip based on the selected target test information; wherein the formed test data of the chip is divided into test data of chip internal scan test and test data of chip interconnect test.
12. The core according to claim 11, characterized in that, The OR gate unit is also connected to the first test storage unit and the second test storage unit to generate the isolation signal; and the OR gate unit also generates a selection signal for the third multiplexer and transmits it to the control terminal of the third multiplexer to control the third multiplexer to select the target test information from the first test information and the second test information.
13. The core according to claim 12, characterized in that, The first test storage unit is a static test storage unit, and the information stored in the static test storage unit is fixed; the second test storage unit is a dynamic test storage unit, and the information stored in the dynamic test storage unit is dynamically adjustable. The first test information includes first test data, a first source selection signal, and first isolation data, wherein the first source selection signal is a selection signal stored in the first test storage unit for selecting the input source of the scan isolation circuit; The second test information includes second test data, a second source selection signal, and a second isolation signal, wherein the second source selection signal is a selection signal stored in the second test storage unit for selecting the input source of the scan isolation circuit.
14. The core element according to claim 5, characterized in that, The chip also includes a clock circuit, which comprises: Internal clock unit, used to provide the chip's internal clock signal; The clock signal switching unit is used to switch the internal clock signal provided by the internal clock unit; A fourth multiplexer is used to select a target clock signal from the internal clock signal and the clock signal provided by the interconnect chip, as the clock signal used by the first scan chain and / or the second scan chain in the chip.
15. A test control method, characterized in that, Applied to the core according to any one of claims 1 to 14, the method comprises: Detect the current mode of the core chip; In the current mode of the core-particle functional mode, the core-particle interconnect data transmitted by the core-particle interconnect interface is selected for output. The core-particle communicates with the interconnected core-particle through the core-particle interconnect interface. In the current mode of the chip's internal scan test mode, select to output the test data registered corresponding to the first test trigger of the chip; wherein, the first test trigger is a trigger set for chip testing in the first scan chain of the chip.
16. A chip, characterized in that, It includes a plurality of cores, wherein the cores are as described in any one of claims 1 to 14.
17. An electronic device, characterized in that, Includes the chip described in claim 16.