Low-dropout linear voltage stabilizing circuit and chip

Abstract

The invention discloses a low-dropout linear voltage stabilizing circuit and a chip. The low-dropout linear voltage stabilizing circuit comprises a voltage input end; a voltage output end; the first end of the power tube is connected with the voltage input end, and the second end is connected with the voltage output end; the first end of the detection transistor is connected with the voltage input end, and the control end is connected with the control end of the power tube; the feedback control circuit is used for generating a corresponding regulation and control signal based on the accessed first reference voltage and the current target voltage and outputting the regulation and control signal to the control end of the power tube and the control end of the detection transistor; the rate regulation and control circuit is used for controlling the current change rate when the feedback control circuit controls the power tube to output the current; and the current limiting circuit is used for limiting the output current of the power tube not to exceed a preset current threshold. According to the low-dropout linear voltage stabilizing circuit, any drop point is limited above the reset voltage when the input voltage drops in the starting stage, so that the problem of chip reset caused by drop of the input voltage in the starting stage can be avoided.

Description

Technical Field

[0001] This invention relates to the field of MCU technology, specifically to a low dropout linear voltage regulator circuit and chip. Background Technology

[0002] Low dropout regulators (LDOs) can convert high, wide-range input voltages into stable, precise low voltages, thereby powering a chip that requires stable, precise low voltages.

[0003] In related technologies, low-dropout linear regulator circuits consist of an amplifier, a feedback network, and a regulating transistor, such as... Figure 1 As shown, when this low-dropout linear regulator circuit is used, the input voltage will drop significantly during the startup phase because charge conservation needs to be considered. The lowest point of the drop during the process may be less than or equal to the chip's reset voltage to reset the chip, making it unsuitable for chips. Summary of the Invention

[0004] The main technical problem solved by this invention is that the low-dropout linear voltage regulator circuit in the related technology may reset the chip when the lowest point of the input voltage drop during the startup phase is less than or equal to the chip's reset voltage, which is not applicable to the chip.

[0005] According to a first aspect, one embodiment of this application provides a low-dropout linear regulator circuit applied to a chip, the low-dropout linear regulator circuit comprising:

[0006] Voltage input terminal, used to connect the input voltage;

[0007] The voltage output terminal is used to output the target voltage after adjusting the input voltage;

[0008] A power transistor, with its first terminal connected to the voltage input terminal and its second terminal connected to the voltage output terminal;

[0009] The detection transistor has its first terminal connected to the voltage input terminal and its control terminal connected to the control terminal of the power transistor.

[0010] A feedback control circuit includes a first voltage input terminal, a second voltage input terminal, and a control terminal. The first voltage input terminal is used to connect to a first reference voltage, and the second voltage input terminal is used to connect to the current target voltage. The control terminal of the feedback control circuit is connected to the control terminal of the power transistor and the control terminal of the detection transistor. The feedback control circuit generates corresponding adjustment signals based on the first reference voltage and the current target voltage, and outputs them to the control terminals of the power transistor and the detection transistor, so that a proportional current is generated on the power transistor and the detection transistor.

[0011] A rate control circuit is connected to the control terminal of the feedback control circuit. The rate control circuit is used to control the rate of change of current when the feedback control circuit controls the output current of the power transistor, so that the lowest point of the input voltage drop caused by the feedback control circuit during the startup phase is greater than a first preset voltage threshold, and the first preset voltage threshold is greater than the reset voltage of the chip.

[0012] A current limiting circuit is connected to the control terminal of the power transistor and the second terminal of the detection transistor. The current limiting circuit is used to limit the output current of the power transistor from exceeding a preset current threshold, and to make the lowest point of the input voltage drop caused by the output current during the startup phase greater than a second preset voltage threshold, wherein the second preset voltage threshold is greater than the reset voltage.

[0013] Specifically, when the input voltage is less than or equal to the chip's reset voltage during the startup phase, the chip is reset.

[0014] In one embodiment, the drop in input voltage during the startup phase includes a first-stage drop and a second-stage drop, wherein the first-stage drop is the drop in input voltage caused by the feedback control circuit during the startup phase, and the second-stage drop is the drop in input voltage caused by the output current during the startup phase.

[0015] The time period during which the input voltage drops in the first stage and the time period during which the input voltage drops in the second stage constitute the total time period during which the input voltage drops in the startup phase.

[0016] In one embodiment, the feedback control unit includes:

[0017] A voltage divider network is connected between the voltage output terminal and ground. The voltage divider network is used to output a first feedback voltage that is proportional to the current target voltage based on the adjusted voltage.

[0018] A first error amplifier, wherein the non-inverting input terminal of the first error amplifier is the second voltage input terminal, the inverting input terminal of the first error amplifier is the first voltage input terminal, and the control terminal of the first error amplifier is the control terminal of the feedback control circuit, wherein the first error amplifier is used to generate the control signal based on the voltage difference between the first reference voltage and the first feedback voltage.

[0019] In one embodiment, the driving capability of the first error amplifier is adjusted to a preset driving capability, such that the lowest point of the input voltage drop caused by the feedback control circuit during the startup phase is greater than a first preset voltage threshold.

[0020] In one embodiment, the rate control circuit includes: a first capacitor, one end of which is connected to the control terminal of the feedback control unit, and the other end is grounded; the capacitance value of the first capacitor represents the rate of change of current when the feedback control circuit controls the output current of the power transistor.

[0021] In one embodiment, the current limiting circuit includes:

[0022] A sampling resistor, one end of which is connected to the second terminal of the detection transistor and the other end is grounded. The sampling resistor is used to adjust the preset current threshold. The resistance value of the sampling resistor represents the preset current threshold that limits the power transistor. The connection node between the sampling resistor and the second terminal of the detection transistor is configured as a feedback terminal for outputting a second feedback voltage.

[0023] The comparator control circuit includes a first input terminal, a second input terminal, and a control terminal; the first input terminal is used to connect to a second reference voltage; the second input terminal is connected to the feedback terminal and is used to connect to the feedback voltage; the control terminal of the comparator control circuit is connected to the control terminal of the power transistor, and the comparator control circuit is used to generate a control signal based on the voltage difference between the second reference voltage and the feedback voltage to output to the control terminal of the power transistor, and the control signal is used to adjust the current flowing through the power transistor.

[0024] In one embodiment, the comparison control circuit includes:

[0025] A driving transistor, the first terminal of which is connected to the voltage input terminal, and the second terminal of which is connected to the control terminal of the power transistor;

[0026] The second error amplifier has a non-inverting input terminal connected to a second reference voltage, an inverting input terminal connected to the feedback terminal, and a control terminal connected to the control terminal of the driving transistor; the second error amplifier is used to generate the control signal based on the voltage difference between the second reference voltage and the second feedback voltage.

[0027] According to a second aspect, one embodiment of this application provides a low-dropout linear regulator circuit applied to a chip, the low-dropout linear regulator circuit comprising:

[0028] Voltage input terminal, used to connect the input voltage;

[0029] The voltage output terminal is used to output the target voltage after adjusting the input voltage;

[0030] A power transistor, with its first terminal connected to the voltage input terminal and its second terminal connected to the voltage output terminal;

[0031] The detection transistor has its first terminal connected to the voltage input terminal and its control terminal connected to the control terminal of the power transistor.

[0032] A feedback control circuit includes a first voltage input terminal, a second voltage input terminal, and a control terminal. The first voltage input terminal is used to connect to a first reference voltage, and the second voltage input terminal is used to connect to the target voltage. The control terminal of the feedback control circuit is connected to the control terminal of the power transistor and the control terminal of the detection transistor. The feedback control circuit generates corresponding adjustment signals based on the connected first reference voltage and the target voltage, and outputs them to the control terminals of the power transistor and the detection transistor, so that a proportional current is generated on the power transistor and the detection transistor.

[0033] A current limiting and sag suppression circuit is connected to the control terminal of the power transistor. The current limiting and sag suppression circuit is used to limit the output current of the power transistor from exceeding a preset current threshold and to limit any drop point of the input voltage during the startup phase above the reset voltage of the chip.

[0034] Specifically, when the input voltage is less than or equal to the chip's reset voltage during the startup phase, the chip is reset.

[0035] In one embodiment, the current limiting and dropout suppression circuit includes:

[0036] A rate control circuit is connected to the control terminal of the feedback control circuit. The rate control circuit is used to control the rate of change of current when the feedback control circuit controls the output current of the power transistor, so that the lowest point of the input voltage drop caused by the feedback control circuit during the startup phase is greater than a first preset voltage threshold, and the first preset voltage threshold is greater than the reset voltage of the chip.

[0037] A current limiting circuit is connected to the control terminal of the power transistor and the second terminal of the detection transistor. The current limiting circuit is used to limit the output current of the power transistor from exceeding a preset current threshold, and to make the lowest point of the input voltage drop caused by the output current during the startup phase greater than a second preset voltage threshold, wherein the second preset voltage threshold is greater than the reset voltage.

[0038] The input voltage drop during the startup phase includes a first-stage drop and a second-stage drop. The first-stage drop is the input voltage drop caused by the feedback control circuit during the startup phase, and the second-stage drop is the input voltage drop caused by the output current during the startup phase.

[0039] The time period during which the input voltage drops in the first stage and the time period during which the input voltage drops in the second stage constitute the total time period during which the input voltage drops in the startup phase.

[0040] According to a third aspect, one embodiment of this application provides a chip, including: a low-dropout linear regulator circuit as described above.

[0041] According to the low-dropout linear regulator circuit and chip of the above embodiment, when the low-dropout linear regulator circuit is applied, the input voltage drops due to the feedback control circuit and the output current of the power transistor during the startup phase. The rate control circuit can limit the lowest point of the input voltage drop caused by the feedback control circuit during the startup phase to be greater than a first preset voltage threshold. The current limiting circuit can limit the lowest point of the input voltage drop caused by the output current of the power transistor during the startup phase to be greater than a second preset voltage threshold. Therefore, it can be seen that any drop point in the input voltage during the startup phase of the low-dropout linear regulator circuit is limited to above the reset voltage, thereby avoiding the problem of chip reset caused by the input voltage drop during the startup phase. Attached Figure Description

[0042] Figure 1 This is a circuit structure diagram of a low-dropout linear voltage regulator circuit in the prior art;

[0043] Figure 2 This is a circuit diagram of a low-dropout linear regulator circuit according to one embodiment;

[0044] Figure 3 The waveform diagram for unrestricted input voltage drop;

[0045] Figure 4 This is a comparison graph showing the waveforms of unrestricted and restricted input voltage drops.

[0046] Reference numerals: 100, Feedback control circuit; 200, Rate control circuit; 300, Current limiting circuit; 301, Comparison control circuit; 400, Current limiting and dropout suppression circuit; OP1, First error amplifier; OP2, Second error amplifier; PM1, Power transistor; PM2, Detection transistor; PM3, Drive transistor; CL, Load capacitor; Cgate, First capacitor; VCC, Voltage input terminal; VLDO, Voltage output terminal; Vref1, First reference voltage; Vref2, Second reference voltage. Detailed Implementation

[0047] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0048] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0049] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0050] The core CPU inside an MCU (Microcontroller Unit) chip has high requirements for speed and power consumption. A wide range of power supply voltages cannot meet these requirements simultaneously. Generally, a low dropout linear regulator circuit is needed to convert the high, wide-range input voltage into a stable, precise low voltage.

[0051] like Figure 1The diagram shown is a circuit structure diagram of a low-dropout linear regulator circuit in the prior art. If this low-dropout linear regulator circuit is applied to a chip, considering the charge conservation C1*VCC=C2*V2 (C1 represents the capacitance on the power supply voltage VCC; C2 represents the sum of the capacitance on VCC and the output capacitance; VCC represents the input voltage; V2 represents the power supply voltage after the voltage drop), there is an instantaneous drop in the input voltage during the startup phase. The lowest point of the voltage drop during the drop process may be less than or equal to the chip's reset voltage to reset the chip, which is not suitable for chips.

[0052] To address the aforementioned technical problems, this application provides a low-dropout linear regulator circuit that can be applied to chips. When this low-dropout linear regulator circuit is applied, the input voltage drops due to the feedback control circuit 100 during the startup phase and the output current of the power transistor PM1. The rate control circuit 200 can limit the lowest point of the input voltage drop caused by the feedback control circuit 100 during the startup phase to be greater than a first preset voltage threshold. The current limiting circuit 300 can limit the lowest point of the input voltage drop caused by the output current of the power transistor PM1 during the startup phase to be greater than a second preset voltage threshold. Thus, any drop point of the input voltage during the startup phase is limited to above the reset voltage, avoiding the problem of chip reset caused by the drop in input voltage during the startup phase.

[0053] In some embodiments, such as Figure 2As shown, the low-dropout linear regulator circuit may include a voltage input terminal VCC, a voltage output terminal VLDO, a power transistor PM1, a detection transistor PM2, a feedback control circuit 100, a rate control circuit 200, and a current limiting circuit 300. The voltage input terminal VCC is used to connect the input voltage. The voltage output terminal VLDO is used to output the target voltage after adjusting the input voltage. A load capacitor CL is provided at the voltage output terminal VLDO; one end of the load capacitor CL is connected to the voltage output terminal VLDO, and the other end of the load capacitor CL is grounded. The first terminal of the power transistor PM1 is connected to the voltage input terminal VCC, and the second terminal is connected to the voltage output terminal VLDO. The first terminal of the detection transistor PM2 is connected to the voltage input terminal VCC, and its control terminal is connected to the control terminal of the power transistor PM1. The feedback control circuit 100 includes a first voltage input terminal VCC, a second voltage input terminal VCC, and a control terminal. The first voltage input terminal VCC is used to connect a first reference voltage Vref1, and the second voltage input terminal VCC is used to connect a target voltage. The control terminal of the feedback control circuit 100 is connected to the control terminal of the power transistor PM1 and the control terminal of the detection transistor PM2. The feedback control circuit 100 generates corresponding control signals based on the connected first reference voltage Vref1 and the target voltage, and outputs them to the control terminals of the power transistor PM1 and the detection transistor PM2, so that a proportional current is generated on the power transistor PM1 and the detection transistor PM2. The first reference voltage Vref1 can be provided by a reference voltage source. The rate regulation circuit 200 is connected to the control terminal of the feedback control circuit 100. The rate regulation circuit 200 controls the rate of change of the current when the feedback control circuit 100 controls the output current of the power transistor PM1, so that the lowest point of the input voltage drop caused by the feedback control circuit 100 during the startup phase is greater than a first preset voltage threshold, which is greater than or equal to the chip's reset voltage. The current limiting circuit 300 is connected to the control terminal of power transistor PM1 and the second terminal of detection transistor PM2. The current limiting circuit 300 limits the output current of power transistor PM1 to not exceed a preset current threshold, ensuring that the lowest point of the input voltage drop caused by the output current during startup is greater than a second preset voltage threshold, which is greater than or equal to the reset voltage. When the input voltage is less than or equal to the chip's reset voltage during startup, the chip resets.

[0054] When this low-dropout linear regulator circuit is applied, during the startup phase, the feedback control circuit 100 causes a voltage drop in the input voltage, and the output current of the power transistor PM1 also causes a voltage drop in the input voltage. The lowest point of the voltage drop caused by the feedback control circuit 100 is related to the rate of change of the output current on the power transistor PM1. A faster rate of change results in a lower lowest point of the voltage drop caused by the feedback control circuit 100. Similarly, the lowest point of the voltage drop caused by the output current of the power transistor PM1 is related to the magnitude of the output current (which is the charging current of the load capacitor CL during startup). A larger output current results in a lower lowest point of the voltage drop caused by the output current of the power transistor PM1.

[0055] The input voltage drop during the startup phase of this low-dropout linear regulator circuit includes a first-stage drop and a second-stage drop. The first-stage drop is the input voltage drop caused by the feedback control circuit 100 during the startup phase, and the second-stage drop is the input voltage drop caused by the output current during the startup phase. The time period of the first-stage drop and the time period of the second-stage drop are the total time period of the input voltage drop during the startup phase.

[0056] like Figure 3 As shown, Figure 3 ① in the figure is the waveform diagram when the input voltage drops due to the feedback control circuit 100, that is, the waveform diagram of the first stage drop; Figure 3 ② in the figure is the waveform diagram when the output current of the power transistor PM1 causes the input voltage to drop, that is, the waveform diagram of the second stage drop.

[0057] When the input voltage drops due to the feedback control circuit 100 during the startup phase, the magnitude of the drop can be determined by the following formula:

[0058] ∆V1=L*(dI / dt);

[0059] Where ∆V1 is the drop amplitude; L is the parasitic inductance; and dI / dt is the rate of change of the output current on the power transistor.

[0060] Based on the above formula, it can be seen that the drop amplitude is related to the rate of change of the output current on the power transistor PM1 and the parasitic inductance. Therefore, when the parasitic inductance is constant, the drop amplitude can be reduced by slowing down the rate of change of the output current on the power transistor PM1. That is, by adjusting the feedback control circuit 100 to cause the input voltage drop to the lowest point, when the lowest point of the drop is raised, the rate of change of the output current on the power transistor PM1 can be controlled to limit the lowest point of the drop to above the first preset voltage threshold.

[0061] In some embodiments, the power transistor PM1 and the detection transistor PM2 can both be P-MOS (P-channel metal-oxide-semiconductor field-effect transistor). For the power transistor PM1 and the detection transistor PM2, the first terminal refers to the source of the P-MOS, the second terminal refers to the drain of the P-MOS, and the control terminal refers to the gate of the P-MOS. Power transistor PM1 and detection transistor PM2 form a current mirror. The size of power transistor PM1 is k times the size of detection transistor PM2. The current flowing through power transistor PM1 can be obtained by mirroring the current flowing through detection transistor PM2. The current in power transistor PM1 (i.e., the output current) is approximately K times the current in detection transistor PM2 (I1≈K*I2, where I1 represents the output current in power transistor PM1 and I2 represents the current in detection transistor PM2). When current is generated in power transistor PM1 and detection transistor PM2, the feedback control circuit 100 can output a control signal to the control terminals of power transistor PM1 and detection transistor PM2. Furthermore, the opening degree of power transistor PM1 and detection transistor PM2 can be adjusted by controlling the control signal to regulate the current in power transistor PM1 and detection transistor PM2.

[0062] Those skilled in the art will understand that different chips may correspond to different reset voltages. Therefore, when determining the first preset voltage threshold and the second preset voltage threshold, they can be determined according to the reset voltage corresponding to the applied chip, ensuring that both the first preset voltage threshold and the second preset voltage threshold are not less than the reset voltage. After the first preset voltage threshold and the second preset voltage threshold are determined, the rate control circuit 200 can limit the lowest point of the input voltage drop caused by the feedback control circuit 100 to above the first preset voltage threshold, and the current limiting circuit 300 can limit the lowest point of the input voltage drop caused by the output current to above the second preset voltage threshold.

[0063] When the rate control circuit 200 limits the minimum input voltage drop caused by the feedback control circuit 100 to be above the first preset voltage threshold, it does so during the startup phase by slowing down the rate of change of the output current on the power transistor PM1, thereby limiting the rate of input voltage drop and thus limiting the minimum input voltage drop caused by the feedback control circuit 100, keeping it above the first preset voltage threshold. Slowing down the rate of change of the output current on the power transistor PM1 can also be understood as slowing down the turn-on speed of the power transistor PM1.

[0064] The current limiting circuit 300 limits the input voltage drop caused by the output current to the lowest point above the second preset voltage threshold. During the startup phase, the charging current (i.e., the output current on the power transistor PM1) is limited by the preset current threshold to limit the magnitude of the charging current when charging the load capacitor CL, thereby limiting the rate of input voltage drop and keeping it above the second preset voltage threshold.

[0065] It should be noted that during the startup phase, the rate of change of the output current controlled by the feedback control circuit 100 on the power transistor PM1 is related to the rate of drop in the input voltage caused by the feedback control circuit 100; a faster rate of change results in a higher rate of drop. Similarly, during the startup phase, the magnitude of the charging current is related to the rate of drop in the input voltage caused by the charging current; a larger charging current results in a higher rate of drop.

[0066] During the startup phase, the feedback control circuit 100 and the output current of the power transistor PM1 cause a voltage drop in the input voltage. To suppress this drop, the rate control circuit 200 limits the minimum input voltage drop caused by the feedback control circuit 100 to be greater than a first preset voltage threshold. Similarly, the current limiting circuit 300 limits the minimum input voltage drop caused by the output current of the power transistor PM1 to be greater than a second preset voltage threshold. Since both the first and second preset voltage thresholds are greater than the chip's reset voltage, any voltage drop point during startup is above the reset voltage, thus preventing the chip from resetting due to input voltage drops and ensuring normal startup. Figure 4 As can be seen, the lowest point of the fall in the first stage was raised, and the lowest point of the fall in the second stage was also raised. Figure 4 The dashed line represents the drop waveform after the rate control circuit 200 and the current limiting circuit 300 adjust the drop minimum point; the solid line represents the drop waveform without adjusting the drop minimum point through the rate control circuit 200 and the current limiting circuit 300.

[0067] In some embodiments, the feedback control unit may include a voltage divider network and a first error amplifier OP1. The voltage divider network is connected between the voltage output terminal VLDO and ground. The voltage divider network is used to output a first feedback voltage that is proportional to the current target voltage output by the voltage output terminal VLDO based on the regulated voltage. The non-inverting input terminal of the first error amplifier OP1 is the second voltage input terminal VCC, and the inverting input terminal of the first error amplifier OP1 is the first voltage input terminal VCC. The control terminal of the first error amplifier OP1 is the control terminal of the feedback control circuit 100. The first error amplifier OP1 is used to generate a control signal based on the voltage difference between the first reference voltage Vref1 and the first feedback voltage.

[0068] Specifically, the voltage divider network is a series resistor voltage divider network, and the connection node between any two adjacent connected resistors in the series resistor voltage divider network is used to output the first feedback voltage.

[0069] In one embodiment, the series resistor voltage divider network includes a first resistor and a second resistor. Specifically, one end of the first resistor is connected to the voltage output terminal VLDO, and the other end of the first resistor is connected to one end of the second resistor, with the other end of the second resistor grounded. The connection node of the first and second resistors is used to output a first feedback voltage. The inverting input terminal of the first error amplifier OP1 is connected to the reference voltage source that outputs the first reference voltage Vref1, the non-inverting input terminal is connected to the connection node of the first and second resistors, and the control terminal is connected to the control terminal of the power transistor PM1 and the control terminal of the detection transistor PM2.

[0070] In specific control, the first feedback voltage increases with the increase of the target voltage, and the difference between the first reference voltage Vref1 and the first feedback voltage decreases with the increase of the first feedback voltage until the first reference voltage Vref1 and the first feedback voltage are equal. During the process of this difference changing to 0, the first error amplifier OP1 pulls down node A, and the output current on the power transistor PM1 gradually increases. The rate control circuit 200 can slow down the speed at which the first error amplifier OP1 pulls down node A, thereby slowing down the rate of change of the output current on the power transistor PM1, so that the minimum drop point when the input voltage drops during the first drop phase is limited to above the first preset threshold.

[0071] During the pull-down process of node A, the rate of change of the output current on power transistor PM1 can be further slowed down by adjusting the driving capability of the first error amplifier OP1. When the driving capability of the first error amplifier OP1 is strong (the pull-down speed of node A is relatively fast), the rate of change of the output current on power transistor PM1 is large; conversely, when the driving capability of the first error amplifier OP1 is weak (the pull-down speed of node A is relatively slow), the rate of change of the output current on power transistor PM1 is small. Node A can be understood as the node connecting the control terminal of power transistor PM1 and the control terminal of detection transistor PM2.

[0072] In some embodiments, the drive capability of the first error amplifier OP1 can be adjusted to a preset drive capability, such that the lowest point of the input voltage drop caused by the feedback control circuit 100 during the startup phase is greater than a first preset voltage threshold. Specifically, when adjusting the drive capability of the first error amplifier OP1, under the premise of meeting the usage requirements, the drive capability of the first error amplifier OP1 can be adjusted to the preset drive capability by adjusting the size of the output stage transistor in the first error amplifier OP1. The preset drive capability can be determined based on the rate of change of the output current on the power transistor PM1 that needs to be adjusted; that is, the preset drive capability ensures that the lowest point of the input voltage drop during the first drop phase is above the first preset voltage threshold.

[0073] It should be noted that when the rate control circuit 200 can limit the lowest point of the input voltage drop in the first drop stage to above the first preset voltage threshold, the driving capability of the first error amplifier OP1 may not need to be adjusted; or, if the rate control circuit 200 wants to further raise the lowest point of the input voltage drop in the first drop stage after limiting it to the first preset voltage threshold, the driving capability of the first error amplifier OP1 can be further adjusted to the preset driving capability to raise the lowest point of the input voltage drop in the first drop stage.

[0074] In some embodiments, the rate control circuit 200 may include a first capacitor Cgate, one end of which is connected to the control terminal of the feedback control circuit 100, and the other end is grounded; the capacitance value of the first capacitor Cgate represents the rate of change of current when the feedback control circuit 100 controls the output current on the power transistor PM1.

[0075] Specifically, one end of the first capacitor Cgate is connected to the control terminal of the first error amplifier OP1, and the other end of the first capacitor Cgate is grounded. The larger the capacitance value of the first capacitor Cgate, the smaller the rate of change of the output current on the power transistor PM1 controlled by the first error amplifier OP1. Therefore, the rate of change of the output current on the power transistor PM1 can be adjusted by adjusting the capacitance value of the first capacitor Cgate. Those skilled in the art can determine the specific capacitance value of the first capacitor Cgate according to the actual situation, without making too many restrictions here. That is, the specific capacitance value of the first capacitor Cgate can ensure that the lowest point of the input voltage drop during the first stage drop is above the first preset threshold.

[0076] During the startup phase, the first error amplifier OP1 discharges the first capacitor Cgate with a constant current. The formula for calculating the constant current is as follows:

[0077] I = C * (dV / dt);

[0078] I represents a constant current; C represents the capacitance of the first capacitor Cgate; dV / dt represents the rate of voltage change.

[0079] As shown in the above calculation formula, the first capacitor can reduce the rate of voltage change (i.e., reduce the rate of change of the output current on power transistor PM1), thus reducing the pull-down speed at node A. Furthermore, this formula also shows that the larger the capacitance of the first capacitor, the slower the pull-down speed at node A, and the smaller the rate of change of the output current on power transistor PM1.

[0080] In some embodiments, the current limiting circuit 300 may include a sampling resistor and a comparison control circuit 301. One end of the sampling resistor is connected to the second terminal of the detection transistor PM2, and the other end is grounded. The sampling resistor is used to adjust a preset current threshold, and the resistance value of the sampling resistor represents the preset current threshold limiting the power transistor PM1. The connection node between the sampling resistor and the second terminal of the detection transistor PM2 is configured as a feedback terminal for outputting a second feedback voltage. The comparison control circuit 301 includes a first input terminal, a second input terminal, and a control terminal. The first input terminal is used to connect a second reference voltage Vref2. The second input terminal is connected to the feedback terminal for connecting the feedback voltage. The control terminal of the comparison control circuit 301 is connected to the control terminal of the power transistor PM1. The comparison control circuit 301 is used to generate a control signal based on the voltage difference between the second reference voltage Vref2 and the feedback voltage to output to the control terminal of the power transistor PM1. The control signal is used to adjust the current flowing through the power transistor PM1.

[0081] Specifically, the comparator control circuit 301 includes a driver transistor PM3 and a second error amplifier OP2. The first terminal of the driver transistor PM3 is connected to the voltage input terminal VCC, and the second terminal of the driver transistor PM3 is connected to the control terminal of the power transistor PM1. The non-inverting input terminal of the second error amplifier OP2 is used to connect to the second reference voltage Vref2, the inverting input terminal of the second error amplifier OP2 is connected to the feedback terminal, and the control terminal of the second error amplifier OP2 is connected to the control terminal of the driver transistor PM3. The second error amplifier OP2 is used to generate a control signal based on the voltage difference between the second reference voltage Vref2 and the second feedback voltage.

[0082] When the output current causes a drop in the input voltage during the startup phase, the magnitude of the drop can be calculated using the following formula:

[0083] ΔV2=I*Rrounting=k*(Vref2 / R)*Rrounting;

[0084] R=(k*Vref2*Rrounting) / ΔV2;

[0085] Where ∆V2 is the magnitude of the input voltage drop caused by the output current of power transistor PM1; I is the output current of power transistor PM1; and Rrouunting is the trace resistance on the printed circuit board.

[0086] k*Vref2*Rrounting is a known value. Based on the above formula, it can be seen that the drop in input voltage caused by the output current can be adjusted by adjusting the resistance value of the sampling resistor. That is, the minimum drop in input voltage caused by the output current can be increased.

[0087] In practical applications, as the opening of power transistor PM1 gradually increases (i.e., as node A is gradually pulled down), the current on sensing transistor PM2 gradually increases, and the feedback voltage output at the feedback terminal also increases accordingly. When the feedback voltage output at the feedback terminal equals the second reference voltage Vref2, the feedback voltage is clamped to the second reference voltage Vref2. The steady-state output current established on power transistor PM1 can then be calculated and determined using the following formula:

[0088] I = K(Vref² / R);

[0089] Where I is the output current of power transistor PM1; K is the ratio coefficient of the current flowing through power transistor PM1 to the current flowing through detection transistor PM2; R is the resistance value of sampling resistor; and Vref2 is the second reference voltage Vref2.

[0090] Once the steady-state current on power transistor PM1 is established, the output current of power transistor PM1 will flow through parasitic resistors on the printed circuit board (PCB). According to Ohm's law, the voltage across the parasitic resistor will cause the input voltage to drop during the startup phase. The larger the voltage across the parasitic resistor, the more significant the drop. Therefore, the rate at which the input voltage drops during the startup phase caused by the voltage across the parasitic resistor is slowed down by adjusting the resistance value of the sampling resistor, thereby raising the minimum drop point when the input voltage drops during the startup phase caused by the voltage across the parasitic resistor. This minimum drop point is then limited to above a second preset voltage threshold, that is, the minimum drop point of the input voltage caused by the output current of power transistor PM1 during the startup phase is limited to above a second preset voltage threshold.

[0091] In some embodiments, the driving transistor PM3 is a P-MOS, the first terminal of the driving transistor PM3 refers to the source of the P-MOS, the second terminal of the driving transistor PM3 refers to the drain of the P-MOS, and the control terminal of the driving transistor PM3 refers to the gate of the P-MOS.

[0092] In some embodiments, the second reference voltage Vref2 can be provided by a reference voltage source.

[0093] In some embodiments, this application also provides a low-dropout linear regulator circuit applied to a chip. This low-dropout linear regulator circuit includes a voltage input terminal VCC, a voltage output terminal VLDO, a power transistor PM1, a detection transistor PM2, a feedback control circuit 100, and a current limiting and dropout suppression circuit 400. The voltage input terminal VCC is used to connect the input voltage. The voltage output terminal VLDO is used to output the target voltage after adjusting the input voltage. The first terminal of the power transistor PM1 is connected to the voltage input terminal VCC, and the second terminal of the power transistor PM1 is connected to the voltage output terminal VLDO. The first terminal of the detection transistor PM2 is connected to the voltage input terminal VCC, and the control terminal of the detection transistor PM2 is connected to the control terminal of the power transistor PM1. The feedback control circuit 100 includes a first voltage input terminal VCC, a second voltage input terminal VCC, and a control terminal. The first voltage input terminal VCC is used to connect to a first reference voltage Vref1, and the second voltage input terminal VCC is used to connect to a target voltage. The control terminal of the feedback control circuit 100 is connected to the control terminal of the power transistor PM1 and the control terminal of the detection transistor PM2. The feedback control circuit 100 generates corresponding control signals based on the connected first reference voltage Vref1 and target voltage, and outputs them to the control terminals of the power transistor PM1 and the detection transistor PM2, so that a proportional current is generated on the power transistor PM1 and the detection transistor PM2. The current limiting and drop suppression circuit 400 is connected to the control terminal of the power transistor PM1 and the second terminal of the detection transistor PM2. The current limiting and drop suppression circuit 400 limits the output current of the power transistor PM1 from exceeding a preset current threshold and limits any drop point of the input voltage during the startup phase from being above the chip's reset voltage; wherein, when the input voltage is less than or equal to the chip's reset voltage during the startup phase, the chip resets.

[0094] During the startup phase, the low-dropout linear regulator circuit causes the input voltage to drop due to the feedback control circuit 100 and the output current of the power transistor PM1. When the input voltage drops due to the feedback control circuit 100, the lowest point of the drop is related to the rate of change of the output current on the power transistor PM1. If the rate of change is fast, the lowest point of the drop caused by the feedback control circuit 100 is correspondingly low. When the input voltage drops due to the output current of the power transistor PM1, the lowest point of the drop is related to the magnitude of the output current (which is also the charging current of the load capacitor CL). If the output current is large, the lowest point of the drop caused by the output current of the power transistor PM1 is correspondingly low. The input voltage drop during the startup phase of this low-dropout linear regulator circuit includes a first-stage drop and a second-stage drop. The first-stage drop is the input voltage drop caused by the feedback control circuit 100 during the startup phase, and the second-stage drop is the input voltage drop caused by the output current during the startup phase. The time periods of the first-stage drop and the second-stage drop are the total time periods of the input voltage drop during the startup phase. In application, the current limiting and drop suppression circuit 400 can limit any drop point during the input voltage drop during the startup phase to be above the chip's reset voltage, thereby preventing the chip from resetting during the startup phase.

[0095] In some embodiments, the current limiting and dropout suppression circuit includes a rate control circuit 200 and a current limiting circuit 300. The rate control circuit 200 is connected to the control terminal of the feedback control circuit 100. The rate control circuit 200 is used to control the rate of change of the current when the feedback control circuit 100 controls the output current of the power transistor PM1, so that the lowest point of the input voltage drop caused by the feedback control circuit 100 during the startup phase is greater than a first preset voltage threshold, which is greater than the chip's reset voltage. The current limiting circuit 300 is connected to the control terminal of the power transistor PM1 and the second terminal of the detection transistor PM2. The current limiting circuit 300 is used to limit the output current of the power transistor PM1 from exceeding a preset current threshold, and to ensure that the lowest point of the input voltage drop caused by the output current during the startup phase is greater than a second preset voltage threshold, which is greater than the reset voltage. Specific details are as described in the above embodiment of a low-dropout linear regulator circuit, and will not be elaborated further here.

[0096] In some embodiments, this application provides a chip including the low-dropout linear regulator circuit described above. Specifically, as described in the specific embodiment of the low-dropout linear regulator circuit above.

[0097] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A low-dropout linear voltage regulator circuit, characterized in that, The low-dropout linear regulator circuit, applied to chips, includes: Voltage input terminal, used to connect the input voltage; The voltage output terminal is used to output the target voltage after adjusting the input voltage; A power transistor, with its first terminal connected to the voltage input terminal and its second terminal connected to the voltage output terminal; The detection transistor has its first terminal connected to the voltage input terminal and its control terminal connected to the control terminal of the power transistor. A feedback control circuit includes a first voltage input terminal, a second voltage input terminal, and a control terminal. The first voltage input terminal is used to connect to a first reference voltage, and the second voltage input terminal is used to connect to the current target voltage. The control terminal of the feedback control circuit is connected to the control terminal of the power transistor and the control terminal of the detection transistor. The feedback control circuit generates corresponding adjustment signals based on the first reference voltage and the current target voltage, and outputs them to the control terminals of the power transistor and the detection transistor, so that a proportional current is generated on the power transistor and the detection transistor. A rate control circuit is connected to the control terminal of the feedback control circuit. The rate control circuit is used to control the rate of change of current when the feedback control circuit controls the output current of the power transistor, so that the lowest point of the input voltage drop caused by the feedback control circuit during the startup phase is greater than a first preset voltage threshold, and the first preset voltage threshold is greater than the reset voltage of the chip. A current limiting circuit is connected to the control terminal of the power transistor and the second terminal of the detection transistor. The current limiting circuit is used to limit the output current of the power transistor from exceeding a preset current threshold, and to make the lowest point of the input voltage drop caused by the output current during the startup phase greater than a second preset voltage threshold, wherein the second preset voltage threshold is greater than the reset voltage. Specifically, when the input voltage is less than or equal to the chip's reset voltage during the startup phase, the chip is reset.

2. The low-dropout linear voltage regulator circuit as described in claim 1, characterized in that, The input voltage drop during the startup phase includes a first-stage drop and a second-stage drop. The first-stage drop is the input voltage drop caused by the feedback control circuit during the startup phase, and the second-stage drop is the input voltage drop caused by the output current during the startup phase. The time period during which the input voltage drops in the first stage and the time period during which the input voltage drops in the second stage constitute the total time period during which the input voltage drops in the startup phase.

3. The low-dropout linear voltage regulator circuit as described in claim 1, characterized in that, The feedback control unit includes: A voltage divider network is connected between the voltage output terminal and ground. The voltage divider network is used to output a first feedback voltage that is proportional to the current target voltage based on the adjusted voltage. A first error amplifier, wherein the non-inverting input terminal of the first error amplifier is the second voltage input terminal, the inverting input terminal of the first error amplifier is the first voltage input terminal, and the control terminal of the first error amplifier is the control terminal of the feedback control circuit, wherein the first error amplifier is used to generate the control signal based on the voltage difference between the first reference voltage and the first feedback voltage.

4. The low-dropout linear voltage regulator circuit as described in claim 3, characterized in that, The driving capability of the first error amplifier is adjusted to a preset driving capability, such that the lowest point of the input voltage drop caused by the feedback control circuit during the startup phase is greater than a first preset voltage threshold.

5. The low-dropout linear regulator circuit as described in any one of claims 1-4, characterized in that, The rate control circuit includes: a first capacitor, one end of which is connected to the control terminal of the feedback control unit, and the other end is grounded; the capacitance value of the first capacitor represents the rate of change of current when the feedback control circuit controls the output current of the power transistor.

6. The low-dropout linear regulator circuit as described in any one of claims 1-4, characterized in that, The current limiting circuit includes: A sampling resistor, one end of which is connected to the second terminal of the detection transistor and the other end is grounded. The sampling resistor is used to adjust the preset current threshold. The resistance value of the sampling resistor represents the preset current threshold that limits the power transistor. The connection node between the sampling resistor and the second terminal of the detection transistor is configured as a feedback terminal for outputting a second feedback voltage. The comparator control circuit includes a first input terminal, a second input terminal, and a control terminal; the first input terminal is used to connect to a second reference voltage; the second input terminal is connected to the feedback terminal and is used to connect to the feedback voltage; the control terminal of the comparator control circuit is connected to the control terminal of the power transistor, and the comparator control circuit is used to generate a control signal based on the voltage difference between the second reference voltage and the feedback voltage to output to the control terminal of the power transistor, and the control signal is used to adjust the current flowing through the power transistor.

7. The low-dropout linear voltage regulator circuit as described in claim 6, characterized in that, The comparison control circuit includes: A driving transistor, the first terminal of which is connected to the voltage input terminal, and the second terminal of which is connected to the control terminal of the power transistor; The second error amplifier has a non-inverting input terminal connected to a second reference voltage, an inverting input terminal connected to the feedback terminal, and a control terminal connected to the control terminal of the driving transistor; the second error amplifier is used to generate the control signal based on the voltage difference between the second reference voltage and the second feedback voltage.

8. A low-dropout linear voltage regulator circuit, characterized in that, The low-dropout linear regulator circuit, applied to chips, includes: Voltage input terminal, used to connect the input voltage; The voltage output terminal is used to output the target voltage after adjusting the input voltage; A power transistor, with its first terminal connected to the voltage input terminal and its second terminal connected to the voltage output terminal; The detection transistor has its first terminal connected to the voltage input terminal and its control terminal connected to the control terminal of the power transistor. A feedback control circuit includes a first voltage input terminal, a second voltage input terminal, and a control terminal. The first voltage input terminal is used to connect to a first reference voltage, and the second voltage input terminal is used to connect to the target voltage. The control terminal of the feedback control circuit is connected to the control terminal of the power transistor and the control terminal of the detection transistor. The feedback control circuit generates corresponding adjustment signals based on the connected first reference voltage and the target voltage, and outputs them to the control terminals of the power transistor and the detection transistor, so that a proportional current is generated on the power transistor and the detection transistor. A current limiting and sag suppression circuit is connected to the control terminal of the power transistor. The current limiting and sag suppression circuit is used to limit the output current of the power transistor from exceeding a preset current threshold and to limit any drop point of the input voltage during the startup phase above the reset voltage of the chip. Specifically, when the input voltage is less than or equal to the chip's reset voltage during the startup phase, the chip is reset.

9. The low-dropout linear voltage regulator circuit as described in claim 8, characterized in that, The current limiting and dropout suppression circuit includes: A rate control circuit is connected to the control terminal of the feedback control circuit. The rate control circuit is used to control the rate of change of current when the feedback control circuit controls the output current of the power transistor, so that the lowest point of the input voltage drop caused by the feedback control circuit during the startup phase is greater than a first preset voltage threshold, and the first preset voltage threshold is greater than the reset voltage of the chip. A current limiting circuit is connected to the control terminal of the power transistor and the second terminal of the detection transistor. The current limiting circuit is used to limit the output current of the power transistor from exceeding a preset current threshold, and to make the lowest point of the input voltage drop caused by the output current during the startup phase greater than a second preset voltage threshold, wherein the second preset voltage threshold is greater than the reset voltage. The input voltage drop during the startup phase includes a first-stage drop and a second-stage drop. The first-stage drop is the input voltage drop caused by the feedback control circuit during the startup phase, and the second-stage drop is the input voltage drop caused by the output current during the startup phase. The time period during which the input voltage drops in the first stage and the time period during which the input voltage drops in the second stage constitute the total time period during which the input voltage drops in the startup phase.

10. A chip, characterized in that, include: The low dropout linear regulator circuit as described in any one of claims 1-7 or the low dropout linear regulator circuit as described in any one of claims 8-9.

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