Storage management method and device, electronic equipment and chip

Abstract

The invention provides a storage management method and device, electronic equipment and a chip, and relates to the technical field of chips, the method comprises the following steps: in response to a storage resource request of a first hardware accelerator, allocating a target virtual address corresponding to the storage resource request in a virtual storage list, the virtual storage list is obtained by uniformly addressing a storage resource pool, the storage resource pool comprises special storage resources of a plurality of hardware accelerators in the chip, and the plurality of hardware accelerators comprise a first hardware accelerator; obtaining a storage resource physical address corresponding to the target virtual address; and opening the access authority of the target storage resource in the storage resource pool to the first hardware accelerator according to the storage resource physical address. By applying the technical scheme of the invention, the method can achieve the unified pooling management, enables the idle special storage resources of the hardware accelerator to be fully utilized, avoids the waste of the storage resources, can achieve the flexible and effective management of the storage resources, and can improve the utilization rate of the storage resources.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a storage management method, apparatus, electronic device and chip. Background Technology

[0002] With the development of technologies such as ultra-high spectral efficiency coding and carrier aggregation, the amount of data processed by baseband and the demand for real-time computing are increasing. In order to achieve a balance between performance and power consumption, baseband chips (SoCs) can adopt a heterogeneous architecture consisting of a processor and multiple dedicated hardware accelerators, with the processor responsible for control flow and the hardware accelerators responsible for data flow.

[0003] In related technologies, the chip includes dedicated storage resources configured for multiple hardware accelerators. These dedicated storage resources are not effectively managed, and each hardware accelerator can only use its own dedicated storage resources, resulting in low utilization of storage resources. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides a storage management method, apparatus, electronic device, and chip.

[0005] According to a first aspect of the present disclosure, a storage management method is provided, comprising: In response to a storage resource request from a first hardware accelerator, a target virtual address corresponding to the storage resource request is allocated in a virtual storage list. The virtual storage list is obtained by uniformly addressing a storage resource pool, which includes dedicated storage resources for multiple hardware accelerators in the chip, including the first hardware accelerator. Obtain the physical address of the storage resource corresponding to the target virtual address; Based on the physical address of the storage resource, grant access permissions to the target storage resource in the storage resource pool to the first hardware accelerator.

[0006] In some possible implementations, the storage resource pool may also include shared storage resources within the chip and external storage resources of the chip; The step of allocating the target virtual address corresponding to the storage resource request in the virtual storage list includes: Determine resource requirement information based on the storage resource request; Based on the resource requirement information and in combination with the access performance priorities corresponding to the dedicated storage resources, the shared storage resources, and the external storage resources, the target virtual address is allocated in the virtual storage list.

[0007] In some possible implementations, the step of allocating the target virtual address in the virtual storage list based on the resource requirement information and in combination with the access performance priorities corresponding to the dedicated storage resource, the shared storage resource, and the external storage resource, includes: According to the access performance priority from high to low, the idle storage resources in the storage resource pool that meet the resource requirement information are matched sequentially. The access performance priority of the dedicated storage resources of the first hardware accelerator is higher than that of the dedicated storage resources of other hardware accelerators. The access performance priority of the dedicated storage resources of other hardware accelerators is higher than that of the shared storage resources. The access performance priority of the shared storage resources is higher than that of the external storage resources. Based on the matched free storage resources, the corresponding virtual address is determined from the virtual storage list as the target virtual address.

[0008] In some possible implementations, before allocating the target virtual address in the virtual storage list based on the resource requirement information and in combination with the access performance priorities corresponding to the dedicated storage resource, the shared storage resource, and the external storage resource, the method further includes: Detect whether there are storage resources pre-allocated for the first hardware accelerator in the storage resource pool; If the pre-allocated storage resource exists in the storage resource pool and the pre-allocated storage resource meets the resource requirement information, then the target virtual address is determined according to the virtual address of the pre-allocated storage resource in the virtual storage list.

[0009] In some possible implementations, the step of allocating the target virtual address in the virtual storage list based on the resource requirement information and in combination with the access performance priorities corresponding to the dedicated storage resources, the shared storage resources, and the external storage resources includes: If the pre-allocated storage resource is not available in the storage resource pool, or if the pre-allocated storage resource does not meet the resource requirement information, then the target virtual address is allocated in the virtual storage list based on the resource requirement information and the access performance priorities corresponding to the dedicated storage resource, the shared storage resource, and the external storage resource, respectively.

[0010] In some possible implementations, the method further includes: The physical address of the storage resource corresponding to the target virtual address is obtained through the hardware accelerator page table, which includes the mapping relationship between the target virtual address and the physical address of the target storage resource.

[0011] In some possible implementations, the hardware accelerator page table also includes at least one of the following attribute bits: The location bit is used to indicate the storage level where the target storage resource is located. The storage level is any one of the storage level of the dedicated storage resources of the hardware accelerator, the storage level of the shared storage resources within the chip, and the storage level of the external storage resources of the chip. A migration bit, which indicates whether migration of the target storage resource between different storage tiers is permitted; An accelerator bit, which indicates a target hardware accelerator that allows the target storage resource to be preferentially accessed.

[0012] In some possible implementations, the method further includes: If migration is allowed based on the migration bit, and the storage tier where the target storage resource is located is not the storage tier corresponding to the highest access performance priority based on the location bit, then the storage tier where the target storage resource is located will be migrated to the storage tier corresponding to the higher access performance priority. After the migration is complete, update the physical address mapping relationship and position bits corresponding to the target virtual address in the hardware accelerator page table.

[0013] In some possible implementations, the method further includes: Send the physical address descriptor of the target storage resource to the second hardware accelerator among the plurality of hardware accelerators; In response to the second hardware accelerator's access request to the target storage resource, access permissions to the target storage resource are granted to the second hardware accelerator based on the physical address descriptor in the access request.

[0014] According to a second aspect of the present disclosure, a storage management apparatus is provided, comprising: an allocation module, configured to allocate a target virtual address corresponding to the storage resource request in a virtual storage list in response to a storage resource request from a first hardware accelerator, wherein the virtual storage list is obtained by uniformly addressing a storage resource pool, the storage resource pool including dedicated storage resources of a plurality of hardware accelerators in a chip, and the plurality of hardware accelerators including the first hardware accelerator; The acquisition module is used to acquire the physical address of the storage resource corresponding to the target virtual address; An open module is used to grant the first hardware accelerator access permissions to the target storage resource in the storage resource pool based on the physical address of the storage resource.

[0015] In some possible implementations, the storage resource pool may also include shared storage resources within the chip and external storage resources of the chip; The allocation module is specifically used to determine resource requirement information based on the storage resource request; and based on the resource requirement information, and in combination with the access performance priorities corresponding to the dedicated storage resource, the shared storage resource and the external storage resource, allocate the target virtual address in the virtual storage list.

[0016] In some possible implementations, the allocation module is specifically used to sequentially match idle storage resources in the storage resource pool that meet the resource requirement information according to the access performance priority from high to low, wherein the access performance priority of the dedicated storage resources of the first hardware accelerator is higher than that of the dedicated storage resources of other hardware accelerators, the access performance priority of the dedicated storage resources of other hardware accelerators is higher than that of the shared storage resources, and the access performance priority of the shared storage resources is higher than that of the external storage resources; based on the matched idle storage resources, the corresponding virtual address is determined as the target virtual address in the virtual storage list.

[0017] In some possible implementations, the opening module is further configured to send the physical address descriptor of the target storage resource to a second hardware accelerator among the plurality of hardware accelerators; and in response to the second hardware accelerator's access request for the target storage resource, grant the second hardware accelerator access rights to the target storage resource according to the physical address descriptor in the access request.

[0018] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; a memory connected to the processor, the memory storing a computer program, the computer program being executed by the processor to implement the storage management method of the first aspect and any possible implementation thereof.

[0019] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the storage management method of the first aspect and any possible implementation.

[0020] According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the storage management method of the first aspect and any possible implementation.

[0021] According to a sixth aspect of the present disclosure, a chip is provided, including one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of an electronic device and send signals to the processors, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, it causes the electronic device to perform the memory management method of the first aspect and any possible implementation.

[0022] By employing the above technical solutions, this disclosure provides a storage management method, apparatus, electronic device, and chip. Compared with related technologies, it can uniformly manage the dedicated storage resources allocated to multiple hardware accelerators within a chip. Specifically, in response to a storage resource request from a first hardware accelerator, a target virtual address corresponding to the storage resource request is allocated in a virtual storage list. This virtual storage list is obtained by uniformly addressing a storage resource pool, which includes dedicated storage resources from multiple hardware accelerators within the chip, including the first hardware accelerator. Then, the physical address of the storage resource corresponding to the target virtual address is obtained. Finally, based on the physical address of the storage resource, access permissions for the target storage resource in the storage resource pool are granted to the first hardware accelerator. By applying the technical solution of this disclosure, the problem of storage resource silos can be solved. Unified pooled management allows for the full utilization of idle dedicated storage resources of hardware accelerators, avoiding waste of storage resources, enabling flexible and effective management of storage resources, and improving the utilization rate of storage resources.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0025] Figure 1 A flowchart illustrating a storage management method provided in an embodiment of this disclosure; Figure 2 A flowchart illustrating another storage management method provided in this disclosure embodiment; Figure 3 A block diagram of a storage management device provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0026] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0027] Numerous specific details are set forth in the following description to provide a full understanding of this disclosure. However, this disclosure can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this disclosure. Therefore, this disclosure is not limited to the specific implementations disclosed below.

[0028] The terminology used in one or more embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this disclosure. The singular forms “a,” “the,” and “the” as used in one or more embodiments of this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this disclosure refers to and includes any or all possible combinations of one or more associated listed items.

[0029] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this disclosure, and similarly, second may also be referred to as first. Depending on the context, the word “if” as used herein may be interpreted as “when”, “in response to a determination”, or “when…”.

[0030] In 5G or 6G wireless communications, to meet the stringent requirements of high throughput and low latency, baseband chips can adopt a heterogeneous architecture consisting of a processor and multiple dedicated hardware accelerators. The processor is responsible for control flow, while the hardware accelerators are responsible for data flow. These heterogeneous hardware accelerators can include: Low-Density Parity-Check (LDPC) accelerators, Fast Fourier Transform (FFT) / Inverse Fast Fourier Transform (IFFT) accelerators, equalizer accelerators, and channel estimation accelerators. Among these, the LDPC accelerator is responsible for LDPC code encoding and decoding operations and is a key module for ensuring signal reliability in communication data transmission; the FFT / IFFT accelerator is a Fast Fourier Transform / Inverse Fast Fourier Transform accelerator used for time-domain to frequency-domain conversion of communication signals; the equalizer accelerator can be used to solve channel distortion problems in communication signal transmission, achieving signal compensation through hardware acceleration and improving the signal quality at the receiving end; the channel estimation accelerator can be used to estimate the transmission characteristics of the wireless channel in real time, providing parameter support for subsequent signal demodulation and equalization, ensuring communication stability in high-speed mobile scenarios.

[0031] These hardware accelerators are typically equipped with proprietary tightly coupled memory (TCM) for optimal energy efficiency. This TCM is dedicated storage resources configured for each hardware accelerator. However, in related technologies, these dedicated storage resources are not effectively managed; each hardware accelerator can only use its own dedicated storage resources, resulting in low utilization. For example, each hardware accelerator may be configured with a fixed size of dedicated storage resources (TCM). When tasks are idle, its dedicated storage resources are wasted; when tasks are overloaded, its dedicated storage resources are insufficient, overflowing to slower external on-chip storage resources, causing a sharp drop in performance.

[0032] To address the aforementioned technical problems, this disclosure provides a storage management method applicable to chip systems in devices such as smart terminals and mobile devices. Compared to related technologies, this method allows for unified management of dedicated storage resources allocated to multiple hardware accelerators within a chip. Figure 1 As shown, the storage management method includes the following steps S101-S103: Step S101: In response to the storage resource request from the first hardware accelerator, allocate the target virtual address corresponding to the storage resource request in the virtual storage list.

[0033] The virtual storage list is obtained by uniformly addressing a storage resource pool, which includes dedicated storage resources for multiple hardware accelerators within the chip. The first hardware accelerator can be one of multiple hardware accelerators within the chip; that is, the first hardware accelerator is included among these multiple hardware accelerators. For example, if the chip is a baseband chip, these hardware accelerators could be LDPC accelerators, FFT / IFFT accelerators, equalizer accelerators, channel estimation accelerators, etc., and the first hardware accelerator can be one of these hardware accelerators.

[0034] Before executing step S101, the construction and unified addressing of the storage resource pool can be completed in advance in this embodiment. For example, the dedicated storage resources of multiple heterogeneous hardware accelerators within the chip can be integrated, namely the private tightly coupled memory (TCM) of each hardware accelerator, which is essentially the static random access memory (SRAM) within the chip. These dedicated storage resources were originally exclusively used by each accelerator, but after integration, they become part of a globally schedulable shared resource pool, and the dedicated storage resources of the first hardware accelerator are also included in this storage resource pool. This embodiment can allocate a continuous virtual address space to the entire storage resource pool through hardware-level address planning, forming a virtual storage list. This virtual storage list makes all storage resources appear as a whole at the virtual address level.

[0035] In some embodiments, the storage resource pool may include not only dedicated storage resources for multiple hardware accelerators within the chip, but also shared storage resources within the chip and external storage resources. The shared storage resources may be publicly available to multiple hardware accelerators within the chip, such as on-chip shared SRAM, while the external storage resources may be external DRAM, used to meet high-capacity storage requirements. This disclosure embodiment can allocate a contiguous virtual address space to the entire storage resource pool composed of these three types of storage resources through hardware-level address planning, forming a virtual storage list. This list masks the differences in physical location, media, and speed among different types of storage resources, making all storage resources appear as a whole at the virtual address level. This solves the problem of siloed traditional dedicated storage and provides a diversified resource selection basis for subsequent on-demand allocation.

[0036] In this embodiment, when the first hardware accelerator needs storage resources to perform a task, it can initiate a corresponding storage resource request. Upon receiving the storage resource request, it can query the global storage resource directory, such as the built-in hardware resource directory table, to track the current status of all storage resources in the storage resource pool in real time (including idle / occupied status, power status, access latency, etc.). The directory table is then used to quickly filter out currently idle storage resources. Next, suitable idle storage resources are matched. For example, based on the task information of the first hardware accelerator, resources suitable for the task are matched from the filtered idle storage resources, such as those meeting the storage access speed and stability requirements of the task. Then, a corresponding virtual address is allocated in the virtual storage list based on the successfully matched idle storage resource. This virtual address is the target virtual address corresponding to the storage resource request of the first hardware accelerator.

[0037] Step S102: Obtain the physical address of the storage resource corresponding to the target virtual address.

[0038] To determine the allocated target storage resource, a physical address translation of the virtual address is required. The first hardware accelerator does not need to participate in the address translation process and can subsequently initiate access requests using the allocated target virtual address.

[0039] In some embodiments, the physical address of the storage resource corresponding to the target virtual address can be obtained through a hardware accelerator page table. The hardware accelerator page table may include a mapping relationship between the target virtual address and the physical address of the target storage resource. For example, through this mapping relationship, the target virtual address can be accurately converted into the corresponding physical address of the storage resource.

[0040] This embodiment of the disclosure can pre-build the hardware accelerator page table, which pre-stores the mapping relationship between each virtual address in the virtual memory list and the physical storage resources in the storage resource pool. The physical storage resources include dedicated storage resources (TCM), shared storage resources (on-chip shared SRAM), and external storage resources (external DRAM) for each hardware accelerator, covering all storage types in the storage resource pool. The page table size can be flexibly divided according to the address characteristics and actual storage structure of the hardware accelerator, such as 4K, 2K, or 1K, to better adapt to the data flow patterns of 5G and 6G signal processing, reducing the number of page table lookups and latency.

[0041] Step S103: Based on the physical address of the storage resource, grant access permissions to the target storage resource in the storage resource pool to the first hardware accelerator.

[0042] The target storage resource can be the dedicated TCM of the first hardware accelerator itself, the dedicated TCM of other idle accelerators, the on-chip shared SRAM, or the external DRAM of the chip.

[0043] As an alternative, verification can be performed before granting access permissions to the target storage resource to the first hardware accelerator. For example, the current status of the target storage resource can be verified through the built-in global storage resource directory to confirm that it is still in an idle state and has not been preempted by other tasks, thereby ensuring that the permissions are granted accurately and avoiding misauthorization.

[0044] For example, the identification information of the first hardware accelerator (such as the hardware accelerator ID) is bound to the physical address of the target storage resource. This association is recorded at the hardware level, clearly indicating that the storage resource corresponding to this physical address is only accessible to the first hardware accelerator, and other accelerators or modules cannot access it temporarily, ensuring resource exclusivity. Access rules are then configured for the physical address of the target storage resource, including allowed access operation types (such as read operations and write operations), access bandwidth limits, etc., to adapt to the task requirements of the first hardware accelerator. For example, signal processing tasks require high-frequency read and write operations, so only read and write permissions are allowed; data caching tasks only require read permissions. After the access association is established and the rules are configured, the permissions are automatically activated, giving the first hardware accelerator the legal right to access the target storage resource through the virtual address. Simultaneously, a hardware signal indicating that permission activation is complete is sent to the first hardware accelerator. Upon receiving the signal, the first hardware accelerator can initiate direct access to the target storage resource through the target virtual address allocated in step S101, without needing to go through an additional permission verification process.

[0045] By applying the technical solutions of the embodiments of this disclosure, storage resources can be managed in a unified manner, which can solve the problem of storage resource silos. Unified pooling management allows the idle dedicated storage resources of hardware accelerators to be fully utilized, avoids the waste of storage resources, enables flexible and effective management of storage resources, and improves the utilization rate of storage resources.

[0046] Furthermore, as Figure 1 An alternative approach to the method shown is provided in this disclosure embodiment as follows: Figure 2 The specific methods shown are as follows: Figure 2 As shown, the method may specifically include the following steps S201-S206: Step S201: In response to the storage resource request of the first hardware accelerator, determine the resource requirement information based on the storage resource request.

[0047] In some examples, resource requirement information can be obtained by parsing the storage resource request. This resource requirement information may include storage capacity requirements, access performance requirements, access type requirements, etc.

[0048] To address storage capacity requirements, the minimum required storage capacity can be determined based on the data block size and the amount of intermediate results cached for task computation, ensuring that the task data can be fully supported.

[0049] To address access performance requirements, access latency thresholds and bandwidth requirements can be derived based on task type. For example, signal processing tasks with high real-time requirements, such as LDPC encoding / decoding and FFT, require low-latency, high-bandwidth storage resources; while large-capacity data caching tasks have relatively relaxed latency requirements but must meet continuous access bandwidth requirements.

[0050] Based on the access type requirements, the type of access operation that a task performs on storage resources can be determined. For example, signal processing tasks require frequent read and write operations (for updating intermediate results and outputting data), while data caching tasks may only require read operations, providing a reference for subsequent permission configuration.

[0051] Step S202: Based on the resource requirement information and combined with the access performance priorities corresponding to the dedicated storage resources of the hardware accelerator, the shared storage resources within the chip, and the external storage resources of the chip, the target virtual address is allocated in the virtual storage list.

[0052] Regarding the access to storage resources by the first hardware accelerator, the access performance priority of the dedicated storage resources (TCM) of the first hardware accelerator is higher than that of the dedicated storage resources (TCM) of other hardware accelerators; the access performance priority of the dedicated storage resources (TCM) of other hardware accelerators is higher than that of the shared storage resources (on-chip shared SRAM) within the chip; and the access performance priority of the shared storage resources (on-chip shared SRAM) is higher than that of the external storage resources (external DRAM) of the chip.

[0053] For example, regarding the access to storage resources by the first hardware accelerator, its own dedicated storage resources (TCM) have the lowest access latency, the highest bandwidth, and require no cross-accelerator scheduling, resulting in the best energy efficiency. Therefore, it can be designated as the first priority, i.e., the highest priority. The idle dedicated storage resources (TCM) of other hardware accelerators have lower performance than the first priority, require virtual address to physical address mapping, and have lower scheduling overhead, making them the second priority. Shared storage resources within the chip (on-chip shared SRAM) are available to all accelerators, have better performance than external storage, and can meet medium real-time requirements, making them the third priority. External storage resources of the chip (such as external DRAM) have the largest capacity but the highest access latency and relatively low bandwidth, making them suitable for large-capacity, low-real-time storage needs, and thus the fourth priority, i.e., the lowest priority.

[0054] In some embodiments, step S202 may specifically include: sequentially matching idle storage resources in the storage resource pool that meet the resource requirement information in descending order of access performance priority, and determining the corresponding virtual address as the target virtual address in the virtual storage list based on the matched idle storage resources.

[0055] For example, first query the global storage resource directory, which tracks the status of all storage resources (including dedicated TCM, on-chip shared SRAM, and external DRAM) in the storage resource pool in real time, and quickly filter out all storage resources that are in an idle state. Next, resources are matched sequentially according to priority. Starting from the first priority, each idle storage resource is checked for compatibility to determine if it meets the resource requirements determined in step S201. For example, when checking a first-priority resource, it is determined whether the dedicated TCM of the first hardware accelerator has free space, and whether the capacity and access performance (latency, bandwidth) of the free portion meet the requirements. If it does, the storage resource is directly selected as the target storage resource. If it does not meet the requirements (e.g., its own TCM is occupied or its capacity is insufficient), the process moves to the next priority, i.e., checking the second-priority resource. This involves traversing the idle dedicated TCMs of other hardware accelerators, filtering out storage resources with the required capacity and performance, and selecting the compatible resource as the target storage resource. If no compatible resource is found, the process moves to the next priority, i.e., checking the third-priority resource. This involves checking whether the free portion of the on-chip shared SRAM meets the requirements. If it does, it is selected as the target storage resource. If it does not meet the requirements, the process continues to the fourth priority, filtering out the free area in the external DRAM that meets the capacity and bandwidth requirements, and selecting it as the target storage resource. After selecting the target storage resource, a corresponding virtual address can be allocated in the virtual storage list. This virtual address is the target virtual address.

[0056] For example, a unified virtual memory list can be created to uniformly address and manage the private SRAM (TCM) scattered within each accelerator and the on-chip shared SRAM / DRAM. This allows for on-demand allocation; the hardware accelerator no longer exclusively occupies a fixed amount of physical SRAM. Virtual memory segments can be dynamically allocated to the hardware accelerator from the virtual memory list based on task requirements. These virtual memory segments can be mapped to: their own physical TCM, the physical TCM of another idle accelerator, the on-chip shared SRAM, or external DRAM. Furthermore, embodiments of this disclosure introduce Hybrid Virtual Address (HVA), which can allocate a dedicated virtual address space to the hardware accelerator. Examples of the format are shown in Table 1 below. Table 1

[0057] As an optional approach, before step S202, it can be detected whether there are pre-allocated storage resources in the storage resource pool for the first hardware accelerator. If there are pre-allocated storage resources in the storage resource pool, and the pre-allocated storage resources meet the resource requirement information, then the target virtual address is determined based on the virtual address of the pre-allocated storage resources in the virtual storage list. Conversely, if there are no pre-allocated storage resources in the storage resource pool, or the pre-allocated storage resources do not meet the resource requirement information, then the process shown in step S202 is executed.

[0058] The pre-allocated storage resources can be storage resources pre-allocated to the first hardware accelerator after the device is powered on, the chip is initialized, or the first hardware accelerator is started. For example, dedicated storage resources for the first hardware accelerator can be allocated first. These resources can be marked accordingly in the global storage resource directory. The hardware accelerator page table containing the mapping relationship between the virtual address and the physical address corresponding to the pre-allocated storage resources can be pre-loaded.

[0059] For example, upon receiving a storage resource request from the first hardware accelerator, the system first searches the global storage resource directory for pre-allocated storage resources bound to the first hardware accelerator's identifier (e.g., accelerator ID). If a pre-allocated resource is detected, a compatibility check is performed using the resource requirement information from step S201. If the pre-allocated resource exists and matches the resource requirement information, the corresponding page table entry for the pre-allocated resource is read from the pre-loaded hardware accelerator page table, the virtual address is converted to a physical address, and access to the corresponding resource is granted to the first hardware accelerator. This method effectively improves storage resource allocation efficiency, reduces storage allocation latency, enables rapid task response from the hardware accelerator, and thus quickly provides the corresponding services. If the pre-allocated resource does not exist, or the pre-allocated resource does not match the resource requirement, or the corresponding entry is not found in the hardware accelerator page table, the process shown in step S202 is executed.

[0060] Step S203: Obtain the physical address of the storage resource corresponding to the target virtual address through the hardware accelerator page table.

[0061] The hardware accelerator page table includes a mapping relationship between the target virtual address and the physical address of the target storage resource. This mapping relationship allows the target virtual address to be converted into the corresponding physical address of the storage resource. This embodiment of the disclosure provides a unified address translation service for all main control units (CPU cores and all heterogeneous accelerators). All units initiate access using a unified virtual address, and the hardware accelerator page table directs them to the fastest and most suitable physical storage location.

[0062] In some embodiments, different page tables can be configured for different accelerators or network slices. For example, even if hardware accelerator a physically shares the same TCM, it cannot access the address space allocated to accelerator b, fundamentally ensuring data security and task isolation. An independent storage domain is created for each accelerator or task, ensuring security in a pooled environment. Access permissions are verified during address translation to prevent malicious or incorrect configurations from causing one accelerator to tamper with the critical data of another.

[0063] In some embodiments, the hardware accelerator page table may contain not only a virtual address to physical address mapping, but also at least one of the following key attribute bits (for memory management): A. Location bit (LOC): This location bit is used to indicate the storage level where the target storage resource is located. The storage level can be any one of the following: the storage level of the dedicated storage resource of the hardware accelerator, the storage level of the shared storage resource within the chip, or the storage level of the external storage resource of the chip.

[0064] For example, the location bit is an identifier bit in the page table of a hardware accelerator used to accurately mark the physical location level of the target storage resource. This location bit can be used to quickly identify the storage medium where the data is located, avoiding the additional latency of querying the resource directory after address translation, and meeting the low latency requirements of baseband processing, as shown in Table 2 below: Table 2

[0065] B. Migration bit (MIG): This migration bit is used to indicate whether migration of the target storage resource between different storage tiers is allowed.

[0066] For example, the migration bit is a control bit in the hardware accelerator page table used to mark whether the target storage resource is allowed to be dynamically migrated between different storage tiers. If the migration bit is a 1-bit binary bit, setting it to 1 (allow migration) means that the data block can be migrated between different tiers according to system policies (such as business type, storage load, temperature); setting it to 0 (disallow migration) means that the data block is fixed in the current storage tier and cannot be moved.

[0067] In some examples, the MIG bit in the page table can be dynamically adjusted based on the service type and system status (power consumption, temperature) to globally control the data migration strategy.

[0068] C. Accelerator bit (ACC_ID): This accelerator bit is used to indicate the target hardware accelerator that allows the target storage resource to be preferentially accessed.

[0069] For example, the accelerator bit is an identifier in the hardware accelerator page table used to mark which hardware accelerator is given priority to access the target storage resource. When multiple accelerators request access to the same shared storage resource at the same time, the request of the hardware accelerator marked by the accelerator bit will be responded to first, so as to avoid the core business having its bandwidth occupied by other businesses.

[0070] Furthermore, if migration is allowed based on the migration bit and the storage tier where the target storage resource is located is not the storage tier corresponding to the highest access performance priority based on the location bit, then the storage tier where the target storage resource is located will be migrated to the storage tier corresponding to the higher access performance priority; after the migration is completed, the physical address mapping relationship and location bit corresponding to the target virtual address in the hardware accelerator page table will be updated.

[0071] For example, when the target storage resource is detected to meet the condition that the migration bit is 1 and the current storage level is not optimal, the migration process is immediately initiated. For instance, if the frequency of an FFT accelerator accessing a data block increases from 10 times per second to 100 times per second, and the migration bit indicates that the data is currently in DRAM (LOC=10), with the optimal level being TCM (LOC=00), the migration conditions are met. If the current level is DRAM (LOC=10), the target level preferentially selects an idle L1 TCM (such as the FFT accelerator's own idle TCM or an idle TCM of another accelerator). If there are no idle resources in the L1 TCM, then L2 shared SRAM (LOC=01) is selected, ensuring that the performance after migration is still better than the original level. The idle status of the target storage level can be queried through the global storage resource directory. In this way, data transfer can be completed at the hardware level. During DMA data transfer, if the hardware accelerator needs to access the data block, the access request will be automatically redirected to the migrated buffer, ensuring that the accelerator is unaware of the migration. Furthermore, data that may be accessed frequently in the future is migrated from DRAM to TCM in advance, further reducing access latency. After the migration is complete, the key information in the page table is updated synchronously, including the mapping relationship and position bits of the virtual address to the physical address, to ensure accurate subsequent address translation.

[0072] Step S204: Based on the physical address of the storage resource, grant access permissions to the target storage resource in the storage resource pool to the first hardware accelerator.

[0073] For example, the identifier of the first hardware accelerator is bound to the physical address of the target storage resource, and it is determined that this physical address is only open to the accelerator. The first hardware accelerator can directly access the storage resource corresponding to the physical address through the target virtual address allocated in step S201.

[0074] Step S205: Send the physical address descriptor of the target storage resource to the second hardware accelerator among multiple hardware accelerators.

[0075] The physical address descriptor can be determined based on the physical starting address of the target storage resource, the length of the storage resource, the sharing permission identifier, etc.

[0076] Step S206: In response to the second hardware accelerator's access request to the target storage resource, grant the second hardware accelerator access rights to the target storage resource according to the physical address descriptor in the access request.

[0077] For example, after hardware accelerator Acc1 completes its computation using the allocated storage resources, it submits the physical address of the SRAM (Structured RAM) to the memory manager as a descriptor. The memory manager then maps this address to hardware accelerator Acc2 via the hardware accelerator's page table address. Subsequently, hardware accelerator Acc2 can directly read the shared SRAM with hardware accelerator Acc1. Alternatively, hardware accelerator Acc2 submits the physical address of its allocated SRAM to the memory manager as a descriptor. The memory manager maps this address to hardware accelerator Acc1 via the hardware accelerator's page table address. After hardware accelerator Acc1 completes its computation, it writes the data directly into the SRAM of hardware accelerator Acc2 and then notifies hardware accelerator Acc2, allowing hardware accelerator Acc2 to directly read its own SRAM.

[0078] The application scenarios of this disclosure cover all mobile terminals and IoT devices that require high-performance, low-power processing of 5G / 6G wireless signals. The baseband chips of high-end 5G / 6G user terminals (UEs) need to process high-speed data and are extremely sensitive to power consumption. For example, during high-speed downloads, the baseband chip operates continuously at high speeds; traditional DMA transfer and multiple data copies consume significant power. However, the solution in this embodiment can achieve zero-copy data, thus significantly reducing power consumption. During high-speed downloads, intelligent data layout stores frequently accessed data blocks in the nearest and fastest TCM, and storage pooling dynamically allocates resources to ensure continuous peak rates. In addition, this solution can also be applied to extended reality chips (AR / VR), industrial IoT chips, and intelligent connected car chips.

[0079] The technical solution provided by this disclosure maximizes storage utilization, transforming fixed allocation into dynamic pooling, fully utilizing previously idle private SRAM resources, and reducing chip costs. Intelligent data layout and zero-copy sharing ensure data is always in the optimal storage medium, significantly reducing inter-accelerator collaboration latency. Furthermore, it is almost transparent to the software and accelerator logic itself; all scheduling and management are handled by hardware, eliminating software overhead and meeting real-time requirements. In addition, adding a new accelerator only requires connecting its storage to the system, resulting in strong system scalability. By changing the design of storage resources in baseband chips through hardware virtualization and management, moving from distributed exclusive use to centralized pooling, it achieves on-demand allocation and efficient utilization of storage resources, providing a key method for resolving the triangular contradiction between terminal chip area, power consumption, and performance.

[0080] In some embodiments, Figure 3 This is a block diagram of a storage management device 30 provided in an embodiment of the present disclosure. The storage management device 30 can be configured to perform... Figures 1 to 2 The method shown. Refer to... Figure 3 The storage management device 30 includes: an allocation module 31, an acquisition module 32, and an access module 33.

[0081] The allocation module 31 is used to allocate a target virtual address corresponding to the storage resource request in a virtual storage list in response to the storage resource request of the first hardware accelerator. The virtual storage list is obtained by uniformly addressing a storage resource pool, and the storage resource pool includes dedicated storage resources of multiple hardware accelerators in the chip, including the first hardware accelerator. The acquisition module 32 is used to acquire the physical address of the storage resource corresponding to the target virtual address; The open module 33 is used to grant the first hardware accelerator access permissions to the target storage resource in the storage resource pool based on the physical address of the storage resource.

[0082] In some embodiments of this disclosure, the storage resource pool further includes shared storage resources within the chip and external storage resources of the chip; The allocation module 31 is specifically used to determine resource requirement information based on the storage resource request; and based on the resource requirement information, and in combination with the access performance priorities corresponding to the dedicated storage resource, the shared storage resource and the external storage resource, allocate the target virtual address in the virtual storage list.

[0083] In some embodiments of this disclosure, the allocation module 31 is specifically used to sequentially match idle storage resources in the storage resource pool that meet the resource requirement information according to the access performance priority from high to low, wherein the access performance priority of the dedicated storage resources of the first hardware accelerator is higher than the access performance priority of the dedicated storage resources of other hardware accelerators, the access performance priority of the dedicated storage resources of other hardware accelerators is higher than the access performance priority of the shared storage resources, and the access performance priority of the shared storage resources is higher than the access performance priority of the external storage resources; based on the matched idle storage resources, the corresponding virtual address is determined as the target virtual address in the virtual storage list.

[0084] In some embodiments of this disclosure, the allocation module 31 is specifically used to detect whether there are storage resources pre-allocated for the first hardware accelerator in the storage resource pool; if the pre-allocated storage resources exist in the storage resource pool and the pre-allocated storage resources meet the resource requirement information, then the target virtual address is determined according to the virtual address of the pre-allocated storage resources in the virtual storage list.

[0085] In some embodiments of this disclosure, the allocation module 31 is specifically used to allocate the target virtual address in the virtual storage list based on the resource requirement information and in combination with the access performance priorities corresponding to the dedicated storage resource, the shared storage resource, and the external storage resource if the pre-allocated storage resource does not exist in the storage resource pool or the pre-allocated storage resource does not meet the resource requirement information.

[0086] In some embodiments of this disclosure, the acquisition module 32 is specifically used to acquire the physical address of the storage resource corresponding to the target virtual address through a hardware accelerator page table, wherein the hardware accelerator page table includes a mapping relationship between the target virtual address and the physical address of the target storage resource.

[0087] In some embodiments of this disclosure, the hardware accelerator page table further includes at least one of the following attribute bits: The location bit is used to indicate the storage level where the target storage resource is located. The storage level is any one of the storage level of the dedicated storage resources of the hardware accelerator, the storage level of the shared storage resources within the chip, and the storage level of the external storage resources of the chip. A migration bit, which indicates whether migration of the target storage resource between different storage tiers is permitted; An accelerator bit, which indicates a target hardware accelerator that allows the target storage resource to be preferentially accessed.

[0088] In some embodiments of this disclosure, the acquisition module 32 is further configured to migrate the storage layer where the target storage resource is located to a storage layer corresponding to a higher access performance priority if it is determined that migration is allowed based on the migration bit and the storage layer where the target storage resource is located is not the storage layer corresponding to the highest access performance priority based on the position bit; after the migration is completed, update the physical address mapping relationship and position bit corresponding to the target virtual address in the hardware accelerator page table.

[0089] In some embodiments of this disclosure, the opening module 33 is further configured to send the physical address descriptor of the target storage resource to a second hardware accelerator among the plurality of hardware accelerators; in response to the second hardware accelerator's access request for the target storage resource, the module grants the second hardware accelerator access rights to the target storage resource according to the physical address descriptor in the access request.

[0090] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0091] It should be noted that other corresponding descriptions of the functional units involved in the storage management device provided in the embodiments of this disclosure can be found in the corresponding descriptions of the storage management methods provided in the above embodiments, and will not be repeated here.

[0092] Based on the storage management method provided in the above embodiments, this disclosure also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the storage management method provided in the above embodiments.

[0093] Based on the storage management method provided in the above embodiments, this disclosure also provides a computer program product, including a computer program that implements the storage management method provided in the above embodiments when executed by a processor.

[0094] Based on this understanding, the technical solution disclosed herein can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, or portable hard drive) and includes several instructions to cause a computer device (such as a personal computer, server, or network device) to execute the methods of various implementation scenarios of this disclosure.

[0095] Based on the storage management method provided in the above embodiments, and Figure 3 The virtual device embodiment shown in this disclosure also provides a chip, including one or more interface circuits and one or more processors; the interface circuits are used to receive signals from the memory of an electronic device and send the signals to the processors, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, it causes the electronic device to perform the memory management method provided in the above embodiments.

[0096] Figure 4A schematic block diagram of an example electronic device 1000 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0097] like Figure 4 As shown, device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes based on a computer program stored in ROM (Read-Only Memory) 1002 or loaded from storage unit 1008 into RAM (Random Access Memory) 1003. RAM 1003 may also store various programs and data required for the operation of device 1000. The computing unit 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. I / O (Input / Output) interface 1005 is also connected to bus 1004.

[0098] Multiple components in device 1000 are connected to I / O interface 1005, including: input unit 1006, such as keyboard, mouse, etc.; output unit 1007, such as various types of monitors, speakers, etc.; storage unit 1008, such as disk, optical disk, etc.; and communication unit 1009, such as network card, modem, wireless transceiver, etc. Communication unit 1009 allows device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0099] The computing unit 1001 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 1001 performs the various methods and processes described above, such as the methods mentioned earlier. For example, in some embodiments, the methods mentioned earlier can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 1008. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM 1002 and / or communication unit 1009. When the computer program is loaded into RAM 1003 and executed by the computing unit 1001, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to perform the aforementioned method by any other suitable means (e.g., by means of firmware).

[0100] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0101] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0102] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0103] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0104] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0105] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0106] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0107] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0108] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A storage management method, characterized in that, include: In response to a storage resource request from a first hardware accelerator, a target virtual address corresponding to the storage resource request is allocated in a virtual storage list. The virtual storage list is obtained by uniformly addressing a storage resource pool, which includes dedicated storage resources for multiple hardware accelerators in the chip, including the first hardware accelerator. Obtain the physical address of the storage resource corresponding to the target virtual address; Based on the physical address of the storage resource, grant access permissions to the target storage resource in the storage resource pool to the first hardware accelerator.

2. The method according to claim 1, characterized in that, The storage resource pool also includes shared storage resources within the chip and external storage resources of the chip; The step of allocating the target virtual address corresponding to the storage resource request in the virtual storage list includes: Determine resource requirement information based on the storage resource request; Based on the resource requirement information and in combination with the access performance priorities corresponding to the dedicated storage resources, the shared storage resources, and the external storage resources, the target virtual address is allocated in the virtual storage list.

3. The method according to claim 2, characterized in that, The step of allocating the target virtual address in the virtual storage list based on the resource requirement information and in combination with the access performance priorities corresponding to the dedicated storage resources, the shared storage resources, and the external storage resources includes: According to the access performance priority from high to low, the idle storage resources in the storage resource pool that meet the resource requirement information are matched sequentially. The access performance priority of the dedicated storage resources of the first hardware accelerator is higher than that of the dedicated storage resources of other hardware accelerators. The access performance priority of the dedicated storage resources of other hardware accelerators is higher than that of the shared storage resources. The access performance priority of the shared storage resources is higher than that of the external storage resources. Based on the matched free storage resources, the corresponding virtual address is determined from the virtual storage list as the target virtual address.

4. The method according to claim 2, characterized in that, Before allocating the target virtual address in the virtual storage list based on the resource requirement information and the access performance priorities corresponding to the dedicated storage resource, the shared storage resource, and the external storage resource, the method further includes: Detect whether there are storage resources pre-allocated for the first hardware accelerator in the storage resource pool; If the pre-allocated storage resource exists in the storage resource pool and the pre-allocated storage resource meets the resource requirement information, then the target virtual address is determined according to the virtual address of the pre-allocated storage resource in the virtual storage list.

5. The method according to claim 4, characterized in that, The process of allocating the target virtual address in the virtual storage list based on the resource requirement information and the access performance priorities corresponding to the dedicated storage resources, the shared storage resources, and the external storage resources includes: If the pre-allocated storage resource is not available in the storage resource pool, or if the pre-allocated storage resource does not meet the resource requirement information, then the target virtual address is allocated in the virtual storage list based on the resource requirement information and the access performance priorities corresponding to the dedicated storage resource, the shared storage resource, and the external storage resource, respectively.

6. The method according to claim 1, characterized in that, The method further includes: The physical address of the storage resource corresponding to the target virtual address is obtained through the hardware accelerator page table, which includes the mapping relationship between the target virtual address and the physical address of the target storage resource.

7. The method according to claim 6, characterized in that, The hardware accelerator page table also includes at least one of the following attribute bits: The location bit is used to indicate the storage level where the target storage resource is located. The storage level is any one of the storage level of the dedicated storage resources of the hardware accelerator, the storage level of the shared storage resources within the chip, and the storage level of the external storage resources of the chip. A migration bit, which indicates whether migration of the target storage resource between different storage tiers is permitted; An accelerator bit, which indicates a target hardware accelerator that allows the target storage resource to be preferentially accessed.

8. The method according to claim 7, characterized in that, The method further includes: If migration is allowed based on the migration bit, and the storage tier where the target storage resource is located is not the storage tier corresponding to the highest access performance priority based on the location bit, then the storage tier where the target storage resource is located will be migrated to the storage tier corresponding to the higher access performance priority. After the migration is complete, update the physical address mapping relationship and position bits corresponding to the target virtual address in the hardware accelerator page table.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: Send the physical address descriptor of the target storage resource to the second hardware accelerator among the plurality of hardware accelerators; In response to the second hardware accelerator's access request to the target storage resource, access permissions to the target storage resource are granted to the second hardware accelerator based on the physical address descriptor in the access request.

10. A storage management device, characterized in that, include: An allocation module is configured to, in response to a storage resource request from a first hardware accelerator, allocate a target virtual address corresponding to the storage resource request in a virtual storage list, wherein the virtual storage list is obtained by uniformly addressing a storage resource pool, the storage resource pool includes dedicated storage resources for multiple hardware accelerators in the chip, and the multiple hardware accelerators include the first hardware accelerator. The acquisition module is used to acquire the physical address of the storage resource corresponding to the target virtual address; An open module is used to grant the first hardware accelerator access permissions to the target storage resource in the storage resource pool based on the physical address of the storage resource.

11. The apparatus according to claim 10, characterized in that, The storage resource pool also includes shared storage resources within the chip and external storage resources of the chip; The allocation module is specifically used to determine resource requirement information based on the storage resource request; and based on the resource requirement information, and in combination with the access performance priorities corresponding to the dedicated storage resource, the shared storage resource and the external storage resource, allocate the target virtual address in the virtual storage list.

12. The apparatus according to claim 11, characterized in that, The allocation module is specifically used for: According to the access performance priority from high to low, the idle storage resources in the storage resource pool that meet the resource requirement information are matched sequentially. The access performance priority of the dedicated storage resources of the first hardware accelerator is higher than that of the dedicated storage resources of other hardware accelerators. The access performance priority of the dedicated storage resources of other hardware accelerators is higher than that of the shared storage resources. The access performance priority of the shared storage resources is higher than that of the external storage resources. Based on the matched free storage resources, the corresponding virtual address is determined from the virtual storage list as the target virtual address.

13. The apparatus according to any one of claims 10 to 12, characterized in that, The open module is also used for: Send the physical address descriptor of the target storage resource to the second hardware accelerator among the plurality of hardware accelerators; In response to the second hardware accelerator's access request to the target storage resource, access permissions to the target storage resource are granted to the second hardware accelerator based on the physical address descriptor in the access request.

14. An electronic device, characterized in that, include: processor; A memory connected to the processor, the memory storing a computer program that, when executed by the processor, implements the method of any one of claims 1 to 9.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 9.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 9.

17. A chip, characterized in that, The device includes one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of an electronic device and send the signals to the processors, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device performs the method according to any one of claims 1 to 9.

Images