5-bit adder, arithmetic operation circuit, computing chip and electronic equipment

Abstract

This invention relates to the field of adder circuit technology, specifically providing a 5-bit adder, an arithmetic operation circuit, a computing chip, and an electronic device. The adder consists of 40 transistors, including multiple XOR gates and inverters. The first input node of the third XOR gate is the first data input node, the second input node of the third XOR gate is the second data input node, the output node of the second inverter is the third data input node, the first input node of the first XOR gate is the fourth data input node, the second input node of the first XOR gate is the fifth data input node, the output node of the first inverter is the data output node, the output node of the third inverter is the first carry signal node, and the output node of the fifth inverter is the second carry signal node. This addresses the problem of the lack of high-efficiency, small-area, and high-speed 5-bit adders in related technologies.

Description

Technical Field

[0001] This invention relates to the field of adder circuit technology, and in particular to a 5-bit adder, arithmetic operation circuit, computing chip and electronic device. Background Technology

[0002] Adders are fundamental arithmetic modules widely used in various computing chips such as in-memory computing, CPUs, and GPUs. They are basic elements that constitute multipliers, floating-point units, and other arithmetic units. In other words, adders are frequently used in computing chips and occupy a significant portion of the chip's hardware area. Therefore, the hardware area, power consumption, and operation latency of adders directly affect the chip's performance.

[0003] The relevant technology uses a cascaded 28T carry full adder to perform 5-bit addition operations. This type of full adder has a large number of transistors, large hardware area, long signal propagation path, and many MOS transistor switching times, resulting in high circuit power consumption and large operation delay. It is difficult to meet the current development requirements of computing chips for high energy efficiency, small area, and high operation speed.

[0004] There is currently no effective solution to the problem of the lack of a 5-bit adder with high energy efficiency, small area, and high computing speed in related technologies. Summary of the Invention

[0005] The present invention provides a 5-bit adder, arithmetic operation circuit, computing chip and electronic device, which at least solves the problem of the lack of high-efficiency, small-area and high-speed 5-bit adders in related technologies.

[0006] This invention provides a 5-bit adder, comprising a first XOR gate, a second XOR gate, a third XOR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The first XOR gate, the second XOR gate, and the third XOR gate have the same internal structure, each including 6 MOS transistors. The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the fifth inverter, the fifth inverter, the sixth ... The internal structures of the first, fourth, and fifth inverters are identical, each including two MOS transistors. The output node of the first XOR gate is connected to the first input node of the second XOR gate; the output node of the second XOR gate is connected to the input node of the first inverter; the output node of the third XOR gate is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor, the source of the second PMOS transistor, and the source of the second NMOS transistor; the source of the first PMOS transistor is connected to the output node of the second inverter and the gate of the second PMOS transistor; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor, and the drain of the second NMOS transistor. The source of the third PMOS transistor, the source of the third NMOS transistor, and the second input node of the second XOR gate are connected; the source of the second NMOS transistor is connected to the input node of the second inverter, the source of the fifth PMOS transistor, and the source of the fifth NMOS transistor; the gate of the third PMOS transistor is connected to the gate of the fourth NMOS transistor and is controlled by the first input node of the second XOR gate; the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, and the input node of the third inverter; the gate of the third NMOS transistor is connected to the gate of the fourth PMOS transistor and the first output node of the second XOR gate; the... The source of the fourth PMOS transistor is connected to the source of the fourth NMOS transistor and is controlled by the first input node of the first XOR gate; the gate of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor and the output node of the fourth inverter; the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the sixth PMOS transistor, the drain of the sixth NMOS transistor, and the input node of the fifth inverter; the gate of the fifth NMOS transistor is connected to the gate of the sixth PMOS transistor, the output node of the third XOR gate, and the input node of the fourth inverter; the source of the sixth PMOS transistor is connected to the source of the sixth NMOS transistor and is controlled by the first input node of the third XOR gate.In this circuit, the first input node of the third XOR gate is the first data input node of the 5-bit adder; the second input node of the third XOR gate is the second data input node of the 5-bit adder; the output node of the second inverter is the third data input node of the 5-bit adder; the first input node of the first XOR gate is the fourth data input node of the 5-bit adder; the second input node of the first XOR gate is the fifth data input node of the 5-bit adder; the output node of the first inverter is the data output node of the 5-bit adder; the output node of the third inverter is the first carry signal node of the 5-bit adder; and the output node of the fifth inverter is the second carry signal node of the 5-bit adder.

[0007] Preferably, the second XOR gate includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; the source of the seventh PMOS transistor is connected to a power supply; the gate of the seventh PMOS transistor is connected to the output node of the first XOR gate, the gate of the seventh NMOS transistor, the source of the eighth PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the third NMOS transistor; the drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the eighth NMOS transistor, the gate of the ninth NMOS transistor, and the gate of the third PMOS transistor, for controlling the gate of the third PMOS transistor and the gate of the fourth NMOS transistor based on the first input node of the second XOR gate. The source of the seventh NMOS transistor is grounded; the gate of the eighth PMOS transistor is connected to the gate of the eighth NMOS transistor, the source of the ninth PMOS transistor, the source of the ninth NMOS transistor, and the drain of the first PMOS transistor; the drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, the drain of the ninth PMOS transistor, and the drain of the ninth NMOS transistor; wherein, the connection node between the gate of the seventh PMOS transistor and the gate of the seventh NMOS transistor is the first input node of the second XOR gate, the connection node between the gate of the eighth PMOS transistor and the gate of the eighth NMOS transistor is the second input node of the second XOR gate, and the connection node between the drain of the ninth PMOS transistor and the drain of the ninth NMOS transistor is the output node of the second XOR gate.

[0008] Preferably, the second XOR gate is configured such that: when the first input node of the second XOR gate is set to 1 and the second input node of the second XOR gate is set to 0, the output node of the second XOR gate is 1; when the first input node of the second XOR gate is set to 0 and the second input node of the second XOR gate is set to 1, the output node of the second XOR gate is 1; when the first input node of the second XOR gate is set to 1 and the second input node of the second XOR gate is set to 1, the output node of the second XOR gate is 0; and when the first input node of the second XOR gate is set to 0 and the second input node of the second XOR gate is set to 0, the output node of the second XOR gate is 0.

[0009] Preferably, the first inverter includes a tenth PMOS transistor and a tenth NMOS transistor; the source of the tenth PMOS transistor is connected to a power supply, the gate of the tenth PMOS transistor is connected to the gate of the tenth NMOS transistor and the output node of the second XOR gate, and the drain of the tenth PMOS transistor is connected to the drain of the tenth NMOS transistor; the source of the tenth NMOS transistor is grounded; wherein, the connection node between the gate of the tenth PMOS transistor and the gate of the tenth NMOS transistor is the input node of the first inverter, and the connection node between the drain of the tenth PMOS transistor and the drain of the tenth NMOS transistor is the output node of the first inverter.

[0010] Preferably, the third XOR gate includes an eleventh PMOS transistor and an eleventh NMOS transistor, and the first XOR gate includes a twelfth PMOS transistor and a twelfth NMOS transistor; the source of the eleventh PMOS transistor is connected to the power supply, and the gate of the eleventh PMOS transistor is connected to the gate of the eleventh NMOS transistor; the drain of the eleventh PMOS transistor is connected to the drain of the eleventh NMOS transistor and the source of the sixth PMOS transistor, for controlling the sources of the sixth PMOS transistor and the sixth NMOS transistor based on the first input node of the third XOR gate; the source of the eleventh NMOS transistor is grounded; and the source of the twelfth PMOS transistor is connected to the power supply. The gate of the twelfth PMOS transistor is connected to the gate of the twelfth NMOS transistor; the drain of the twelfth PMOS transistor is connected to the drain of the twelfth NMOS transistor and the source of the fourth PMOS transistor, and is used to control the source of the fourth PMOS transistor and the source of the fourth NMOS transistor based on the first input node of the first XOR gate; the source of the twelfth NMOS transistor is grounded; wherein, the connection node between the gate of the eleventh PMOS transistor and the gate of the eleventh NMOS transistor is the first input node of the third XOR gate, and the connection node between the gate of the twelfth PMOS transistor and the gate of the twelfth NMOS transistor is the first input node of the first XOR gate.

[0011] Preferably, the logical relationship between the data output node, the first carry signal node, and the second carry signal node of the 5-bit adder is as follows:

[0012] ;

[0013] ;

[0014] ;

[0015] In the formula, Indicates the data output node. Indicates the output node of the first XOR gate. This represents the XOR operation. This indicates the connection node between the drain of the second PMOS transistor and the drain of the second NMOS transistor. Indicates the fourth data input node. This represents the XOR operation. Indicates the fifth data input node. Indicates the first data input node. Indicates the second data input node. This indicates the input node of the second inverter. Indicates the first carry signal node. This indicates the output node of the third XOR gate. Indicates the third data input node. This indicates the second carry signal node.

[0016] The present invention also provides an arithmetic operation circuit, which is provided with any of the above-mentioned 5-bit adders.

[0017] The present invention also provides a computing chip having the above-described arithmetic operation circuit.

[0018] Preferably, the computing chip is an in-memory computing chip, a CPU chip, or a GPU chip.

[0019] The present invention also provides an electronic device having any of the above-described computing chips.

[0020] This invention provides a 5-bit adder composed of 40 transistors, including multiple XOR gates and inverters. The first input node of the third XOR gate is the first data input node, the second input node of the third XOR gate is the second data input node, the output node of the second inverter is the third data input node, the first input node of the first XOR gate is the fourth data input node, the second input node of the first XOR gate is the fifth data input node, the output node of the first inverter is the data output node, the output node of the third inverter is the first carry signal node, and the output node of the fifth inverter is the second carry signal node. This 5-bit adder has fewer transistors, fewer transistor flip-flops, and a shorter signal propagation path, resulting in improvements in hardware area, power consumption, and computational latency. It solves the problem of the lack of high-efficiency, small-area, and high-speed 5-bit adders in related technologies. Attached Figure Description

[0021] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a 5-bit adder in an embodiment of the present invention.

[0023] Figure 2 This is an equivalent schematic diagram of a 5-bit adder and two full adders in an embodiment of the present invention.

[0024] The above figures include the following reference numerals:

[0025] YH1, the first XOR gate; YH2, the second XOR gate; YH3, the third XOR gate;

[0026] FX1, First inverter; FX2, Second inverter; FX3, Third inverter; FX4, Fourth inverter; FX5, Fifth inverter;

[0027] P01, First PMOS transistor; P02, Second PMOS transistor; P03, Third PMOS transistor; P04, Fourth PMOS transistor; P05, Fifth PMOS transistor; P06, Sixth PMOS transistor; P07, Seventh PMOS transistor; P08, Eighth PMOS transistor; P09, Ninth PMOS transistor; P10, Tenth PMOS transistor; P11, Eleventh PMOS transistor; P12, Twelfth PMOS transistor; P13, Thirteenth PMOS transistor; P14, Fourteenth PMOS transistor; P15, Fifteenth PMOS transistor; P16, Sixteenth PMOS transistor; P17, Seventeenth PMOS transistor; P18, Eighteenth PMOS transistor; P19, Nineteenth PMOS transistor; P20, Twentieth PMOS transistor;

[0028] N01, First NMOS transistor; N02, Second NMOS transistor; N03, Third NMOS transistor; N04, Fourth NMOS transistor; N05, Fifth NMOS transistor; N06, Sixth NMOS transistor; N07, Seventh NMOS transistor; N08, Eighth NMOS transistor; N09, Nth NMOS transistor; N10, Tenth NMOS transistor; N11, Eleventh NMOS transistor; N12, Twelfth NMOS transistor; N13, Thirteenth NMOS transistor; N14, Fourteenth NMOS transistor; N15, Fifteenth NMOS transistor; N16, Sixteenth NMOS transistor; N17, Seventeenth NMOS transistor; N18, Eighteenth NMOS transistor; N19, Nineteenth NMOS transistor; N20, Twentieth NMOS transistor;

[0029] D1, First data input node (first input node of the third XOR gate); D2, Second data input node (second input node of the third XOR gate); D3, Third data input node; D4, Fourth data input node (first input node of the first XOR gate); D5, Fifth data input node (second input node of the first XOR gate); S, Data output node; C1, First carry signal node; C2, First carry signal node;

[0030] N1, the output node of the third XOR gate; N2, the output node of the first XOR gate; N3, the connection node between the drain of the second PMOS transistor and the drain of the second NMOS transistor; D1N, the connection node between the source of the sixth PMOS transistor and the source of the sixth NMOS transistor; D4N, the connection node between the source of the fourth PMOS transistor and the source of the fourth NMOS transistor; D3N, the input node of the second inverter. Detailed Implementation

[0031] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0032] Adders are fundamental arithmetic modules widely used in various computing chips such as in-memory computing, CPUs, and GPUs. They are basic elements that constitute multipliers, floating-point units, and other arithmetic units. In other words, adders are frequently used in computing chips and occupy a significant portion of the chip's hardware area. Therefore, the hardware area, power consumption, and operation latency of adders directly affect the chip's performance.

[0033] The relevant technology uses a cascaded 28T carry full adder to perform 5-bit addition operations. This type of full adder has a large number of transistors, large hardware area, long signal propagation path, and many MOS transistor switching times, resulting in high circuit power consumption and large operation delay. It is difficult to meet the current development requirements of computing chips for high energy efficiency, small area, and high operation speed.

[0034] Specifically, the 28T carry-full adder used in the related technology consists of 28 transistors. An adder that performs 5-bit addition requires two 28T carry-full adders, which means 56 transistors are needed.

[0035] Therefore, please refer to Figure 1As shown, an embodiment of the present invention provides a 5-bit adder, including a first XOR gate YH1, a second XOR gate YH2, a third XOR gate YH3, a first inverter FX1, a second inverter FX2, a third inverter FX3, a fourth inverter FX4, a fifth inverter FX5, a first PMOS transistor P01, a second PMOS transistor P02, a third PMOS transistor P03, a fourth PMOS transistor P04, a fifth PMOS transistor P05, a sixth PMOS transistor P06, a first NMOS transistor N01, a second NMOS transistor N02, a third NMOS transistor N03, a fourth NMOS transistor N04, a fifth NMOS transistor N05, and a sixth NMOS transistor N06.

[0036] The internal structures of the first XOR gate YH1, the second XOR gate YH2, and the third XOR gate YH3 are the same, each including 6 MOS transistors.

[0037] The first inverter FX1, the second inverter FX2, the third inverter FX3, the fourth inverter FX4, and the fifth inverter FX5 have the same internal structure, each including two MOSFETs.

[0038] The output node of the first XOR gate YH1 is connected to the first input node of the second XOR gate YH2.

[0039] The output node of the second XOR gate YH2 is connected to the input node of the first inverter FX1.

[0040] The output node of the third XOR gate YH3 is connected to the gate of the first PMOS transistor P01, the gate of the first NMOS transistor N01, the source of the second PMOS transistor P02, and the source of the second NMOS transistor N02.

[0041] The source of the first PMOS transistor P01 is connected to the output node of the second inverter FX2 and the gate of the second PMOS transistor P02. The drain of the first PMOS transistor P01 is connected to the drain of the first NMOS transistor N01, the drain of the second PMOS transistor P02, the drain of the second NMOS transistor N02, the source of the third PMOS transistor P03, the source of the third NMOS transistor N03, and the second input node of the second XOR gate YH2.

[0042] The source of the second NMOS transistor N02 is connected to the input node of the second inverter FX2, the source of the fifth PMOS transistor P05, and the source of the fifth NMOS transistor N05.

[0043] The gate of the third PMOS transistor P03 is connected to the gate of the fourth NMOS transistor N04 and is controlled by the first input node of the second XOR gate YH2. The drain of the third PMOS transistor P03 is connected to the drain of the third NMOS transistor N03, the drain of the fourth PMOS transistor P04, the drain of the fourth NMOS transistor N04, and the input node of the third inverter FX3.

[0044] The gate of the third NMOS transistor N03 is connected to the gate of the fourth PMOS transistor P04 and the first output node of the second XOR gate YH2.

[0045] The source of the fourth PMOS transistor P04 is connected to the source of the fourth NMOS transistor N04 and is controlled by the first input node of the first XOR gate YH1. Specifically, the connection node D4N between the source of the fourth PMOS transistor P04 and the source of the fourth NMOS transistor N04 is controlled by the first input node D4 of the first XOR gate YH1.

[0046] The gate of the fifth PMOS transistor P05 is connected to the gate of the sixth NMOS transistor N06 and the output node of the fourth inverter FX4. The drain of the fifth PMOS transistor P05 is connected to the drain of the fifth NMOS transistor N05, the drain of the sixth PMOS transistor P06, the drain of the sixth NMOS transistor N06, and the input node of the fifth inverter FX5.

[0047] The gate of the fifth NMOS transistor N05 is connected to the gate of the sixth PMOS transistor P06, the output node of the third XOR gate YH3, and the input node of the fourth inverter FX4.

[0048] The source of the sixth PMOS transistor P06 is connected to the source of the sixth NMOS transistor N06 and is controlled by the first input node of the third XOR gate YH3. Specifically, the connection node D1N between the source of the sixth PMOS transistor P06 and the source of the sixth NMOS transistor N06 is controlled by the first input node D1 of the third XOR gate YH3.

[0049] Specifically, the first input node of the third XOR gate YH3 is the first data input node D1 of the 5-bit adder, the second input node of the third XOR gate YH3 is the second data input node D2 of the 5-bit adder, the output node of the second inverter FX2 is the third data input node D3 of the 5-bit adder, the first input node of the first XOR gate YH1 is the fourth data input node D4 of the 5-bit adder, the second input node of the first XOR gate YH1 is the fifth data input node D5 of the 5-bit adder, the output node of the first inverter FX1 is the data output node S of the 5-bit adder, the output node of the third inverter FX3 is the first carry signal node C1 of the 5-bit adder, and the output node of the fifth inverter FX5 is the second carry signal node C2 of the 5-bit adder.

[0050] Nodes D1, D2, D3, D4, and D5 correspond to the 5-bit input data. Node N1 corresponds to the XOR result of the input data of node D1 and the input data of node D2; node N2 corresponds to the XOR result of the input data of node D4 and the input data of node D5; node N3 corresponds to the XOR result of the data of node D3N and the data of node N1. Node D3N is the input node of the second inverter FX2.

[0051] like Figure 2 As shown, the 5-bit adder provided in this embodiment is equivalent to two carry-full adders, but requires only 40 transistors, and its signal propagation path is shorter than that of cascaded 28T carry-full adders in related technologies. The adder provided in this embodiment has fewer MOS transistor switching times, resulting in improvements in hardware area, power consumption, and computational latency. As the frequency of adders used in in-memory computing, GPUs, and CPUs increases, this improvement will have a significant cumulative effect. Therefore, the adder provided in this embodiment can be widely used in computing circuits to shorten the chip's critical path and improve chip performance.

[0052] Preferably, the second XOR gate YH2 includes a seventh PMOS transistor P07, an eighth PMOS transistor P08, a ninth PMOS transistor P09, a seventh NMOS transistor N07, an eighth NMOS transistor N08, and a ninth NMOS transistor N09.

[0053] The source of the seventh PMOS transistor P07 is connected to the power supply.

[0054] The gate of the seventh PMOS transistor P07 is connected to the output node of the first XOR gate YH1, the gate of the seventh NMOS transistor N07, the source of the eighth PMOS transistor P08, the gate of the ninth PMOS transistor P09, and the gate of the third NMOS transistor N03.

[0055] The drain of the seventh PMOS transistor P07 is connected to the drain of the seventh NMOS transistor N07, the source of the eighth NMOS transistor N08, the gate of the ninth NMOS transistor N09, and the gate of the third PMOS transistor P03, and is used to control the gate of the third PMOS transistor P03 and the gate of the fourth NMOS transistor N04 based on the first input node of the second XOR gate YH2.

[0056] The source of the seventh NMOS transistor N07 is grounded.

[0057] The gate of the eighth PMOS transistor P08 is connected to the gate of the eighth NMOS transistor N08, the source of the ninth PMOS transistor P09, the source of the ninth NMOS transistor N09, and the drain of the first PMOS transistor P01.

[0058] The drain of the eighth PMOS transistor P08 is connected to the drain of the eighth NMOS transistor N08, the drain of the ninth PMOS transistor P09, and the drain of the ninth NMOS transistor N09.

[0059] The connection node between the gate of the seventh PMOS transistor P07 and the gate of the seventh NMOS transistor N07 is the first input node of the second XOR gate YH2; the connection node between the gate of the eighth PMOS transistor P08 and the gate of the eighth NMOS transistor N08 is the second input node of the second XOR gate YH2; and the connection node between the drain of the ninth PMOS transistor P09 and the drain of the ninth NMOS transistor N09 is the output node of the second XOR gate YH2.

[0060] Preferably, the second XOR gate YH2 is configured such that when the first input node of the second XOR gate YH2 is set to 1 and the second input node of the second XOR gate YH2 is set to 0, the output node of the second XOR gate YH2 is 1.

[0061] When the first input node of the second XOR gate YH2 is set to 0 and the second input node of the second XOR gate YH2 is set to 1, the output node of the second XOR gate YH2 is 1.

[0062] When the first input node of the second XOR gate YH2 is set to 1 and the second input node of the second XOR gate YH2 is set to 1, the output node of the second XOR gate YH2 is 0.

[0063] When the first input node of the second XOR gate YH2 is set to 0 and the second input node of the second XOR gate YH2 is set to 0, the output node of the second XOR gate YH2 is 0.

[0064] Preferably, the first inverter FX1 includes a tenth PMOS transistor P10 and a tenth NMOS transistor N10.

[0065] The source of the tenth PMOS transistor P10 is connected to the power supply, the gate of the tenth PMOS transistor P10 is connected to the gate of the tenth NMOS transistor N10 and the output node of the second XOR gate YH2, and the drain of the tenth PMOS transistor P10 is connected to the drain of the tenth NMOS transistor N10.

[0066] The source of the tenth NMOS transistor N10 is grounded.

[0067] The connection node between the gate of the tenth PMOS transistor P10 and the gate of the tenth NMOS transistor N10 is the input node of the first inverter FX1, and the connection node between the drain of the tenth PMOS transistor P10 and the drain of the tenth NMOS transistor N10 is the output node of the first inverter FX1.

[0068] The internal structures of the first inverter FX1, the second inverter FX2, the third inverter FX3, the fourth inverter FX4, and the fifth inverter FX5 are the same.

[0069] For example, the second inverter FX2 includes a seventeenth PMOS transistor P17 and a seventeenth NMOS transistor N17.

[0070] The source of the seventeenth PMOS transistor P17 is connected to the power supply, the gate of the seventeenth PMOS transistor P17 is connected to the gate of the seventeenth NMOS transistor N17 and the source of the first NMOS transistor N01, and the drain of the seventeenth PMOS transistor P17 is connected to the drain of the seventeenth NMOS transistor N17 and the source of the first PMOS transistor P01.

[0071] The source of the seventeenth NMOS transistor N17 is grounded.

[0072] The connection node between the gate of the seventeenth PMOS transistor P17 and the gate of the seventeenth NMOS transistor N17 is the input node of the second inverter FX2, and the connection node between the drain of the seventeenth PMOS transistor P17 and the drain of the seventeenth NMOS transistor N17 is the output node of the second inverter FX2.

[0073] For example, the third inverter FX3 includes an eighteenth PMOS transistor P18 and an eighteenth NMOS transistor N18.

[0074] The source of the eighteenth PMOS transistor P18 is connected to the power supply, the gate of the eighteenth PMOS transistor P18 is connected to the gate of the eighteenth NMOS transistor N18 and the drain of the third PMOS transistor P03, and the drain of the eighteenth PMOS transistor P18 is connected to the drain of the eighteenth NMOS transistor N18.

[0075] The source of the eighteenth NMOS transistor N18 is grounded.

[0076] The connection node between the gate of the eighteenth PMOS transistor P18 and the gate of the eighteenth NMOS transistor N18 is the input node of the third inverter FX3, and the connection node between the drain of the eighteenth PMOS transistor P18 and the drain of the eighteenth NMOS transistor N18 is the output node of the third inverter FX3.

[0077] For example, the fourth inverter FX4 includes a nineteenth PMOS transistor P19 and a nineteenth NMOS transistor N19.

[0078] The source of the nineteenth PMOS transistor P19 is connected to the power supply, the gate of the nineteenth PMOS transistor P19 is connected to the gate of the nineteenth NMOS transistor N19 and the output node of the third XOR gate YH3, and the drain of the nineteenth PMOS transistor P19 is connected to the drain of the nineteenth NMOS transistor N19 and the gate of the fifth PMOS transistor P05.

[0079] The source of the nineteenth NMOS transistor N19 is grounded.

[0080] The connection node between the gate of the nineteenth PMOS transistor P19 and the gate of the nineteenth NMOS transistor N19 is the input node of the fourth inverter FX4, and the connection node between the drain of the nineteenth PMOS transistor P19 and the drain of the nineteenth NMOS transistor N19 is the output node of the fourth inverter FX4.

[0081] For example, the fifth inverter FX5 includes a twentieth PMOS transistor P20 and a twentieth NMOS transistor N20.

[0082] The source of the twentieth PMOS transistor P20 is connected to the power supply, the gate of the twentieth PMOS transistor P20 is connected to the gate of the twentieth NMOS transistor N20 and the drain of the fifth PMOS transistor P05, and the drain of the twentieth PMOS transistor P20 is connected to the drain of the twentieth NMOS transistor N20.

[0083] The source of the twentieth NMOS transistor N20 is grounded.

[0084] The connection node between the gate of the twentieth PMOS transistor P20 and the gate of the twentieth NMOS transistor N20 is the input node of the fifth inverter FX5, and the connection node between the drain of the twentieth PMOS transistor P20 and the drain of the twentieth NMOS transistor N20 is the output node of the fifth inverter FX5.

[0085] Preferably, the third XOR gate YH3 includes an eleventh PMOS transistor P11 and an eleventh NMOS transistor N11, and the first XOR gate YH1 includes a twelfth PMOS transistor P12 and a twelfth NMOS transistor N12.

[0086] The source of the eleventh PMOS transistor P11 is connected to the power supply, and the gate of the eleventh PMOS transistor P11 is connected to the gate of the eleventh NMOS transistor N11.

[0087] The drain of the eleventh PMOS transistor P11 is connected to the drain of the eleventh NMOS transistor N11 and the source of the sixth PMOS transistor P06, and is used to control the source of the sixth PMOS transistor P06 and the source of the sixth NMOS transistor N06 based on the first input node of the third XOR gate YH3.

[0088] The source of the eleventh NMOS transistor N11 is grounded.

[0089] The source of the twelfth PMOS transistor P12 is connected to the power supply, and the gate of the twelfth PMOS transistor P12 is connected to the gate of the twelfth NMOS transistor N12.

[0090] The drain of the twelfth PMOS transistor P12 is connected to the drain of the twelfth NMOS transistor N12 and the source of the fourth PMOS transistor P04, and is used to control the source of the fourth PMOS transistor P04 and the source of the fourth NMOS transistor N04 based on the first input node of the first XOR gate YH1.

[0091] The source of the twelfth NMOS transistor N12 is grounded.

[0092] The connection node between the gate of the eleventh PMOS transistor P11 and the gate of the eleventh NMOS transistor N11 is the first input node of the third XOR gate YH3, and the connection node between the gate of the twelfth PMOS transistor P12 and the gate of the twelfth NMOS transistor N12 is the first input node of the first XOR gate YH1.

[0093] The internal structures of the first XOR gate YH1, the second XOR gate YH2, and the third XOR gate YH3 are the same.

[0094] For example, the first XOR gate YH1 includes the twelfth PMOS transistor P12, the fifteenth PMOS transistor P15, the sixteenth PMOS transistor P16, the twelfth NMOS transistor N12, the fifteenth NMOS transistor N15, and the sixteenth NMOS transistor N16.

[0095] The source of the twelfth PMOS transistor P12 is connected to the power supply.

[0096] The gate of the twelfth PMOS transistor P12 is connected to the gate of the twelfth NMOS transistor N12, the source of the fifteenth PMOS transistor P15, and the gate of the sixteenth PMOS transistor P16.

[0097] The drain of the twelfth PMOS transistor P12 is connected to the drain of the twelfth NMOS transistor N12, the source of the fifteenth NMOS transistor N15, the gate of the sixteenth NMOS transistor N16, and the source of the fourth PMOS transistor P04, and is used to control the source of the fourth PMOS transistor P04 and the source of the fourth NMOS transistor N04 based on the first input node of the first XOR gate YH1.

[0098] The source of the twelfth NMOS transistor N12 is grounded.

[0099] The gate of the fifteenth PMOS transistor P15 is connected to the gate of the fifteenth NMOS transistor N15, the source of the sixteenth PMOS transistor P16, and the source of the sixteenth NMOS transistor N16.

[0100] The drain of the fifteenth PMOS transistor P15 is connected to the drain of the fifteenth NMOS transistor N15, the drain of the sixteenth PMOS transistor P16, and the drain of the sixteenth NMOS transistor N16.

[0101] The connection node between the gate of the twelfth PMOS transistor P12 and the gate of the twelfth NMOS transistor N12 is the first input node of the first XOR gate YH1; the connection node between the gate of the fifteenth PMOS transistor P15 and the gate of the fifteenth NMOS transistor N15 is the second input node of the first XOR gate YH1; and the connection node between the drain of the sixteenth PMOS transistor P16 and the drain of the sixteenth NMOS transistor N16 is the output node of the first XOR gate YH1.

[0102] For example, the third XOR gate YH3 includes the eleventh PMOS transistor P11, the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, the eleventh NMOS transistor N11, the thirteenth NMOS transistor N13, and the fourteenth NMOS transistor N14.

[0103] The source of the eleventh PMOS transistor P11 is connected to the power supply.

[0104] The gate of the eleventh PMOS transistor P11 is connected to the gate of the eleventh NMOS transistor N11, the source of the thirteenth PMOS transistor P13, and the gate of the fourteenth PMOS transistor P14.

[0105] The drain of the eleventh PMOS transistor P11 is connected to the drain of the eleventh NMOS transistor N11, the source of the thirteenth NMOS transistor N13, the gate of the fourteenth NMOS transistor N14, and the source of the sixth PMOS transistor P06. This connection is used to control the source of the sixth PMOS transistor P06 and the source of the sixth NMOS transistor N06 based on the first input node of the third XOR gate YH3.

[0106] The source of the eleventh NMOS transistor N11 is grounded.

[0107] The gate of the thirteenth PMOS transistor P13 is connected to the gate of the thirteenth NMOS transistor N13, the source of the fourteenth PMOS transistor P14, and the source of the fourteenth NMOS transistor N14.

[0108] The drain of the thirteenth PMOS transistor P13 is connected to the drain of the thirteenth NMOS transistor N13, the drain of the fourteenth PMOS transistor P14, and the drain of the fourteenth NMOS transistor N14.

[0109] The connection node between the gate of the eleventh PMOS transistor P11 and the gate of the eleventh NMOS transistor N11 is the first input node of the third XOR gate YH3; the connection node between the gate of the thirteenth PMOS transistor P13 and the gate of the thirteenth NMOS transistor N13 is the second input node of the third XOR gate YH3; and the connection node between the drain of the fourteenth PMOS transistor P14 and the drain of the fourteenth NMOS transistor N14 is the output node of the third XOR gate YH3.

[0110] The XOR logic of the first XOR gate YH1 and the third XOR gate YH3 is the same as that of the second XOR gate YH2, and will not be described again in this embodiment.

[0111] Preferably, the logical relationship between the data output node, the first carry signal node, and the second carry signal node of the 5-bit adder is as follows:

[0112] ;

[0113] ;

[0114] ;

[0115] In the formula, Indicates the data output node. This indicates the output node of the first XOR gate YH1. This represents the XOR operation. This indicates the connection node between the drain of the second PMOS transistor P02 and the drain of the second NMOS transistor N02. Indicates the fourth data input node. This represents the XOR operation. Indicates the fifth data input node. Indicates the first data input node. Indicates the second data input node. This indicates the input node of the second inverter FX2. Indicates the first carry signal node. This indicates the output node of the third XOR gate YH3. Indicates the third data input node. This indicates the second carry signal node.

[0116] For example, the input data of the first data input node D1 and the fifth data input node D5 are both 1. When input D1=D2=1, the output node N1 of the third XOR gate is 0.

[0117] When the input data of the fourth data input node D4 and the fifth data input node D5 are both 1, the output node N2 of the first XOR gate is 0.

[0118] When the third data input node D3 is 1, the connection node N3 between the drain of the second PMOS transistor and the drain of the second NMOS transistor is also 0, so the data output node S is 1.

[0119] Since the output node N1 of the third XOR gate and the output node N2 of the first XOR gate are both 0, C1=D4=1 and C2=D1=1.

[0120] The carry signal weights of the first carry signal nodes C1 and C2 are both 2. At this time, 2*C1+2*C2+S=5, which is consistent with the result of adding 5 1-bit data signals.

[0121] The present invention also provides an arithmetic operation circuit, which is provided with the above-mentioned 5-bit adder.

[0122] The present invention also provides a computing chip having the above-described arithmetic operation circuit.

[0123] Preferably, the computing chip is an in-memory computing chip, a CPU chip, or a GPU chip.

[0124] In-memory computing chips are a new type of chip that breaks through the traditional von Neumann architecture, deeply integrating storage units and computing units, and performing calculations directly in the storage array, reducing the movement of data between computing and storage.

[0125] CPU chip refers to the core control and general computing core chip of a computer system. It is responsible for executing program instructions and controlling the coordinated operation of various computer components. It is the core of a general-purpose processor.

[0126] GPU chips are dedicated processor chips designed for graphics rendering and high-performance parallel computing chips; they are the core hardware in the field of parallel computing.

[0127] The present invention also provides an electronic device having the aforementioned computing chip.

[0128] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more". The descriptions of terms such as "first", "second", etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features.

[0129] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply that it is independent of or alternative to other embodiments. The various embodiments in this specification are described in a related manner, and similar or identical parts between embodiments can be referred to mutually.

[0130] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A 5-bit adder, characterized in that, Including a first XOR gate, a second XOR gate, a third XOR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The first XOR gate, the second XOR gate, and the third XOR gate have the same internal structure, each including 6 MOS transistors; The first inverter, second inverter, third inverter, fourth inverter, and fifth inverter have the same internal structure, each including two MOSFETs; The output node of the first XOR gate is connected to the first input node of the second XOR gate; The output node of the second XOR gate is connected to the input node of the first inverter; The output node of the third XOR gate is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor, the source of the second PMOS transistor, and the source of the second NMOS transistor. The source of the first PMOS transistor is connected to the output node of the second inverter and the gate of the second PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the second PMOS transistor, the drain of the second NMOS transistor, the source of the third PMOS transistor, the source of the third NMOS transistor, and the second input node of the second XOR gate. The source of the second NMOS transistor is connected to the input node of the second inverter, the source of the fifth PMOS transistor, and the source of the fifth NMOS transistor; The gate of the third PMOS transistor is connected to the gate of the fourth NMOS transistor and is controlled by the first input node of the second XOR gate. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the drain of the fourth PMOS transistor, the drain of the fourth NMOS transistor, and the input node of the third inverter. The gate of the third NMOS transistor is connected to the gate of the fourth PMOS transistor and the first output node of the second XOR gate; The source of the fourth PMOS transistor is connected to the source of the fourth NMOS transistor and is controlled by the first input node of the first XOR gate. The gate of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor and the output node of the fourth inverter, and the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the sixth PMOS transistor, the drain of the sixth NMOS transistor, and the input node of the fifth inverter. The gate of the fifth NMOS transistor is connected to the gate of the sixth PMOS transistor, the output node of the third XOR gate, and the input node of the fourth inverter. The source of the sixth PMOS transistor is connected to the source of the sixth NMOS transistor and is controlled by the first input node of the third XOR gate. Wherein, the first input node of the third XOR gate is the first data input node of the 5-bit adder, the second input node of the third XOR gate is the second data input node of the 5-bit adder, the output node of the second inverter is the third data input node of the 5-bit adder, the first input node of the first XOR gate is the fourth data input node of the 5-bit adder, the second input node of the first XOR gate is the fifth data input node of the 5-bit adder, the output node of the first inverter is the data output node of the 5-bit adder, the output node of the third inverter is the first carry signal node of the 5-bit adder, and the output node of the fifth inverter is the second carry signal node of the 5-bit adder.

2. The 5-bit adder according to claim 1, characterized in that, The second XOR gate includes a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The source of the seventh PMOS transistor is connected to the power supply; The gate of the seventh PMOS transistor is connected to the output node of the first XOR gate, the gate of the seventh NMOS transistor, the source of the eighth PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the third NMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the eighth NMOS transistor, the gate of the ninth NMOS transistor, and the gate of the third PMOS transistor, and is used to control the gate of the third PMOS transistor and the gate of the fourth NMOS transistor based on the first input node of the second XOR gate. The source of the seventh NMOS transistor is grounded; The gate of the eighth PMOS transistor is connected to the gate of the eighth NMOS transistor, the source of the ninth PMOS transistor, the source of the ninth NMOS transistor, and the drain of the first PMOS transistor. The drain of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, the drain of the ninth PMOS transistor, and the drain of the ninth NMOS transistor. Wherein, the connection node between the gate of the seventh PMOS transistor and the gate of the seventh NMOS transistor is the first input node of the second XOR gate, the connection node between the gate of the eighth PMOS transistor and the gate of the eighth NMOS transistor is the second input node of the second XOR gate, and the connection node between the drain of the ninth PMOS transistor and the drain of the ninth NMOS transistor is the output node of the second XOR gate.

3. The 5-bit adder according to claim 2, characterized in that, The second XOR gate is configured as follows: When the first input node of the second XOR gate is set to 1 and the second input node of the second XOR gate is set to 0, the output node of the second XOR gate is 1; When the first input node of the second XOR gate is set to 0 and the second input node of the second XOR gate is set to 1, the output node of the second XOR gate is 1; When the first input node of the second XOR gate is set to 1 and the second input node of the second XOR gate is set to 1, the output node of the second XOR gate is 0; When the first input node of the second XOR gate is set to 0 and the second input node of the second XOR gate is set to 0, the output node of the second XOR gate is 0.

4. The 5-bit adder according to claim 1, characterized in that, The first inverter includes a tenth PMOS transistor and a tenth NMOS transistor; The source of the tenth PMOS transistor is connected to the power supply, the gate of the tenth PMOS transistor is connected to the gate of the tenth NMOS transistor and the output node of the second XOR gate, and the drain of the tenth PMOS transistor is connected to the drain of the tenth NMOS transistor. The source of the tenth NMOS transistor is grounded; The connection node between the gate of the tenth PMOS transistor and the gate of the tenth NMOS transistor is the input node of the first inverter, and the connection node between the drain of the tenth PMOS transistor and the drain of the tenth NMOS transistor is the output node of the first inverter.

5. The 5-bit adder according to claim 1, characterized in that, The third XOR gate includes an eleventh PMOS transistor and an eleventh NMOS transistor, and the first XOR gate includes a twelfth PMOS transistor and a twelfth NMOS transistor; The source of the eleventh PMOS transistor is connected to the power supply, and the gate of the eleventh PMOS transistor is connected to the gate of the eleventh NMOS transistor. The drain of the eleventh PMOS transistor is connected to the drain of the eleventh NMOS transistor and the source of the sixth PMOS transistor, and is used to control the source of the sixth PMOS transistor and the source of the sixth NMOS transistor based on the first input node of the third XOR gate. The source of the eleventh NMOS transistor is grounded; The source of the twelfth PMOS transistor is connected to the power supply, and the gate of the twelfth PMOS transistor is connected to the gate of the twelfth NMOS transistor. The drain of the twelfth PMOS transistor is connected to the drain of the twelfth NMOS transistor and the source of the fourth PMOS transistor, and is used to control the source of the fourth PMOS transistor and the source of the fourth NMOS transistor based on the first input node of the first XOR gate. The source of the twelfth NMOS transistor is grounded; The connection node between the gate of the eleventh PMOS transistor and the gate of the eleventh NMOS transistor is the first input node of the third XOR gate, and the connection node between the gate of the twelfth PMOS transistor and the gate of the twelfth NMOS transistor is the first input node of the first XOR gate.

6. The 5-bit adder according to claim 1, characterized in that, The logical relationship between the data output node, the first carry signal node, and the second carry signal node of the 5-bit adder is as follows: ； ； ； In the formula, Indicates the data output node. Indicates the output node of the first XOR gate. This represents the XOR operation. This indicates the connection node between the drain of the second PMOS transistor and the drain of the second NMOS transistor. Indicates the fourth data input node. This represents the XOR operation. Indicates the fifth data input node. Indicates the first data input node. Indicates the second data input node. This indicates the input node of the second inverter. Indicates the first carry signal node. This indicates the output node of the third XOR gate. Indicates the third data input node. This indicates the second carry signal node.

7. An arithmetic operation circuit, characterized in that, The arithmetic operation circuit is provided with a 5-bit adder as described in any one of claims 1 to 6.

8. A computing chip, characterized in that, The computing chip is provided with the arithmetic operation circuit as described in claim 7.

9. The computing chip according to claim 8, characterized in that, The computing chip is either a memory computing chip, a CPU chip, or a GPU chip.

10. An electronic device, characterized in that, The electronic device is provided with a computing chip as described in any one of claims 8 to 9.

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