Heterogeneous transplantation and parallel optimization method for multiphase flow numerical simulation software

Abstract

The invention discloses a heterogeneous transplantation and parallel optimization method for multiphase flow numerical simulation software, and belongs to the technical field of heterogeneous parallel calculation of computational fluid mechanics. According to the method, cross-language adaptation is realized by establishing a cross-language calling interface, unifying an array storage access mode, adapting a function interface format and reconstructing a core calculation function module; computing deployment is completed through efficient management of a storage space of a device end, directional copying and synchronization of data, optimization and definition of a kernel function, thread scheduling optimization, result return and parallel communication. In combination with a grid management scheme of double-layer boundary expansion, grid data interaction efficiency is optimized; efficient parallel scheduling and expansibility optimization are realized by dividing computational domains, allocating processes, cooperatively dividing tasks and formulating a weak expansibility optimization strategy. Software seamless transplantation and efficient interoperation can be achieved, the single-step iteration throughput rate and the speed-up ratio are improved, the communication transmission bottleneck is relieved, and good expansibility and engineering practicability are achieved.

Description

Technical Field

[0001] This invention relates to a heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software, belonging to the field of heterogeneous parallel computing technology in computational fluid dynamics. Background Technology

[0002] In the fields of shipbuilding and ocean engineering, aerospace engineering, and hydraulic equipment, the geometric design complexity of engineering equipment continues to increase, and the requirements for the accuracy of physical modeling of the flow field characteristics of the equipment are increasing simultaneously. Flow mechanism research is also evolving from macroscopic phenomenon analysis to refined microscopic-scale investigation. Computational fluid dynamics (CFD) technology is making breakthroughs towards higher precision and more complex application scenarios, with an exponential increase in the size of solution meshes and continuous iterative optimization of complex flow simulation models. Traditional CPU-based serial computing schemes or small-scale parallel computing schemes cannot meet the computational efficiency requirements of high-precision CFD simulations; even with the introduction of CPU-accelerator heterogeneous computing platforms, existing technologies still struggle to efficiently support the stable operation of large-scale CFD parallel computing tasks. Therefore, it is urgent to overcome key technological bottlenecks in hardware adaptation, data interaction, and parallel scheduling to unleash the application value of CFD simulations with high-performance computing capabilities and improve the efficiency of engineering equipment R&D and performance optimization.

[0003] MultiPHydro is a domestically developed CFD simulation software that uses the finite difference method to construct a numerical simulation method for cavitation flow physics. It is mainly used for refined numerical simulation of complex multiphase and multifield flows. MultiPHydro's source code is written in Fortran. However, in the porting and application of high-performance heterogeneous parallel computing platforms, the ROCm open computing platform and HIP programming interface, which are relied upon by mainstream DCU accelerators, lack compatibility with Fortran. This means that Fortran code cannot directly call DCU kernel functions for acceleration. Furthermore, cross-language adaptation requires addressing the fundamental differences between Fortran and C languages ​​in array storage methods and function calling conventions, directly hindering the software's migration to heterogeneous platforms and making it difficult to fully utilize hardware computing power. Additionally, the computational logic of the finite difference method requires frequent inter-process interaction of boundary mesh data. In DCU deployment scenarios, the time overhead of data copying and communication operations between the computational data storage and the device is extremely high, directly leading to a significant decrease in the overall computational efficiency of the software. Summary of the Invention

[0004] To address the technical challenges of existing MultiPHydro numerical simulation software, such as difficulties in adapting to heterogeneous platforms, low efficiency of cross-language data interaction, and high data transmission overhead between the host (CPU) and device (DCU) due to the characteristics of the Fortran language, the purpose of this invention is to provide a heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software, enabling efficient and stable operation of complex multiphase and multifield flow numerical simulations on heterogeneous high-performance computing platforms.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] The present invention provides a method for heterogeneous porting and parallel optimization of multiphase flow numerical simulation software, comprising the following steps:

[0007] Step 1: Cross-language adaptation and computation function refactoring;

[0008] The MultiPHydro numerical computation software is written in Fortran, while the heterogeneous computing platform at the DCU mainly relies on C / C++ interfaces. A cross-language migration method based on mixed Fortran and C programming is used to solve compatibility issues and enable efficient calling and reconstruction of core computing modules in a heterogeneous environment. This includes the following sub-steps:

[0009] Step 1.1: Establish a cross-language calling interface;

[0010] In Fortran, external C function interfaces are constructed using the interface statement, and a consistent lowercase naming convention is used to avoid linking errors caused by the compiler automatically adding underscores;

[0011] On the C side, by adding the extern "C" modifier, the calling convention consistency between the two languages ​​is achieved, ensuring the recognizability and linkability of cross-language functions;

[0012] Step 1.2: Standardize array storage and access methods;

[0013] Fortran uses column-major storage, while C uses row-major storage. On the C side, multidimensional arrays are uniformly converted into one-dimensional arrays, and the offset mapping relationship is used to achieve equivalent addressing between the multidimensional array subscripts on the Fortran side and the one-dimensional arrays on the C side, ensuring the consistency and correctness of cross-language data reading and writing.

[0014] Step 1.3, Adapt the function call interface;

[0015] Fortran distinguishes between functions and subroutines, while C only provides function definitions. Based on the return value characteristics, the corresponding interfaces are declared in Fortran as functions or subroutines respectively, and pointer parameter passing is used to achieve compatibility between Fortran's reference-based parameter passing mechanism and C's value-based parameter passing mechanism.

[0016] For cases involving complex data structures, structure definitions with consistent field order and memory size are established simultaneously in both the Fortran and C languages ​​to ensure address consistency and data integrity of structure type parameters during cross-language calls.

[0017] Step 1.4, Modular reconstruction of core computation functions;

[0018] The original Fortran core calculation function was refactored into a C language version in a modular way, in which the loop logic was separated from the main calculation body: the loop control part was retained in the C end, and the specific calculation formula was encapsulated into an independent function module;

[0019] The Fortran side only needs to pass the necessary input data and index information to the C side. On the C side, the computation function is further encapsulated into a kernel function that can be executed on the DCU side through the HIP interface, so as to realize the heterogeneous deployment of the computing core and accelerate the execution.

[0020] Step 2, Deployment and execution of DCU computation functions;

[0021] After completing cross-language adaptation and rewriting the computation functions, the rewritten C language computation functions are ported to the DCU device for execution, enabling efficient parallel operation of the core computation of multiphase flow numerical simulation on a heterogeneous platform. This includes the following sub-processes:

[0022] Step 2.1, Device-side storage space management;

[0023] During the initialization phase, the host prepares the input data and completes preprocessing. The hipMalloc interface allocates corresponding storage space in the DCU's video memory to store the input and intermediate variables required for the calculation. At the same time, hipSetDevice is called to bind the MPI process to the target DCU device one by one to ensure the independence of device resources and the consistency of task allocation in a multi-process environment. After the calculation task is completed, the video memory space is released through the hipFree interface to complete the closed loop of device memory management.

[0024] Step 2.2: Directed data copying and synchronization between the host and the device;

[0025] hipMemcpy is used to implement directional data transfer between the CPU and DCU. Before each round of iteration calculation, the initialized or updated data is copied from the CPU to the DCU's video memory. After the calculation is completed, the calculation results are sent back from the DCU to the CPU's storage space to ensure the consistency of data required for subsequent communication and analysis.

[0026] Step 2.3, kernel function definition and thread scheduling optimization;

[0027] The reconstructed computing entity is encapsulated into a global kernel function executable on the DCU, and the computing logic is further modularized into device functions for reuse and maintenance. The coordinates of the corresponding grid cell are determined according to the thread index parameters (threadIdx, blockIdx, blockDim), and the thread block and grid size are set in combination with the overall grid size to achieve balanced distribution and parallel coverage of computing tasks.

[0028] Preferably, by setting a small-scale local matrix to cache neighborhood cell data inside the kernel function, the frequent access to video memory is reduced, thereby improving the memory access efficiency of the computation and the overall execution performance.

[0029] Step 2.4: Result feedback and parallel communication with MPI;

[0030] After the kernel function on the DCU side completes one iteration of calculation, the result data is sent back to the CPU side through the hipMemcpy interface. The MPI module is responsible for the boundary data synchronization and exchange between processes. After the communication is completed, the updated data is sent back to the DCU side to provide input for the next round of iteration calculation, realizing the cyclic execution of multi-process-multi-device collaborative computing.

[0031] Step 3: Grid expansion and data interaction optimization;

[0032] In parallel computing, the finite difference method requires the DCU to frequently send data back to the CPU to complete boundary updates. The grid management and data interaction optimization method based on double-layer boundary expansion reduces the number of data transmissions between the host and device and the cross-process communication overhead, thus solving the data transmission bottleneck problem.

[0033] Based on the local computing domain corresponding to each computing process, two redundant boundary layers are set along the region boundary direction: the first layer is a regular inter-process communication boundary, used to receive data from adjacent processes and realize the synchronization of boundary conditions; the second layer is a newly added extended boundary layer, used to perform one-time redundant computing at the DCU end to support the continuous updating of local boundary data during multi-step iterative computing.

[0034] The first-layer boundary data is transmitted by adjacent processes during the iterative synchronization phase, while the second-layer extended boundary data is directly generated at the DCU end based on the calculation results of the previous iteration, without the need for additional communication.

[0035] During computation execution, by loading the expanded computation data region at the DCU end at once, the kernel function can cover the computation operations of two boundary units in the same round of execution. By performing redundant computation within the second boundary, the validity of local boundary data is maintained in multiple consecutive iterations.

[0036] Step 4: Parallel scheduling and scalability optimization;

[0037] A method for constructing a CPU-DCU collaborative hybrid parallel architecture based on MPI communication mechanism and weak scalability verification improves computing efficiency and scalability in multi-device environments. This method includes the following sub-steps:

[0038] Step 4.1, computational domain partitioning and process allocation;

[0039] Based on the meshing principle of the finite difference method, the overall computing domain is regularly divided along the Y and Z directions to form multiple independent sub-computing regions. During the initialization phase, an MPI process is allocated to each sub-region, and each MPI process is bound to an independent DCU terminal to realize a distributed parallel computing mode with one-to-one correspondence between processes and devices.

[0040] Step 4.2, CPU-DCU collaborative task division;

[0041] In a hybrid architecture, the CPU primarily undertakes control and management functions, including: computation domain partitioning, MPI process communication scheduling, boundary data synchronization, and output and storage of result data;

[0042] The DCU focuses on the highly parallel execution of the core computing modules and is responsible for the numerical iteration and update of the main physical quantities, including the velocity field, pressure field and volume fraction.

[0043] The CPU and DCU interact via a high-speed PCI-E bus, forming a highly efficient collaborative mechanism between host control and device computing.

[0044] Step 4.3, Weak scalability optimization strategy;

[0045] By employing a weak scalability optimization method, the input file automatically adjusts its grid partitioning and data size based on the number of processes as the parallel scale increases. This ensures that the computational load borne by each process remains approximately consistent with that of a single-card operation. By maintaining a constant computational scale per unit device, the overall system maintains high computational efficiency and communication load even when scaled to a larger scale. This achieves good weak scalability characteristics and a linear performance growth trend, guaranteeing parallel efficiency under multi-process and multi-device conditions.

[0046] Beneficial effects:

[0047] 1. The present invention provides a heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software. By constructing a mixed programming interface of Fortran and C language and adopting array one-dimensionalization and memory mapping consistency, the core computing module can be seamlessly ported and efficiently interoperated between the host and device sides, solving the problems of difficult adaptation of traditional Fortran source code on heterogeneous computing platforms and limited interface calls.

[0048] 2. The present invention provides a heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software. It uses the HIP programming interface to reconstruct the core calculation function into a kernel function. Through multi-threaded scheduling and local caching optimization strategies, it fully releases the parallel computing capabilities of the device and achieves high throughput and significant speedup in the single-step iteration process.

[0049] 3. The present invention provides a heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software. Based on the computational domain optimization method of "double-layer boundary layer expansion", it significantly reduces the number of cross-process communication and data round-trip transmission between the host and device through local redundant calculation without affecting the numerical accuracy, thereby reducing communication and transmission bottlenecks and improving overall computational efficiency.

[0050] 4. The present invention provides a heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software, which constructs a hybrid parallel architecture that coordinates the host and device sides. Combining the MPI communication mechanism and the weakly scalable scheduling strategy, it can maintain excellent parallel efficiency and load balancing characteristics in a multi-node, multi-DCU environment, and has good scalability and engineering applicability. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the boundary layer data parallel optimization method of the heterogeneous porting and parallel optimization method of multiphase flow numerical simulation software according to the present invention;

[0052] Figure 2 The flowchart below shows a method for heterogeneous porting and parallel optimization of multiphase flow numerical simulation software according to the present invention. Detailed Implementation

[0053] To better illustrate the purpose and advantages of the present invention, the invention will be further described below in conjunction with the accompanying drawings and examples.

[0054] Example 1

[0055] This embodiment uses the basic solver module CavHydro BM 1.0 of MultiPHydro, a method for heterogeneous porting and parallel optimization of multiphase flow numerical simulation software, as an application demonstration. For a typical Clark-Y hydrofoil flow field example, the heterogeneous porting and parallel optimization method of multiphase flow numerical simulation software of this invention is applied in the above scenario, such as... Figure 1 As shown, it includes the following steps:

[0056] The computational domain for this example is 6C×C×3C. Boundary conditions are set as velocity inlet and pressure outlet. The hydrofoil surface uses the immersion boundary method, and the top, bottom, left, and right sides are solid wall conditions. In single-card operation, the total grid size is 6,912,000, and the single-step simulation time is 0.1s. In parallel operation with 16 cards, the computational grid expands to 110,592,000, and the total single-step simulation time is 0.38s.

[0057] Step 1: Cross-language adaptation and computation function refactoring;

[0058] The MultiPHydro numerical computation software is written in Fortran, while the heterogeneous computing platform at the DCU mainly relies on C / C++ interfaces. A cross-language migration method based on mixed Fortran and C programming is used to solve compatibility issues and enable efficient calling and reconstruction of core computing modules in a heterogeneous environment. This includes the following sub-steps:

[0059] Step 1.1: Establish a cross-language calling interface;

[0060] In Fortran, external C function interfaces are constructed using the interface statement, and a consistent lowercase naming convention is used to avoid linking errors caused by the compiler automatically adding underscores;

[0061] On the C side, by adding the extern "C" modifier, the calling convention consistency between the two languages ​​is achieved, ensuring the recognizability and linkability of cross-language functions;

[0062] Step 1.2: Standardize array storage and access methods;

[0063] Fortran uses column-major storage, while C uses row-major storage. In C, multidimensional arrays are uniformly converted into one-dimensional arrays, and the offset mapping relationship is used to achieve equivalent addressing between the subscripts of multidimensional arrays in Fortran and one-dimensional arrays in C, ensuring the consistency and correctness of cross-language data reading and writing. The mapping formula is shown in equation (1):

[0064] index = (Y - (Yst - 2)) * X_len + (Z - (Zst - 2)) * Y_len * X_len + X (1)

[0065] Where X, Y, and Z are the coordinate indices of a certain element in the three-dimensional array, Yst and Yed are the start and end indices of the current process in the Y direction, Zst and Zed are the start and end indices of the current process in the Z direction, X_len, Y_len, and Z_len are the array lengths in the X, Y, and Z directions, respectively, and index is the final linear storage address in the one-dimensional array C.

[0066] In the embodiment, in the 480×240×60 grid of the Clark-Y hydrofoil example, the flow field variable information of each grid point is directly located through linear index using the above formula, realizing the accurate correspondence between the Fortran side and the C side data;

[0067] Step 1.3, Adapt the function call interface;

[0068] Fortran distinguishes between functions and subroutines, while C only provides function definitions. Based on the return value characteristics, the corresponding interfaces are declared in Fortran as functions or subroutines respectively, and pointer parameter passing is used to achieve compatibility between Fortran's reference-based parameter passing mechanism and C's value-based parameter passing mechanism.

[0069] For cases involving complex data structures, structure definitions with consistent field order and memory size are established simultaneously in both the Fortran and C languages ​​to ensure address consistency and data integrity of structure type parameters during cross-language calls.

[0070] In this embodiment, all parameters are passed by pointers on the C side. The pressure value p(i,j,k) in Fortran is passed to C and corresponds to float *p. The C function determines the actual memory address through the offset.

[0071] Step 1.4, Modular reconstruction of core computation functions;

[0072] The original Fortran core calculation function was refactored into a C language version in a modular way, in which the loop logic was separated from the main calculation body: the loop control part was retained in the C end, and the specific calculation formula was encapsulated into an independent function module;

[0073] The Fortran side only needs to pass the necessary input data and index information to the C side. On the C side, the computation function is further encapsulated into a kernel function that can be executed on the DCU side through the HIP interface, so as to realize the heterogeneous deployment of the computing core and accelerate the execution.

[0074] In this embodiment, the core computation module Upwind format in Fortran, including the flow terms, pressure solution, and volume fraction transport, is rewritten as a C function module. Taking the Upwind function as an example, Fortran only retains the loop scheduling logic, while the computation kernel is transferred to the C / HIP end function for execution, thereby enabling heterogeneous access to the same flow field data.

[0075] Step 2, Deployment and execution of DCU computation functions;

[0076] After completing cross-language adaptation and rewriting the computation functions, the rewritten C language computation functions are ported to the DCU device for execution, enabling efficient parallel operation of the core computation of multiphase flow numerical simulation on a heterogeneous platform. In this embodiment, the rewritten C language functions are further deployed to the device for execution, specifically including the following sub-processes:

[0077] Step 2.1, Device-side storage space management;

[0078] During the initialization phase, the host prepares the input data and completes preprocessing. The hipMalloc interface allocates corresponding storage space in the DCU's video memory to store the input and intermediate variables required for the calculation. At the same time, hipSetDevice is called to bind the MPI process to the target DCU device one by one to ensure the independence of device resources and the consistency of task allocation in a multi-process environment. After the calculation task is completed, the video memory space is released through the hipFree interface to complete the closed loop of device memory management.

[0079] In this embodiment, the CPU first completes the initial condition preparation and region allocation, and allocates about 1.2 GB of storage space in the DCU's video memory through hipMalloc to store the main variables, including the velocity field, pressure field and volume fraction.

[0080] Step 2.2: Directed data copying and synchronization between the host and the device;

[0081] hipMemcpy is used to implement directional data transfer between the CPU and DCU. Before each round of iteration calculation, the initialized or updated data is copied from the CPU to the DCU's video memory. After the calculation is completed, the calculation results are sent back from the DCU to the CPU's storage space to ensure the consistency of data required for subsequent communication and analysis.

[0082] In this embodiment, the data is uploaded using hipMemcpyHostToDevice and the calculation is performed in the form of a kernel function on the DCU. The kernel function is automatically mapped to the grid cell according to the thread index to realize the single-point physical quantity update.

[0083] Step 2.3, kernel function definition and thread scheduling optimization;

[0084] The reconstructed computing entity is encapsulated into a global kernel function executable on the DCU, and the computing logic is further modularized into device functions for reuse and maintenance. The coordinates of the corresponding grid cell are determined according to the thread index parameters (threadIdx, blockIdx, blockDim), and the thread block and grid size are set in combination with the overall grid size to achieve balanced distribution and parallel coverage of computing tasks.

[0085] In this embodiment, after the calculation is completed, the result is transmitted back to the CPU via hipMemcpyDeviceToHost. The MPI module completes the boundary data synchronization between adjacent processes. In the Y direction, a row of data is transmitted from the upper process, and in the Z direction, a layer of data is transmitted from the right process to ensure that the boundary conditions for the next iteration are correct.

[0086] Step 2.4: Result feedback and parallel communication with MPI;

[0087] After the kernel function on the DCU side completes one iteration of calculation, the result data is sent back to the CPU side through the hipMemcpy interface. The MPI module is responsible for the boundary data synchronization and exchange between processes. After the communication is completed, the updated data is sent back to the DCU side to provide input for the next round of iteration calculation, realizing the cyclic execution of multi-process-multi-device collaborative computing.

[0088] In the embodiments, the test results of the Clark-Y example show that when running a single DCU card, the sub-iteration calculation time is 0.0929s, which is about 38% shorter than the 0.1504s of a 20-core CPU, and the single-step calculation speedup is about 1.62 times.

[0089] Step 3: Grid expansion and data interaction optimization;

[0090] In parallel computing, the finite difference method requires the DCU to frequently send data back to the CPU to complete boundary updates. The grid management and data interaction optimization method based on double-layer boundary expansion reduces the number of data transmissions between the host and device and the cross-process communication overhead, thus solving the data transmission bottleneck problem.

[0091] Based on the local computing domain corresponding to each computing process, two redundant boundary layers are set along the region boundary direction: the first layer is a regular inter-process communication boundary, used to receive data from adjacent processes and realize the synchronization of boundary conditions; the second layer is a newly added extended boundary layer, used to perform one-time redundant computing at the DCU end to support the continuous updating of local boundary data during multi-step iterative computing.

[0092] The first-layer boundary data is transmitted by adjacent processes during the iterative synchronization phase, while the second-layer extended boundary data is directly generated at the DCU end based on the calculation results of the previous iteration, without the need for additional communication.

[0093] During computation execution, by loading the expanded computation data region at the DCU end at once, the kernel function can cover the computation operations of two boundary units in the same round of execution. By performing redundant computation within the second boundary, the validity of local boundary data is maintained in multiple consecutive iterations.

[0094] In the embodiments, such as Figure 2 As shown, the original regions are Yst–Yed and Zst–Zed, and after expansion they are Yst_all–Yed and Zst–Zed_all. The Yst_all–Yst data is transmitted by the process above, and the Zed–Zed_all data is transmitted by the process on the right.

[0095] In actual calculations, the extended calculation region is Yst–1–Yed and Zst–Zed+1, which means redundant calculation of one boundary layer. In a single iteration, the DCU end directly completes the boundary calculation within the extended region, without needing to send back the CPU end for updates at each step.

[0096] Step 4, Parallel scheduling and scalability optimization;

[0097] A method for constructing a CPU-DCU collaborative hybrid parallel architecture based on MPI communication mechanism and weak scalability verification improves computing efficiency and scalability in multi-device environments. This method includes the following sub-steps:

[0098] Step 4.1, computational domain partitioning and process allocation;

[0099] Based on the meshing principle of the finite difference method, the overall computing domain is regularly divided along the Y and Z directions to form multiple independent sub-computing regions. During the initialization phase, an MPI process is allocated to each sub-region, and each MPI process is bound to an independent DCU terminal to realize a distributed parallel computing mode with one-to-one correspondence between processes and devices.

[0100] In the embodiment, in the Clark-Y example, the overall computation domain is divided along the Y and Z directions, and each subdomain corresponds to an MPI process. When there are 4 cards in a single node, npy=2 and npz=2 are set. When there are 8 cards in a dual-node system, npy=4 and npz=2 are set.

[0101] Step 4.2, CPU-DCU collaborative task division;

[0102] In a hybrid architecture, the CPU primarily undertakes control and management functions, including: computation domain partitioning, MPI process communication scheduling, boundary data synchronization, and output and storage of result data;

[0103] The DCU focuses on the highly parallel execution of the core computing modules and is responsible for the numerical iteration and update of the main physical quantities, including the velocity field, pressure field and volume fraction.

[0104] The CPU and DCU interact via a high-speed PCI-E bus, forming a highly efficient collaborative mechanism between host control and device computing.

[0105] Step 4.3, Weak scalability optimization strategy;

[0106] By employing a weak scalability optimization method, as the parallel scale increases, the input file automatically adjusts the grid partitioning and data size according to the number of processes, so that the computational load borne by each process remains approximately consistent with that of a single card. By keeping the computational scale of a unit device constant, the overall system ensures that the computational efficiency and communication load remain at a high level when it is expanded to a larger scale, achieving good weak scalability characteristics and a linear performance growth trend, and guaranteeing parallel efficiency under multi-process and multi-device conditions.

[0107] In the embodiments, the parallel expansion test results of the Clark-Y example show that the single-card iteration time is 0.0929s, the 16-card parallel time is 0.387s, corresponding to a weak expansion parallel efficiency of 23.99%. Although the communication ratio increases, the overall computation time decreases linearly with the parallel scale, proving that the method of the present invention has good heterogeneous scalability.

[0108] The above detailed description further illustrates the purpose, technical solution, and beneficial effects of the invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for heterogeneous porting and parallel optimization of multiphase flow numerical simulation software, characterized in that, By establishing cross-language calling interfaces, unifying array storage and access methods, adapting function calling interfaces, and modularly refactoring core calculation functions, cross-language adaptation and calculation function refactoring are achieved; through device-side storage space management, targeted data copying and synchronization, kernel function definition and thread scheduling optimization, result return and parallel communication, the deployment and execution of calculation functions are achieved. A grid management and data interaction optimization method based on two-layer boundary expansion is used to achieve grid expansion and data interaction optimization. Through computational domain partitioning and process allocation, collaborative task partitioning, and weak scalability optimization strategy, parallel scheduling and scalability optimization are achieved, enabling efficient and stable operation of complex multiphase and multifield flow numerical simulations on heterogeneous high-performance computing platforms.

2. The heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software as described in claim 1, characterized in that, Includes the following steps: Step 1: Cross-language adaptation and computation function refactoring; A cross-language migration method based on mixed Fortran and C programming is used to solve compatibility issues and enable efficient calling and reconstruction of core computing modules in heterogeneous environments. Step 2, Deployment and execution of DCU computation functions; After completing cross-language adaptation and rewriting of computation functions, the rewritten C language computation functions were ported to the DCU device for execution, enabling efficient parallel operation of the core computation of multiphase flow numerical simulation on a heterogeneous platform. Step 3: Grid expansion and data interaction optimization; A grid management and data interaction optimization method based on two-layer boundary expansion reduces the number of data transmissions between the host and device sides and the overhead of cross-process communication. Step 4: Parallel scheduling and scalability optimization; A CPU-DCU collaborative hybrid parallel architecture construction method based on MPI communication mechanism and weak scalability verification improves computing efficiency and scalability in multi-device environments.

3. The heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software as described in claim 2, characterized in that, Step 1, cross-language adaptation and computation function refactoring, includes the following sub-steps: Step 1.1: Establish a cross-language calling interface; In Fortran, external C function interfaces are constructed using the interface statement, and a consistent lowercase naming convention is used to avoid linking errors caused by the compiler automatically adding underscores; On the C side, adding the `extern "C"` modifier ensures consistency in calling conventions between the two languages, guaranteeing the recognizability and linkability of cross-language functions; Step 1.2: Standardize array storage and access methods; Fortran uses column-major storage, while C uses row-major storage. On the C side, multidimensional arrays are uniformly converted into one-dimensional arrays, and the offset mapping relationship is used to achieve equivalent addressing between the multidimensional array subscripts on the Fortran side and the one-dimensional arrays on the C side, ensuring the consistency and correctness of cross-language data reading and writing. Step 1.3, Adapt the function call interface; Fortran distinguishes between functions and subroutines, while C only provides function definitions. Based on the return value characteristics, the corresponding interfaces are declared in Fortran as functions or subroutines respectively, and pointer parameter passing is used to achieve compatibility between Fortran's reference-based parameter passing mechanism and C's value-based parameter passing mechanism. For cases involving complex data structures, structure definitions with consistent field order and memory size are established simultaneously in both the Fortran and C languages ​​to ensure address consistency and data integrity of structure type parameters during cross-language calls. Step 1.4, Modular reconstruction of core computation functions; The original Fortran core calculation function was refactored into a C language version in a modular way, in which the loop logic was separated from the main calculation body: the loop control part was retained in the C end, and the specific calculation formula was encapsulated into an independent function module; The Fortran side only needs to pass the necessary input data and index information to the C side. The C side further encapsulates the computation function into a kernel function that can be executed on the DCU side through the HIP interface, thereby realizing the heterogeneous deployment of the computing core and accelerating execution.

4. The heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software as described in claim 2, characterized in that, Step 2, the deployment and execution of the DCU computation function, includes the following sub-steps: Step 2.1, Device-side storage space management; During the initialization phase, the host prepares the input data and completes preprocessing. The hipMalloc interface allocates corresponding storage space in the DCU's video memory to store the input and intermediate variables required for the calculation. At the same time, hipSetDevice is called to bind the MPI process to the target DCU device one by one to ensure the independence of device resources and the consistency of task allocation in a multi-process environment. After the calculation task is completed, the video memory space is released through the hipFree interface to complete the closed loop of device memory management. Step 2.2: Directed data copying and synchronization between the host and the device; hipMemcpy is used to implement directional data transfer between the CPU and DCU. Before each round of iteration calculation, the initialized or updated data is copied from the CPU to the DCU's video memory. After the calculation is completed, the calculation results are sent back from the DCU to the CPU's storage space to ensure the consistency of data required for subsequent communication and analysis. Step 2.3, kernel function definition and thread scheduling optimization; The reconstructed computing entity is encapsulated into a global kernel function executable on the DCU, and the computing logic is further modularized into device functions for reuse and maintenance. The coordinates of the corresponding grid cell are determined according to the thread index parameters (threadIdx, blockIdx, blockDim), and the thread block and grid size are set in combination with the overall grid size to achieve balanced distribution and parallel coverage of computing tasks. Step 2.4: Result feedback and parallel communication with MPI; After the kernel function on the DCU side completes an iterative calculation, the result data is sent back to the CPU side through the hipMemcpy interface. The MPI module is responsible for the boundary data synchronization and exchange between processes. After the communication is completed, the updated data is sent back to the DCU side to provide input for the next round of iterative calculation, realizing the cyclic execution of multi-process-multi-device collaborative computing.

5. The heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software as described in claim 2, characterized in that, In step 3, grid expansion and data interaction optimization are performed. In parallel computing, the finite difference method requires the DCU to frequently send data back to the CPU to complete boundary updates. The grid management and data interaction optimization method based on double-layer boundary expansion reduces the number of data transmissions between the host and device and the cross-process communication overhead, thus solving the data transmission bottleneck problem. Based on the local computing domain corresponding to each computing process, two redundant boundary layers are set along the region boundary direction: the first layer is a regular inter-process communication boundary, used to receive data from adjacent processes and realize the synchronization of boundary conditions; the second layer is a newly added extended boundary layer, used to perform one-time redundant computing at the DCU end to support the continuous updating of local boundary data during multi-step iterative computing. The first-layer boundary data is transmitted by adjacent processes during the iterative synchronization phase, while the second-layer extended boundary data is directly generated at the DCU end based on the calculation results of the previous iteration, without the need for additional communication. During computation execution, by loading the expanded computation data region at the DCU end at once, the kernel function can cover the computation operations of two boundary units in the same round of execution. By performing redundant computation within the second boundary, the validity of local boundary data is maintained in multiple consecutive iterations.

6. The heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software as described in claim 2, characterized in that, Step 4, parallel scheduling and scalability optimization, includes the following sub-steps: Step 4.1, computational domain partitioning and process allocation; Based on the meshing principle of the finite difference method, the overall computing domain is regularly divided along the Y and Z directions to form multiple independent sub-computing regions. During the initialization phase, an MPI process is allocated to each sub-region, and each MPI process is bound to an independent DCU terminal to realize a distributed parallel computing mode with one-to-one correspondence between processes and devices. Step 4.2, CPU-DCU collaborative task division; In a hybrid architecture, the CPU primarily handles control and management functions. The DCU focuses on the highly parallel execution of the core computing modules and is responsible for the numerical iteration and update of the main physical quantities. The CPU and DCU interact via a high-speed PCI-E bus, forming a highly efficient collaborative mechanism between host control and device computing. Step 4.3, Weak scalability optimization strategy; By employing a weak scalability optimization method, the input file automatically adjusts its grid partitioning and data size based on the number of processes as the parallel scale increases. This ensures that the computational load borne by each process remains approximately consistent with that of a single-card operation. By maintaining a constant computational scale per unit device, the overall system maintains high computational efficiency and communication load even when scaled to a larger scale. This achieves good weak scalability characteristics and a linear performance growth trend, guaranteeing parallel efficiency under multi-process and multi-device conditions.

7. The heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software as described in claim 4, characterized in that, In step 2.3, a small-scale local matrix is ​​set up inside the kernel function to cache neighborhood cell data, thereby reducing frequent access to video memory, improving memory access efficiency and overall execution performance.

8. The heterogeneous porting and parallel optimization method for multiphase flow numerical simulation software as described in claim 6, characterized in that: In step 4.2, the CPU mainly undertakes control and management functions, including: computing domain partitioning, MPI process communication scheduling, boundary data synchronization, and output and storage of result data; The main physical quantities that the DCU is responsible for in numerical iteration and updates include: velocity field, pressure field, and volume fraction.

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