Methods, systems, devices, and media for recording important signal behavior by module bind
By using the module bind method to record important signal behaviors in the soc, the problem that UVM sequence cannot record non-UVM agent commands is solved, and independent, simplified file management and efficient signal monitoring are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JIANGSU XINSHENG INTELLIGENT TECH CO LTD
- Filing Date
- 2026-04-08
- Publication Date
- 2026-06-23
AI Technical Summary
Existing technologies cannot record commands and key signals issued by non-UVM agents in a SoC via UVM sequence, and file management is complex, affecting the efficiency of setting up the verification environment.
The module bind method is used to create a new monitoring module file, set the input port, identify valid operations according to the preset protocol, use intermediate variables to mark the operation status, and bind the module file to the DUT interface to record signal behavior.
It enables signal recording independent of UVM, simplifies file management, improves verification efficiency, and supports the monitoring and recording of critical signals in real SoC environments.
Smart Images
Figure CN121981035B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of verification technology, and particularly relates to a method, system, device and medium for recording important signal behaviors through module bind. BACKGROUND
[0002] In the current verification environment, UVM is widely used as a verification methodology, which provides convenience and a relatively unified verification idea for verification personnel, and reduces the communication cost between verification personnel. The agent of UVM can be used as a master or a slave to send or receive commands and data streams. Verification personnel can record the commands and data streams through a related sequence and save them into a file for verification and design personnel to debug. Meanwhile, verification personnel can also obtain related signals of the DUT through a sequence to perform logical combination and detect the internal behavior.
[0003] The following is a simple example of recording master behavior through UVM sequence in the prior art:
[0004] class example_seq extends uvm_sequence;
[0005] integer file_handle;
[0006] function new();
[0007] super.new();
[0008] / / save the file name
[0009] file_handle = $fopen(“cfg.log”);
[0010] endfunction
[0011] / / take write register as an example
[0012] virtual task cpu_write_reg(input bit[31:0] addr, input bit[31:0]data);
[0013] / / write the address and data written by cpu_write_reg into the file through $fdisplay
[0014] $fdisplay(file_handle, “0x%0h =>‘h%0h, addr, data);
[0015] endtask
[0016] endclass
[0017] However, this debugging method has limitations in SoCs. If the command issuer is the CPU and not the UVM agent, the command cannot be saved through the sequence, and there is no way to detect key signals. Furthermore, the agent requires layer-by-layer instantiation and configuration, making file management cumbersome and adding complexity to the setup of the verification environment. Summary of the Invention
[0018] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, system, device and medium for recording important signal behavior through module bind.
[0019] The objective of this invention is achieved through the following technical solution:
[0020] Firstly, this application discloses a method for recording important signal behaviors through module binding, including:
[0021] Create a new module file for monitoring;
[0022] Configure the input ports of the module file according to all the signals that need to be monitored;
[0023] The signals from the input ports are processed according to a preset protocol to identify the time points corresponding to valid operations in the signals.
[0024] Set at least one intermediate variable. When a valid operation is detected, set the corresponding intermediate variable to the first state. When the detected valid operation is completed, set the corresponding intermediate variable to the second state.
[0025] Create a log file to record relevant information of the identified valid operations;
[0026] Bind the module file with the configured input ports to the specified DUT internal interface, and connect the input ports one by one with the signals to be monitored for recording the monitored signals.
[0027] Based on the first aspect, the preset protocols include the amba ahb protocol and the ddr protocol.
[0028] Based on the first aspect, the effective operation includes a read operation or a write operation.
[0029] Based on the first aspect, the processing of the input port signal according to the preset protocol specifically includes:
[0030] If the default protocol is amba ahb, the system identifies whether the valid operation is a read or write operation based on the hwrite and htrans signals. If it is a write operation, the write operation flag is written to the log file, and the address and data of the write operation are also recorded in the log file. If it is a read operation, the read operation flag is written to the log file, and the data read from the address of the read operation is also recorded in the log file.
[0031] If the default protocol is ddr protocol, then the operations MRS, REF, SRE, SRX, PRE, PRE, RFU, ACT, WR, RD, NOP, DES, PDE, PDX, ZQCL and ZQCS are identified by judging the CKE, CS_n, ACT_n, ADDR, BG, BA and C signals.
[0032] Based on the first aspect, if a write operation is detected, the first intermediate variable of the write operation is set to logic 1, and when the write operation is completed, the first intermediate variable is set to logic 0; if a read operation is detected, the second intermediate variable of the read operation is set to logic 1, and when the read operation is completed, the second intermediate variable is set to 0.
[0033] Based on the first aspect, the values represented by MRS, REF, SRE, SRX, PRE, PREA, RFU, ACT, WR, RD, NOP, DES, PDE, PDX, ZQCL, and ZQCS operations are assigned to a third intermediate variable. When viewing the waveform, the third intermediate variable is directly viewed to intuitively understand the commands issued by the ddr interface.
[0034] Secondly, this application discloses a system for recording important signal behaviors via module binding, and the method for recording important signal behaviors via module binding as described above includes:
[0035] The input port definition module is used to set the input ports of the module file according to the signals to be monitored;
[0036] The identification module is used to identify the time point corresponding to the valid operation in the signal according to a preset protocol;
[0037] An intermediate state management module is used to set at least one intermediate variable, which is set to a first state when a valid operation is detected to begin, and to a second state when a valid operation is detected to end.
[0038] The log triggering module is used to collect relevant information when a valid operation is detected and to send a log recording request.
[0039] The log management module is used to create log files and write relevant information about valid operations into the log files according to the log recording request.
[0040] The binding configuration module is used to bind the module file with the configured input ports to the specified internal interface of the DUT, and connect the input ports to the signals to be monitored one by one for recording the signals to be monitored.
[0041] Thirdly, this application discloses an electronic device, the electronic device comprising:
[0042] Memory, which stores executable instructions;
[0043] A processor that executes the executable instructions in the memory to implement the method described above for recording important signal behaviors via module bind.
[0044] Fourthly, this application discloses a computer storage medium storing a computer program, which is executed by a processor to implement the method described above for recording important signal behavior through module bind.
[0045] The beneficial effects of this invention are:
[0046] 1) This application binds the pre-configured module file for monitoring to the specified DUT internal interface, which can directly capture the key signals to be monitored and the results of multiple signal combinations. At the same time, with the help of the state switching of intermediate variables, the start and end timing of effective operations can be clearly marked in the waveform.
[0047] 2) This application works independently of UVM, adopts an independent design, does not require layer-by-layer instantiation or configuration, greatly reduces the number of related files, and does not affect the reusability of files; thus lowering the threshold for use.
[0048] 3) This application can automatically record the identified valid operations to a separate log file for easy viewing; at the same time, this application can be used in a real SoC environment to monitor CPU commands and improve its verification system.
[0049] 4) This application allows for the reuse of common protocols, simplifying the work of verification personnel; verification personnel only need to adjust the input port according to the target protocol, which significantly improves the efficiency of verification work. Attached Figure Description
[0050] Figure 1This is a flowchart illustrating the method for recording important signal behaviors via module bind according to an embodiment of the present invention. Detailed Implementation
[0051] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0052] This application discloses a method for recording important signal behaviors through module binding. Using the `bind` function in SystemVerilog, a pre-configured module file is bound to a specified DUT interface. This allows the system to operate independently of UVM (Underwriters Modem) while still monitoring commands and data streams issued by the actual master (non-UVM component) and received by the slave (non-UVM component). When monitoring specific combinational logic, the results can be directly displayed, visually represented in waveforms. For example, for variable `c`, the waveform of `c` can be directly viewed, and the times `c` is high can be recorded in a separate file, facilitating debugging. For instance, some CPUs have AHB (Automatic Bootstrap) interfaces; a corresponding module can be written according to the AHB protocol, bound to the CPU, and the AHB commands issued by the CPU can be monitored and recorded in real time. This application operates independently of UVM, eliminating the need for layered instantiation or configuration, significantly reducing the number of associated files without compromising file reusability.
[0053] The technical terms used in this application are explained below:
[0054] UVM (Universal Verification Methodology) was officially released by Accellera in February 2011. UVM almost entirely inherits from OVM while also adopting the register-based solution from VMM. It is a verification methodology based on SystemVerilog and can also be viewed as a library, providing a series of interfaces. UVM can be used to build verification platforms for verifying the correct form of digital logic circuits.
[0055] Agent: A UVM agent consists of a driver, a monitor, and a sequencer. When in use, the entire agent can be invoked directly, eliminating the need to write separate drivers, monitors, and sequencers, greatly simplifying the verification process. In conjunction with an interface, the agent can be connected to a specific interface. By modifying the agent's operating mode (active or passive), it can effectively meet different verification requirements (actively generating stimuli or passively monitoring the interface).
[0056] Debug: Here, debug specifically refers to the process of debugging and analyzing problems during simulation, as well as the reasons for those problems.
[0057] DUT: an abbreviation for device under test, refers to an integrated circuit or electronic component whose performance is measured, analyzed, or verified during the testing process.
[0058] Interface: An interface is an important structure in SystemVerilog. It encapsulates a set of related signals, simplifying the connection between modules and enabling reuse.
[0059] AHB: Advanced High-Performance Bus, supporting 2-level pipelined operation.
[0060] The flowchart of the method is shown below. Figure 1 As shown, it specifically includes:
[0061] Create a new module file for monitoring;
[0062] Configure the input ports of the module file according to all the signals that need to be monitored.
[0063] The signals from the input ports are processed according to a preset protocol to identify the time points corresponding to valid operations in the signals.
[0064] Set at least one intermediate variable. When a valid operation is detected, set the corresponding intermediate variable to the first state. When the detected valid operation is completed, set the corresponding intermediate variable to the second state. This intermediate variable can be viewed visually in the waveform.
[0065] Create a log file to record relevant information of the identified valid operations;
[0066] Bind the module file with the configured input ports to the specified DUT internal interface, and connect the input ports one by one with the signals to be monitored for recording the monitored signals.
[0067] Specifically, the preset protocols include the amba ahb protocol and the ddr protocol. Amba ahb: Advanced Microcontroller Bus Architecture (amba), Advanced High Performance Bus (ahb); Ddr: DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).
[0068] Specifically, the effective operations include read operations or write operations, etc.
[0069] Specifically, the processing of the input port signal according to the preset protocol includes:
[0070] If the default protocol is Amb AHB, the system identifies whether a valid operation is a read or write operation based on the hwrite and htrans signals. If a write operation is identified, the write operation flag is written to the log file, and the address and data of the write operation are also recorded in the log file. If a read operation is identified, the read operation flag is written to the log file, and the data read from the address of the read operation is also recorded in the log file. If the default protocol is DDR, the system identifies MRS, REF, SRE, SRX, PRE, PREA, RFU, ACT, WR, RD, NOP, DES, PDE, PDX, ZQCL, and ZQCS operations by using the CKE, CS_n, ACT_n, ADDR, BG, BA, and C signals. CKE, CS_n, ACT_n, ADDR, BG, and BA are DDR interface signal names; MRS is the mode register configuration; REF is refresh; SRE is self-refresh; SRX is exit self-refresh; PRE is pre-charge a specific part of a specific area; PREA is pre-charge the entire area; RFU is a reserved operation (no actual operation); ACT is activated for a specific part of a specific area; WR is a write operation; RD is a read operation; NOP is no operation (no operation); DES is deselect device; PDE is power-off; PDX is power-off; ZQCL is a long operation for resistor / capacitor calibration; ZQCS is a short operation for resistor / capacitor calibration.
[0071] Specifically, if a write operation is detected, the first intermediate variable for the write operation is set to logic 1, and when the write operation is completed, the first intermediate variable is set to logic 0; if a read operation is detected, the second intermediate variable for the read operation is set to logic 1, and when the read operation is completed, the second intermediate variable is set to 0.
[0072] Specifically, the values represented by MRS, REF, SRE, SRX, PRE, PREA, RFU, ACT, WR, RD, NOP, DES, PDE, PDX, ZQCL, and ZQCS operations are assigned to a third intermediate variable. When viewing the waveform, directly view the third intermediate variable to intuitively understand the commands issued by the ddr interface.
[0073] For example, this application discloses a system for recording important signal behavior through module binding, and the method for recording important signal behavior through module binding as described above includes:
[0074] The input port definition module is used to set the input ports of the module file according to the signals to be monitored;
[0075] The identification module is used to identify the time point corresponding to the valid operation in the signal according to a preset protocol;
[0076] An intermediate state management module is used to set at least one intermediate variable, which is set to a first state when a valid operation is detected to begin, and to a second state when a valid operation is detected to end.
[0077] The log triggering module is used to collect relevant information when a valid operation is detected and to send a log recording request.
[0078] The log management module is used to create log files and write relevant information about valid operations into the log files according to the log recording request.
[0079] The binding configuration module is used to bind the module file with the configured input ports to the specified internal interface of the DUT, and connect the input ports to the signals to be monitored one by one for recording the signals to be monitored.
[0080] For example, this application discloses an electronic device, the electronic device comprising:
[0081] Memory, which stores executable instructions;
[0082] A processor that executes the executable instructions in the memory to implement the method described above.
[0083] For example, this application discloses a computer storage medium storing a computer program that is executed by a processor to implement the method described above.
[0084] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A method for recording important signal behaviors via module bind, characterized in that, include: Create a new module file for monitoring; Configure the input ports of the module file according to all the signals that need to be monitored; The signals from the input ports are processed according to a preset protocol to identify the time points corresponding to valid operations in the signals. Set at least one intermediate variable. When a valid operation is detected, set the corresponding intermediate variable to the first state. When the detected valid operation is completed, set the corresponding intermediate variable to the second state. Create a log file to record relevant information of the identified valid operations; Bind the module file with the input ports configured to the specified DUT internal interface, and connect the input ports one by one with the signals to be monitored for recording the signals to be monitored; The specific processing of the input port signals according to the preset protocol includes: If the default protocol is amba ahb, the system identifies whether the valid operation is a read or write operation based on the hwrite and htrans signals. If it is a write operation, the write operation flag is written to the log file, and the address and data of the write operation are also recorded in the log file. If it is a read operation, the read operation flag is written to the log file, and the data read from the address of the read operation is also recorded in the log file. If the default protocol is ddr protocol, then the MRS, REF, SRE, SRX, PRE, PRE, RFU, ACT, WR, RD, NOP, DES, PDE, PDX, ZQCL and ZQCS operations are identified by judging the CKE, CS_n, ACT_n, ADDR, BG, BA and C signals. If a write operation is detected, the first intermediate variable for the write operation is set to logic 1, and when the write operation is completed, the first intermediate variable is set to logic 0; if a read operation is detected, the second intermediate variable for the read operation is set to logic 1, and when the read operation is completed, the second intermediate variable is set to 0. Assign the values represented by the operations MRS, REF, SRE, SRX, PRE, PREA, RFU, ACT, WR, RD, NOP, DES, PDE, PDX, ZQCL, and ZQCS to the third intermediate variable. When viewing the waveform, directly view the third intermediate variable.
2. The method for recording important signal behavior via module bind according to claim 1, characterized in that, The preset protocols include the amba ahb protocol and the ddr protocol.
3. The method for recording important signal behavior via module bind according to claim 1, characterized in that: The valid operations include read operations or write operations.
4. A system for recording important signal behavior via module binding, employing the method for recording important signal behavior via module binding as described in any one of claims 1-3, characterized in that, include: The input port definition module is used to set the input ports of the module file according to the signals to be monitored; The identification module is used to identify the time point corresponding to the valid operation in the signal according to a preset protocol; An intermediate state management module is used to set at least one intermediate variable, which is set to a first state when a valid operation is detected to begin, and to a second state when a valid operation is detected to end. The log triggering module is used to collect relevant information when a valid operation is detected and to send a log recording request. The log management module is used to create log files and write relevant information about valid operations into the log files according to the log recording request. The binding configuration module is used to bind the module file with the configured input ports to the specified internal interface of the DUT, and connect the input ports to the signals to be monitored one by one for recording the signals to be monitored.
5. An electronic device, characterized in that, The electronic device includes: Memory, which stores executable instructions; A processor that executes the executable instructions in the memory to implement the method of recording important signal behavior by module bind as described in any one of claims 1-3.
6. A computer storage medium, characterized in that, The medium stores a computer program, which is executed by a processor to implement the method for recording important signal behavior by module bind as described in any one of claims 1-3.