Method, tool and program product for optimizing time sequence consistency
By reading the timing database during the routing phase of chip physical design, creating violation path groups, and analyzing and calculating timing differences, timing consistency is optimized, solving the problem of inadequate critical path optimization caused by timing differences, and improving the accuracy and speed of the design process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LOONGSON TECH CORP
- Filing Date
- 2025-12-12
- Publication Date
- 2026-05-05
AI Technical Summary
In the chip physical design process, timing differences can cause the critical path to be hidden in the early stages of the design process, resulting in inadequate optimization and affecting the convergence of timing targets. Existing technologies rely on the experience of designers and are prone to overly strict or loose constraints, leading to resource shortages or increased power consumption.
After the routing phase of the physical design is completed, data is read from the timing database of each phase, violation path groups are created, path adjustment parameters and timing differences are analyzed and calculated, timing consistency is optimized based on the differences, and timing is precisely adjusted by adjusting or proceeding to the next process using the data of the violation path groups.
It improves timing accuracy and consistency, reduces iteration cycles, avoids problems of overly strict or loose constraints, and enhances the automation capabilities of physical design.
Smart Images
Figure CN121981069A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip design, and more specifically, to a method, tool, and computer program product for optimizing timing consistency. Background Technology
[0002] As the physical design difficulty of high-performance chips, especially the timing optimization and convergence difficulty, increases accordingly, the project iteration cycle becomes longer and longer. This requires designers to improve the timing accuracy, consistency and iteration speed of the physical design process.
[0003] However, there are timing discrepancies in the current physical design process, which can cause the chip's true critical path to be hidden and ignored in the early stages of the design process, only to be revealed after routing. This results in inadequate optimization of the critical path and affects the convergence of timing objectives.
[0004] Currently, optimizing timing consistency in the process flow is mainly achieved by tightening constraints on early clock cycles or timing uncertainties. This is often based on the designer's experience, which can easily lead to constraints that are either too strict or too lenient. Overly strict timing constraints introduce too many buffers and other units, causing strain on area and routing resources and exacerbating routing congestion; or they introduce more low-threshold voltage units, significantly increasing chip power consumption. Overly lenient constraints, on the other hand, result in inadequate optimization of the critical path, making it difficult to achieve timing goals. Summary of the Invention
[0005] In view of the above problems, this application proposes a coupling construction method for a distributed fiber optic acoustic sensing system in underground mines that is efficient in construction, reliable in coupling, and has excellent protection, so as to maximize the monitoring performance and service life of the DAS system and overcome the shortcomings of the prior art.
[0006] In a first aspect, embodiments of this application provide a method for optimizing timing consistency, including: After the routing phase of the first physical design is completed, timing data is read from the timing database of each phase. Based on the time-series data, create violation path groups corresponding to each stage; The analysis and calculation yielded the path adjustment parameters for each violated path group at different stages and the temporal differences between each violated path group at different stages.
[0007] Based on the aforementioned timing differences, the target stage is instructed to make adjustments or to proceed to the next process. If the instruction is to proceed to the next process, then proceed to the signing and verification. If the instruction is to adjust the target stage, then set the path adjustment parameters corresponding to the target stage to run before the target stage is implemented, in order to optimize timing consistency.
[0008] Optionally, based on the time-series data, groups of violated paths are created for each stage, including: After the routing phase of the first physical design is completed, the timing data of each phase is grouped according to a preset grouping strategy, and a corresponding violation path group is created for all timing violation paths in the timing data of each phase.
[0009] Optionally, the time series data of each stage are grouped according to a preset grouping strategy, and a corresponding violation path group is created for all time series violation paths in the time series data of each stage, including: In each time series data, all time series violation paths are grouped according to the names of their emit triggers and capture triggers or the names of the module hierarchy they belong to, thus creating a violation path group corresponding to the stage of that time series data.
[0010] Optionally, the module hierarchy name includes: hierarchy names from level 1 to level N; all timing violation paths are grouped according to the names of their emit and capture triggers or the module hierarchy name, including: A violation path group is created by taking the name of the emit trigger in the timing violation path as the starting point of a path group and the name of the capture trigger as the ending point of the path group. This violation path group contains multiple timing violation paths. The path group starts with the module hierarchy name of any emit trigger in the timing violation path as the starting point of a group, and the module hierarchy name of the capture trigger at the same level as the emit trigger is taken as the ending point of the path group. The higher the level of the module hierarchy name, the fewer violation path groups can be created for all timing violation paths, and the more timing violation paths are in each violation path group.
[0011] Optionally, the path adjustment parameters corresponding to each violated path group at different stages and the temporal differences of each violated path group at different stages are analyzed and calculated, including: The violation path group corresponding to the target stage in each stage of the physical design process is defined as the baseline path group. The baseline path group is the violation path group corresponding to the Tth stage in the physical design process, where T is greater than 1. The violation values corresponding to each violation path in the baseline path group are compared and analyzed with the violation values corresponding to the same violation path in the previous violation path group, and the path adjustment parameters and the time series differences of each violation path group in different stages are calculated.
[0012] Optionally, a comparative analysis is performed to calculate the path adjustment parameters and time-series differences for each violated path group at different stages, including: When the baseline path group is the violation path group corresponding to stage T, it contains m violation paths, and the violation values of each of the m violation paths are S1, S2, ..., S... m The violation values of the m violation paths within the violation path group corresponding to the TX stage are P1, P2, ..., P. m Comparative analysis reveals that the temporal differences between the path group in stages TX and T are ΔS1=S1-P1, ΔS2=S2-P2, ..., ΔS m =S m -P m ; The maximum time difference value M is obtained by finding the maximum value among the aforementioned time differences. When there are n violation path groups, there are n maximum time difference values M1, M2, ..., M. n This is used as the path adjustment parameter for the n violation path groups between the TX and T stages; Calculate the n maximum time series differences M1, M2, ..., M n The variance of the time series difference between stage TX and stage T is obtained by calculating the variance of the time series difference. Following the method described above for comparing and analyzing the time series difference variances between stages TX and T, we can perform analysis on any two stages before stage T to obtain all time series difference variances. Compare the variance of all time series differences with a preset time series consistency threshold, and obtain the time series difference status based on the comparison results.
[0013] Optionally, based on the timing differences, the target stage may be instructed to make adjustments or to proceed to the next process, including: If the variance of each time-series difference is less than the preset time-series consistency threshold, then proceed to the next step. If, in any of the timing difference scenarios, the variance of any timing difference is not less than the preset timing consistency threshold, then an adjustment is indicated to the target stage. During the adjustment process, the n maximum timing difference values M1, M2, ..., M corresponding to the timing difference variances not less than the preset timing consistency threshold are used. n .
[0014] Optionally, if an adjustment is indicated to the target stage, the path adjustment parameters corresponding to the target stage are set to run before the implementation of its corresponding stage to optimize timing consistency, including: The n maximum time-series difference values M1, M2, ..., M corresponding to the time-series difference variance that is not less than the preset time-series consistency threshold are... nGiven the variance of the temporal difference between stage TX and stage T, the maximum temporal difference values M1, M2, ..., M n Set to run before the TX phase implementation to optimize timing consistency; Wherein, if the maximum time series difference values M1, M2, ..., M n If the value is negative, then the timing constraints of the n violation path groups in the TX stage are tightened. If the maximum time series difference values are M1, M2, ..., M n If the value is positive, then the timing constraints of the n violation path groups in the TX stage are relaxed.
[0015] Optionally, proceed to the signature verification process, including: After the signature verification is completed, time series data is read from the time series database of the signature verification and violation path group corresponding to the static time series analysis is created; The analysis and calculation yielded the path adjustment parameters for the violation path group during the routing and approval verification phases, as well as the timing differences of the violation path group during these two phases. Based on the timing differences between these two stages, the routing stage is instructed to make adjustments or proceed to the next process; If the instruction is to proceed to the next process, the layout and routing are completed, and the signing and verification are completed. If the instruction is to adjust the routing stage, the path adjustment parameters corresponding to the violation path group in the routing stage and the signing and verification stage are set before the routing stage is implemented and the routing stage is repeated to optimize timing consistency.
[0016] Optionally, when grouping violation paths by the module hierarchy name of the emit trigger and capture trigger in the timing violation path, the higher the level of the module hierarchy name, the more timing violation paths are contained in each violation path group, the fewer violation path groups can be created, and the lower the fineness of the timing consistency optimization. The lower the level of the module hierarchy name, the fewer the timing violation paths contained in each violation path group, the more violation path groups can be created, and the higher the granularity of the timing consistency optimization.
[0017] This application provides an apparatus for optimizing timing consistency, comprising: Multiple interfaces are provided for reading timing data from the timing database of each stage after the routing phase of the first physical design is completed. A creation module is used to create violation path groups for each stage based on the time-series data; The analysis and calculation module is used to analyze and calculate the path adjustment parameters corresponding to each violation path group at different stages and the time series differences of each violation path group at different stages. The instruction module is used to instruct the target stage to make adjustments or to proceed to the next process based on the timing differences. The execution module is used to enter the signature verification process and display the signature verification process if the instruction is to proceed to the next process, and to set the path adjustment parameters corresponding to the target stage before the target stage is implemented if the instruction is to adjust the target stage.
[0018] Optionally, the tool further includes: User interface for receiving user actions / selections, including: The first operation instruction is used to instruct the creation module to create violation path groups corresponding to each stage based on the time series data, and to display the violation path groups corresponding to each stage through the user interface. The second operation instruction is used to instruct the analysis and calculation module to analyze and calculate the path adjustment parameters corresponding to each violation path group at different stages and the temporal differences of each violation path group at different stages, and to display the path adjustment parameters and the temporal differences. The first selection instruction is used to select any two stages, instructing the analysis and calculation module to analyze and calculate the path adjustment parameters corresponding to each violation path group in these two stages and the timing differences of each violation path group in these two stages, and to display the path adjustment parameters and the timing differences. The second selection instruction is used to select the instruction module to perform a target operation, which includes: instructing the target stage to make adjustments or instructing to proceed to the next process; the third operation instruction is used to instruct the execution module to perform the target operation, wherein, if the target operation is to instruct to proceed to the next process, the signing and verification process is entered and displayed; if the target operation is to instruct the target stage to make adjustments, the path adjustment parameters corresponding to the target stage are set to run before the implementation of the target stage, and the data of the path adjustment parameters corresponding to the target stage is displayed.
[0019] This application provides a computer-readable storage medium storing a computer program that causes a processor to perform the method for optimizing timing consistency as described in any of the preceding claims.
[0020] This application provides a computer program product, including a computer program / instruction, characterized in that, when the computer program / instruction is executed by a processor, it implements the method for optimizing timing consistency as described above.
[0021] The proposed method for optimizing timing consistency involves, after the initial physical design routing phase, first reading timing data from the timing database of each phase; then creating violation path groups for each phase based on the timing data; subsequently analyzing and calculating the path adjustment parameters for each violation path group at different phases and the timing differences between each violation path group at different phases; then, instructing the target phase to make adjustments or instructing it to proceed to the next process based on the timing differences; finally, if instructing it to proceed to the next process, it enters the approval and verification stage; if instructing the target phase to make adjustments, the path adjustment parameters corresponding to the target phase are set and run before the target phase is implemented to optimize timing consistency.
[0022] This application creatively proposes a novel method for optimizing timing in the physical design process, providing improved timing accuracy, consistency, and iteration speed. It utilizes data from all violation paths to create precise violation path groups, and compares and analyzes the timing differences of each violation path group at different physical design stages. Then, it calculates the corresponding path adjustment parameters for each violation path group at different physical design stages and returns them to the process iteration, improving timing consistency and critical path accuracy at each physical design stage. This eliminates the need for judgment based on designer experience and avoids overly strict or slack constraints. It significantly accelerates the iteration speed and timing convergence speed of physical design, enhances the automation capability of the physical design process, and has broad application prospects and high practicality. Attached Figure Description
[0023] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart of a method for optimizing timing consistency according to an embodiment of this application; Figure 2 This is a flowchart illustrating the various stages of physical design, exemplified in the embodiments of this application, including synthesis, placement, clock tree generation, routing, and approval. Figure 3 This is a block diagram of an apparatus for optimizing timing consistency according to an embodiment of this application. Detailed Implementation
[0024] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0025] The inventors discovered that with the continuous development of advanced processes, the scale of digital integrated circuit chips is gradually increasing, and the performance requirements for chips are also gradually increasing. The physical design difficulty, especially the timing optimization and convergence difficulty, of high-performance chips such as central processing units (CPUs), graphics processing units (GPUs), and artificial intelligence processors (APUs / NPUs) is correspondingly increasing, and the project iteration cycle is becoming longer and longer. This requires designers to improve the timing accuracy, consistency, and iteration speed of the physical design process.
[0026] The main reasons for the differences in physical design timing are as follows: 1) The large size and high complexity of chips, along with the large number of timing paths, result in long running times for electronic design automation (EDA) tools, uneven resource allocation, and insufficient optimization of secondary critical paths.
[0027] 2) Advanced processes increase line delays, and EDA tools are inaccurate in their initial line delay estimates during the design phase. Furthermore, the proportion of line delay varies across different paths; paths with longer physical distances have greater line delays, while paths with more logic levels but shorter bus lengths have less impact from line delays. This results in different timing differences between different paths before and after the process.
[0028] 3) After generating the real clock tree, the path timing will also differ from the previous ideal clock stage due to the influence of clock deviation.
[0029] 4) Fixing hold-time timing violations will add more buffer units, leading to increased unit density in local areas, exacerbating wiring congestion, and further affecting timing differences on line delay.
[0030] The aforementioned timing differences can cause the chip's true critical path to be hidden and ignored in the early stages of the design process, only to be revealed after routing. This results in inadequate optimization of the critical path and affects the convergence of timing objectives.
[0031] Further research by the inventors revealed that current optimization processes primarily achieve timing consistency by tightening constraints on early clock cycles or timing uncertainties. This is often based on the designer's experience, which can easily lead to constraints that are either too strict or too lenient. Overly strict timing constraints introduce excessive buffers and other units, causing strain on area and routing resources and exacerbating wiring congestion; or they introduce more low-threshold voltage units, significantly increasing chip power consumption. Conversely, overly lenient constraints result in inadequate optimization of the critical path, making it difficult to achieve timing targets.
[0032] To address the aforementioned problems, the inventors, through extensive research, have creatively proposed the method, apparatus, computer-readable storage medium, computer program product, and chip for optimizing timing consistency, as described in this application. The technical solution of this application is explained and illustrated in detail below.
[0033] This application provides a method for optimizing timing consistency, referring to... Figure 1 The flowchart shown includes the following methods: Step 101: After the routing phase of the first physical design is completed, read the timing data from the timing database of each phase.
[0034] The known stages in chip physical design include synthesis, placement, clock tree generation, routing, sign-off, and layout. At each stage, timing violation path data can be saved, forming a timing database for each stage. However, when using the timing consistency optimization method of this application, timing data needs to be read from the timing databases of each stage after the routing stage of the first physical design is completed.
[0035] In one embodiment of this application, a preferred method for reading timing data from timing databases at various stages of the physical design process includes: firstly, performing chip physical design according to conventional design principles, i.e., completing the routing stage of the first physical design; during the chip physical design process, saving all timing violation path data at each stage of the chip physical design to obtain the initial layout and routing results and timing databases at each stage.
[0036] In other words, the chip is first designed according to conventional physical design principles to obtain an initial chip with completed wiring. At this point, the chip has not yet been approved. Each stage before the approval stage has its own corresponding timing database, which is then available.
[0037] Step 102: Create violation path groups for each stage based on time series data.
[0038] Once the timing data for each stage of the physical design process is obtained, violation path groups corresponding to each stage can be created based on the timing data. For example: violation path groups for the synthesis stage, violation path groups for the placement stage, violation path groups for the clock tree generation stage, violation path groups for the routing stage, and so on.
[0039] In one embodiment of this application, a preferred method for creating violation path groups corresponding to each stage includes: after the routing stage of the first physical design is completed, grouping the timing data of each stage according to a preset grouping strategy, and creating a corresponding violation path group for all timing violation paths in the timing data of each stage. For example: creating a corresponding violation path group for all timing violation paths in the timing data of the synthesis stage according to the preset grouping strategy, creating a corresponding violation path group for all timing violation paths in the timing data of the placement stage according to the preset grouping strategy, creating a corresponding violation path group for all timing violation paths in the timing data of the clock tree generation stage according to the preset grouping strategy, creating a corresponding violation path group for all timing violation paths in the timing data of the routing stage according to the preset grouping strategy, and so on.
[0040] The preferred preset grouping strategy is to group by the names of the emit and capture triggers or the names of their respective module hierarchies. That is, within each time series data, all timing violation paths are grouped according to the names of their emit and capture triggers or the names of their respective module hierarchies, creating violation path groups for the corresponding stage of that time series data. Of course, other grouping strategies can also be used, as long as the grouping of violation paths is achieved.
[0041] Generally, the module hierarchy name includes levels 1 to N; therefore, the method for grouping all timing violation paths according to the names of their emit and capture triggers or the module hierarchy name includes: A violation path group is created by using the name of the emit trigger in a timing violation path as the starting point of the path group and the name of the capture trigger as the ending point of the path group. This violation path group contains multiple timing violation paths. For example, if the emit trigger name of a timing violation path is top / moduleA / moduleB / regC* and the capture trigger name is top / moduleX / moduleY / regZ* (* means omitted characters), then grouping by the names of the emit and capture triggers would result in a violation path group starting with regC* and ending with regZ*.
[0042] By using the module hierarchy name of any emit trigger in a timing violation path as the starting point of a path group, and the capture trigger at the same level as the emit trigger as the ending point of that path group, multiple violation path groups can be created. Each violation path group contains multiple timing violation paths. The higher the level of the module hierarchy name, the fewer violation path groups can be created, and the more timing violation paths are within each violation path group. Continuing with the previous example: for grouping by level 1 hierarchy name (N=1), the violation path group starts with all triggers in module B and ends with all triggers in module Y; for grouping by level 2 hierarchy name (N=2), the violation path group starts with all triggers in module A and ends with all triggers in module X.
[0043] As can be seen from the grouping examples above: the grouping method with the starting point of violation path group regC* and the ending point of violation path group regZ* contains the fewest timing violation paths, thus it has the highest granularity of timing constraints and the highest granularity of timing consistency optimization. On the other hand, the grouping method with the starting point of violation path group all triggers of moduleA and the ending point of violation path group all triggers of moduleX contains the most timing violation paths, thus it has the lowest granularity of timing constraints and the lowest granularity of timing consistency optimization. Naturally, it can be understood that the grouping method with the starting point of violation path group all triggers of moduleB and the ending point of violation path group all triggers of moduleY contains more timing violation paths than the former but less than the latter, falling in the middle. Therefore, its granularity of timing constraints is also lower than the former but higher than the latter, and its granularity of timing consistency optimization is also lower than the former but higher than the latter. This approach ensures that timing consistency optimization has a high degree of fine-grainedness, down to each specific trigger. Furthermore, the fine-grainedness can be adjusted by modifying the violation path grouping strategy. The degree of adjustment depends on whether the designer prioritizes performance or efficiency. If performance is prioritized, a high-fine-grained grouping method is chosen; if efficiency is prioritized, a low-fine-grained grouping method is chosen.
[0044] Step 103: Analyze and calculate the path adjustment parameters corresponding to each path violation group at different stages and the temporal differences of each path violation group at different stages.
[0045] After the violation path groups are grouped, the path adjustment parameters corresponding to each violation path group at different stages and the temporal differences of each violation path group at different stages are analyzed and calculated.
[0046] In one embodiment of this application, a preferred analysis and calculation method includes: firstly, defining the violation path group corresponding to the target stage in each stage of the physical design process as the baseline path group. The baseline path group is the violation path group corresponding to stage T in the physical design process, where T is greater than 1; that is, the violation path group corresponding to any stage other than the first stage can be used as the baseline path group. For example, taking the aforementioned synthesis, placement, clock tree generation, and routing as examples, except for the synthesis stage, the violation path group corresponding to the placement stage can be used as the baseline path group, or the violation path group corresponding to the clock tree generation stage can be used as the baseline path group, or the violation path group corresponding to the routing stage can be used as the baseline path group. Of course, according to the current physical design process, the timing of the placement and routing stages is relatively more important and complex, so the preferred choice is to use the violation path group corresponding to the routing stage as the baseline path group.
[0047] After determining the baseline path group, the violation values of each violation path within the baseline path group are compared and analyzed with the violation values of the same violation paths within the violation path groups of each previous stage. This analysis yields the path adjustment parameters and timing differences for each violation path group at different stages. For example, if the violation path group corresponding to the routing stage is used as the baseline path group, then the violation values of each violation path within the routing stage violation path group are compared and analyzed with the violation values of the same violation paths within the synthesis stage violation path group, the placement stage violation path group, and the clock tree generation stage violation path group, respectively. Other cases follow the same principle and will not be elaborated further.
[0048] Of course, considering efficiency, a better option is to compare and calculate the violation values of each violation path in the violation path group during the routing phase with the violation values of the same violation paths in the violation path group during the placement phase, and then compare and calculate the violation values of the same violation paths in the violation path group during the clock tree generation phase with the violation values of the same violation paths in the violation path group during the synthesis phase. Performing two analyses and calculations in total will yield path adjustment parameters and timing differences with good accuracy. However, for the highest accuracy, it is best to perform all comparative analyses and calculations.
[0049] In one embodiment of this application, a preferred method for comparative analysis to calculate the path adjustment parameters and timing differences of each violated path group at different stages includes: When the baseline path group is the violation path group corresponding to stage T, it contains m violation paths, and the violation values of each of the m violation paths are S1, S2, ..., S... mThe violation values of the m violation paths within the violation path group corresponding to the TX stage are P1, P2, ..., P. m Comparative analysis reveals that the temporal differences between the path group in stages TX and T are ΔS1=S1-P1, ΔS2=S2-P2, ..., ΔS m =S m -P m For example, taking stage T as the routing stage and stage TX as the placement stage: the violation path group corresponding to the routing stage contains m violation paths, and the violation values of each of the m violation paths are S1, S2, ..., S. m In the layout phase, the violation values of each of the m violation paths within the violation path group are P1, P2, ..., P. m Then, by comparative analysis, the timing difference between the placement and routing phases of the violated path group is found to be ΔS1=S1-P1, ΔS2=S2-P2, ..., ΔS m =S m -P m .
[0050] The maximum time series difference (M) is obtained by finding the maximum value among the time series differences, which is the value within ΔS1~ΔS. m The value with the largest value is selected as the maximum time difference value M. When there are n violation path groups, there are n maximum time difference values M1, M2, ..., Mn. n This is used as the path adjustment parameter for the n violation path groups between the TX and T stages.
[0051] Then calculate the n maximum time series differences M1, M2, ..., M n The variance of the time series difference is obtained between stage TX and stage T. Following the method of comparing and analyzing the time series difference between stage TX and stage T and calculating the time series difference variance, the analysis technique is applied to any two stages before stage T to obtain all time series difference variances. Finally, all time series difference variances are compared with a preset time series consistency threshold (which affects the physical design quality and iteration cycle). That is, each time series difference variance is compared with the preset time series consistency threshold, and the time series difference situation is obtained based on the comparison results.
[0052] Step 104: Based on the timing differences, indicate to the target stage to make adjustments or indicate to proceed to the next process.
[0053] After obtaining the path adjustment parameters and timing differences for each violation path group at different stages through steps 101 to 103, it is necessary to determine whether to use the path adjustment parameters for each violation path group at different stages based on the timing differences.
[0054] In one embodiment of this application, a preferred method for obtaining timing difference status based on comparison results includes: if the variance of each timing difference is less than a preset timing consistency threshold, then the initial layout and routing result is considered to meet timing consistency requirements, and no timing consistency optimization is needed, and then the process is instructed to proceed to the next step.
[0055] If any timing difference variance is not less than a preset timing consistency threshold, it indicates that there are timing consistency issues in the initial placement and routing results, requiring timing consistency optimization. In this case, an adjustment is indicated to the target stage. During the adjustment process, the n maximum timing difference values M1, M2, ..., Mn corresponding to timing difference variances not less than the preset timing consistency threshold are used. n For example, if the timing difference variance between the placement and routing phases is not less than a preset timing consistency threshold, then the n maximum timing difference values M1, M2, ..., Mn corresponding to the placement and routing phases are used. n .
[0056] Step 105: If the instruction is to proceed to the next process, proceed to the signing and verification. If the instruction is to adjust the target stage, set the path adjustment parameters corresponding to the target stage to run before the target stage is implemented in order to optimize timing consistency.
[0057] For situations where adjustments are required to align with the target phase: The path adjustment parameters need to be set to run before the target phase implementation to optimize timing consistency. Specifically, this includes: The n maximum time difference values M1, M2, ..., M corresponding to the time difference variance that is not less than a preset time consistency threshold are... n Given the variance of the temporal difference between stage TX and stage T, the maximum temporal difference values M1, M2, ..., M n This is set to run before the TX phase to optimize timing consistency; among these, if the maximum timing difference values are M1, M2, ..., M... n If the value is negative, then the timing constraints of the nth path violation group in the TX stage are tightened; if the maximum timing difference value is M1, M2, ..., M n If the value is positive, then the timing constraints of the nth violation path group in the TX stage are relaxed. For example, if the timing difference variance between the placement and routing stages is not less than a preset timing consistency threshold, then the maximum timing difference values M1, M2, ..., M between the placement and routing stages are set to... n Set to run before the layout phase to optimize timing consistency.
[0058] If the instruction is to proceed to the next step: then you can directly enter the approval and verification stage (approval stage), which specifically includes: After the signature verification is completed, time series data is read from the time series database of the signature verification and violation path group corresponding to the static time series analysis is created; The analysis and calculation yield the path adjustment parameters corresponding to the violation path group in the routing and approval / verification phases, as well as the timing differences of the violation path group in these two phases. Based on the timing differences in these two phases, the routing phase is instructed to make adjustments or to proceed to the next process. If the next process is instructed, the layout and routing are completed, and the approval / verification is completed. If the routing phase is instructed to make adjustments, the path adjustment parameters corresponding to the violation path group in the routing and approval / verification phases are set and run before the routing phase is implemented, and the routing phase is repeated to optimize timing consistency.
[0059] That is, in the approval and verification stage, the same timing consistency optimization method described in steps 101 to 105 above is used to optimize the timing consistency of the routing stage, which is the last stage before the approval and verification stage. Based on the timing differences, it is determined whether to directly enter the approval and verification stage if the timing consistency is satisfied, or to set the path adjustment parameters corresponding to the violation path group in the routing stage and the approval and verification stage before the routing stage is implemented and repeat the routing stage to optimize timing consistency and finally complete the timing consistency optimization.
[0060] The entire process described above is referred to Figure 2 The flowchart shown, which takes synthesis, placement, clock tree generation, routing, and approval as examples of the physical design stages, can be summarized as follows: First, the initial placement and routing results are obtained through the design file, as well as the timing databases for each stage of synthesis, placement, clock tree generation, routing, and approval, which include at least all emit triggers, capture triggers, and violation values for establishing time violation paths.
[0061] Using all setup time violation path data after the routing phase as the baseline data, and based on the optional grouping strategy, namely the names of the emit triggers and capture triggers and the names of the module hierarchy, the timing violation paths in the baseline data are grouped using the path grouping command of EDA or other tools.
[0062] By setting different name matching strategies, the granularity of path grouping can be controlled. For example, if the name of an emitter trigger that violates a path is top / moduleA / moduleB / regC*, and the name of a capture trigger is top / moduleX / moduleY / regZ* (* means omitted characters), the path can be grouped according to the trigger name, so the starting point of this violation path group is regC*, and the ending point is regZ*. Alternatively, it can be grouped according to the first-level name, so the starting point of this violation path group is all triggers in moduleB, and the ending point is all triggers in moduleY. Similarly, it can be grouped according to the second-level name, so the starting point of this violation path group is all triggers in moduleA, and the ending point is all triggers in moduleX. Correspondingly, the number of paths included in the group gradually increases, and the granularity gradually decreases.
[0063] Consistency analysis involves analyzing and calculating the violation values of the baseline violation path group and the violation path groups in previous stages. Taking a violation path group in the layout stage as an example, the number of paths in the group is m, and the violation values are S1, S2, ..., S... m Find the violation values P1, P2, ..., P during the routing phase. m Then the timing difference between the placement and routing phases for this violated path group is ΔS1=S1-P1, ΔS2=S2-P2, ..., ΔS m =S m -P m The maximum time difference value M is obtained by finding the maximum value of the path. If there are n path groups, then there are n maximum time difference values M1, M2, ..., Mn. n Find the maximum temporal difference values M1~M for all n path groups. n S was obtained by calculating the variance. 2 This refers to the timing difference variance at this stage, which is the timing difference variance S of all stages before routing. 2 x If all stages are less than the preset timing consistency threshold θ, the timing consistency requirement is met, and the process proceeds to the signature verification stage; otherwise, the timing consistency requirement is not met, the path adjustment parameters required for each violated path group are calculated, and the process is returned to the design flow iterative optimization.
[0064] The path adjustment parameters are the maximum timing difference values of each violation path group between the current stage and the routing stage, i.e., M1~M mentioned earlier. n It is important to note that the path adjustment parameter can be positive or negative. If M is negative, it means that the violation value of the path group in this stage is less than that in the routing stage, i.e., the constraint of the path group is too loose in this stage and needs to be tightened. Positive values are the opposite of the above.
[0065] Route adjustments can be executed using a route adjustment program. The generated route adjustment program can include violations of route grouping operations and route adjustment parameter setting operations. That is, the results of the above-mentioned violations of route grouping and calculation of violations of route adjustment parameters are used to generate the route adjustment program, which is set to run before each stage of implementation.
[0066] Finally, in the verification stage, the timing consistency optimization mentioned above can be performed on the results obtained in the routing stage and the static timing analysis results. The principle is the same: the static timing analysis results are grouped into violation paths, and timing consistency analysis is performed on the violation path groups corresponding to the routing stage to obtain the timing differences of the groups and path adjustment parameters. Then, a path adjustment program is generated and brought into the running settings before the routing stage to achieve the goal of optimizing timing consistency. Finally, it enters the layout and completes the physical design of the chip.
[0067] Based on the above-described method for optimizing timing consistency, this application also proposes a tool for optimizing timing consistency, as described above. Figure 3 The illustrated device block diagram includes: Multiple interfaces 310 are used to read timing data from the timing database of each stage after the routing phase of the first physical design is completed. The aforementioned tool for optimizing timing consistency can be a set of tools specifically designed for optimizing timing consistency. It can interact with the EDA tool through multiple interfaces to obtain timing data from the timing database of each stage from the EDA tool. Alternatively, the EDA tool can be used directly as the tool for optimizing timing consistency, which is relatively cheaper.
[0068] A creation module 320 is used to create violation path groups corresponding to each stage based on the time series data; The analysis and calculation module 330 is used to analyze and calculate the path adjustment parameters corresponding to each violation path group at different stages and the time series differences of each violation path group at different stages. Instruction module 340 is used to instruct the target stage to make adjustments or to proceed to the next process based on the timing differences. The execution module 350 is used to enter the signing and verification process and display the signing and verification process if the instruction is to proceed to the next process, and to set the path adjustment parameters corresponding to the target stage before the target stage is implemented if the instruction is to adjust the target stage.
[0069] Optionally, the tool for optimizing timing consistency also includes: User interface for receiving user actions / selections, including: The first operation instruction is used to instruct the creation module to create violation path groups corresponding to each stage based on the time series data, and to display the violation path groups corresponding to each stage through the user interface. The second operation instruction is used to instruct the analysis and calculation module to analyze and calculate the path adjustment parameters corresponding to each violation path group at different stages and the temporal differences of each violation path group at different stages, and to display the path adjustment parameters and the temporal differences. The first selection instruction is used to select any two stages, instructing the analysis and calculation module to analyze and calculate the path adjustment parameters corresponding to each violation path group in these two stages and the timing differences of each violation path group in these two stages, and to display the path adjustment parameters and the timing differences. The second selection instruction is used to select the instruction module to perform a target operation, which includes: instructing the target stage to make adjustments or instructing to proceed to the next process; the third operation instruction is used to instruct the execution module to perform the target operation, wherein, if the target operation is to instruct to proceed to the next process, the signing and verification process is entered and displayed; if the target operation is to instruct the target stage to make adjustments, the path adjustment parameters corresponding to the target stage are set to run before the implementation of the target stage, and the data of the path adjustment parameters corresponding to the target stage is displayed.
[0070] Optionally, creating module 320 includes: The group creation submodule is used to create a corresponding violation path group for all time-series violation paths in each time-series data according to a preset grouping strategy in the time-series data of each stage; Among them, when grouping violation paths by the module hierarchy name of the emit trigger and capture trigger in the timing violation path, the higher the level of the module hierarchy name, the more timing violation paths are contained in each violation path group, the fewer violation path groups can be created, and the lower the fineness of the timing consistency optimization. The lower the level of the module hierarchy name, the fewer the timing violation paths contained in each violation path group, the more violation path groups can be created, and the higher the granularity of the timing consistency optimization.
[0071] Optionally, the group creation submodule is specifically used for: Within each time series data set, all timing violation paths are grouped according to the names of their emit and capture triggers or the name of their respective module hierarchy, creating a violation path group for the corresponding stage of that time series data set. The name of the respective module hierarchy includes: level 1 to level N hierarchy names; specifically: A violation path group is created by taking the name of the emit trigger in the timing violation path as the starting point of a path group and the name of the capture trigger as the ending point of the path group. This violation path group contains multiple timing violation paths. Using the module hierarchy name of any emit trigger in a timing violation path as the starting point of a path group, and the capture trigger at the same level as the module hierarchy name of that emit trigger as the ending point of the path group, multiple violation path groups can be created. Each violation path group contains multiple timing violation paths. The higher the level of the module hierarchy name, the fewer violation path groups can be created for all timing violation paths, and the more timing violation paths are in each violation path group.
[0072] Optionally, the analysis and calculation module 330 includes: Define a submodule to define the violation path group corresponding to the target stage in each stage of the physical design process as the baseline path group. The baseline path group is the violation path group corresponding to the Tth stage in the physical design process, where T is greater than 1. The analysis and calculation submodule is used to compare and analyze the violation value corresponding to each violation path in the baseline path group with the violation value corresponding to the same violation path in the previous violation path group, and calculate the path adjustment parameters and the timing difference of each violation path group in different stages.
[0073] Optionally, the analysis and calculation submodule is specifically used for: When the baseline path group is the violation path group corresponding to stage T, it contains m violation paths, and the violation values of each of the m violation paths are S1, S2, ..., S... m The violation values of the m violation paths within the violation path group corresponding to the TX stage are P1, P2, ..., P. m Comparative analysis reveals that the temporal differences between the path group in stages TX and T are ΔS1=S1-P1, ΔS2=S2-P2, ..., ΔS m =S m -P m ; The maximum time difference value M is obtained by finding the maximum value among the time differences. When there are n violation path groups, there are n maximum time difference values M1, M2, ..., M. n This is used as the path adjustment parameter for the n violation path groups between the TX and T stages; For the n maximum time series difference values M1, M2, ..., M n The variance was calculated to obtain the time series difference variance between stage TX and stage T. For any two stages before stage T, a comparative analysis is performed between stages TX and T as described above, and the variances of all time series differences are calculated. The variances of all time series differences are compared with a preset time series consistency threshold, and the time series difference status is obtained based on the comparison results; wherein, obtaining the time series difference status based on the comparison results includes: If the variance of each of the time-series differences is less than the preset time-series consistency threshold, then the time-series difference situation is that the path adjustment parameters corresponding to each violated path group at different stages are not used; If any time series variance is not less than the preset time series consistency threshold, then the time series variance situation is to use the n maximum time series variance values M1, M2, ..., M corresponding to the time series variance that is not less than the preset time series consistency threshold. n .
[0074] Optionally, the execution module 350 includes: The submodule is configured to set up n maximum time-series difference values M1, M2, ..., Mn corresponding to time-series difference variances that are not less than the preset time-series consistency threshold. n Let M1, M2, ..., M be the variance of the temporal difference between stage TX and stage T. Then, the maximum temporal difference values M1, M2, ..., M... n Set to run before the TX phase implementation to optimize timing consistency; Wherein, if the maximum time series difference values M1, M2, ..., M n If the value is negative, then the timing constraints of the n violation path groups in the TX stage are tightened. If the maximum time series difference values are M1, M2, ..., M n If the value is positive, then the timing constraints of the n violation path groups in the TX stage are relaxed.
[0075] Optionally, the execution module 350 may further include: Create a submodule to read time series data from the time series database of the signing and verification process after the signing and verification is completed, and create the violation path group corresponding to the static time series analysis. The signing-off submodule is used to analyze and calculate the path adjustment parameters corresponding to the violation path group in the routing phase and the signing-off verification phase, as well as the timing differences of the violation path group in these two phases. The approval submodule is used to determine whether to adjust the wiring stage or indicate to proceed to the next process based on the timing differences between the two stages. The approval execution submodule is used to indicate that the layout and routing are completed when the next process is started, and the approval verification is completed. If the routing stage is instructed to make adjustments, the path adjustment parameters corresponding to the violation path group in the routing stage and the approval verification stage are set before the routing stage is implemented and the routing stage is repeated to optimize timing consistency.
[0076] Based on the above-described method for optimizing timing consistency, embodiments of this application also propose a computer-readable storage medium storing a computer program that causes a processor to execute the method for optimizing timing consistency as described in any one of steps 101 to 105. This application also proposes a computer program product, including a computer program / instruction, which, when executed by a processor, implements the method for optimizing timing consistency as described in any one of steps 101 to 105.
[0077] In summary, this application proposes a method for optimizing timing consistency. After the routing phase of the first physical design is completed, timing data is first read from the timing database of each phase. Then, violation path groups corresponding to each phase are created based on the timing data. Next, the path adjustment parameters corresponding to each violation path group in different phases and the timing differences of each violation path group in different phases are analyzed and calculated. Then, based on the timing differences, the target phase is instructed to make adjustments or to proceed to the next process. Finally, if the target phase is instructed to proceed to the next process, the approval and verification process begins. If the target phase is instructed to make adjustments, the path adjustment parameters of the target phase are set to run before the implementation of the target phase to optimize timing consistency.
[0078] This application creatively proposes a novel method for optimizing timing in the physical design process, providing improved timing accuracy, consistency, and iteration speed. It utilizes data from all violation paths to create precise violation path groups and compares and analyzes the timing differences of each violation path group across different physical design stages. Then, it calculates the corresponding path adjustment parameters for each violation path group at different physical design stages and returns them to the process iteration, ensuring high granularity in timing consistency optimization, accurate to each individual trigger. This granularity can be adjusted by modifying the violation path grouping strategy; the degree of adjustment depends on whether the designer prioritizes performance or efficiency. A higher granularity grouping method is chosen for performance, while a lower granularity grouping method is chosen for efficiency. This improves timing consistency and critical path accuracy across physical design stages, eliminating the need for designer experience-based judgment and preventing overly strict or lenient constraints. It significantly accelerates the iteration speed and timing convergence speed of physical design, enhances the automation capability of the physical design process, and has broad application prospects and high practicality.
[0079] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.
[0080] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0081] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.
Claims
1. A method for optimizing timing consistency, characterized in that, include: Read time series data from time series databases at each stage; Based on the time-series data, create violation path groups corresponding to each stage; The analysis and calculation yielded the path adjustment parameters for each violated path group at different stages and the temporal differences between each violated path group at different stages; Based on the aforementioned timing differences, the target stage is instructed to make adjustments or to proceed to the next process. If the instruction is to proceed to the next process, then proceed to the signing and verification. If the instruction is to adjust the target stage, then set the path adjustment parameters corresponding to the target stage to run before the target stage is implemented, in order to optimize timing consistency.
2. The method according to claim 1, characterized in that, Based on the time-series data, violation path groups are created for each stage, including: After the routing phase of the first physical design is completed, the timing data of each phase is grouped according to a preset grouping strategy, and a corresponding violation path group is created for all timing violation paths in the timing data of each phase.
3. The method according to claim 2, characterized in that, The time series data for each stage is grouped according to a preset grouping strategy. For all time series violation paths in the time series data of each stage, a corresponding violation path group is created, including: In each time series data, all time series violation paths are grouped according to the names of their emit triggers and capture triggers or the names of the module hierarchy they belong to, thus creating a violation path group corresponding to the stage of that time series data.
4. The method according to claim 3, characterized in that, The module hierarchy name includes: hierarchy names from level 1 to level N; all timing violation paths are grouped according to the names of their emit and capture triggers or the module hierarchy name, including: A violation path group is created by taking the name of the emit trigger in the timing violation path as the starting point of a path group and the name of the capture trigger as the ending point of the path group. This violation path group contains multiple timing violation paths. The path group starts with the module hierarchy name of any emit trigger in the timing violation path as the starting point of a group, and the module hierarchy name of the capture trigger at the same level as the emit trigger is taken as the ending point of the path group. The higher the level of the module hierarchy name, the fewer violation path groups can be created for all timing violation paths, and the more timing violation paths are in each violation path group.
5. The method according to claim 1, characterized in that, The analysis and calculation yielded the path adjustment parameters for each violated path group at different stages and the temporal differences between each violated path group at different stages, including: The violation path group corresponding to the target stage in each stage of the physical design process is defined as the baseline path group. The baseline path group is the violation path group corresponding to the Tth stage in the physical design process, where T is greater than 1. The violation values corresponding to each violation path in the baseline path group are compared and analyzed with the violation values corresponding to the same violation path in the previous violation path group, and the path adjustment parameters and the time series differences of each violation path group in different stages are calculated.
6. The method according to claim 5, characterized in that, A comparative analysis was performed to calculate the path adjustment parameters and time-series differences for each violated path group at different stages, including: When the baseline path group is the violation path group corresponding to stage T, it contains m violation paths, and the violation values of each of the m violation paths are S1, S2, ..., S... m The violation values of the m violation paths within the violation path group corresponding to the TX stage are P1, P2, ..., P. m Comparative analysis reveals that the temporal differences between the path group in stages TX and T are ΔS1=S1-P1, ΔS2=S2-P2, ..., ΔS m =S m -P m ; The maximum time difference value M is obtained by finding the maximum value among the aforementioned time differences. When there are n violation path groups, there are n maximum time difference values M1, M2, ..., M. n This is used as the path adjustment parameter for the n violation path groups between the TX and T stages; Calculate the n maximum time series differences M1, M2, ..., M n The variance of the time series difference between stage TX and stage T is obtained by calculating the variance of the time series difference. Following the method described above for comparing and analyzing the time series difference variances between stages TX and T, we can perform analysis on any two stages before stage T to obtain all time series difference variances. Compare the variance of all time series differences with a preset time series consistency threshold, and obtain the time series difference status based on the comparison results.
7. The method according to claim 6, characterized in that, Based on the aforementioned timing differences, instruct the target stage to make adjustments or to proceed to the next process, including: If the variance of each time-series difference is less than the preset time-series consistency threshold, then proceed to the next step. If, in any of the timing difference scenarios, the variance of any timing difference is not less than the preset timing consistency threshold, then an adjustment is indicated to the target stage. During the adjustment process, the n maximum timing difference values M1, M2, ..., M corresponding to the timing difference variances not less than the preset timing consistency threshold are used. n .
8. The method according to claim 7, characterized in that, If adjustments are indicated for the target stage, the path adjustment parameters corresponding to the target stage are set to run before the implementation of its corresponding stage to optimize timing consistency, including: The n maximum time-series difference values M1, M2, ..., M corresponding to the time-series difference variance that is not less than the preset time-series consistency threshold are... n Given the variance of the temporal difference between stage TX and stage T, the maximum temporal difference values M1, M2, ..., M n Set to run before the TX phase implementation to optimize timing consistency; Wherein, if the maximum time series difference values M1, M2, ..., M n If the value is negative, then the timing constraints of the n violation path groups in the TX stage are tightened. If the maximum time series difference values are M1, M2, ..., M n If the value is positive, then the timing constraints of the n violation path groups in the TX stage are relaxed.
9. The method according to claim 1, characterized in that, Entering the signature verification process includes: After the signature verification is completed, time series data is read from the time series database of the signature verification and violation path group corresponding to the static time series analysis is created; The analysis and calculation yielded the path adjustment parameters for the violation path group during the routing and approval verification phases, as well as the timing differences of the violation path group during these two phases. Based on the timing differences between these two stages, the routing stage is instructed to make adjustments or proceed to the next process; If the instruction is to proceed to the next process, the layout and routing are completed, and the signing and verification are completed. If the instruction is to adjust the routing stage, the path adjustment parameters corresponding to the violation path group in the routing stage and the signing and verification stage are set before the routing stage is implemented and the routing stage is repeated to optimize timing consistency.
10. The method according to claim 1, characterized in that, When grouping violation paths by the module hierarchy name of the emit trigger and capture trigger in the timing violation path, the higher the level of the module hierarchy name, the more timing violation paths are contained in each violation path group, the fewer violation path groups can be created, and the lower the fineness of the timing consistency optimization. The lower the level of the module hierarchy name, the fewer the timing violation paths contained in each violation path group, the more violation path groups can be created, and the higher the granularity of the timing consistency optimization.
11. A tool for optimizing timing consistency, characterized in that, include: Multiple interfaces are provided for reading timing data from the timing database of each stage after the routing phase of the first physical design is completed. A creation module is used to create violation path groups for each stage based on the time-series data; The analysis and calculation module is used to analyze and calculate the path adjustment parameters corresponding to each violation path group at different stages and the time series differences of each violation path group at different stages. The instruction module is used to instruct the target stage to make adjustments or to proceed to the next process based on the timing differences. The execution module is used to enter the signature verification process and display the signature verification process if the instruction is to proceed to the next process, and to set the path adjustment parameters corresponding to the target stage before the target stage is implemented if the instruction is to adjust the target stage.
12. The tool according to claim 11, characterized in that, The tool also includes: User interface for receiving user actions / selections, including: The first operation instruction is used to instruct the creation module to create violation path groups corresponding to each stage based on the time series data, and to display the violation path groups corresponding to each stage through the user interface. The second operation instruction is used to instruct the analysis and calculation module to analyze and calculate the path adjustment parameters corresponding to each violation path group at different stages and the temporal differences of each violation path group at different stages, and to display the path adjustment parameters and the temporal differences. The first selection instruction is used to select any two stages, instructing the analysis and calculation module to analyze and calculate the path adjustment parameters corresponding to each violation path group in these two stages and the timing differences of each violation path group in these two stages, and to display the path adjustment parameters and the timing differences. The second selection instruction is used to select the instruction module to perform a target operation, which includes: instructing the target stage to make adjustments or instructing to proceed to the next process; the third operation instruction is used to instruct the execution module to perform the target operation, wherein, if the target operation is to instruct to proceed to the next process, the signing and verification process is entered and displayed; if the target operation is to instruct the target stage to make adjustments, the path adjustment parameters corresponding to the target stage are set to run before the implementation of the target stage, and the data of the path adjustment parameters corresponding to the target stage is displayed.
13. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the method for optimizing timing consistency as described in any one of claims 1 to 10.