High-performance dual-mode frequency multiplier circuit
By introducing a gain-enhancing cross-coupled pair and a self-mixing principle into a dual-mode frequency multiplier, the problems of low conversion gain and complex structure in existing technologies are solved, and high-performance second and third harmonic signal output is achieved.
Patent Information
- Application Number
- CN202511571649.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-05-05
AI Technical Summary
Existing dual-mode frequency multiplier circuits suffer from low conversion gain, complex structure, and difficulty in simultaneously achieving frequency doubling and tripleting.
A high-performance dual-mode frequency multiplier circuit was designed, employing a push-push frequency multiplier with enhanced gain cross-coupling pairs and a third frequency multiplier based on a single balanced mixer. By simplifying the circuit structure through the self-mixing principle, the circuit achieves up-conversion of the second harmonic and the fundamental frequency, and outputs second and third harmonic signals.
It achieves high-performance dual-mode frequency multiplication, enhances the conversion gain of the frequency doubler, simplifies the circuit structure, and can simultaneously output high-performance frequency double and frequency triple signals.
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Figure CN121984446A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radio frequency integrated circuits, and in particular to a high-performance dual-mode frequency multiplier circuit. Background Technology
[0002] With the continuous development of communication technology, the microwave frequency band is experiencing spectrum congestion, leading to an increasing demand for high-performance frequency sources in high-frequency bands such as millimeter waves. There are two ways to obtain high-performance frequency sources: one is to directly design a high-frequency signal source. This method suffers from low frequency stability and poor phase noise. The other is to use frequency multiplication technology to multiply a stable, high-performance signal from a low-frequency band to the required high-frequency band. Comparatively, this method yields high-output power, low phase noise, and good stability in high-frequency signals. Therefore, high-performance frequency multiplier technology has become a research hotspot for millimeter-wave band signal sources.
[0003] In recent years, the demand for multi-frequency signals in communication systems and measuring instruments has been gradually increasing. To simultaneously meet the needs of multiple application scenarios, integrating the second / third frequency multiplier function into a single frequency multiplier has become a superior solution compared to the traditional approach of integrating second / third frequency multipliers into the system. Currently, research on dual-mode frequency multiplier circuits is limited, mainly due to the following issues:
[0004] (1) The frequency doubler adopts the traditional push-push structure, which has the problem of low conversion gain.
[0005] (2) Triplers often use an injection-locked structure, which has problems such as complex structure and high design difficulty.
[0006] (3) Traditional dual-frequency power combining networks extract the second harmonic by combining in-phase power and extract the third harmonic by combining out-of-phase power. However, they cannot obtain two frequency multiplication outputs at the same time, resulting in poor practicality. Summary of the Invention
[0007] This invention provides a high-performance dual-mode frequency multiplier circuit. This frequency multiplier can be applied to the millimeter-wave band and can simultaneously provide two frequency-multiplied signals: a second harmonic signal and a third harmonic signal. The second harmonic multiplier utilizes a gain-enhanced cross-coupling pair to improve the gain of the push-push second harmonic multiplier, solving the problem of low conversion gain. The third harmonic multiplier section utilizes a self-mixing principle to up-convert the second harmonic with the fundamental frequency, effectively simplifying the circuit structure and achieving the third harmonic function.
[0008] In the first aspect, a high-performance dual-mode frequency multiplier circuit is provided, including an input balun, a push-push frequency multiplier, a tripler based on a single-balanced mixer, and an output balun;
[0009] The input balun includes a first DC blocking capacitor, a second DC blocking capacitor, a third DC blocking capacitor, and a first transformer; the input balun has a LOin input terminal; the input balun has two output terminals, namely f0in+ and f0in-; wherein, the LOin input terminal is connected to the left end of the first DC blocking capacitor, the right end of the first DC blocking capacitor is connected to the upper end of the primary coil of the first transformer, the lower end of the primary coil of the first transformer is grounded, the upper end of the secondary coil of the first transformer is connected to the left end of the second DC blocking capacitor, the right end of the second DC blocking capacitor is connected to the f0in+ output terminal, the lower end of the secondary coil of the first transformer is connected to the left end of the third DC blocking capacitor, and the right end of the third DC blocking capacitor is connected to the f0in- output terminal;
[0010] The push-push frequency multiplier includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first bias resistor, a second bias resistor, and a fourth DC blocking capacitor. The push-push frequency multiplier has three input terminals: a first frequency multiplier input terminal, a second frequency multiplier input terminal, and a third frequency multiplier input terminal. The first frequency multiplier input terminal is connected to the f0in+ output terminal of the input balun, the second frequency multiplier input terminal is connected to the f0in- output terminal of the input balun, and the third frequency multiplier input terminal is connected to the Vb1 bias voltage terminal. The push-push frequency multiplier has 2f0 output terminals. The first frequency multiplier input terminal is connected to the first bias resistor... One end of the circuit connects the gate of the first NMOS transistor and the drain of the third NMOS transistor. The second end of the first bias resistor is connected to the input of the third frequency doubler. The input of the second frequency doubler is connected to the first end of the second bias resistor, the gate of the second NMOS transistor, and the drain of the fourth NMOS transistor. The second end of the second bias resistor is connected to the input of the third frequency doubler. The source of the first NMOS transistor is connected to the gate of the fourth NMOS transistor. The source of the second NMOS transistor is connected to the gate of the third NMOS transistor. The source of the third NMOS transistor is connected to ground. The source of the fourth NMOS transistor is connected to ground. The drain of the first NMOS transistor and the drain of the second NMOS transistor are connected to the left end of the fourth DC blocking capacitor. The right end of the fourth DC blocking capacitor is connected to the 2f0 output.
[0011] The frequency multiplier based on a single-balanced mixer includes a fifth NMOS transistor, a sixth NMOS transistor, a third bias resistor, a fourth bias resistor, a fifth DC blocking capacitor, a sixth DC blocking capacitor, a first inductor, and a second inductor. The frequency multiplier has four input terminals: a first frequency multiplier input terminal, a second frequency multiplier input terminal, a third frequency multiplier input terminal, and a fourth frequency multiplier input terminal. The first frequency multiplier input terminal is connected to the f0in+ output terminal of the input balun, the second frequency multiplier input terminal is connected to the f0in- output terminal of the input balun, the third frequency multiplier input terminal is connected to the Vb2 bias voltage terminal, and the fourth frequency multiplier input terminal is connected to the VDD power supply terminal. The frequency multiplier has two output terminals: an out+ output terminal and an out- output terminal. The first frequency multiplier input terminal is connected to the first terminal of the third bias resistor and the fifth NMOS transistor. The gate of the NMOS transistor is connected to the second end of the third bias resistor, which is connected to the input of the third frequency multiplier. The input of the second frequency multiplier is connected to the first end of the fourth bias resistor and the gate of the sixth NMOS transistor. The second end of the fourth bias resistor is connected to the input of the third frequency multiplier. The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected together and then connected to the left end of the fourth DC blocking capacitor in the push-push frequency multiplier. The drain of the fifth NMOS transistor is connected to the first end of the first inductor and the first end of the fifth DC blocking capacitor and is connected to the out+ output terminal. The drain of the sixth NMOS transistor is connected to the first end of the second inductor and the first end of the sixth DC blocking capacitor and is connected to the out- output terminal. The second ends of the first inductor, the fifth DC blocking capacitor, the second inductor, and the sixth DC blocking capacitor are connected together and connected to the input of the fourth frequency multiplier.
[0012] The output balun includes a seventh DC blocking capacitor, an eighth DC blocking capacitor, a ninth DC blocking capacitor, and a second transformer. The output balun has two input terminals, connected to the out+ and out- output terminals of the tripler, respectively. The output balun also has a 3f0 output terminal. Specifically, the out+ output terminal of the tripler is connected to the left end of the seventh DC blocking capacitor, and the right end of the seventh DC blocking capacitor is connected to the upper end of the primary coil of the second transformer. The out- output terminal of the tripler is connected to the left end of the eighth DC blocking capacitor, and the right end of the eighth DC blocking capacitor is connected to the lower end of the primary coil of the second transformer. The upper end of the secondary coil of the second transformer is connected to the left end of the ninth DC blocking capacitor, and the lower end of the secondary coil of the second transformer is grounded. The right end of the ninth DC blocking capacitor is connected to the 3f0 output terminal.
[0013] In conjunction with the first aspect, in some implementations of the first aspect, the function of the input balun is to convert a single-ended signal into a differential double-ended signal and provide input matching; the input signal of the input balun is the fundamental signal LOin generated by the local oscillator. The fundamental signal LOin enters the first transformer through the first DC blocking capacitor, and after passing through the second DC blocking capacitor and the third DC blocking capacitor respectively, it outputs a pair of differential signals f0in+ and f0in- with the same amplitude and opposite phase.
[0014] In conjunction with the first aspect, in some implementations of the first aspect, the push-push frequency doubler functions to double the differential signals f0in+ and f0in- to generate a doubled frequency signal 2f0; wherein the first NMOS transistor and the second NMOS transistor are the main push-push frequency doubler, and the third NMOS transistor and the fourth NMOS transistor are the gain enhancement cross-coupling pair; the bias voltage terminal of Vb1 provides bias to the gates of the first NMOS transistor and the second NMOS transistor through the first bias resistor and the second bias resistor, so that the first NMOS transistor and the second NMOS transistor are biased in the subthreshold conductance region, generating odd harmonic components and even harmonic components.
[0015] In conjunction with the first aspect, in some implementations of the first aspect, the function of the tripler is to inject the second harmonic and the fundamental frequency together into the mixer to obtain the third harmonic 3f0; the fifth NMOS transistor and the sixth NMOS transistor are the mixer, and the first inductor, the fifth DC blocking capacitor, the second inductor, and the sixth DC blocking capacitor constitute the third harmonic output matching; the Vb2 bias voltage terminal provides bias to the fifth NMOS transistor and the sixth NMOS transistor through the third bias resistor and the fourth bias resistor, and the drain of the fifth NMOS transistor and the drain of the sixth NMOS transistor output a pair of tripler signals out+ and out-.
[0016] In conjunction with the first aspect, in some implementations of the first aspect, the output balun functions to convert the differential double-ended signal into a single-ended signal and provide output matching. The tripled frequency signals out+ and out- generated by the tripler pass through the seventh and eighth DC blocking capacitors and enter the second transformer for subtraction. Thus, the tripled frequency signal is output through the ninth DC blocking capacitor.
[0017] In conjunction with the first aspect, in some implementations of the first aspect, the push-push frequency doubler satisfies:
[0018] I d1 =k0+k1(V G +V D1 )+k2(V G +V D1 ) 2 +k3(V G +V D1 ) 3
[0019] I d2 =k0-k1(V G +V D1 )+k2(V G +V D1 ) 2 -k3(V G +V D1) 3
[0020] I OUT =I d1 +I d2 =2k0+2k2(V G +V D1 ) 2
[0021] The drain current generated by the first NMOS transistor is I. d1 The drain current generated by the second NMOS transistor is I. d2 The sum of the drain current of the first NMOS transistor and the drain current of the second NMOS transistor is I. OUT The initial gate voltage swing of the first NMOS transistor is V. G The initial gate voltage swing of the second NMOS transistor is -V G The drain voltage swing of the third NMOS transistor is V. D1 The drain voltage swing of the fourth NMOS transistor is -V D1 k0 to k3 are constants related to the manufacturing process.
[0022] In conjunction with the first aspect, in some implementations of the first aspect,
[0023] V D1 =V G1 +n·g m ·R
[0024] or,
[0025] V D1 =V G +[(n·R-1 / k)g m -V TH ]
[0026] The gate voltage swing of the third NMOS transistor is -V G1 The gate voltage swing of the fourth NMOS transistor is V. G1 The transconductance of the first NMOS transistor and the second NMOS transistor is g. m The transconductance of the third and fourth NMOS transistors is n·gm, where n represents the field-effect transistor size ratio, V TH is the threshold voltage of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor; k is a constant related to the manufacturing process; and the resistance values of the first bias resistor and the second bias resistor are R.
[0027] In conjunction with the first aspect, in some implementations of the first aspect, the first bias resistor and the second bias resistor have the same resistance value, the third bias resistor and the fourth bias resistor have the same resistance value, the first inductor and the second inductor have the same inductance value, the second DC blocking capacitor and the third DC blocking capacitor have the same capacitance value, the fifth DC blocking capacitor and the sixth DC blocking capacitor have the same capacitance value, the seventh DC blocking capacitor and the eighth DC blocking capacitor have the same capacitance value, the first NMOS transistor and the second NMOS transistor have the same size, the third NMOS transistor and the fourth NMOS transistor have the same size, and the fifth NMOS transistor and the sixth NMOS transistor have the same size.
[0028] In conjunction with the first aspect, in some implementations of the first aspect, the bias voltage terminal Vb1 provides a DC operating point for the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor, and the bias voltage terminal Vb2 provides a DC operating point for the fifth NMOS transistor and the sixth NMOS transistor.
[0029] In conjunction with the first aspect, in some implementations of the first aspect, the first transformer provides input matching, and the second transformer, together with the first inductor, the second inductor, the fifth DC blocking capacitor, and the sixth DC blocking capacitor, provides output matching.
[0030] Compared with the prior art, the solution provided by the present invention has at least the following beneficial technical effects:
[0031] Compared to traditional frequency multipliers, this invention can achieve two multiplication ratios simultaneously. Furthermore, the improved push-push doubler structure can effectively enhance the doubler gain, thereby improving the overall performance of the frequency multiplier. This invention features dual-mode multiplication ratio, high gain, and simple structure. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of a high-performance dual-mode frequency multiplier circuit structure according to the present invention.
[0033] Figure 2 This is a schematic diagram of a traditional push-push frequency doubler structure.
[0034] Figure 3 This is a schematic diagram of an improved push-push frequency doubler. Detailed Implementation
[0035] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0036] The following is combined Figure 1 The present invention will be described in detail below. It should be understood that the embodiments shown and described in the accompanying drawings are merely exemplary and intended to illustrate the principles and spirit of the invention, and are not intended to limit the scope of the invention.
[0037] like Figure 1 As shown, this invention proposes a high-performance dual-mode frequency multiplier circuit, comprising: an input balun, an improved push-push frequency multiplier, a tripler based on a single-balanced mixer, and an output balun. The specific circuit structure and connection relationships of each part are described below.
[0038] The input balun includes a first DC blocking capacitor C1, a second DC blocking capacitor C2, a third DC blocking capacitor C3, and a first transformer TR1. The input balun has a LOin input terminal for inputting the fundamental signal LOin. The input balun has two output terminals, f0in+ and f0in-, for outputting signals f0in+ and f0in-, respectively.
[0039] The LOin input terminal is connected to the left end of the first DC blocking capacitor C1. The right end of the first DC blocking capacitor C1 is connected to the upper end of the primary coil of the first transformer TR1. The lower end of the primary coil of the first transformer TR1 is grounded. The upper end of the secondary coil of the first transformer TR1 is connected to the left end of the second DC blocking capacitor C2. The right end of the second DC blocking capacitor C2 is connected to the f0in+ output terminal. The lower end of the secondary coil of the first transformer TR1 is connected to the left end of the third DC blocking capacitor C3. The right end of the third DC blocking capacitor C3 is connected to the f0in- output terminal.
[0040] The improved push-push frequency doubler includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first bias resistor R1, a second bias resistor R2, and a fourth DC blocking capacitor C4. The improved push-push frequency doubler has three input terminals: a first frequency doubler input terminal, a second frequency doubler input terminal, and a third frequency doubler input terminal. The first frequency doubler input terminal is connected to the f0in+ output terminal of the input balun, the second frequency doubler input terminal is connected to the f0in- output terminal of the input balun, and the third frequency doubler input terminal is connected to the Vb1 bias voltage terminal for input bias voltage Vb1. The improved push-push frequency doubler has a 2f0 output terminal for outputting the signal 2f0.
[0041] The first frequency doubler input (input signal f0in+) is connected to the first terminal of the first bias resistor R1, the gate of the first NMOS transistor M1, and the drain of the third NMOS transistor M3. The second terminal of the first bias resistor R1 is connected to the third frequency doubler input (input bias voltage Vb1). The second frequency doubler input (input signal f0in-) is connected to the first terminal of the second bias resistor R2, the gate of the second NMOS transistor M2, and the drain of the fourth NMOS transistor M4. The second terminal of the second bias resistor R2 is connected to the third frequency doubler input (input bias voltage Vb1). The source of the first NMOS transistor M1 is connected to the gate of the fourth NMOS transistor M4. The source of the second NMOS transistor M2 is connected to the gate of the third NMOS transistor M3. The source of the third NMOS transistor M3 is connected to ground. The source of the fourth NMOS transistor M4 is connected to ground. The drain of the first NMOS transistor M1 is connected to the drain of the second NMOS transistor M2, and then connected to the left end of the fourth DC blocking capacitor C4. The right end of the fourth DC blocking capacitor C4 is connected to the 2f0 output terminal.
[0042] The tripler based on a single-balanced mixer includes a fifth NMOS transistor M5, a sixth NMOS transistor M6, a third bias resistor R3, a fourth bias resistor R4, a fifth DC blocking capacitor C5, a sixth DC blocking capacitor C6, a first inductor L1, and a second inductor L2. The tripler has four input terminals: a first tripler input, a second tripler input, a third tripler input, and a fourth tripler input. The first tripler input is connected to the f0in+ output of the input balun; the second tripler input is connected to the f0in- output of the input balun; the third tripler input is connected to the Vb2 bias voltage terminal for input bias voltage Vb2; and the fourth tripler input is connected to the VDD power supply terminal for connection to the power supply VDD. The tripler has two output terminals: out+ and out-, used to output signals out+ and out-, respectively.
[0043] The first tripler input (input signal f0in+) is connected to the first terminal of the third bias resistor R3 and the gate of the fifth NMOS transistor M5. The second terminal of the third bias resistor R3 is connected to the third tripler input (input bias voltage Vb2). The second tripler input (input signal f0in-) is connected to the first terminal of the fourth bias resistor R4 and the gate of the sixth NMOS transistor M6. The second terminal of the fourth bias resistor R4 is connected to the third tripler input (input bias voltage Vb2). The source of the fifth NMOS transistor M5 and the source of the sixth NMOS transistor M6 are connected to the left end of the fourth DC blocking capacitor C4 in the improved push-push doubler. The drain of the fifth NMOS transistor M5 is connected to the first terminal of the first inductor L1, the first terminal of the fifth DC blocking capacitor C5, and is connected to the out+ output terminal. The drain of the sixth NMOS transistor M6 is connected to the first terminal of the second inductor L2 and the first terminal of the sixth DC blocking capacitor C6, and is connected to the out- output terminal. The second terminal of the first inductor L1, the second terminal of the fifth DC blocking capacitor C5, the second terminal of the second inductor L2, and the second terminal of the sixth DC blocking capacitor C6 are connected together and connected to the input terminal of the fourth tripler (connected to power supply VDD).
[0044] The output balun includes a seventh DC blocking capacitor C7, an eighth DC blocking capacitor C8, a ninth DC blocking capacitor C9, and a second transformer TR2. The output balun has two input terminals, connected to the out+ and out- output terminals of the aforementioned tripler, respectively. The output balun also has a 3f0 output terminal for outputting the signal 3f0.
[0045] The above-mentioned tripler's out+ output terminal is connected to the left end of the seventh DC blocking capacitor C7, and the right end of the seventh DC blocking capacitor C7 is connected to the upper end of the primary coil of the second transformer TR2. The above-mentioned tripler's out- output terminal is connected to the left end of the eighth DC blocking capacitor C8, and the right end of the eighth DC blocking capacitor C8 is connected to the lower end of the primary coil of the second transformer TR2. The upper end of the secondary coil of the second transformer TR2 is connected to the left end of the ninth DC blocking capacitor C9, and the lower end of the secondary coil of the second transformer TR2 is grounded. The right end of the ninth DC blocking capacitor C9 is connected to the 3f0 output terminal.
[0046] In some embodiments, the first bias resistor R1 and the second bias resistor R2 have the same resistance value; the third bias resistor R3 and the fourth bias resistor R4 have the same resistance value; the first inductor L1 and the second inductor L2 have the same inductance value; the second DC blocking capacitor C2 and the third DC blocking capacitor C3 have the same capacitance value; the fifth DC blocking capacitor C5 and the sixth DC blocking capacitor C6 have the same capacitance value; the seventh DC blocking capacitor C7 and the eighth DC blocking capacitor C8 have the same capacitance value; the first NMOS transistor M1 and the second NMOS transistor M2 have the same dimensions; the third NMOS transistor M3 and the fourth NMOS transistor M4 have the same dimensions; and the fifth NMOS transistor M5 and the sixth NMOS transistor M6 have the same dimensions. The above devices can be designed according to the specific circuit system requirements.
[0047] In some embodiments, the bias voltage terminal Vb1 provides a DC operating point for the first NMOS transistor M1 / second NMOS transistor M2, third NMOS transistor M3 / fourth NMOS transistor M4, and the bias voltage terminal Vb2 provides a DC operating point for the fifth NMOS transistor M5 / sixth NMOS transistor M6. The magnitudes of the bias voltages Vb1 and Vb2 can be designed according to the specific circuit system requirements.
[0048] In some embodiments, the first transformer TR1 provides input matching, and the second transformer TR2, together with the first inductor L1, the second inductor L2, the fifth DC blocking capacitor C5, and the sixth DC blocking capacitor C6, provides output matching. Their sizes can be designed according to the specific circuit system requirements.
[0049] The working principle of the above-mentioned high-performance dual-mode frequency multiplier circuit is described below.
[0050] The input balun converts a single-ended signal into a differential double-ended signal and provides input matching. The input signal is the fundamental signal LOin generated by the local oscillator. LOin passes through the first DC blocking capacitor C1 and enters the first transformer TR1. After passing through the second DC blocking capacitor C2 and the third DC blocking capacitor C3, it outputs a pair of differential signals f0in+ / f0in- with the same amplitude but opposite phase.
[0051] The improved push-push frequency doubler functions to double the frequency of a pair of differential fundamental signals f0in+ / f0in-, generating a doubled frequency signal 2f0. The first NMOS transistor M1 and the second NMOS transistor M2 form the main push-push frequency doubler, while the third NMOS transistor M3 and the fourth NMOS transistor M4 form a gain-enhancing cross-coupling pair. The bias voltage Vb1 provides bias to the gates of the first NMOS transistor M1 and the second NMOS transistor M2 through the first bias resistor R1 and the second bias resistor R2, biasing the first NMOS transistor M1 and the second NMOS transistor M2 in the subthreshold conductance region, generating odd and even harmonic components.
[0052] The following analysis, using a traditional push-push frequency doubler as an example, examines the role of the gain-enhancing cross-coupling pair in the solution provided by this invention.
[0053] Traditional push-push frequency doublers, such as Figure 2 As shown. A traditional push-push frequency doubler includes capacitors C1, C2, and C3, a transformer, capacitor C4, NMOS transistors M1 and M2. The input of a traditional push-push frequency doubler is the fundamental frequency. Let the drain current generated by NMOS transistor M1 be I. d1 The drain current generated by NMOS transistor M2 is I. d2 V G -V is the gate voltage swing of NMOS transistor M1. G This represents the gate voltage swing of NMOS transistor M2. The drains of NMOS transistors M1 and M2 are connected to obtain I0. OUT I OUT After passing through the fourth DC blocking capacitor C4, only the second term is retained, and the second harmonic output is obtained from the second harmonic output terminal, which is the second harmonic frequency multiplier signal. The traditional push-push frequency multiplier satisfies formulas (1) to (3).
[0054]
[0055] Where k0 to k3 are constants related to the manufacturing process.
[0056] After adding a gain-enhancing cross-coupling pair, the improved push-push frequency doubler is as follows: Figure 3 As shown. Combined with Figure 1 and Figure 3 The gate voltage swing of the first NMOS transistor M1 is superimposed with the drain signal V of the third NMOS transistor M3. D1 The gate voltage swing of the second NMOS transistor M2 is superimposed with the drain signal -V of the fourth NMOS transistor M4. D1 Let the transconductance of the first NMOS transistor M1 / the second NMOS transistor M2 be g. m The transconductance of the third NMOS transistor M3 / fourth NMOS transistor M4 is selected as n·gm, where n represents the size ratio of the field-effect transistors. The initial gate voltage swing of the first NMOS transistor M1 is V. G (and Figure 1 Chinese V G Correspondingly, the initial gate voltage swing of the second NMOS transistor M2 is -V G (and Figure 1 China-V G (Corresponding). Since the gate input of the third NMOS transistor M3 is the source output of the second NMOS transistor M2, the gate voltage swing of the third NMOS transistor M3 is assumed to be -V. G1The drain voltage swing of the third NMOS transistor M3 is V. D1 Since the gate input of the fourth NMOS transistor M4 is the source output of the first NMOS transistor M1, let the gate voltage swing of the fourth NMOS transistor M4 be V. G1 The drain voltage swing of the fourth NMOS transistor M4 is -V D1 The improved push-push frequency doubler satisfies formula (4).
[0057] V D1 =V G1 +n·g m ·R=V G +[(n·R-1 / k)g m -V TH (4)
[0058] Among them, V TH is the threshold voltage of the first NMOS transistor M1 / second NMOS transistor M2 / third NMOS transistor M3 / fourth NMOS transistor M4, which is a fixed value related to the manufacturing process; k is a constant related to the manufacturing process, and the resistance of resistors R1 / R2 is R.
[0059] Let a = n·R⁻¹ / k, then we can obtain
[0060] V D1 =V G +a·g m -V TH (5) It is usually known that equation (5) is greater than 0 during the design process. Substituting equation (5) into equations (1) to (2) yields equations (6) to (7). Substituting equations (6) to (7) into equation (8) yields the second harmonic output of the improved push-push frequency doubler, where A is the equivalent value of the constant after substituting into equations (6) to (7). As can be seen from equation (8), this improved push-push frequency doubler structure can effectively improve the frequency conversion gain. Compared with the traditional push-push structure, its second harmonic amplitude is increased by four times, which can significantly improve the frequency doubling performance of the frequency doubler.
[0061] I d1 =k0+k1(V G +V D1 )+k2(V G +V D1 ) 2 +k3(V G +V D1 ) 3 (6)
[0062] I d2 =k0-k1(V G +V D1 )+k2(VG +V D1 ) 2 -k3(V G +V D1 ) 3 (7)
[0063]
[0064] The function of a third harmonic mixer based on a single-balanced mixer is to utilize the mixing principle to inject the second harmonic along with the fundamental frequency into the mixer to obtain the third harmonic 3f0. Figure 1 In this circuit, the fifth NMOS transistor M5 and the sixth NMOS transistor M6 form a mixer. The first inductor L1, the fifth DC blocking capacitor C5, the second inductor L2, and the sixth DC blocking capacitor C6 at the load end constitute the third harmonic output matching, effectively suppressing other frequency amplitudes and improving the third harmonic gain. The bias voltage Vb2 provides bias to the fifth NMOS transistor M5 and the sixth NMOS transistor M6 through the third bias resistor R3 and the fourth bias resistor R4. The drains of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 output a pair of third harmonic signals, out+ and out-.
[0065] The function of the output balun is to convert differential two-ended signals into single-ended signals and provide output matching. Figure 1 The input signal is the tripled frequency signal out+ / out- generated by the tripler. out+ / out- passes through the seventh DC blocking capacitor C7 and the eighth DC blocking capacitor C8 and enters the second transformer TR2 for subtraction operation, retaining odd harmonics and suppressing even harmonics. Finally, the tripled frequency signal is output as 3f0 through the ninth DC blocking capacitor C9.
[0066] In summary, the improved push-push frequency multiplier can provide a greater second harmonic gain, resulting in superior second harmonic performance. Similarly, it can improve the performance of a third frequency multiplier based on the self-mixing principle, while simultaneously outputting high-performance second and third harmonic signals. In the entire high-performance dual-mode frequency multiplier circuit, the size of the MOSFETs, bias voltage, and the values of other resistors, capacitors, and inductors are determined by comprehensively considering various indicators such as the overall circuit's conversion gain and matching characteristics. Through subsequent layout design and proper arrangement, the required indicators can be better achieved, resulting in high gain and good input-output matching characteristics.
[0067] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims of the present invention.
Claims
1. A high-performance dual-mode frequency multiplier circuit, characterized in that, This includes input baluns, push-push frequency doublers, triplers based on single-balanced mixers, and output baluns; The input balun includes a first DC blocking capacitor (C1), a second DC blocking capacitor (C2), a third DC blocking capacitor (C3), and a first transformer (TR1). The input balun has a LOin input terminal and two output terminals, namely f0in+ and f0in-. The LOin input terminal is connected to the left end of the first DC blocking capacitor (C1), the right end of the first DC blocking capacitor (C1) is connected to the upper end of the primary coil of the first transformer (TR1), the lower end of the primary coil of the first transformer (TR1) is grounded, the upper end of the secondary coil of the first transformer (TR1) is connected to the left end of the second DC blocking capacitor (C2), the right end of the second DC blocking capacitor (C2) is connected to the f0in+ output terminal, the lower end of the secondary coil of the first transformer (TR1) is connected to the left end of the third DC blocking capacitor (C3), and the right end of the third DC blocking capacitor (C3) is connected to the f0in- output terminal. The push-push frequency multiplier includes a first NMOS transistor (M1), a second NMOS transistor (M2), a third NMOS transistor (M3), a fourth NMOS transistor (M4), a first bias resistor (R1), a second bias resistor (R2), and a fourth DC blocking capacitor (C4). The push-push frequency multiplier has three input terminals: a first frequency multiplier input terminal, a second frequency multiplier input terminal, and a third frequency multiplier input terminal. The first frequency multiplier input terminal is connected to the f0in+ output terminal of the input balun, the second frequency multiplier input terminal is connected to the f0in- output terminal of the input balun, and the third frequency multiplier input terminal is connected to the Vb1 bias voltage terminal. The push-push frequency multiplier has a 2f0 output terminal. The first frequency multiplier input terminal is connected to the first terminal of the first bias resistor (R1), the gate of the first NMOS transistor (M1), and... The drain of the third NMOS transistor (M3) is connected to the second terminal of the first bias resistor (R1), which is connected to the input terminal of the third frequency multiplier. The input terminal of the second frequency multiplier is connected to the first terminal of the second bias resistor (R2), the gate of the second NMOS transistor (M2), and the drain of the fourth NMOS transistor (M4). The second terminal of the second bias resistor (R2) is connected to the input terminal of the third frequency multiplier. The source of the first NMOS transistor (M1) is connected to the gate of the fourth NMOS transistor (M4). The source of the second NMOS transistor (M2) is connected to the gate of the third NMOS transistor (M3). The source of the third NMOS transistor (M3) is connected to ground. The source of the fourth NMOS transistor (M4) is connected to ground. The drain of the first NMOS transistor (M1) and the drain of the second NMOS transistor (M2) are connected to the left terminal of the fourth DC blocking capacitor (C4), and the right terminal of the fourth DC blocking capacitor (C4) is connected to the 2f0 output terminal. The tripler based on a single-balanced mixer includes a fifth NMOS transistor (M5), a sixth NMOS transistor (M6), a third bias resistor (R3), a fourth bias resistor (R4), a fifth DC blocking capacitor (C5), a sixth DC blocking capacitor (C6), a first inductor (L1), and a second inductor (L2). The tripler has four input terminals: a first tripler input terminal, a second tripler input terminal, a third tripler input terminal, and a fourth tripler input terminal. The first tripler input terminal is connected to the f0in+ output terminal of the input balun, the second tripler input terminal is connected to the f0in- output terminal of the input balun, the third tripler input terminal is connected to the Vb2 bias voltage terminal, and the fourth tripler input terminal is connected to the VDD power supply terminal. The tripler has two output terminals: out+ and out-. The first tripler input terminal is connected to the first terminal of the third bias resistor (R3) and the gate of the fifth NMOS transistor (M5). The second end of resistor (R3) is connected to the input terminal of the third frequency multiplier; the input terminal of the second frequency multiplier is connected to the first end of the fourth bias resistor (R4) and the gate of the sixth NMOS transistor (M6), and the second end of the fourth bias resistor (R4) is connected to the input terminal of the third frequency multiplier; the source of the fifth NMOS transistor (M5) and the source of the sixth NMOS transistor (M6) are connected and then connected to the left end of the fourth DC blocking capacitor (C4) in the push-push frequency multiplier; the drain of the fifth NMOS transistor (M5) is connected to the first end of the first inductor (L1) and the first end of the fifth DC blocking capacitor (C5) and connected to the out+ output terminal; the drain of the sixth NMOS transistor (M6) is connected to the first end of the second inductor (L2) and the first end of the sixth DC blocking capacitor (C6) and connected to the out- output terminal; the second ends of the first inductor (L1), the fifth DC blocking capacitor (C5), the second inductor (L2), and the sixth DC blocking capacitor (C6) are connected and connected to the input terminal of the fourth frequency multiplier; The output balun includes a seventh DC blocking capacitor (C7), an eighth DC blocking capacitor (C8), a ninth DC blocking capacitor (C9), and a second transformer (TR2). The output balun has two input terminals, connected to the out+ and out- output terminals of the tripler, respectively. The output balun also has a 3f0 output terminal. Specifically, the out+ output terminal of the tripler is connected to the left end of the seventh DC blocking capacitor (C7), and the right end of the seventh DC blocking capacitor (C7) is connected to the upper end of the primary coil of the second transformer (TR2). The out- output terminal of the tripler is connected to the left end of the eighth DC blocking capacitor (C8), and the right end of the eighth DC blocking capacitor (C8) is connected to the lower end of the primary coil of the second transformer (TR2). The upper end of the secondary coil of the second transformer (TR2) is connected to the left end of the ninth DC blocking capacitor (C9), and the lower end of the secondary coil of the second transformer (TR2) is grounded. The right end of the ninth DC blocking capacitor (C9) is connected to the 3f0 output terminal.
2. The high-performance dual-mode frequency multiplier circuit according to claim 1, characterized in that, The function of the input balun is to convert a single-ended signal into a differential double-ended signal and provide input matching. The input signal of the input balun is the fundamental signal LOin generated by the local oscillator. The fundamental signal LOin enters the first transformer (TR1) through the first DC blocking capacitor (C1), and after passing through the second DC blocking capacitor (C2) and the third DC blocking capacitor (C3), it outputs a pair of differential signals f0in+ and f0in- with the same amplitude and opposite phase.
3. The high-performance dual-mode frequency multiplier circuit according to claim 2, characterized in that, The push-push frequency doubler functions to double the differential signals f0in+ and f0in- to generate a doubled frequency signal 2f0. The first NMOS transistor (M1) and the second NMOS transistor (M2) form the main push-push frequency doubler, while the third NMOS transistor (M3) and the fourth NMOS transistor (M4) form a gain-enhancing cross-coupled pair. The bias voltage terminal of Vb1 provides bias to the gates of the first NMOS transistor (M1) and the second NMOS transistor (M2) through the first bias resistor (R1) and the second bias resistor (R2), so that the first NMOS transistor (M1) and the second NMOS transistor (M2) are biased in the subthreshold conductance region, generating odd harmonic components and even harmonic components.
4. The high-performance dual-mode frequency multiplier circuit according to claim 3, characterized in that, The function of the tripler is to inject the second harmonic and the fundamental frequency together into the mixer to obtain the third harmonic 3f0; the fifth NMOS transistor (M5) and the sixth NMOS transistor (M6) are the mixer, and the first inductor (L1), the fifth DC blocking capacitor (C5), the second inductor (L2), and the sixth DC blocking capacitor (C6) constitute the third harmonic output matching; the Vb2 bias voltage terminal provides bias to the fifth NMOS transistor (M5) and the sixth NMOS transistor (M6) through the third bias resistor (R3) and the fourth bias resistor (R4), and the drain of the fifth NMOS transistor (M5) and the drain of the sixth NMOS transistor (M6) output a pair of tripler signals out+ and out-.
5. The high-performance dual-mode frequency multiplier circuit according to claim 4, characterized in that, The function of the output balun is to convert the differential double-ended signal into a single-ended signal and provide output matching. The tripled frequency signals out+ and out- generated by the tripler pass through the seventh DC blocking capacitor (C7) and the eighth DC blocking capacitor (C8) and enter the second transformer (TR2) for subtraction. Thus, the tripled frequency signal is output through the ninth DC blocking capacitor (C9).
6. The high-performance dual-mode frequency multiplier circuit according to claim 1, characterized in that, The push-push frequency multiplier satisfies: I d1 =k0+k1(V G +V D1 )+k2(V G +V D1 ) 2 +k3(V G +V D1 ) 3 I d2 =k0-k1(V G +V D1 )+k2(V G +V D1 ) 2 -k3(V G +V D1 ) 3 I OUT =I d1 +I d2 =2k0+2k2(V G +V D1 ) 2 The drain current generated by the first NMOS transistor (M1) is I. d1 The drain current generated by the second NMOS transistor (M2) is I. d2 The sum of the drain current of the first NMOS transistor (M1) and the drain current of the second NMOS transistor (M2) is I. OUT The initial gate voltage swing of the first NMOS transistor (M1) is V. G The initial gate voltage swing of the second NMOS transistor (M2) is -V G The drain voltage swing of the third NMOS transistor (M3) is V. D1 The drain voltage swing of the fourth NMOS transistor (M4) is -V D1 k0 to k3 are constants related to the manufacturing process.
7. The high-performance dual-mode frequency multiplier circuit according to claim 6, characterized in that, V D1 =V G1 +n·g m ·R or, V D1 =V G +[(n·R-1 k )g m -V TH ] The gate voltage swing of the third NMOS transistor (M3) is -V G1 The gate voltage swing of the fourth NMOS transistor (M4) is V. G1 The transconductance of the first NMOS transistor (M1) and the second NMOS transistor (M2) is g. m The transconductance of the third NMOS transistor (M3) and the fourth NMOS transistor (M4) is n·gm, where n represents the field-effect transistor size ratio, and V TH is the threshold voltage of the first NMOS transistor (M1), the second NMOS transistor (M2), the third NMOS transistor (M3), and the fourth NMOS transistor (M4); k is a constant related to the manufacturing process; and the resistance values of the first bias resistor (R1) and the second bias resistor (R2) are R.
8. The high-performance dual-mode frequency multiplier circuit according to claim 1, characterized in that, The first bias resistor (R1) and the second bias resistor (R2) have the same resistance value; the third bias resistor (R3) and the fourth bias resistor (R4) have the same resistance value; the first inductor (L1) and the second inductor (L2) have the same inductance value; the second DC blocking capacitor (C2) and the third DC blocking capacitor (C3) have the same capacitance value; the fifth DC blocking capacitor (C5) and the sixth DC blocking capacitor (C6) have the same capacitance value; the seventh DC blocking capacitor (C7) and the eighth DC blocking capacitor (C8) have the same capacitance value; the first NMOS transistor (M1) and the second NMOS transistor (M2) have the same dimensions; the third NMOS transistor (M3) and the fourth NMOS transistor (M4) have the same dimensions; and the fifth NMOS transistor (M5) and the sixth NMOS transistor (M6) have the same dimensions.
9. The high-performance dual-mode frequency multiplier circuit according to claim 1, characterized in that, The Vb1 bias voltage terminal provides the DC operating point for the first NMOS transistor (M1), the second NMOS transistor (M2), the third NMOS transistor (M3), and the fourth NMOS transistor (M4), while the Vb2 bias voltage terminal provides the DC operating point for the fifth NMOS transistor (M5) and the sixth NMOS transistor (M6).
10. The high-performance dual-mode frequency multiplier circuit according to claim 1, characterized in that, The first transformer (TR1) provides input matching, while the second transformer (TR2), together with the first inductor (L1), the second inductor (L2), the fifth DC blocking capacitor (C5), and the sixth DC blocking capacitor (C6), provide output matching.