A pixel front-end circuit, a pixel sensor and a detector system
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG NORMAL UNIV
- Filing Date
- 2026-03-31
- Publication Date
- 2026-07-03
Smart Images
Figure CN121985231B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power electronics technology, and in particular to a pixel front-end circuit, a pixel sensor, and a detector system. Background Technology
[0002] Pixel sensors are the core detection devices for next-generation high-energy physics experiments and high-end complementary metal-oxide-semiconductor (CMOS) image sensors. Their front-end circuits generally employ the traditional "source follower + discriminator" architecture. However, this architecture suffers from the following fundamental contradictions when facing larger-scale, higher-performance applications:
[0003] First, there is a direct conflict between power consumption and speed / gain. Achieving high gain and fast response requires increasing the bias current, which leads to a sharp increase in total pixel power consumption, failing to meet the heat dissipation and power consumption constraints of large-scale arrays. Second, uniformity and integration density are mutually restrictive. To improve the uniformity of threshold and response time, the transistor area needs to be increased to suppress mismatch, but this contradicts the stringent requirements of fine pixel pitch on circuit area. Furthermore, the relative variation of parasitic capacitance in deep submicron processes is significant, directly affecting the uniformity of gain and threshold between pixels, and traditional circuits lack effective suppression methods. In addition, traditional architectures are insufficient for large signal processing; when the input charge is too large, the output pulse will nonlinearly broaden, leading to time information distortion, increased dead time, and increased complexity in global timing design.
[0004] Therefore, traditional architectures struggle to simultaneously meet the requirements of low power consumption, high uniformity, strong resistance to parasitic interference, and wide dynamic range within a limited area, becoming a key bottleneck restricting further improvements in pixel sensor performance. A pixel front-end circuit capable of solving these problems is urgently needed. Summary of the Invention
[0005] The purpose of this application is to provide a pixel front-end circuit, a pixel sensor, and a detector system, so that the pixel front-end circuit can simultaneously meet the requirements of low power consumption, high uniformity, and high detection performance within a limited area.
[0006] To achieve the above objectives, this application provides the following solution.
[0007] In a first aspect, this application provides a pixel front-end circuit, including: an input stage and a charge transfer amplification branch, a bias and baseline setting network, and a discrimination output stage and a second common-source cascode shielding module;
[0008] The input stage and charge transfer amplification branch include: a source follower transistor, a first common-source shielded transistor, a load current source, and a current feedback network; the current feedback network includes: a feedback capacitor, a first feedback transistor, and a second feedback transistor; the gate of the load current source is controlled by the current feedback network;
[0009] The bias and baseline setting network includes: a main bias current transistor and a threshold current and baseline recovery circuit; the threshold current and baseline recovery circuit includes a first feedback transistor and a second feedback transistor; the main bias current transistor is used to provide a main bias current in the nanoampere range;
[0010] The discrimination output stage and the second common source cascode shielding module include: a load transistor, a second common source cascode shielding transistor, and an input transistor.
[0011] In one embodiment, in the input stage and charge transfer amplification branch, the gate of the source follower transistor is connected to the input node, and the source of the source follower transistor is connected to the charge transfer node; the input node is directly connected to the ohmic contact of the N-type collector well of the sensor to receive the collected charge from the N-type collector well; the source of the first cascode shielded transistor is connected to the drain of the source follower transistor, the drain of the first cascode shielded transistor is connected to the first-stage output node, and the gate of the first cascode shielded transistor is connected to the first PMOS bias voltage; the source of the load current source transistor is grounded, and the drain of the load current source transistor is connected to the first-stage output node; the gate of the load current source transistor is connected to the feedback node; one end of the feedback capacitor is connected to the charge transfer node, and the other end of the feedback capacitor, the drain of the first feedback transistor, and the drain of the second feedback transistor are all connected to the feedback node; the gate of the first feedback transistor is connected to the second PMOS bias voltage, and the source of the first feedback transistor is connected to the power supply voltage; the source of the second feedback transistor is connected to the first-stage output node, and the gate of the second feedback transistor is connected to the first NMOS bias voltage.
[0012] In one embodiment, in the bias and baseline setting network, the gate of the main bias current transistor is connected to a third PMOS bias voltage, the source of the main bias current transistor is connected to a power supply voltage, and the drain of the main bias current transistor is connected to a charge transfer node.
[0013] In one embodiment, in the discrimination output stage and the second cascode shielding module, the gate of the load transistor is connected to a fourth PMOS bias voltage, the source of the load transistor is connected to a power supply voltage, and the drain of the load transistor is connected to the second-stage output node; the gate of the second cascode shielding transistor is connected to a second NMOS bias voltage, the drain of the second cascode shielding transistor is connected to the second-stage output node, the source of the second cascode shielding transistor is connected to the drain of the input transistor, the source of the input transistor is grounded, and the gate of the input transistor is connected to the first-stage output node.
[0014] In one embodiment, the pixel front-end circuit further includes a pulse limiting module;
[0015] The pulse limiting module includes: a limiting transistor;
[0016] The gate of the limiting transistor is connected to the fifth PMOS bias voltage, the source of the limiting transistor is connected to the feedback node, and the drain of the limiting transistor is connected to the first-stage output node.
[0017] In one embodiment, the source follower transistor, the first cascode shielded transistor, the load current source, the main bias current transistor, the first feedback transistor, the second feedback transistor, the load transistor, the second cascode shielded transistor, the input transistor, and the limiting transistor are all metal-oxide-semiconductor field-effect transistors; each metal-oxide-semiconductor field-effect transistor is configured to operate in the weak inversion region.
[0018] In one embodiment, the source follower transistor, the load current source, the main bias current transistor, the first feedback transistor, the second feedback transistor, the load transistor, the input transistor, and the limiting transistor are all metal-oxide-semiconductor field-effect transistors;
[0019] Both the first cascode shielded transistor and the second cascode shielded transistor are gain bootstrap operational amplifiers.
[0020] In one embodiment, the feedback capacitor is a MIM capacitor.
[0021] Secondly, this application provides a pixel sensor, including a pixel array, wherein at least one pixel unit in the pixel array includes the pixel front-end circuit described in any of the preceding claims.
[0022] Thirdly, this application provides a detector system, including the pixel sensor and data acquisition circuit described above;
[0023] The data acquisition circuit is connected to the second-stage output node of the pixel front-end circuit in each pixel unit, and is used to receive pulse signals.
[0024] According to the specific embodiments provided in this application, the following technical effects are disclosed:
[0025] This application discloses a pixel front-end circuit, a pixel sensor, and a detector system. The pixel front-end circuit includes a bias and baseline setting network, specifically a main bias current transistor. This main bias current transistor provides a single, precisely settable main bias current for the entire circuit. In CMOS circuits, static power consumption primarily depends on the bias current. By setting the main bias current to the nanoampere level, extremely low static power consumption can be locked at the architecture level. Furthermore, using a single transistor like the main bias current transistor to generate global bias significantly saves area compared to complex multi-branch bias circuits.
[0026] The circuit incorporates both a first cascode shield and a second cascode shield, forming a unique dual cascode shielding structure. The first cascode shield significantly suppresses the Miller parasitic capacitance effect between the input node and the first-stage output node, preventing variations in Miller parasitic capacitance from causing uncontrollable changes in voltage gain between pixels and improving charge threshold uniformity. The second cascode shield shields the gate-drain parasitic capacitance of the input transistor. Changes in the gate-drain parasitic capacitance directly modulate the effective gate voltage of the input transistor, severely affecting charge threshold uniformity. The introduction of the second cascode shield isolates the second output node from the gate-drain parasitic capacitance, significantly reducing the sensitivity of the charge threshold to changes in gate-drain parasitic capacitance. Both the first and second cascode shields improve charge threshold uniformity.
[0027] The specific structure of the input stage and charge transfer amplification branch is defined, especially the source follower transistor, the first common-source cascode shielded transistor, and the load current source controlled by the current feedback network. This structure realizes charge transfer amplification, that is, the collection of charge causes the voltage of the charge transfer node to change, which causes the charge on the feedback capacitor to be transferred to the capacitor of the first-stage output node through the first common-source cascode shielded transistor, resulting in voltage amplification, improving the gain, and thus improving the detection performance.
[0028] In summary, this application enables the pixel front-end circuit to simultaneously meet the requirements of low power consumption, high uniformity, and high detection performance within a limited area. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is a schematic diagram of a pixel front-end circuit structure provided in an embodiment of this application.
[0031] Figure label:
[0032] Main bias current transistor—M0, source follower transistor—M1, first cascode shielded transistor—M2, load current source—M3, first feedback transistor—M4, second feedback transistor—M5, limiting transistor—M6, load transistor—M7, input transistor—M8, second cascode shielded transistor—M9, feedback capacitor—Cs. Detailed Implementation
[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0034] The purpose of this application is to provide a pixel front-end circuit, a pixel sensor, and a detector system, which aims to enable the pixel front-end circuit to simultaneously meet the requirements of low power consumption, high uniformity, and high detection performance within a limited area.
[0035] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0036] In one exemplary embodiment, such as Figure 1 As shown, a pixel front-end circuit is provided, including: an input stage and a charge transfer amplification branch, a bias and baseline setting network, and a discrimination output stage and a second common-source cascode shielding module;
[0037] The input stage and charge transfer amplification branch include: a source follower transistor M1, a first common-source shielded transistor M2, a load current source M3, and a current feedback network; the current feedback network includes: a feedback capacitor Cs, a first feedback transistor M4, and a second feedback transistor M5; the gate of the load current source M3 is controlled by the current feedback network.
[0038] The bias and baseline setting network includes: a main bias current transistor M0 and a threshold current and baseline recovery circuit; the threshold current and baseline recovery circuit includes a first feedback transistor M4 and a second feedback transistor M5; the main bias current transistor M0 is used to provide a main bias current in the nanoampere range;
[0039] The output stage and the second common-source cascode shielding module are distinguished by: load transistor M7, second common-source cascode shielding transistor M9, and input transistor M8.
[0040] As an optional implementation, in the input stage and charge transfer amplification branch, the gate of the source follower transistor M1 is connected to the input node, and the source of the source follower transistor M1 is connected to the charge transfer node; the input node is directly connected to the ohmic contact of the N-type collector well of the sensor to receive the collected charge from the N-type collector well; the source of the first cascode shielded transistor M2 is connected to the drain of the source follower transistor M1, the drain of the first cascode shielded transistor M2 is connected to the first stage output node, and the gate of the first cascode shielded transistor M2 is connected to the first PMOS bias voltage (i.e., the first P-type transistor bias voltage); the source of the load current source transistor M3 is grounded, and the load current... The drain of source transistor M3 is connected to the first-stage output node; the gate of load current source transistor M3 is connected to the feedback node; one end of feedback capacitor Cs is connected to the charge transfer node, and the other end of feedback capacitor Cs, the drain of the first feedback transistor M4, and the drain of the second feedback transistor M5 are all connected to the feedback node; the gate of the first feedback transistor M4 is connected to the second PMOS bias voltage (i.e., the second P-transistor bias voltage), and the source of the first feedback transistor M4 is connected to the power supply voltage; the source of the second feedback transistor M5 is connected to the first-stage output node, and the gate of the second feedback transistor M5 is connected to the first NMOS bias voltage (i.e., the first N-transistor bias voltage).
[0041] Specifically, the gate of the source follower transistor M1 is connected to the input node, and its source is connected to the charge transfer node. This allows it to sense the voltage change at the input node caused by charge collection and buffer this voltage change to the charge transfer node with a gain close to 1. The calculation formula is: .in, In order to collect the charge, The total capacitance of the input node includes the collector junction capacitance, the reset transistor parasitic capacitance, and the gate capacitance of the source follower transistor M1.
[0042] The first cascode shielded transistor M2 is a shielded transistor, which greatly suppresses the effect of Miller parasitic capacitance between the input node and the first-stage output node, preventing variations in this parasitic capacitance from causing voltage gain issues. Uncontrollable changes occur between pixels. , This is the amplified positive voltage transition generated at the first-stage output node.
[0043] The gate of the load current source M3 is controlled by the current feedback network, providing a current sinking path for the first common-source cascode shielded transistor M2.
[0044] The feedback capacitor Cs has a dual function: (1) it serves as the source capacitor of the source follower transistor M1 to store charge; (2) it serves as the current feedback capacitor to stabilize the bias point of the load current source M3.
[0045] The charge transfer gain of the input stage and the charge transfer amplification branch is as follows: when the input node collects charge... As the voltage decreases, the voltage at the charge transfer node also decreases, causing some of the charge stored on the feedback capacitor Cs to be transferred to the capacitor at the first-stage output node through the first cascode transistor M2. Since the design satisfies the condition that the feedback capacitor Cs >> the capacitor at the first-stage output node, an amplified positive voltage jump is generated at the first-stage output node. : The typical feedback capacitor Cs has a value of 10fF, which is the capacitance of the first-stage output node. The value is 1fF, which can achieve a voltage gain of about 10 times.
[0046] As an optional implementation, in the bias and baseline setting network, the gate of the main bias current transistor M0 is connected to the third PMOS bias voltage (i.e., the third P-transistor bias voltage), the source of the main bias current transistor M0 is connected to the power supply voltage, and the drain of the main bias current transistor M0 is connected to the charge transfer node.
[0047] Specifically, the main bias current transistor M0 provides the main bias current, which is set to 20nA. The main bias current determines the quiescent operating current of the source follower transistor M1 and the load current source M3, forming the cornerstone of the circuit's low power consumption. The first feedback transistor M4 and the second feedback transistor M5 constitute the discharge current path for the first-stage output node. The bias and baseline setting network has two functions: 1) In the absence of a signal, it balances the current with the load current source M3 to jointly set the quiescent DC voltage (baseline) of the first-stage output node; 2) After a signal is received, it is responsible for pulling the voltage of the first-stage output node back to the baseline. The reference discharge current generated by the bias and baseline setting network and the first NMOS bias voltage determine the charge threshold Qth of the pixel front-end circuit.
[0048] As an optional implementation, in the output stage and the second cascode shielding module, the gate of the load transistor M7 is connected to the fourth PMOS bias voltage (i.e., the fourth P-transistor bias voltage), the source of the load transistor M7 is connected to the power supply voltage, and the drain of the load transistor M7 is connected to the second-stage output node; the gate of the second cascode shielding transistor M9 is connected to the second NMOS bias voltage (i.e., the second N-transistor bias voltage), the drain of the second cascode shielding transistor M9 is connected to the second-stage output node, the source of the second cascode shielding transistor M9 is connected to the drain of the input transistor M8, the source of the input transistor M8 is grounded, and the gate of the input transistor M8 is connected to the first-stage output node.
[0049] Specifically, the fourth PMOS bias voltage connected to the gate of the load transistor M7 is a fixed bias voltage, providing an active load for the input transistor M8, and together with the input transistor M8, determining the transconductance and gain of the second stage; the input transistor M8 compares the analog voltage signal of the first stage output node with a threshold voltage indirectly set by a reference discharge current; the second cascode shielded transistor M9 is inserted between the drain of the input transistor M8 and the second stage output node, and the second NMOS bias voltage connected to its gate is a fixed bias voltage. The core function of the second cascode shielded transistor M9 is to shield the gate-drain parasitic capacitance CP1 of the input transistor M8. Changes in CP1 directly modulate the effective gate voltage of the input transistor M8, thus severely affecting the uniformity of the charge threshold. The introduction of the second cascode shielded transistor M9 isolates the second stage output node from CP1, significantly reducing the sensitivity of the charge threshold to changes in CP1. This is the second key measure to improve the uniformity of the charge threshold. When the voltage of the first stage output node is higher than the threshold, the input transistor M8 conducts more strongly, the voltage of the second stage output node is pulled low, generating a low-level effective hit pulse.
[0050] As an optional implementation, the pixel front-end circuit also includes a pulse limiting module;
[0051] The pulse limiting module includes: limiting transistor M6;
[0052] The gate of the limiting transistor M6 is connected to the fifth PMOS bias voltage (i.e., the fifth P-transistor bias voltage), the source of the limiting transistor M6 is connected to the feedback node, and the drain of the limiting transistor M6 is connected to the first-stage output node.
[0053] Specifically, the pulse limiting module is connected in a controllable manner (voltage mode). In this case, the bias voltage of the fifth PMOS connected to the gate of the limiting transistor M6 is an independent limiting control voltage. By adjusting the second PMOS bias voltage, the amount of input charge at which the pulse begins to be compressed (clipping point) can be precisely set, providing flexibility for system debugging and optimization. The function of the pulse limiting module is to effectively compress the width (duration) of the pulse signal output by the second-stage output node for large input charges exceeding the design range, preventing it from becoming too long. This significantly improves the time response uniformity between signals of different amplitudes and simplifies the design of the subsequent gating window.
[0054] In addition, the pulse limiting module can also be connected in a standard connection (diode mode): the gate and drain of the limiting transistor M6 are connected to the feedback node, and the source is connected to the first-stage output node. When the voltage of the first-stage output node rises very high due to a large signal, causing the gate-source voltage of the limiting transistor M6 to exceed its threshold, the limiting transistor M6 turns on, providing an additional, powerful discharge path for the first-stage output node.
[0055] As an optional implementation, the source follower transistor M1, the first cascode shielded transistor M2, the load current source M3, the main bias current transistor M0, the first feedback transistor M4, the second feedback transistor M5, the load transistor M7, the second cascode shielded transistor M9, the input transistor M8, and the limiting transistor M6 are all metal-oxide-semiconductor field-effect transistors; each metal-oxide-semiconductor field-effect transistor is configured to operate in the weak inversion region.
[0056] Specifically, the bias voltage of each metal-oxide-semiconductor field-effect transistor is set near its threshold voltage to ensure operation in the subthreshold region (weak inversion).
[0057] As an optional implementation, the source follower transistor M1, the load current source M3, the main bias current transistor M0, the first feedback transistor M4, the second feedback transistor M5, the load transistor M7, the input transistor M8, and the limiting transistor M6 are all metal-oxide-semiconductor field-effect transistors.
[0058] Both the first cascode transistor M2 and the second cascode transistor M9 are gain bootstrap operational amplifiers.
[0059] As an optional implementation, the feedback capacitor Cs is a metal-insulator-metal (MIM) capacitor.
[0060] Specifically, the following operations were performed when setting up the pixel front-end circuit of this application: Monte Carlo process deviation simulation was performed on all transistors in the circuit to evaluate the impact coefficient (sensitivity) of their mismatch on the charge threshold Qth; based on the sensitivity, the gate area of each metal-oxide-semiconductor field-effect transistor was scaled inversely. Metal-oxide-semiconductor field-effect transistors with a large impact on Qth (such as M0, M4, M5, M7, and M8) were allocated a larger area to reduce the random mismatch of their threshold voltage Vth. The bias voltage of each metal-oxide-semiconductor field-effect transistor was set near its threshold voltage to ensure operation in the subthreshold region (weak inversion). In this region, the transconductance to current ratio of each metal-oxide-semiconductor field-effect transistor is the largest, enabling the achievement of the required gain and speed with the minimum bias current, which is key to achieving nanowatt-level power consumption. During layout design, techniques such as symmetrical layout and shared centroid were used to draw current mirrors with high matching requirements.
[0061] Compared to related pixel front-end amplifier circuits (such as conventional charge-sensitive amplifiers or transconductance amplifiers), the pixel front-end circuit of this application has the following significant advantages: 1. Ultra-low power consumption: All transistors operate in the weak inversion region. 2. High charge threshold uniformity: The first cascode transistor M2 shields the input stage gain from parasitic capacitance variations; the second cascode transistor M9 shields the discrimination stage from the gate-drain capacitance variations of M8; based on Monte Carlo transistor size optimization, the Vth mismatch effect is systematically reduced. 3. High time response uniformity:
[0062] Optimizing the size of the first feedback transistor M4 reduces discharge current variation; optimizing the size of the limiting transistor M6 or using voltage control with the second PMOS bias voltage stabilizes the clipping point; the second cascode shielded transistor M9 stabilizes the capacitive load of the second-stage output node. 4. High detection performance: The charge transfer mechanism provides high voltage gain; low noise design and high uniformity. 5. Design flexibility: The second PMOS bias voltage pin provides adjustable pulse limiting functionality.
[0063] In one exemplary embodiment, a pixel sensor is provided, including a pixel array, wherein at least one pixel unit in the pixel array includes the pixel front-end circuitry of any of the above.
[0064] In one exemplary embodiment, a detector system is provided, including the pixel sensor and data acquisition circuit described above;
[0065] The data acquisition circuit is connected to the second-stage output node of the pixel front-end circuit in each pixel unit and is used to receive pulse signals.
[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0067] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the circuit and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. In summary, the content of this specification should not be construed as a limitation of this application.
Claims
1. A pixel front-end circuit, characterized in that, The pixel front-end circuit includes: an input stage and a charge transfer amplification branch, a bias and baseline setting network, and a discrimination output stage and a second common-source common-gate shielding module; The input stage and charge transfer amplification branch include: a source follower transistor, a first common-source shielded transistor, a load current source transistor, and a current feedback network; the current feedback network includes: a feedback capacitor, a first feedback transistor, and a second feedback transistor; the gate of the load current source transistor is controlled by the current feedback network; The bias and baseline setting network includes: a main bias current transistor and a threshold current and baseline recovery circuit; the threshold current and baseline recovery circuit includes a first feedback transistor and a second feedback transistor; the main bias current transistor is used to provide a main bias current in the nanoampere range; The discrimination output stage and the second common source cascode shielding module include: a load transistor, a second common source cascode shielding transistor, and an input transistor; In the input stage and charge transfer amplification branch, the gate of the source follower transistor is connected to the input node, and the source of the source follower transistor is connected to the charge transfer node. The input node is directly connected to the ohmic contact of the N-type collector well of the sensor to receive the collected charge from the N-type collector well. The source of the first common-source gate shielded transistor is connected to the drain of the source follower transistor, and the drain of the first common-source gate shielded transistor is connected to the first-stage output node. The gate of the first common-source gate shielded transistor is connected to the first PMOS bias voltage. The source of the load current source transistor is grounded, and the drain of the load current source transistor is connected to the first-stage output node. The gate of the load current source transistor is connected to the feedback node. One end of the feedback capacitor is connected to the charge transfer node, and the other end of the feedback capacitor, the drain of the first feedback transistor, and the drain of the second feedback transistor are all connected to the feedback node. The gate of the first feedback transistor is connected to the second PMOS bias voltage, and the source of the first feedback transistor is connected to the power supply voltage. The source of the second feedback transistor is connected to the first-stage output node, and the gate of the second feedback transistor is connected to the first NMOS bias voltage.
2. The pixel front-end circuit according to claim 1, characterized in that, In the bias and baseline setting network, the gate of the main bias current transistor is connected to the third PMOS bias voltage, the source of the main bias current transistor is connected to the power supply voltage, and the drain of the main bias current transistor is connected to the charge transfer node.
3. The pixel front-end circuit according to claim 2, characterized in that, In the discrimination output stage and the second common source common gate shielding module, the gate of the load transistor is connected to the fourth PMOS bias voltage, the source of the load transistor is connected to the power supply voltage, and the drain of the load transistor is connected to the second stage output node. The gate of the second common-source cascode shielded transistor is connected to the second NMOS bias voltage, the drain of the second common-source cascode shielded transistor is connected to the second-stage output node, the source of the second common-source cascode shielded transistor is connected to the drain of the input transistor, the source of the input transistor is grounded, and the gate of the input transistor is connected to the first-stage output node.
4. The pixel front-end circuit according to claim 3, characterized in that, The pixel front-end circuit also includes a pulse limiting module; The pulse limiting module includes: a limiting transistor; The gate of the limiting transistor is connected to the fifth PMOS bias voltage, the source of the limiting transistor is connected to the feedback node, and the drain of the limiting transistor is connected to the first-stage output node.
5. The pixel front-end circuit according to claim 4, characterized in that, The source follower transistor, the first common-source cascode shielded transistor, the load current source transistor, the main bias current transistor, the first feedback transistor, the second feedback transistor, the load transistor, the second common-source cascode shielded transistor, the input transistor, and the limiting transistor are all metal-oxide-semiconductor field-effect transistors; each metal-oxide-semiconductor field-effect transistor is configured to operate in the weak inversion region.
6. The pixel front-end circuit according to claim 4, characterized in that, The source follower transistor, the load current source transistor, the main bias current transistor, the first feedback transistor, the second feedback transistor, the load transistor, the input transistor, and the limiting transistor are all metal-oxide-semiconductor field-effect transistors. Both the first cascode shielded transistor and the second cascode shielded transistor are gain bootstrap operational amplifiers.
7. The pixel front-end circuit according to claim 1, characterized in that, The feedback capacitor is a MIM capacitor.
8. A pixel sensor, characterized in that, It includes a pixel array, wherein at least one pixel unit in the pixel array comprises a pixel front-end circuit as described in any one of claims 1-7.
9. A detector system, characterized in that, Includes the pixel sensor and data acquisition circuit as described in claim 8; The data acquisition circuit is connected to the second-stage output node of the pixel front-end circuit in each pixel unit, and is used to receive pulse signals.