A semiconductor device with a more uniform thermal stress distribution across a chip surface

Abstract

The application provides a semiconductor device with more uniform thermal stress distribution on the chip surface, which comprises a substrate of a first conductive type, a plurality of rows of units arranged along the longitudinal direction on the substrate, and a plurality of units arranged along the transverse direction in each row, wherein the units are active units, dummy units or dummy gate units; the active units, the dummy units and the dummy gate units are arranged in any proportion in the transverse direction and the longitudinal direction; the thermal stress on the surface of the semiconductor device is customized by adjusting the proportion of the active units, the dummy units and the dummy gate units in different regions or the length of the source region of the active units or the spacing of the units or the mesa width of the units. The semiconductor device adopts a non-repetitive unit structure layout, and the chip surface temperature is adjusted according to the designer's requirements by adjusting the unit layout or the unit structure; the thermal gradient on the chip surface can be reduced, the large thermal mechanical stress borne by the semiconductor package can be reduced, and the service life and reliability of the device and the interconnection structure thereof can be prolonged.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and more specifically to a semiconductor device with a more uniform distribution of thermal stress on the chip surface. Background Technology

[0002] Semiconductor power devices with trench gate structures, such as trench-type insulated-gate bipolar transistors (IGBTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs), have a gate contact that is electrically isolated from the rest of the transistor structure by a suitable dielectric material (e.g., silicon dioxide). This dielectric material controls the device, allowing it to switch between a blocking and conducting state, or vice versa. Modern IGBT designs may incorporate many different design elements to achieve ideal device performance, such as cells that do not form a metal-oxide-semiconductor (MOS) channel (inactive cells), regions with floating p-well layers, or additional trenches connected to the emitter potential (virtual trenches). Virtual cells, active cells, and virtual gate cells can be laid out with or without floating p-well layers to provide electric field protection at the bottom of the gate trench and improve switching performance. These structures are typically repeated to form the active region of a semiconductor device. For example, Chinese patent document CN117936573A discloses an IGBT semiconductor structure and its manufacturing method.

[0003] However, for large-area semiconductors, the thermal stress distribution on the chip surface can be very uneven, with temperature differences reaching tens of degrees Celsius. For example... Figure 1 In the diagram, 'a' represents the temperature gradient map of the chip surface in the existing technology. Figure 1 Curve A in section b represents the cross-sectional temperature gradient along the diagonal. The average surface temperature of the emitter metallization on an IGBT chip is usually referred to as the junction temperature, denoted by Tj. Due to the temperature gradient, the thermal stress experienced by the semiconductor device during operation can cause premature degradation of the package interconnect structure (such as solder layers or bonding wires). Therefore, it is necessary to modify the temperature distribution on the chip surface to reduce the temperature gradient. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor device with a more uniform distribution of thermal stress on the chip surface. It adopts a non-repetitive cell structure layout, and the chip surface temperature can be adjusted according to the designer's needs by adjusting the cell layout or cell structure. This can reduce the thermal gradient on the chip surface, alleviate the large thermomechanical stress borne by the semiconductor package, and extend the life and reliability of the device and its interconnect structure.

[0005] To address the aforementioned problems, this invention provides a semiconductor device with a more uniform thermal stress distribution on the chip surface, comprising a substrate of a first conductivity type, on which multiple rows of units are arranged longitudinally, and each row has multiple units arranged laterally, the units being active units, virtual units, or virtual gate units; the active units, virtual units, and virtual gate units are arranged in any proportion in both the lateral and longitudinal directions; the multiple rows of units on the semiconductor device are divided into a central region, a side region, and a corner region by a grid pattern; the thermal stress on the surface of the semiconductor device is customized by adjusting the proportion of active units, virtual units, and virtual gate units in different regions, or by adjusting the length of the source region of the active units in different regions, or by adjusting the spacing between units in different regions, or by adjusting the mesa width of the units in different regions.

[0006] Preferably, the active unit includes two first gate trenches disposed in the substrate, a first body region of a second conductivity type, a highly doped first source region of a first conductivity type, a first contact region, and a first enhancement region of a first conductivity type; the first body region, the first source region, and the first enhancement region are located between the two first gate trenches, the first source region is located above the first body region, the first enhancement region is located below the first body region, and the first contact region is used to connect the first body region and the gate; the first gate trenches are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the first gate trenches are connected to the gate contacts;

[0007] The virtual cell includes two first emitter trenches disposed in the substrate, a second body region of a second conductivity type, a second contact region, and a second reinforcement region of a first conductivity type; the second body region and the second reinforcement region are located between the two first emitter trenches; the second reinforcement region is located below the second body region; the second contact region is used to connect the second body region and the emitter; the first emitter trenches are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the first emitter trenches are connected to the emitter contacts.

[0008] The virtual gate cell includes two second gate trenches disposed in the substrate, a third body region of a second conductivity type, a third contact region, and a third enhancement region of a first conductivity type; the third body region and the third enhancement region are located between the two second gate trenches; the third enhancement region is located below the third body region; the third contact region is used to connect the third body region and the gate; the second gate trenches are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the second gate trenches are connected to the gate contacts.

[0009] Preferably, the active unit includes two second emitter trenches, a third gate trench, a fourth body region of a second conductivity type, a second source region of a first conductivity type, a fourth contact region, and a fourth enhancement region of a first conductivity type disposed in the substrate; the third gate trench is disposed between the two second emitter trenches; the fourth body region, the second source region, and the fourth enhancement region are located between the second emitter trench and the third gate trench, the second source region is located above the fourth body region, the fourth enhancement region is located below the fourth body region, and the fourth contact region is used to connect the fourth body region and the gate; the third gate trench and the second emitter trench are electrically isolated from other parts of the semiconductor device through a dielectric layer, the third gate trench is connected to the gate, and the second emitter trench is connected to the emitter;

[0010] The virtual cell includes three third emitter trenches disposed in the substrate, a fifth body region of the second conductivity type, a fifth contact region, and a fifth enhancement region of the first conductivity type; the fifth body region and the fifth enhancement region are located between the three third emitter trenches; the fifth enhancement region is located below the fifth body region, and the fifth contact region is used to connect the fifth body region and the emitter; the third emitter trenches are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the third emitter trenches are connected to the emitter.

[0011] The virtual gate cell includes two fourth emitter trenches, a fourth gate trench, a sixth body region of the second conductivity type, a sixth contact region, and a sixth enhancement region of the first conductivity type, all disposed in the substrate. The fourth gate trench is disposed between the two fourth emitter trenches. The sixth body region and the sixth enhancement region are located between the fourth emitter trench and the fourth gate trench. The sixth enhancement region is located below the sixth body region, and the sixth contact region is used to connect the sixth body region and the gate. The fourth emitter trench and the fourth gate trench are electrically isolated from other parts of the semiconductor device through a dielectric layer. The fourth gate trench is connected to the gate, and the fourth emitter trench is connected to the emitter.

[0012] Preferably, one side of the emitter trench is provided with a highly doped region of a second conductivity type that is electrically levitated.

[0013] Preferably, the proportion of active units in the central region is less than the proportion of active units in the side regions, which in turn is less than the proportion of active units in the corner regions.

[0014] Preferably, the length of the source region of the active unit in the central region is less than the length of the source region of the active unit in the side region, which is less than the length of the source region of the active unit in the corner region.

[0015] Preferably, the spacing between units in the central region is less than the spacing between units in the side regions, which in turn is less than the spacing between units in the corner regions.

[0016] Preferably, the tabletop width of the unit in the central region is less than the tabletop width of the unit in the side region, which is less than the tabletop width of the unit in the corner region.

[0017] Preferably, the ratio of active cells, virtual cells, and virtual gate cells in each region remains unchanged to maintain the ratio of gate to emitter. By removing part of the contact area between emitter trenches or part of the contact area and source area between emitter trenches and gate trenches, more inactive cells are formed, reducing the current density in the center of the semiconductor device and making the thermal stress distribution on the chip surface uniform.

[0018] Preferably, a first gate electrode with a heavily doped polysilicon layer is disposed at the top of the gate trench; in some regions where the first contact area of ​​the active cell is located, the polysilicon layer is partially interrupted; in some regions where the first contact area of ​​the active cell is located, the polysilicon layer is partially uninterrupted and is transformed into an inactive cell by omitting the first source region; a second gate electrode with a heavily doped polysilicon layer is disposed at the top of the emitter trench, and the second gate electrode is interrupted from the first gate electrode along the longitudinal direction; by adjusting the ratio of active cells and inactive cells in different regions, the thermal stress on the surface of the semiconductor device is customized.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] The semiconductor device of the present invention, which has a more uniform distribution of thermal stress on the chip surface, adopts a non-repetitive unit structure layout, namely active unit, virtual unit, and virtual gate unit. By adjusting the unit layout or unit structure, the chip surface temperature can be adjusted according to the designer's needs. The chip surface temperature distribution can present a variety of modes, such as the highest temperature at the center and the lowest and gentler temperature at the edge, or the highest temperature at the edge and the lowest temperature at the center.

[0021] The semiconductor device of the present invention provides a more uniform distribution of thermal stress on the chip surface. It adopts a non-repetitive unit structure layout. By adjusting the unit layout or unit structure, the current density in the central region of the chip surface can be reduced, thereby reducing the thermal gradient on the chip surface (especially the significant non-uniform thermal gradient present in large-area chips), alleviating the stress at the contact points of the emitter bonding leads, and reducing the mechanical stress borne by the solder layer connecting the chip to the shell and subsequent layers, thus extending the life and reliability of the device and its interconnect structure.

[0022] The semiconductor device of the present invention provides a more uniform distribution of thermal stress on the chip surface, and can be based on temperature-related parameters (such as on-state voltage drop V). ce,on The junction temperature estimation method provides a better solution because the junction temperature distribution on the chip surface is more uniform. Attached Figure Description

[0023] Figure 1 This is a diagram showing the temperature gradient on the chip surface and the temperature gradient along the diagonal of the cross section in the prior art and embodiments of the present invention. Figure 1 In the diagram, 'a' represents the temperature gradient on the chip surface. Figure 1In Figure b, the temperature gradient diagram of the chip surface along the diagonal a is shown; where A represents the prior art, and B and C represent embodiments of the present invention.

[0024] Figure 2 This is a top view of a semiconductor device with a more uniform distribution of thermal stress on the chip surface in various embodiments of the present invention;

[0025] Figure 3 This is a top view of each unit in the semiconductor device with a more uniform distribution of thermal stress on the chip surface in embodiments 1-4 of the present invention;

[0026] Figure 4 This is a schematic diagram of the unit arrangement in Embodiment 1 of the present invention; the proportion of active units decreases from A to B to C; wherein, AC is an active unit, DC is a virtual unit, and DGC is a virtual gate unit;

[0027] Figure 5 This is a schematic diagram showing the reduction in the length of the source region within the active unit in Embodiment 2 of the present invention; the length of the source region within the active unit decreases from A to B to C;

[0028] Figure 6 This is a schematic diagram of the change in unit spacing in Embodiment 3 of the present invention; where d is the unit spacing. Figure 6 b is Figure 6 A schematic diagram showing the reduced spacing between elements a;

[0029] Figure 7 This is a schematic diagram of the change in tabletop width in Embodiment 4 of the present invention; where d is the tabletop width. Figure 7 b is Figure 7 A schematic diagram showing the increased width of platform a.

[0030] Figure 8 This is a schematic diagram of the structure of each unit in the semiconductor device with a more uniform thermal stress distribution on the chip surface in Embodiment 5 of the present invention; wherein, Figure 8 In the diagram, 'a' represents the top view of each unit. Figure 8 In diagram b, the active unit is shown in a longitudinal cross-sectional view.

[0031] Figure 9 This is a schematic diagram of the arrangement of units in the semiconductor device in embodiments 5, 6, and 7 of the present invention; Figure 9 In Figure a, it is a schematic diagram of the arrangement of cells in the semiconductor device in Example 5. By adjusting the ratio of active / inactive cells, the thermal stress on the chip surface is adjusted, and the ratio of active cells decreases from A to B to C. Figure 9 Figure b is a schematic diagram of the arrangement of cells in the semiconductor device in Example 6. Compared with Example 5, the ratio of active / inactive cells remains unchanged. The thermal stress on the chip surface is adjusted by omitting the contact area between the emitter trenches. Figure 9Figure c is a schematic diagram of the arrangement of cells in the semiconductor device in Example 7. Compared with Example 5, the ratio of active / inactive cells remains unchanged. The thermal stress on the chip surface is adjusted by omitting the contact area and source area at the gate trench. In each figure, E is the emitter trench and G is the gate trench.

[0032] Figure 10 This is a top view of the semiconductor device according to Embodiment 8 of the present invention; Figure 10 b is Figure 10 A schematic diagram showing how the active unit in part a becomes an inactive unit after the source region is omitted.

[0033] Wherein: 1-Active cell; 11-Gate trench; 12-Body region; 13-Source region; 14-Contact region; 15-Enhancement region; 16-Floating p-type well region; 2-Dummy cell; 21-Emitter trench; 22-Body region; 23-Contact region; 24-Enhancement region; 25-Floating p-type well region; 3-Dummy gate cell; 31-Gate trench; 32-Body region; 33-Contact region; 34-Enhancement region; 35-Floating p-type well region; 4-Center region; 5-Side region; 6-Corner region; 7-Active cell; 71-Emitter trench; 72-Gate trench; 73-Body region; 74-Source region; 75-Contact region; 76-Enhancement region; 77-Floating p-type well region; 8-Dummy cell; 81-Emitter trench; 82-Floating p-type well region; 83-Contact region; 9-Virtual gate cell; 91-Emitter trench; 92-Gate trench; 93-Floating p-type well region; 94-Contact region; 10-Gate electrode; 11-Gate electrode. Detailed Implementation

[0034] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0035] Example 1

[0036] This embodiment provides a semiconductor device with more uniform thermal stress distribution on the chip surface, comprising a substrate of a first conductivity type. Multiple rows of units are arranged longitudinally on the substrate, and each row has multiple units arranged laterally. The units are active units 1, virtual units 2, or virtual gate units 3; the active units 1, virtual units 2, and virtual gate units 3 are arranged in any proportion in both the transverse and longitudinal directions. For example... Figure 2As shown, the multiple rows of units on the semiconductor device are divided into a central region 4, a side region 5, and a corner region 6 in a grid pattern. In this embodiment, the thermal stress on the surface of the semiconductor device is customized by adjusting the ratio of active units 1, virtual units 2, and virtual gate units 3 in the central region 4, side regions 5, and corner regions 6.

[0037] like Figure 3 As shown, in this embodiment, the active unit 1 includes two gate trenches 11 disposed in the substrate, a body region 12 of the second conductivity type, a highly doped source region 13 of the first conductivity type, a contact region 14, and a reinforcement region 15 of the first conductivity type. The body region 12, source region 13, and reinforcement region 15 are located between the two gate trenches, with the source region 13 located above the body region 12 and the reinforcement region 15 located below the body region 12. The contact region 14 is used to connect the body region and the gate. The gate trenches are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the gate trenches are connected to the gate contacts. Preferably, an electrically floating highly doped region 16 of the second conductivity type (floating p-type well region) is provided on one side of the gate trench to change the charge balance inside the device.

[0038] The virtual cell 2 includes two emitter trenches 21 disposed in the substrate, a body region 22 of a second conductivity type, a contact region 23, and a reinforcement region 24 of a first conductivity type. The body region 22 and the reinforcement region 24 are located between the two emitter trenches 21. The reinforcement region 24 is located below the body region 22. The contact region 23 is used to connect the body region 22 and the emitter. The emitter trenches 21 are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the emitter trenches are connected to the emitter contacts. The virtual cell is a passive cell, that is, there is no electron injection region or it is located in a low current density region. Preferably, an electrically floating, highly doped region 25 of the second conductivity type (floating p-type well region) is provided on one side of the emitter trench to change the charge balance inside the device.

[0039] The virtual gate cell 3 includes two gate trenches 31 disposed in the substrate, a body region 32 of a second conductivity type, a contact region 33, and a reinforcement region 34 of a first conductivity type. The body region 32 and the reinforcement region 34 are located between the two gate trenches 31. The reinforcement region 34 is located below the body region 32. The contact region 33 is used to connect the body region 32 and the gate. The gate trenches 31 are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the gate trenches are connected to the gate contacts. The virtual gate cell is similar to the virtual cell. In this case, the trench is at the gate potential, rather than the emitter potential, which changes the charge distribution. Preferably, an electrically floating, highly doped region 35 of the second conductivity type (floating p-type well region) is provided on one side of the gate trench to change the charge balance inside the device.

[0040] In this embodiment, as Figure 4As shown, the thermal stress on the surface of a semiconductor device is customized by changing the layout ratio of active cells 1, dummy cells 2, and dummy gate cells 3. Specifically, more active cells 4 are arranged in the side regions 5 and corner regions 6 of the chip surface, while fewer active cells are arranged in the central region 4. More specifically, in the central region, the number of active cells 1 is greater than the number of passive dummy cells 2 or dummy gate cells 3. The specific number can be customized according to the specific requirements of the thermal stress on the surface of the semiconductor device. Any ratio is acceptable as long as the above description is met.

[0041] The above are preferred embodiments of the present invention, but another extreme case (such as...) Figure 1 The curve B in the middle (b), which shows a temperature distribution with higher temperatures at the corners and lower temperatures at the center, is also included in this invention.

[0042] Example 2

[0043] like Figure 5 As shown, this embodiment provides a semiconductor device with a more uniform distribution of thermal stress on the chip surface. The structure of the active unit 1, virtual unit 2, or virtual gate unit 3 is the same as that in embodiment 1. The difference from embodiment 1 is that the layout ratio of the active unit 1, virtual unit 2, and virtual gate unit 3 in the central region 4, side region 5, and corner region 6 of the semiconductor device is fixed. The current density on the chip surface is adjusted by increasing or decreasing the length of the n+ source region of the active unit, thereby adjusting the thermal stress.

[0044] Preferably, in this embodiment, the length of the source region of the active unit in the central region 4 is less than the length of the source region of the active unit in the side region 5, which is less than the length of the source region of the active unit in the corner region 6.

[0045] The above are preferred embodiments of the present invention, but another extreme case (such as...) Figure 1 The curve B in the middle (b), which shows a temperature distribution with higher temperatures at the corners and lower temperatures at the center, is also included in this invention.

[0046] Example 3

[0047] like Figure 6 As shown, this embodiment provides a semiconductor device with a more uniform distribution of thermal stress on the chip surface. The structure of the active unit 1, virtual unit 2, or virtual gate unit 3 is the same as that in embodiment 1. The difference from embodiment 1 is that the layout ratio of the active unit 1, virtual unit 2, and virtual gate unit 3 in the central region 4, side region 5, and corner region 6 of the semiconductor device is fixed. By adjusting the unit spacing, the current density on the chip surface is adjusted, thereby adjusting the thermal stress.

[0048] Specifically, as a preferred embodiment, a smaller cell spacing is used in the central region 4 of the chip surface, that is, the cell spacing in the central region is less than the cell spacing in the side region and less than the cell spacing in the corner region.

[0049] The above are preferred embodiments of the present invention, but another extreme case (such as...) Figure 1 The curve B in the middle (b), which shows a temperature distribution with higher temperatures at the corners and lower temperatures at the center, is also included in this invention.

[0050] Example 4

[0051] like Figure 7 As shown, this embodiment provides a semiconductor device with a more uniform distribution of thermal stress on the chip surface. The structure of the active unit 1, virtual unit 2, or virtual gate unit 3 is the same as that in embodiment 1. The difference from embodiment 1 is that the layout ratio of the active unit 1, virtual unit 2, and virtual gate unit 3 in the central region 4, side region 5, and corner region 6 of the semiconductor device is fixed. The current density on the chip surface is adjusted by adjusting the width of the mesa, thereby adjusting the thermal stress.

[0052] Specifically, as a preferred embodiment, a smaller mesa width is used in the central region 4 of the chip surface, that is, the mesa width of the cell in the central region < the mesa width of the cell in the side region < the mesa width of the cell in the corner region.

[0053] The above are preferred embodiments of the present invention, but another extreme case (such as...) Figure 1 The curve B in the middle (b), which shows a temperature distribution with higher temperatures at the corners and lower temperatures at the center, is also included in this invention.

[0054] In the above embodiments, the ratio of active cells, virtual cells, and virtual gate cells, the source region length, the cell spacing, and the mesa width can be arbitrarily combined and configured to customize the thermal stress on the chip surface.

[0055] Example 5

[0056] like Figure 9 As shown in Figure a, this embodiment of a semiconductor device with more uniform thermal stress distribution on the chip surface includes a substrate of a first conductivity type. Multiple rows of units are arranged longitudinally on the substrate, and each row has multiple units arranged laterally. The units are active units 7, virtual units 8, or virtual gate units 9; the active units 7, virtual units 8, and virtual gate units 9 are arranged in any proportion in both the transverse and longitudinal directions. Figure 2As shown, the multiple rows of units on the semiconductor device are divided into a central region 4, a side region 5, and a corner region 6 in a grid pattern. In this embodiment, the thermal stress on the surface of the semiconductor device is customized by adjusting the ratio of active units 7, virtual units 8, and virtual gate units 9 in the central region 4, side region 5, and corner region 6.

[0057] In this embodiment, the structures of the active unit 7, the virtual unit 8, and the virtual gate unit 9 are different from those in Embodiment 1.

[0058] like Figure 8 As shown, in this embodiment, the active unit 7 includes two emitter trenches 71, a gate trench 72, a body region 73 of a second conductivity type, a source region 74 of a first conductivity type, a contact region 75, and a reinforcement region 76 of a first conductivity type disposed in the substrate; the gate trench 72 is disposed between the two emitter trenches 71; the body region 73, the source region 74, and the reinforcement region 76 are located between the emitter trenches 71 and the gate trench 72, with the source region 74 located above the body region 73 and the reinforcement region 76 located below the body region 73; the contact region 75 is used to connect the body region 73 and the gate; the gate trench 72 and the emitter trench 71 are electrically isolated from other parts of the semiconductor device through a dielectric layer, the gate trench 72 is connected to the gate, and the emitter trench 71 is connected to the emitter. Preferably, an electrically floating, highly doped region 77 of the second conductivity type (floating p-type well region) is provided on one side of the emitter trench to change the charge balance inside the device.

[0059] The virtual cell 8 includes three emitter trenches 81 disposed in the substrate, a body region of a second conductivity type (not shown), a contact region 83, and a reinforcement region of a first conductivity type (not shown). The body region and the reinforcement region are located between the three emitter trenches 81. The reinforcement region is located below the body region, and the contact region 83 is used to connect the body region and the emitter. The emitter trenches 81 are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the emitter trenches 81 are connected to the emitter. The virtual cell is a passive cell, that is, there is no electron injection region or it is located in a low current density region. Preferably, an electrically floating, highly doped region 82 of the second conductivity type (floating p-type well region) is provided on one side of the emitter trench to change the charge balance inside the device.

[0060] The virtual gate cell 9 includes two emitter trenches 91, a gate trench 92, a body region of a second conductivity type (not shown), a contact region 94, and a reinforcement region of a first conductivity type (not shown) disposed in the substrate. The gate trench 92 is located between the two emitter trenches 91; the body region and the reinforcement region are located between the emitter trenches 91 and the gate trench 92; the reinforcement region is located below the body region, and the contact region 94 is used to connect the body region and the gate; the emitter trenches 91 and the gate trench 92 are electrically isolated from other parts of the semiconductor device through a dielectric layer, the gate trench 92 is connected to the gate, and the emitter trench 91 is connected to the emitter. The virtual gate cell is similar to the virtual cell. In this case, the trench is at the gate potential, not the emitter potential, which changes the charge distribution. Preferably, an electrically floating, highly doped region 93 of the second conductivity type (floating p-type well region) is provided on one side of the emitter trench to change the charge balance inside the device.

[0061] In this embodiment, the thermal stress on the surface of the semiconductor device is customized by changing the layout ratio of active cells 7, dummy cells 8, and dummy gate cells 9. Specifically, more active cells 7 are arranged in the side regions 5 and corner regions 6 of the chip surface, while fewer active cells are arranged in the central region 4 of the chip surface. More specifically, in the central region, the number of active cells 1 is greater than the number of passive dummy cells 2 or dummy gate cells 3. The specific number can be customized according to the specific requirements of the thermal stress on the surface of the semiconductor device. Any ratio is acceptable as long as the above description is met.

[0062] Furthermore, this embodiment can also use a fixed layout ratio of active units 7, dummy units 8, and dummy gate units 9 in the central region 4, side region 5, and corner region 6 of the semiconductor device. By increasing or decreasing the length of the n+ source region of the active units, the current density on the chip surface can be adjusted, thereby regulating the thermal stress. Specifically, the length of the source region of the active unit in the central region 4 is less than the length of the source region of the active unit in the side region 5, which is less than the length of the source region of the active unit in the corner region 6.

[0063] This embodiment can also employ a fixed layout ratio of active units 7, virtual units 8, and virtual gate units 9 in the central region 4, side region 5, and corner region 6 of the semiconductor device. By adjusting the unit spacing, the current density on the chip surface can be adjusted, thereby regulating thermal stress. Specifically, the unit spacing in the central region is less than the unit spacing in the side region, which in turn is less than the unit spacing in the corner region.

[0064] This embodiment can also use a fixed layout ratio of active units 7, virtual units 8, and virtual gate units 9 in the central region 4, side region 5, and corner region 6 of the semiconductor device. By adjusting the mesa width, the current density on the chip surface can be adjusted, thereby regulating the thermal stress. Specifically, the mesa width of the unit in the central region is less than the mesa width of the unit in the side region, which is less than the mesa width of the unit in the corner region.

[0065] In this embodiment, the ratio of active cells, virtual cells, and virtual gate cells, the source region length, the cell spacing, and the mesa width can be arbitrarily combined and configured to customize the thermal stress on the chip surface.

[0066] The above are preferred embodiments of the present invention, but another extreme case (see Figure 1 b), that is, the temperature distribution showing a higher temperature at the corners and a lower temperature at the center, is also included in this invention.

[0067] Example 6

[0068] like Figure 9 As shown in Figure b, this embodiment provides a semiconductor device with a more uniform distribution of thermal stress on the chip surface. The structure of the active unit 1, the virtual unit 2, or the virtual gate unit 3 is the same as that in Embodiment 2. The difference from Embodiment 2 is that the layout ratio of the active unit 1, the virtual unit 2, and the virtual gate unit 3 in the central region 4, the side region 5, and the corner region 6 of the semiconductor device is fixed to maintain the ratio of the gate to the emitter. By removing part of the contact area between the emitter trenches, more inactive units are formed, reducing the current density in the central part of the semiconductor device and making the thermal stress distribution on the chip surface more uniform.

[0069] Example 7

[0070] like Figure 9 As shown in Figure c, this embodiment provides a semiconductor device with a more uniform distribution of thermal stress on the chip surface. The structure of the active unit 1, the virtual unit 2, or the virtual gate unit 3 is the same as that in Embodiment 2. The difference from Embodiment 2 is that the layout ratio of the active unit 1, the virtual unit 2, and the virtual gate unit 3 in the central region 4, the side region 5, and the corner region 6 of the semiconductor device is fixed to maintain the ratio of the gate to the emitter. By removing part of the contact area and source region between the emitter trench and the gate trench, more inactive units are formed, reducing the current density in the central part of the semiconductor device and making the thermal stress distribution on the chip surface more uniform.

[0071] Example 8

[0072] like Figure 10As shown, this embodiment provides a semiconductor device with a more uniform thermal stress distribution on the chip surface. The structures of the active unit 1, virtual unit 2, or virtual gate unit 3 are the same as in Embodiment 1. A gate electrode 10 with a heavily doped polysilicon layer is provided at the top of the gate trench. In some areas where the contact region of the active unit is located, the polysilicon layer is partially interrupted; in some areas where the contact region of the active unit is located, the polysilicon layer is partially uninterrupted and is transformed into an inactive unit by omitting the source region. A gate electrode 11 with a heavily doped polysilicon layer is provided at the top of the emitter trench. The gate electrode 11 is interrupted from the gate electrode 10 along the longitudinal direction. By adjusting the ratio of active units and inactive units in different regions, the thermal stress on the surface of the semiconductor device is customized.

[0073] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor device with more uniform thermal stress distribution on the chip surface, characterized in that: The device includes a substrate of the first conductivity type, on which multiple rows of units are arranged longitudinally, and each row has multiple units arranged laterally. The units are active units, virtual units, or virtual gate units. The active units, virtual units, and virtual gate units are arranged in any proportion in the lateral and longitudinal directions. The multiple rows of units on the semiconductor device are divided into central regions, side regions, and corner regions by a grid pattern. The thermal stress on the surface of the semiconductor device is customized by adjusting the proportion of active units, virtual units, and virtual gate units in different regions, or by adjusting the length of the source region of the active units in different regions, or by adjusting the spacing between units in different regions, or by adjusting the mesa width of the units in different regions. The active unit includes two first gate trenches disposed in a substrate, a first body region of a second conductivity type, a highly doped first source region of a first conductivity type, a first contact region, and a first enhancement region of a first conductivity type. The first body region, the first source region, and the first enhancement region are located between the two first gate trenches, with the first source region located above the first body region and the first enhancement region located below the first body region. The first contact region is used to connect the first body region and the gate. The first gate trenches are electrically isolated from other parts of the semiconductor device through a dielectric layer and are connected to the gate contacts. The virtual cell includes two first emitter trenches disposed in the substrate, a second body region of a second conductivity type, a second contact region, and a second reinforcement region of a first conductivity type; the second body region and the second reinforcement region are located between the two first emitter trenches. The second enhancement region is located below the second body region; the second contact region is used to connect the second body region and the emitter; the first emitter trench is electrically isolated from other parts of the semiconductor device through the dielectric layer, and the first emitter trench is connected to the emitter contact. The virtual gate cell includes two second gate trenches disposed in the substrate, a third body region of a second conductivity type, a third contact region, and a third enhancement region of a first conductivity type; the third body region and the third enhancement region are located between the two second gate trenches; the third enhancement region is located below the third body region; the third contact region is used to connect the third body region and the gate; the second gate trenches are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the second gate trenches are connected to the gate contacts.

2. The semiconductor device with more uniform thermal stress distribution on the chip surface according to claim 1, characterized in that: The active unit includes two second emitter trenches, a third gate trench, a fourth body region of a second conductivity type, a second source region of a first conductivity type, a fourth contact region, and a fourth enhancement region of a first conductivity type disposed in the substrate; the third gate trench is disposed between the two second emitter trenches; the fourth body region, the second source region, and the fourth enhancement region are located between the second emitter trench and the third gate trench, the second source region is located above the fourth body region, the fourth enhancement region is located below the fourth body region, and the fourth contact region is used to connect the fourth body region and the gate; The third gate trench and the second emitter trench are electrically isolated from other parts of the semiconductor device through a dielectric layer. The third gate trench is connected to the gate, and the second emitter trench is connected to the emitter. The virtual cell includes three third emitter trenches disposed in the substrate, a fifth body region of the second conductivity type, a fifth contact region, and a fifth enhancement region of the first conductivity type; the fifth body region and the fifth enhancement region are located between the three third emitter trenches. The fifth enhancement region is located below the fifth body region, and the fifth contact region is used to connect the fifth body region and the emitter; the third emitter trench is electrically isolated from other parts of the semiconductor device through the dielectric layer, and the third emitter trench is connected to the emitter; The virtual gate cell includes two fourth emitter trenches, a fourth gate trench, a sixth body region of the second conductivity type, a sixth contact region, and a sixth enhancement region of the first conductivity type, all disposed in the substrate. The fourth gate trench is disposed between the two fourth emitter trenches. The sixth body region and the sixth enhancement region are located between the fourth emitter trench and the fourth gate trench. The sixth enhancement region is located below the sixth body region, and the sixth contact region is used to connect the sixth body region and the gate. The fourth emitter trench and the fourth gate trench are electrically isolated from other parts of the semiconductor device through a dielectric layer. The fourth gate trench is connected to the gate, and the fourth emitter trench is connected to the emitter.

3. The semiconductor device with more uniform thermal stress distribution on the chip surface according to claim 1 or 2, characterized in that: One side of the emitter trench or gate trench is provided with a highly doped region of a second conductivity type that is electrically floating.

4. The semiconductor device with more uniform thermal stress distribution on the chip surface according to claim 1 or 2, characterized in that: The proportion of active cells in the central region is less than the proportion of active cells in the side regions, which is less than the proportion of active cells in the corner regions.

5. The semiconductor device with more uniform thermal stress distribution on the chip surface according to claim 1 or 2, characterized in that: The length of the source region of the active cell in the central region is less than the length of the source region of the active cell in the side region, which is less than the length of the source region of the active cell in the corner region.

6. The semiconductor device with more uniform thermal stress distribution on the chip surface according to claim 1 or 2, characterized in that: The spacing between units in the central area is less than the spacing between units in the side areas, which in turn is less than the spacing between units in the corner areas.

7. The semiconductor device with more uniform thermal stress distribution on the chip surface according to claim 1 or 2, characterized in that: The tabletop width of the unit in the central area is less than the tabletop width of the unit in the side area, which in turn is less than the tabletop width of the unit in the corner area.

8. The semiconductor device with more uniform thermal stress distribution on the chip surface according to claim 2, characterized in that: The ratio of active cells, virtual cells, and virtual gate cells in each region remains unchanged to maintain the ratio of gate to emitter. By removing some of the contact areas between emitter trenches or some of the contact areas and source areas between emitter trenches and gate trenches, more inactive cells are formed, reducing the current density in the center of the semiconductor device and making the thermal stress distribution on the chip surface more uniform.

9. The semiconductor device with more uniform thermal stress distribution on the chip surface according to claim 1, characterized in that: A first gate electrode with a heavily doped polysilicon layer is disposed at the top of the gate trench. In some regions where the first contact area of ​​active cells is located, the polysilicon layer is partially interrupted; in some regions where the first contact area of ​​active cells is located, the polysilicon layer is not interrupted and is transformed into an inactive cell by omitting the first source region. A second gate electrode with a heavily doped polysilicon layer is disposed at the top of the emitter trench. The second gate electrode is interrupted from the first gate electrode in the longitudinal direction. By adjusting the ratio of active cells to inactive cells in different regions, the thermal stress on the surface of the semiconductor device is customized.

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