Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a display area and a binding area located on one side of the display area in the first direction. The display area comprises a first sub-display area and a second sub-display area; the data signal line comprises a first data signal line located in the first sub-display area and a second data signal line located in the second sub-display area; the data transmission line is connected with the second data signal line and extends to the binding area. The data transmission line comprises a first transmission line extending in the second direction and a second transmission line extending in the first direction. The display substrate further comprises an insulating layer located between the first transmission line and the second transmission line, and the second end of the first transmission line and the first through hole are at least partially overlapped in the direction perpendicular to the substrate. When the density of the data signal lines and the density of the data transmission lines are large, the second transmission lines in the data transmission lines are at least partially overlapped with the first via holes in the insulating layer, and wiring arrangement is facilitated.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0002] As people continue to pursue better visual effects in display products, high resolution (PPI, Pixels Per Inch) and narrow bezels are gradually becoming the development trend of organic light-emitting diode (OLED) display products. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a display substrate and a display device.

[0004] At least one embodiment of this disclosure provides a display substrate, comprising: a display area and a bonding area located on one side of the display area along a first direction; the size of the display area along a second direction perpendicular to the first direction is greater than the size of the bonding area along the second direction, the edge of the display area near the bonding area is a bonding edge, the display area includes a first sub-display area that at least partially overlaps with the bonding area in the first direction and a second sub-display area located on at least one side of the first sub-display area and not overlapping with the bonding area in the first direction; a plurality of data signal lines, at least partially located within the display area, extending along the first direction and arranged along the second direction, the plurality of data signal lines including a first data signal line located within the first sub-display area and a second data signal line located within the second sub-display area; and a data transmission line, connected to the second data... The signal line is connected and extends to the bonding area. At least a portion of the data transmission line includes a first transmission line and a second transmission line, the first transmission line extending along a second direction and the second transmission line extending along the first direction; wherein a first end of the first transmission line is connected to the second data signal line to form a first connection point; the display substrate further includes a substrate, and both the data signal line and the data transmission line are disposed on the substrate; the display substrate further includes an insulating layer located between the first transmission line and the second transmission line, and a second end of the first transmission line is connected to one end of the second transmission line through a first via in the insulating layer to form a second connection point; both the first connection point and the second connection point are located within the display area; the second end of the first transmission line and the first via at least partially overlap in a direction perpendicular to the substrate.

[0005] For example, according to at least one embodiment of this disclosure, the data signal line and the first transmission line are disposed on different layers; the second transmission line includes a first transmission sublayer and a second transmission sublayer, the first transmission sublayer and the first transmission line are disposed on the same layer, the second transmission sublayer and the data signal line are disposed on the same layer, and the first transmission sublayer and the second transmission sublayer are electrically connected through a second via in the insulating layer; the distance between the center line connecting the orthographic projection of the second via on the substrate and the orthographic projection of the first via on the substrate is a first distance, and the distance between the orthographic projection of the second via on the substrate and the orthographic projection of the first transmission line on the substrate in the first direction is a second distance; the ratio of the first distance to the second distance is 0.9-1.1.

[0006] For example, according to at least one embodiment of this disclosure, the data transmission line includes multiple data transmission lines to be connected to a corresponding number of second data signal lines. Each of the multiple data transmission lines is provided with a plurality of first connection points and a plurality of second connection points. The plurality of first connection points are located in the second sub-display area, and the plurality of second connection points are located in the first sub-display area. The plurality of first connection points, as the corresponding second data signal line moves further away from the first sub-display area, are closer to the edge of the second sub-display area away from the first sub-display area, and further away from the binding edge. Similarly, the plurality of second connection points, as the corresponding second data signal line moves further away from the second sub-display area, are further away from the boundary line between the first and second sub-display areas, and further away from the binding edge. The area where the first transmission line is located is a first fan-out area, and the area where the second transmission line is located is a second fan-out area. Within the first fan-out area, the length of the first transmission line of the multiple data transmission lines increases sequentially in the direction away from the binding edge. Within the second fan-out area, the length of the second transmission line of the multiple data transmission lines increases sequentially in the direction away from the boundary line between the first and second sub-display areas.

[0007] For example, according to at least one embodiment of this disclosure, the first transmission line of the plurality of data transmission lines is arranged along the first direction, and the second transmission line of the plurality of data transmission lines is arranged along the second direction.

[0008] For example, according to at least one embodiment of this disclosure, the display substrate further includes a first connection line located in the first fan-out region and extending along the first direction, the first connection line being disconnected from the data transmission line; the display substrate includes a first source / drain metal layer and a second source / drain metal layer, the first source / drain metal layer being located between the second source / drain metal layer and the substrate; the display substrate further includes a first power supply voltage lead, the first transmission line being located in the first source / drain metal layer, the second data signal line and at least a portion of the first power supply voltage lead being located in the second source / drain metal layer; the first connection line being electrically connected to the first power supply voltage lead, the first power supply voltage lead being configured to provide a high-level signal.

[0009] For example, according to at least one embodiment of the present disclosure, the second transmission sublayer includes a plurality of sub-parts spaced apart in the first direction, each sub-part having a contact pad at at least one end in the first direction; the contact pad and the second via at least partially overlap in a direction perpendicular to the substrate, such that the contact pad is electrically connected to the first source / drain metal layer through the second via.

[0010] For example, according to at least one embodiment of the present disclosure, the first connection line includes a first portion and a second portion that are electrically connected; the first portion is located in the first source / drain metal layer, the second portion is located in the second source / drain metal layer, and the orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the second portion on the substrate.

[0011] For example, according to at least one embodiment of the present disclosure, the first part includes a connecting body portion and a first connecting portion connected to at least one side of the connecting body portion along the second direction, the first connecting portion being electrically connected to the first power supply voltage lead.

[0012] For example, according to at least one embodiment of the present disclosure, at least a portion of the extension direction of the first connecting line and at least a portion of the extension direction of the second transmission line are on the same straight line; the two ends of the first connecting line located between two adjacent first transmission lines are respectively disconnected from a corresponding first transmission line through a first break in the first direction; the adjacent first connecting lines and second transmission lines in the first direction are disconnected from each other through a second break.

[0013] For example, according to at least one embodiment of the present disclosure, the display substrate further includes a driving transistor and a power control transistor, wherein a first terminal of the power control transistor is electrically connected to the first power supply voltage lead, and a second terminal of the power control transistor is electrically connected to the first terminal of the driving transistor.

[0014] For example, according to at least one embodiment of this disclosure, the display substrate further includes a second connecting line located in the second fan-out region and extending along the second direction, the second connecting line being disconnected from the data transmission line; the display substrate further includes a gate metal layer located between the substrate and the first source / drain metal layer; the first transmission line and the second connecting line are located in the first source / drain metal layer, the second data signal line is located in the second source / drain metal layer, the gate metal layer further includes a plurality of initialization signal lines extending along the second direction and arranged along the first direction; the second connecting line is electrically connected to the initialization signal line; the extension direction of the second connecting line is on the same straight line as the extension direction of the first transmission line; adjacent second connecting lines and first transmission lines in the second direction are disconnected from each other through a third break, and the two ends of the second connecting line located between two adjacent second transmission lines in the second direction are disconnected from the second transmission lines through a fourth break.

[0015] For example, according to at least one embodiment of the present disclosure, the gate metal layer includes a first gate metal layer, the initialization signal line includes a first initialization signal line located in the first gate metal layer and extending along a first direction; the second connection line includes a second connection portion extending along the first direction toward a side away from the bonding region, the second connection portion at least partially overlapping the first initialization signal line in a direction perpendicular to the substrate, and the second connection portion being electrically connected to the first initialization signal line.

[0016] For example, according to at least one embodiment of the present disclosure, at least one of the third break and the fourth break overlaps at least partially with the first initialization signal line in a direction perpendicular to the substrate.

[0017] For example, according to at least one embodiment of the present disclosure, the second source / drain metal layer further includes a plurality of initialization compensation lines arranged along the second direction, each of the initialization compensation lines extending along the first direction and disposed between two adjacent first power supply voltage leads, the initialization compensation lines being electrically connected to the initialization signal lines; the second transmission line is located between two adjacent second data signal lines, and the first power supply voltage lead is located on the side of the second data signal line away from the second transmission line.

[0018] For example, according to at least one embodiment of the present disclosure, the sub-pixel includes a compensation transistor and a first reset transistor, the first terminal of the compensation transistor is electrically connected to the second terminal of the driving transistor, the second terminal of the compensation transistor is electrically connected to the gate of the driving transistor, the first terminal of the first reset transistor is electrically connected to the corresponding first initialization signal line, and the second terminal of the first reset transistor is electrically connected to the second terminal of the driving transistor.

[0019] For example, according to at least one embodiment of the present disclosure, the gate metal layer includes a second gate metal layer; the second gate metal layer includes a plurality of second initialization signal lines extending along the second direction and arranged in the first direction and a plurality of third initialization signal lines; one of the second initialization signal lines and the third initialization signal lines is electrically connected to a corresponding second connection line.

[0020] For example, according to at least one embodiment of the present disclosure, the second connecting line is electrically connected to the second initialization signal line, the second connecting line includes a third connecting portion extending along the first direction toward a side away from the binding region, and one of the second initialization signal line and the third initialization signal line is electrically connected to the third connecting portion.

[0021] For example, according to at least one embodiment of this disclosure, the initialization compensation line includes a first initialization compensation line, a second initialization compensation line, and a third initialization compensation line located in the second source / drain metal layer. The first initialization compensation line is electrically connected to the first initialization signal line, the second initialization compensation line is electrically connected to the second initialization signal line, and the third initialization compensation line is electrically connected to the third initialization signal line. The first initialization compensation line, the second initialization compensation line, and the third initialization compensation line are arranged sequentially along the second direction.

[0022] For example, according to at least one embodiment of the present disclosure, the sub-pixel includes a second reset transistor and a light-emitting element, wherein the first terminal of the second reset transistor is electrically connected to a corresponding second initialization signal line, and the second terminal of the second reset transistor is electrically connected to the anode of the light-emitting element.

[0023] For example, according to at least one embodiment of this disclosure, the display substrate further includes a second reset signal line, the gate of the first reset transistor being coupled to a corresponding second reset signal line; the second reset signal line and the second initialization signal line are disposed on different layers and at least partially overlap in a direction perpendicular to the substrate; the first break includes a first sub-break and a second sub-break opposite to each other in the first direction, the first sub-break being further away from the bonding edge than the second sub-break; the first sub-break at least partially overlaps with the second reset signal line in a direction perpendicular to the substrate; at least one of the second sub-break and the second break at least partially overlaps with the anode of the light-emitting element in a direction perpendicular to the substrate.

[0024] For example, according to at least one embodiment of the present disclosure, the sub-pixel further includes a third reset transistor, the first terminal of which is electrically connected to the corresponding third initialization signal line, and the second terminal of which is electrically connected to the first terminal of the driving transistor.

[0025] For example, according to at least one embodiment of the present disclosure, the first transmission line includes a main body portion and a connecting portion connected to each other, the main body portion extending along a second direction and the connecting portion extending along a first direction; the end of the connecting portion away from the main body portion includes a first connection point, the first connection point being closer to the bonding region in the first direction than the main body portion.

[0026] For example, according to at least one embodiment of the present disclosure, the display substrate further includes a third transmission line located in the second sub-display area and extending along the second direction, the extension direction of the third transmission line being on the same straight line as the extension direction of the first transmission line and disconnected from each other by a fifth break; the display substrate further includes a second power supply voltage lead and a light-emitting element, the second power supply voltage lead being configured to provide a low-level signal, the third transmission line being electrically connected to the second power supply voltage lead, and the second power supply voltage lead being electrically connected to the cathode of the light-emitting element.

[0027] For example, according to at least one embodiment of the present disclosure, the fifth break point at least partially overlaps with the first initialization signal line in a direction perpendicular to the substrate.

[0028] For example, according to at least one embodiment of the present disclosure, the display substrate further includes a fourth transmission line located in the second sub-display area and extending along the first direction, wherein the orthographic projection of the fourth transmission line on the substrate is located between the orthographic projections of two adjacent first data signal lines on the substrate; the display substrate further includes a second power supply voltage lead and a light-emitting element, wherein the second power supply voltage lead is configured to provide a low-level signal, the fourth transmission line is electrically connected to the second power supply voltage lead, and the second power supply voltage lead is electrically connected to the cathode of the light-emitting element.

[0029] At least one embodiment of this disclosure provides a display device including the display substrate described in any of the above embodiments. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0031] Figure 1 This is a schematic diagram of a portion of the film layers in a display substrate.

[0032] Figure 2 This is a schematic plan view of the display substrate provided in at least one embodiment of the present disclosure.

[0033] Figure 3 This is a stack-up diagram of a portion of the film layers of a display substrate provided in at least one embodiment of the present disclosure.

[0034] Figure 4 This is an equivalent circuit diagram of the pixel circuit of a display substrate provided as an example in at least one embodiment of the present disclosure.

[0035] Figures 5A to 5H This is a schematic diagram of different film layers in a display substrate provided in at least one embodiment of the present disclosure.

[0036] Figure 5I 5A to Figure 5H The diagram shows the stacked layers of the films.

[0037] Figure 6 This is a stack-up diagram of a portion of the film layers in a display substrate provided as an example in at least one embodiment of the present disclosure.

[0038] Figure 7 This is a stacked diagram of a portion of the film layers in a display substrate provided in at least one embodiment of the present disclosure.

[0039] Figure 8 and Figure 9 This is a stack-up diagram of a portion of the film layers in a display substrate provided in at least one embodiment of the present disclosure. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0042] The terms "parallel," "perpendicular," and "identical" as used in this disclosure include the strict meanings of "parallel," "perpendicular," and "identical," as well as terms such as "approximately parallel," "approximately perpendicular," and "approximately identical," which include a certain degree of error. Considering the measurement and the errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. The term "center" in the embodiments of this disclosure can include a position strictly located at the geometric center as well as a position approximately at the center within a small area surrounding the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component is implied to mean that the component can be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two. The term "same layer" in the embodiments of this disclosure refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). Here, "same layer" does not always mean that the multiple film layers have the same thickness or the same height in a cross-sectional view.

[0043] With the development of OLED display technology, consumers have increasingly higher requirements for the display effect of OLED display devices. Adopting a narrow bezel design is an important measure to improve the display effect of OLED display devices, and an important technology to achieve a narrow bezel is to use FIP (Fanout In Pixel) technology.

[0044] FIP (Fanout In Panel) technology uses fan-out wiring within the pixel area to reduce the space occupied by peripheral circuits, thus narrowing the bezel. For example, a display substrate includes a display area and a bonding area. The bonding area is used to bond with external driving circuits or chips. Signal lines in the display area, such as data lines, can be led out to the bonding area via adapter cables located in the fanout region, thereby bonding with the external driving circuits or chips. After completing the connection of the data lines and adapter cables, floating, dummy leads can be connected to the VSS (Vanout Signal Support) signal, also known as SIP (VSS in Panel) technology.

[0045] Figure 1 This is a schematic diagram of a portion of the film layers in a display substrate.

[0046] like Figure 1As shown, the display substrate includes a first source / drain metal layer SD01 and a second source / drain metal layer SD02. A data line DA0 located in the second source / drain metal layer SD02 extends along a first direction Y. The display substrate includes a first adapter line L01 located in the first source / drain metal layer SD01 and extending along a second direction X, and a second adapter line L02 located in the second source / drain metal layer SD02 and extending along the first direction Y. Signal lines in the first source / drain metal layer SD01 (e.g., the first adapter line L01) and signal lines in the second source / drain metal layer SD02 (e.g., the second adapter line L02) can be electrically connected at locations requiring electrical connection via adapter holes PLN1. The first adapter line L01 is disconnected from other leads FD in the same circuit row via a break point OP, and the second adapter line L02 is disconnected from other leads in the same circuit column via a break point, thereby enabling data signal transmission.

[0047] refer to Figure 1 Because of the large spacing between signal lines, the circuit row containing the first adapter line L01 can bypass the adapter hole PLN1, for example, it can be bypassed. Therefore, the first adapter line L01 will not be divided into multiple segments due to the presence of the adapter hole PLN1, resulting in fewer redundant leads due to disconnection. For similar reasons, there are also relatively few redundant leads within a circuit row, making it easier to connect redundant leads in the fan-out area to the VSS signal to prevent lead floating.

[0048] In their research, the inventors of this application discovered that in some high-PPI display products, the display area contains a high density of sub-pixels for display, each sub-pixel including a light-emitting device and a pixel circuit driving the light-emitting device. As pixel density increases, the wiring space in the pixel circuit becomes limited. Consequently, the spacing between the first transition lines in the first source / drain metal layer decreases, making it difficult for the first transition lines within a circuit row to bypass the transition holes.

[0049] Therefore, after connecting the data cable and the adapter cable, the number of redundant floating leads within a circuit row or column increases due to the presence of adapter holes. These floating leads are then distributed in segments within the fan-out area. Consequently, as pixel density increases, the difficulty of routing increases, necessitating a new FIP routing method.

[0050] At least one embodiment of this disclosure provides a display substrate, comprising: a display area and a bonding area located on one side of the display area along a first direction; the dimension of the display area along a second direction perpendicular to the first direction is greater than the dimension of the bonding area along the second direction, the edge of the display area near the bonding area is a bonding edge, the display area includes a first sub-display area that at least partially overlaps with the bonding area in the first direction and a second sub-display area located on at least one side of the first sub-display area and not overlapping with the bonding area in the first direction; a plurality of data signal lines, at least partially located within the display area, extending along the first direction and arranged along the second direction, the plurality of data signal lines including a first data signal line located within the first sub-display area and a second data signal line located within the second sub-display area; and a data transmission line, connected to the second... A data signal line is connected and extends to the bonding area. At least a portion of the data transmission line includes a first transmission line and a second transmission line. The first transmission line extends along a second direction, and the second transmission line extends along the first direction. A first end of the first transmission line is connected to the second data signal line to form a first connection point. The display substrate further includes a substrate, and both the data signal line and the data transmission line are disposed on the substrate. The display substrate also includes an insulating layer located between the first transmission line and the second transmission line. A second end of the first transmission line is connected to one end of the second transmission line through a first via in the insulating layer to form a second connection point. Both the first connection point and the second connection point are located within the display area. The second end of the first transmission line and the first via at least partially overlap in a direction perpendicular to the substrate.

[0051] A display device includes the display substrate described above.

[0052] The display substrate and display device provided in at least one embodiment of this disclosure, when the density of data signal lines and data transmission lines is high, such as in some high PPI display products, allow the first transmission line extending along the second direction to pass through the first via, which is beneficial for the arrangement of the traces.

[0053] The display substrate and display device are described below with reference to the accompanying drawings and through some embodiments.

[0054] Figure 2 This is a schematic plan view of the display substrate provided in at least one embodiment of the present disclosure. Figure 3 This is a stack-up diagram of a portion of the film layers of a display substrate provided in at least one embodiment of the present disclosure. Figure 3 Schematic illustration Figure 2 The layer stack diagram in the lower left corner of the image.

[0055] refer to Figure 2 and Figure 3 At least one embodiment of this disclosure provides a display substrate, including a display area AA and a bonding area BB located on one side of the display area AA along a first direction Y. The dimension D1 of the display area AA along a second direction X perpendicular to the first direction Y is greater than the dimension D2 of the bonding area BB along the second direction X.

[0056] refer to Figure 2 and Figure 3 The edge of the display area AA near the binding area BB is the binding edge B1. The display area AA includes a first sub-display area 01 that at least partially overlaps with the binding area BB in the first direction Y, and a second sub-display area 02 located on at least one side of the first sub-display area 01 and not overlapping with the binding area BB in the first direction Y. For example, the second sub-display area 02 may be located on both sides of the first sub-display area 01 in the second direction X. For example, the second sub-display area may be located only on one side of the first sub-display area in the second direction, and this disclosure is not limited thereto. For example, the first sub-display area 01 may completely overlap with the binding area BB in the first direction Y. For example, the first sub-display area may also partially overlap with the binding area in the first direction, and partially not overlap, and this disclosure is not limited thereto.

[0057] refer to Figure 2 and Figure 3 The display substrate includes multiple data signal lines DA, which are at least partially located within the display area AA, extending along a first direction Y and arranged along a second direction X. The multiple data signal lines DA include a first data signal line DA1 located within a first sub-display area 01 and a second data signal line DA2 located within a second sub-display area 02. For example, the first data signal line DA1 located within the first sub-display area 01 may extend along the first direction Y to the bonding area BB.

[0058] refer to Figure 2 and Figure 3 The data transmission line 100 is connected to the second data signal line DA2 and extends to the bonding area BB. For example, the second data signal line DA2 located in the second sub-display area 02 can be led out to the bonding area BB through the data transmission line 100. For example, the above-mentioned fan-out method of adding the data transmission line 100 can be called display area fan-out (FIAA) or pixel fan-out (FIP).

[0059] refer to Figure 2 and Figure 3The data transmission line 100 includes at least a first transmission line 110 and a second transmission line 120, the first transmission line 110 extending along a second direction X and the second transmission line 120 extending along a first direction Y. For example, the data transmission line 100 is generally a zigzag line. The first end 111 of the first transmission line 110 is connected to the second data signal line DA2 to form a first connection point P1.

[0060] refer to Figure 2 and Figure 3 The display substrate also includes a substrate 1, on which data signal lines DA and data transmission lines 100 are disposed. The display substrate further includes an insulating layer PLN located between the first transmission line 110 and the second transmission line 120. The second end 112 of the first transmission line 110 and one end of the second transmission line 120 are connected through a first via PLN1 in the insulating layer PLN to form a second connection point P2. Both the first connection point P1 and the second connection point P2 are located within the display area AA. For example, the first end 111 and the second end 112 of the first transmission line 110 are disposed approximately opposite each other in the second direction X.

[0061] refer to Figure 2 and Figure 3 The second end 112 and the first via PLN1 at least partially overlap in a direction perpendicular to the substrate. For example, the orthographic projection of the second end 112 on the substrate may cover the orthographic projection of the first via PLN1 on the substrate. For example, the second end and the first via may partially overlap and partially not overlap, and this disclosure is not limiting in this regard.

[0062] refer to Figure 2 and Figure 3 The display substrate provided in this embodiment can facilitate the routing of the first transmission line 110 extending along the second direction X through the first via PLN1 when the density of the data signal line DA and the data transmission line 100 is high, such as in some high PPI display products.

[0063] refer to Figure 2 and Figure 3 In some examples, the data signal line DA and the first transmission line 110 are disposed on different layers. For example, the data signal line DA and the first transmission line 110 are located in different layers of a plurality of film layers of the display substrate. For example, in conjunction with the example described later, the data signal line DA is located in the second source / drain metal layer SD2, and the first transmission line 110 is located in the first source / drain metal layer SD1.

[0064] refer to Figure 2 and Figure 3The second transmission line 120 includes a first transmission sublayer 121 and a second transmission sublayer 122. For example, the first transmission sublayer 121 and the second transmission sublayer 122 are located in different layers of a plurality of film layers in the display substrate. For example, in conjunction with the example described later, the first transmission sublayer 121 is located in the first source / drain metal layer SD1, and the second transmission sublayer 122 is located in the second source / drain metal layer SD2.

[0065] refer to Figure 2 and Figure 3 The first transmission sublayer 121 is disposed on the same layer as the first transmission line 110, and the second transmission sublayer 122 is disposed on the same layer as the data signal line DA. The first transmission sublayer 121 and the second transmission sublayer 122 are electrically connected. For example, the first transmission sublayer 121 and the second transmission sublayer 122 can be electrically connected through a second via PLN2 in the insulating layer PLN located between them.

[0066] refer to Figure 2 and Figure 3 The data signal line DA and the first transmission line 110 are arranged in different layers, allowing for the use of different film layers to arrange the patterns of the data signal line DA and the data transmission line 100. The first transmission sub-layer 121 and the second transmission sub-layer 122 of the first transmission line 110 are located on different layers, thus enabling the electrical connection between the data signal line DA and the first transmission line 110 using a jumper design. Therefore, when the density of the data signal line DA and the data transmission line 100 is high, using a jumper design for the data transmission line 100 helps reduce the space required for its arrangement, facilitating wiring.

[0067] refer to Figure 2 and Figure 3 The distance between the center lines connecting the orthographic projection of the second via PLN2 on the substrate 1 and the orthographic projection of the first via PLN1 on the substrate 1 is the first distance DT1. The distance between the orthographic projection of the second via PLN2 on the substrate 1 and the orthographic projection of the first transmission line 110 on the substrate 1 in the first direction Y is the second distance DT2. The ratio of the first distance DT1 to the second distance DT2 is 0.9-1.1. For example, Figure 3 The illustration shows that the first distance DT1 is equal to the second distance DT2, that is, the ratio of the first distance DT1 to the second distance DT2 is 1. However, this disclosure is not limited to this, such as the ratio of the first distance to the second distance being 0.95, or the ratio of the first distance to the second distance being 1.05, etc.

[0068] refer to Figure 2 and Figure 3In some examples, the data transmission line 100 includes multiple data transmission lines 100 to be connected to a corresponding number of second data signal lines DA2. For example, each second data signal line DA2 extends to the bonding area BB via a corresponding data transmission line 100.

[0069] refer to Figure 2 and Figure 3 Each data transmission line 100 has a corresponding first connection point P1 and a second connection point P2. The first connection points P1 are located in the second sub-display area 02, and the second connection points P2 are located in the first sub-display area 01. For example, a portion of the data transmission line 100 is located in the first sub-display area 01, and another portion is located in the second sub-display area 02.

[0070] refer to Figure 2 and Figure 3 Multiple first connection points P1 are located further away from the first sub-display area 01 and closer to the edge A1 of the second sub-display area 02 that is further away from the first sub-display area 01 and further away from the binding edge B1, depending on the corresponding second data signal line DA2. For example, the first connection point P1 of the second data signal line DA2 closest to the first sub-display area 01 is the closest to the binding edge B1 in the first direction Y. For example, multiple first connection points P1 are approximately located on or on both sides of the first straight line L1, and the extension direction of the first straight line L1 intersects the first direction Y and the second direction X, respectively.

[0071] refer to Figure 2 and Figure 3 The multiple second connection points P2 are located further away from the second sub-display area 02, the boundary line L between the first sub-display area 01 and the second sub-display area 02, and the binding edge B1 as the corresponding second data signal line DA2 moves away from it. For example, the second connection point P2 of the second data signal line DA2 closest to the first sub-display area 01 is the closest to the binding edge B1 in the first direction Y. For example, the multiple first connection points P1 are approximately located on or on both sides of the second straight line L2, the extension direction of the second straight line L2 intersecting the first direction Y and the second direction X, respectively.

[0072] refer to Figure 2 and Figure 3The area where the first transmission line 110 is located is the first fan-out area H, and the area where the second transmission line 120 is located is the second fan-out area V. Within the first fan-out area H, the lengths of the first transmission lines 110 of the multiple data transmission lines 100 increase sequentially in a direction away from the bonding edge B1. Within the second fan-out area V, the lengths of the second transmission lines 120 of the multiple data transmission lines 100 increase sequentially in a direction away from the boundary line L between the first sub-display area 01 and the second sub-display area 02. Therefore, the data transmission lines 100 connected to different second data signal lines DA2 will not overlap, which is beneficial for the arrangement of the first transmission lines 110 and the second transmission lines 120.

[0073] refer to Figure 2 and Figure 3 For example, the first straight line L1, the second straight line L2, and the boundary line L roughly divide the first sub-display area 01 and the second sub-display area 02 into a normal display area N, a first fan-out area H, and a second fan-out area V. For example, the first transmission line 110, which is farthest from the binding edge B1, has the longest length in the second direction X. For example, the second transmission line 120, which is farthest from the boundary line L, has the longest length in the first direction Y.

[0074] refer to Figure 2 and Figure 3 In some examples, the first transmission lines 110 of the multiple data transmission lines 100 are arranged along a first direction Y, and the second transmission lines 120 of the multiple data transmission lines 100 are arranged along a second direction X. For example, among two adjacent first transmission lines 110 in the first direction Y, the first transmission line 110 closer to the binding edge B1 is shorter in the second direction X. For example, among two adjacent second transmission lines 120 in the second direction X, the second transmission line 120 closer to the boundary line L is shorter in the first direction Y.

[0075] refer to Figure 2 and Figure 3 In some examples, the first transmission line 110 includes a main body portion 1101 and a connecting portion 1102 connected to each other. The main body portion 1101 extends along a second direction X, and the connecting portion 1102 extends along a first direction Y. The end of the connecting portion 1102 away from the main body portion 1101 includes a first connection point P1, which is closer to the bonding region BB in the first direction Y than the main body portion 1101. For example, the first connection point P1 can be a transition section of the first transmission line 110. For example, the transition section can be connected to the main body portion 1101 using the connecting portion 1102, and electrically connected to the second data signal line DA2 via the transition section.

[0076] Figure 4 This is an equivalent circuit diagram of the pixel circuit of a display substrate provided as an example in at least one embodiment of the present disclosure. Figures 5A to 5HThis is a schematic diagram of different film layers in a display substrate provided in at least one embodiment of the present disclosure. Figure 5I 5A to Figure 5H The diagram shows the stacked layers of the films. Figure 6 This is a stack-up diagram of a portion of the film layers in a display substrate provided as an example in at least one embodiment of the present disclosure.

[0077] refer to Figure 2 , Figures 4 to 6 For example, the display substrate includes a plurality of sub-pixels PX disposed on a substrate 1. Each sub-pixel PX includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a plurality of transistors and at least one capacitor. For example, the pixel circuit 10 includes a first reset transistor T1, a second reset transistor T7, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a power control transistor T5, a light-emitting control transistor T6, a third reset transistor T8, and a storage capacitor C.

[0078] refer to Figures 4 to 6 For example, the display substrate includes a first power supply voltage lead VDD, a second power supply voltage lead VSS, a data signal line DA, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a third initialization signal line Vinit3, a first reset signal line Rst1, a second reset signal line Rst2, scan lines, and a light emission control signal line EM. The scan lines include a first scan line G1 and a second scan line G2.

[0079] refer to Figures 4 to 6 The gate of the first reset transistor T1 is electrically connected to the corresponding second reset signal line Rst2, the first terminal of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, and the second terminal of the first reset transistor T1 is electrically connected to the second terminal of the driving transistor T3.

[0080] refer to Figures 4 to 6 The gate of compensation transistor T2 is electrically connected to the corresponding first scan line G1, the first terminal of compensation transistor T2 is electrically connected to the second terminal of driving transistor T3, and the second terminal of compensation transistor T2 is electrically connected to the gate of driving transistor T3. Compensation transistor T2 includes an oxide transistor.

[0081] refer to Figures 4 to 6 The gate of the data writing transistor T4 is electrically connected to the corresponding second scan line G2, the first terminal of the data writing transistor T4 is electrically connected to the corresponding data signal line DA, and the second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T3.

[0082] refer to Figures 4 to 6The gate of the power control transistor T5 is electrically connected to the corresponding light-emitting control signal line EM, the first terminal of the power control transistor T5 is electrically connected to the first power supply voltage lead VDD, and the second terminal of the power control transistor T5 is electrically connected to the first terminal of the driving transistor T3.

[0083] refer to Figures 4 to 6 The gate of the light-emitting control transistor T6 is electrically connected to the corresponding light-emitting control signal line EM. The first terminal of the light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T3. The second terminal of the light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element 20. The cathode of the light-emitting element 20 receives the low-level signal VSS.

[0084] refer to Figures 4 to 6 The gate of the second reset transistor T7 is electrically connected to the corresponding first reset signal line Rst1, the first terminal of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second terminal of the second reset transistor T7 is electrically connected to the anode of the light-emitting element 20.

[0085] refer to Figures 4 to 6 The gate of the third reset transistor T8 is electrically connected to the corresponding first reset signal line Rst1, the first terminal of the third reset transistor T8 is electrically connected to the third initialization signal transmission layer Vinit3, and the second terminal of the third reset transistor T8 is electrically connected to the first terminal of the driving transistor T3.

[0086] refer to Figures 4 to 6 The first plate Cst1 of the storage capacitor Cst is reused as the gate T3-g of the driving transistor T3, and the second plate Cst2 of the storage capacitor Cst is electrically connected to the first power supply voltage lead VDD.

[0087] It should be noted that, in the embodiments of this disclosure, each pixel circuit 10 can, in addition to being able to... Figure 4 In addition to the 8T1C (i.e., eight transistors and one capacitor) structure shown, other structures including other numbers of transistors are also possible, such as 7T1C, 7T2C, 6T1C, 6T2C or 9T2C structures. This disclosure does not limit the specific implementation of these structures.

[0088] refer to Figures 5A to 5IFor example, the display substrate includes a light-shielding layer BSM, a first active layer PL, a third gate metal layer gate1, a first gate metal layer gate2, a second active layer ZL, a second gate metal layer gate3, a first source / drain metal layer SD1, and a second source / drain metal layer SD2, which are sequentially stacked along a direction away from the substrate. For example, the third gate metal layer gate1, the first gate metal layer gate2, and the first source / drain metal layer SD1 can be electrically connected vias (ILDs) in the interlayer insulating layer between them. For example, the first active layer PL and the first source / drain metal layer SD1 can be electrically connected vias (ILDs) in the interlayer insulating layer. For example, the second active layer ZL and the second gate metal layer gate3 can be electrically connected vias (EBBs) in the interlayer insulating layer. For example, the first source / drain metal layer SD1 and the second source / drain metal layer SD2 can be electrically connected vias in the insulating layer between them, such as vias (PVX) in the passivation layer or vias (PLN) in the planarization layer.

[0089] It should be noted that, in the embodiments disclosed herein, the display substrate is only schematically shown to include two source / drain metal layers. However, this disclosure is not limited thereto, and the display substrate may include three source / drain metal layers.

[0090] refer to Figure 5A and Figure 5C For example, the light-shielding layer BSM includes multiple light-shielding patterns BSM0 and multiple first light-shielding connection portions BSM1. The multiple light-shielding patterns BSM0 are arranged in an array, and the orthographic projection of the light-shielding pattern BSM0 on the substrate can at least partially overlap with the orthographic projection of the gate T3-g of the corresponding driving transistor T3 on the substrate. For example, the orthographic projection of the light-shielding pattern on the substrate can completely cover the orthographic projection of the gate of the corresponding driving transistor on the substrate. For example, the material of the light-shielding layer can include a metallic material such as molybdenum (Mo). For example, the material of the light-shielding layer can include single-crystal silicon.

[0091] refer to Figure 5A For example, the first light-shielding connection portion BSM1 includes at least a portion extending along the first direction Y, and the first light-shielding connection portion BSM1 is electrically connected to the light-shielding pattern BSM0 adjacent along the first direction Y. The light-shielding layer BSM also includes a plurality of second light-shielding connection portions BSM2, each of which includes at least a portion extending along the second direction X, and the second light-shielding connection portion BSM2 is electrically connected to the light-shielding pattern BSM0 adjacent along the second direction X, such that the light-shielding layer BSM is formed into a grid-like structure.

[0092] refer to Figure 5B For example, the material of the first active layer PL may include semiconductor materials such as amorphous silicon, monocrystalline silicon, and polycrystalline silicon. Figure 5BThe dashed box schematically illustrates the region of a sub-pixel. For example, the first active layer PL can be used to fabricate the active layers of the aforementioned driving transistor T3, data writing transistor T4, power control transistor T5, light-emitting control transistor T6, second reset control transistor T7, and third reset control transistor T8 to form the channel regions of the aforementioned transistors. The first active layer PL includes the active layer pattern (channel region) and doped region pattern (source / drain region) of the aforementioned transistors in each sub-pixel, and the active layer pattern and doped region pattern of the aforementioned transistors in the same pixel circuit are integrally formed.

[0093] refer to Figure 5C For example, the first reset signal line Rst1, the second reset signal line Rst2, the second scan line G2, the first plate Cst1 of the storage capacitor Cst, and the light emission control signal line EM are all located in the third gate metal layer gate1.

[0094] refer to Figure 5D For example, the first initialization signal line Vinit1, the first sub-layer G101 of the first scan line G1, and the second plate Cst2 of the storage capacitor Cst are all located in the first gate metal layer gate2.

[0095] refer to Figure 5D For example, the first scan line G1 includes a first scan pattern G11 and a second scan pattern G12 alternately arranged in the second direction X. Adjacent first scan patterns G11 and second scan patterns G12 are electrically connected, and the size of the first scan pattern G11 along the first direction Y is larger than the size of the second scan pattern G12 along the first direction Y. The first scan pattern G11 is multiplexed as the gate T2-g of the corresponding compensation transistor T2.

[0096] refer to Figure 5C For example, the second scan line G2 includes a third scan pattern G21 and a fourth scan pattern G22 alternately arranged in the second direction X. Adjacent third scan patterns G21 and fourth scan patterns G22 are electrically connected, and the size of the third scan pattern G21 along the first direction Y is larger than the size of the fourth scan pattern G22 along the first direction Y.

[0097] refer to Figure 5C and Figure 5D For example, the first gate metal layer gate2 and the third gate metal layer gate1 respectively include the second plate Cst2 and the first plate Cst1 of the storage capacitor Cst.

[0098] refer to Figure 5EFor example, the material of the second active layer ZL may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). For example, the second active layer ZL can be used to fabricate the active layer of the aforementioned compensation transistor T2 to form the channel region of the transistor.

[0099] refer to Figure 5F For example, the second initialization signal line Vinit2, the third initialization signal line Vinit3, and the second sub-layer G102 of the first scan line G1 are all located in the second gate metal layer gate3.

[0100] refer to Figure 5D , Figure 5E and Figure 5F For example, in the first scan line G1, the first sub-layer G101 located in the first gate metal layer gate2 and the second sub-layer G102 located in the second gate metal layer gate3 overlap each other in a direction perpendicular to the substrate, and at least a portion of the second active layer ZL is located between the first sub-layer G101 and the second sub-layer G102 to form a compensation transistor T2 with a dual-gate structure. For example, the first sub-layer G101 and the second sub-layer G102 may respectively include a first scan pattern G11 and a second scan pattern G12, which is not limited in this disclosure.

[0101] Figure 5G and Figure 5H The first source / drain metal layer SD1 and the second source / drain metal layer SD2 are shown respectively. For example, the materials of the first gate metal layer, the second gate metal layer, and the third gate metal layer can be the same or different. For example, the materials of the first source / drain metal layer and the second source / drain metal layer can be the same or different. For example, the materials of the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source / drain metal layer, and the second source / drain metal layer can include materials such as molybdenum (Mo), aluminum (Al), and titanium (Ti). For example, the above metal layers can be a single-layer metal structure or a multilayer metal structure. For example, the source / drain metal layer can include a three-layer stacked structure, such as an aluminum metal layer sandwiched between two titanium metal layers, i.e., a titanium-aluminum-titanium (Ti-Al-Ti) composite material.

[0102] refer to Figure 2 and Figure 3 In some examples, the display substrate further includes a first connection line 210 located in the first fan-out area H and extending along the first direction Y. The first connection line 210 is disconnected from the data transmission line 100 to prevent the first connection line 210 from being connected to the data transmission line 100 and receiving unwanted signals (e.g., data signals), and to reduce display loading. For example, the first connection line 210 is disconnected from the data transmission line 100 by a break.

[0103] refer to Figure 2 and Figure 3 The display substrate includes a first source / drain metal layer SD1 and a second source / drain metal layer SD2, with the first source / drain metal layer SD1 located between the second source / drain metal layer SD2 and the substrate 1. The display substrate includes a first power supply voltage lead VDD, a first transmission line 110 located on the first source / drain metal layer SD1, a second data signal line DA2, and at least a portion of the first power supply voltage lead VDD located on the second source / drain metal layer SD2. A first connection line 210 can be electrically connected to the first power supply voltage lead VDD, which is closer to the first connection line 210, thereby applying a constant voltage signal to the first connection line 210 through the first power supply voltage lead VDD, preventing the first connection line 210 from being in a floating state, and simplifying the connection between the traces. For example, the first power supply voltage lead VDD is configured to provide a high-level signal.

[0104] refer to Figure 2 , Figure 3 and Figure 5H In some examples, the second transmission sublayer 122 includes a plurality of sub-sections 1221 spaced apart in the first direction Y, each sub-section 1221 having a contact pad CP at at least one end in the first direction Y. For example, the sub-section 1221 may have contact pads CP at both ends in the first direction Y. However, this disclosure is not limited to this, and the sub-section may also have a contact pad at only one end in the first direction. For example, the dimension of the contact pad CP in the second direction X is larger than the dimension of the sub-section 1221 in the second direction X. For example, the contact pad CP and the sub-section 1221 may be an integrally formed structure.

[0105] refer to Figure 2 , Figure 3 and Figure 5H The contact pad CP and the second via PLN2 at least partially overlap in a direction perpendicular to the substrate 1, so that the contact pad CP is electrically connected to the first source / drain metal layer SD1 through the second via PLN2. For example, the orthographic projection of the second via PLN2 on the substrate 1 can be located within the orthographic projection of the contact pad CP on the substrate 1 to facilitate signal transmission. However, this disclosure is not limited to this; for example, the contact pad and the second via can partially overlap and partially not overlap in a direction perpendicular to the substrate.

[0106] refer to Figure 2 and Figure 3 For example, in the first fan-out region H, there are more first connection lines 210 in the circuit rows that are farther away from the binding edge B1.

[0107] refer to Figure 2 and Figure 3In some examples, the first connection line 210 includes a first portion 211 and a second portion 212 that are electrically connected; the first portion 211 is located in the first source-drain metal layer SD1, and the second portion 212 is located in the second source-drain metal layer SD2. The orthographic projection of the first portion 211 on the substrate 1 overlaps with the orthographic projection of the second portion 212 on the substrate 1. Thus, a constant voltage signal can be applied to the leads floating in the first source-drain metal layer SD1 and the leads floating in the second source-drain metal layer SD2.

[0108] refer to Figure 2 , Figure 3 and Figure 5G In some examples, the first portion 211 includes a connecting body portion M1 and a first connecting portion S1 connected to at least one side of the connecting body portion M1 along the second direction X. The first connecting portion S1 is electrically connected to a first power supply voltage lead VDD. For example, the first portion 211 includes first connecting portions S1 connected to both sides of the connecting body portion M1 along the second direction X, and the two first connecting portions S1 are respectively electrically connected to a corresponding first power supply voltage lead VDD. For example, the two first connecting portions S1 connected to both sides of the connecting body portion M1 are generally on a straight line extending along the second direction X, thereby forming a generally cross-shaped structure together with the connecting body portion M1.

[0109] For example, combining Figure 3 and Figure 5G The connecting body part M1 is a continuous structure extending along the first direction Y, and the connecting body part M1 and the first connecting part S1 are integrally formed. For example, the connecting body part M1 is formed by means of... Figure 5G The connecting portion M11 shown makes the connecting body portion M1 form a continuous structure in the first direction Y. For example, the portion of the first source-drain metal layer SD1 used to form the second transmission line 120 (that is, the first transmission sublayer 121) can be a discontinuous structure, that is, the connecting portion M11 is not provided. The first transmission sublayer 121 can include multiple segments spaced apart from each other, and the transition is realized by the second transmission sublayer 122.

[0110] refer to Figure 2 and Figure 3In some examples, at least a portion of the first connection line 210 extends in a straight line along the same direction as at least a portion of the second transmission line 120. For example, the first connection line 210 includes a first portion 211 located in the first source-drain metal layer SD1, and the second transmission line 120 includes a first transmission sublayer 121 located in the first source-drain metal layer SD1, with the extension direction of the first portion 211 and the extension direction of the first transmission sublayer 121 aligned in a straight line. For example, the first portion 211 of the first connection line 210 located in the first source-drain metal layer SD1 and the first transmission sublayer 121 of the corresponding second transmission line 120 located in the same column of the pixel circuit 10.

[0111] refer to Figure 2 and Figure 3 For example, the first connection line 210 includes a second portion 212 located in the second source-drain metal layer SD2, and the second transmission line 120 includes a second transmission sublayer 122 located in the second source-drain metal layer SD2. The extension direction of the second portion 212 is in a straight line with the extension direction of the second transmission sublayer 122. For example, the second portion 212 of the first connection line 210 located in the second source-drain metal layer SD2 and the second transmission sublayer 122 of the corresponding second transmission line 120 located in the second source-drain metal layer SD2 are located in the same column of the pixel circuit 10.

[0112] refer to Figure 2 and Figure 3 The first connecting line 210 located between two adjacent first transmission lines 110 is disconnected from its corresponding first transmission line 110 at both ends in the first direction Y, and the adjacent first connecting line 210 and second transmission line 120 in the first direction Y are disconnected from each other. Thus, the first connecting line 210 can be disconnected from the first transmission line 110 and the second transmission line 120 in the data transmission line 100, respectively.

[0113] refer to Figure 2 and Figure 3 For example, the two opposite endpoints of the first connecting line 210 in the first direction Y are respectively disconnected from an adjacent first transmission line 110 through the first break OP1. For example, the first part 211 is disconnected from the first transmission sublayer 121 through the first break OP1, and the second part 212 is disconnected from the second transmission sublayer 122 through the first break OP1.

[0114] refer to Figure 2 and Figure 3 For example, the endpoint of the first connecting line 210 near the binding edge B1 is adjacent to the second transmission line 120 closest to that endpoint and is disconnected from each other through the second break OP2.

[0115] refer to Figure 2 and Figure 3 For example, two adjacent first transmission lines 110 mean that there are no other first transmission lines between these two first transmission lines 110. For example, a first connecting line 210 and a second transmission line 120 adjacent in the first direction Y mean that there are no other leads between these two leads.

[0116] refer to Figure 2 , Figure 3 and Figure 5C In some examples, the display substrate further includes a second reset signal line Rst2, and the gate of the first reset transistor T1 is coupled to the corresponding second reset signal line Rst2. The second reset signal line Rst2 and the second initialization signal line Vinit2 are disposed on different layers and at least partially overlap in a direction perpendicular to the substrate. For example, the second reset signal line Rst2 and the second initialization signal line Vinit2 may partially overlap in a direction perpendicular to the substrate, and partially not overlap.

[0117] refer to Figure 2 , Figure 3 and Figure 5C The first break OP1 includes a first sub-break OP11 and a second sub-break OP12 opposite each other in the first direction Y, with the first sub-break OP11 being further away from the bonding edge BB than the second sub-break OP12. The first sub-break OP11 at least partially overlaps with the second reset signal line Rst2 in a direction perpendicular to the substrate. For example, the second reset signal line may completely cover the first sub-break or only cover a portion of the first sub-break. At least one of the second sub-break OP12 and the second break OP2 at least partially overlaps with the anode 21 of the light-emitting element 20 in a direction perpendicular to the substrate. It is understood that... Figure 3 The anode 21 of the light-emitting element 20 is shown schematically only within the dashed box, but this disclosure is not limiting. For example, the anode of the light-emitting element may cover the second sub-port and the second break. For example, the anode of the light-emitting element may completely cover both the second sub-port and the second break. For example, the anode of the light-emitting element may only cover a portion of the second sub-port and a portion of the second break.

[0118] refer to Figure 2 and Figure 3 In some examples, the display substrate includes a second connection line 220 located in the second fan-out region V and extending along the second direction X. The second connection line 220 is disconnected from the data transmission line 100 to prevent the second connection line 220 from being connected to the data transmission line 100 and receiving unwanted signals (e.g., data signals), and to reduce the display load. For example, the second connection line 220 is disconnected from the data transmission line 100 by a break.

[0119] Figure 7 This is a stacked diagram of a portion of the film layers in a display substrate provided in at least one embodiment of the present disclosure.

[0120] refer to Figure 3 , Figure 5I and Figure 7 The display substrate includes a gate metal layer, a first source / drain metal layer SD1, and a second source / drain metal layer SD2. The gate metal layer is located between the substrate and the first source / drain metal layer SD1, and the second source / drain metal layer SD2 is located on the side of the first source / drain metal layer SD1 away from the substrate. The gate metal layer, the first source / drain metal layer SD1, and the second source / drain metal layer SD2 can be referred to the description in the foregoing embodiments, and will not be repeated here.

[0121] refer to Figure 3 , Figure 5I and Figure 7 The first transmission line 110 and the second connection line 220 are located in the first source-drain metal layer SD1, and the second data signal line DA2 is located in the second source-drain metal layer SD2. The gate metal layer also includes multiple initialization signal lines Vinit extending along the second direction X and arranged along the first direction Y. The second connection line 220 is electrically connected to the initialization signal line Vinit. By electrically connecting the second connection line 220 to the initialization signal line Vinit, an initialization signal can be applied to the second connection line 220 through the initialization signal line Vinit, preventing the second connection line 220 from being in a floating state. For example, the second connection line 220 can be electrically connected to an initialization signal line Vinit that is close to the second connection line 220, thereby simplifying the routing.

[0122] refer to Figure 3 and Figure 7 For example, in the second fan-out region V, the more first connection lines 210 exist in the circuit column farther away from the boundary line L.

[0123] refer to Figure 3 and Figure 7 In some examples, the extension direction of the second connection line 220 is on the same straight line as the extension direction of the first transmission line 110. For example, the second connection line 220 and the first transmission line 110 are both located in the first source-drain metal layer SD1, and the second connection line 220 and a corresponding first transmission line 110 are located in the same row of the pixel circuit 10.

[0124] refer to Figure 3 and Figure 7In the second direction X, the adjacent second connecting line 220 and the first transmission line 110 are disconnected from each other through the third break OP3. The two ends of the second connecting line 220 located between two adjacent second transmission lines 120 are disconnected from the second transmission line 120 in the second direction X through the fourth break OP4. Thus, the second connecting line 220 can be disconnected from the first transmission line 110 and the second transmission line 120 in the data transmission line 100, respectively.

[0125] refer to Figure 3 and Figure 7 For example, the endpoint of the second connecting line 220 near the second sub-display area 02 is adjacent to the first transmission line 110 closest to that endpoint and is disconnected from each other through a third break OP3. For example, the two opposite endpoints of the second connecting line 220 in the second direction X are respectively disconnected from an adjacent second transmission line 120 through a fourth break OP4.

[0126] refer to Figure 3 and Figure 7 For example, two adjacent second transmission lines 120 means that there are no other second transmission lines 120 between these two second transmission lines 120. For example, a second connecting line 220 and a first transmission line 110 adjacent in the second direction X means that there are no other leads between these two leads.

[0127] refer to Figure 3 , Figure 5D , Figure 5I and Figure 7 In some examples, the gate metal layer includes a first gate metal layer gate2, the initialization signal line Vinit includes a first initialization signal line Vinit1 located on the first gate metal layer gate2 and extending along the first direction Y, and the second connection line 220 is electrically connected to the first initialization signal line Vinit1 to prevent the second connection line 220 from floating by applying a first initialization signal to the second connection line 220 through the first initialization signal line Vinit1.

[0128] refer to Figure 3 , Figure 5D , Figure 5I and Figure 7In some examples, the second connection line 220 includes a second connection portion S2 extending along the first direction Y toward a side away from the bonding region BB. The second connection portion S2 at least partially overlaps with the first initialization signal line Vinit1 in a direction perpendicular to the substrate, and the second connection portion S2 is electrically connected to the first initialization signal line Vinit1. For example, the second connection portion may completely overlap with the first initialization signal line in a direction perpendicular to the substrate, or it may partially overlap and partially not overlap; this disclosure does not limit this. For example, in the circuit row where the second connection line is located, the connection portion in the first source / drain metal layer for connecting to signal lines such as initialization compensation lines and second power supply voltage leads is disconnected from the second connection line.

[0129] refer to Figure 3 , Figure 5D , Figure 5I and Figure 7 The second connection portion S2 of the second connection line 220 overlaps with the first initialization signal line Vinit1 in a direction perpendicular to the substrate, so as to electrically connect the second connection portion S2 to the first initialization signal line Vinit1. For example, the first initialization signal line Vinit1 and the second connection portion S2 are close to each other in a direction perpendicular to the substrate, thereby facilitating the electrical connection between the second connection line 220 and the first initialization signal line Vinit1. For example, the second connection portion S2 and the first initialization signal line Vinit1 are electrically connected through a via in the interlayer insulating layer (ILD).

[0130] refer to Figure 3 , Figure 5D , Figure 5I and Figure 7 In some examples, at least one of the third break OP3 and the fourth break OP4 at least partially overlaps with the first initialization signal line Vinit1 in a direction perpendicular to the substrate, so as to cover the third break OP3 and the fourth break OP4 through the first initialization signal line Vinit1. For example, the third break OP3 and the fourth break OP4 at least partially overlap with the first initialization signal line Vinit1 in a direction perpendicular to the substrate. For example, the first initialization signal line may completely cover the third break and the fourth break, or it may only cover part of them; this disclosure does not limit this.

[0131] refer to Figure 3The second source-drain metal layer SD2 also includes multiple initialization compensation lines Vinit0 arranged along the second direction X. Each initialization compensation line Vinit0 extends along the first direction Y and is disposed between two adjacent first power supply voltage leads VDD. The initialization compensation line Vinit0 is electrically connected to the initialization signal line Vinit. The second transmission line 120 is located between two adjacent second data signal lines DA2, and the first power supply voltage lead VDD is located on the side of the second data signal line DA2 away from the second transmission line 120. Thus, in the second source-drain metal layer SD2, the first power supply voltage lead VDD, the second data signal line DA2, the second transmission sublayer 122 in the second transmission line 120, the second data signal line DA2, the first power supply voltage lead VDD, and the initialization compensation line Vinit0 are arranged sequentially along the second direction Y.

[0132] Figure 8 and Figure 9 This is a stack-up diagram of partial film layers in a display substrate provided in at least one embodiment of this disclosure. For example, Figure 8 The first source / drain metal layer in the middle Figure 9 The first source / drain metal layer and Figure 3 The first source and drain metal layers in each are different.

[0133] refer to Figure 3 , Figure 5F , Figure 8 and Figure 9 In some examples, the gate metal layer includes a second gate metal layer gate3, which includes a plurality of second initialization signal lines Vinit2 extending along a second direction X and arranged in a first direction Y, and a plurality of third initialization signal lines Vinit3. One of the second initialization signal lines Vinit2 and the third initialization signal lines Vinit3 is electrically connected to a corresponding second connection line 220 to prevent the second connection line 220 from floating.

[0134] refer to Figure 3 , Figure 5F and Figure 8 For example, the second connection line 220 can be electrically connected to the second initialization signal line Vinit2 to apply a second initialization signal to the second connection line 220 via the second initialization signal line Vinit2. (See reference...) Figure 3 , Figure 5F and Figure 9 For example, the second connection line 220 can be electrically connected to the third initialization signal line Vinit3 to apply a third initialization signal to the second connection line 220 via the third initialization signal line Vinit3.

[0135] refer to Figure 3 , Figure 5F , Figure 5Hand Figure 8 In some examples, the initialization compensation line Vinit0 includes a first initialization compensation line Vinit01, a second initialization compensation line Vinit02, and a third initialization compensation line Vinit03 located in the second source-drain metal layer SD2. The first initialization compensation line Vinit01 is electrically connected to the first initialization signal line Vinit1, the second initialization compensation line Vinit02 is electrically connected to the second initialization signal line Vinit2, and the third initialization compensation line Vinit03 is electrically connected to the third initialization signal line Vinit3. The first initialization compensation line Vinit01, the second initialization compensation line Vinit02, and the third initialization compensation line Vinit03 are arranged sequentially along the second direction X.

[0136] For example, the first initialization signal line extending along the first direction is electrically connected to the first initialization compensation line extending along the second direction to form a first initialization signal line layer with a grid structure, which is beneficial to improving the signal transmission uniformity of the first initialization signal line layer.

[0137] For example, the second initialization signal line extending along the first direction is electrically connected to the second initialization compensation line extending along the second direction to form a mesh-like structure of the second initialization signal line layer, which is beneficial to improving the signal transmission uniformity of the second initialization signal line layer.

[0138] For example, the third initialization signal line extending along the first direction is electrically connected to the third initialization compensation line extending along the second direction to form a mesh-like third initialization signal line layer, which is beneficial to improving the signal transmission uniformity of the third initialization signal line layer.

[0139] refer to Figure 3 , Figure 5F , Figure 8 and Figure 9 In some examples, the second connection line 220 is electrically connected to the second initialization signal line Vinit2. The second connection line 220 includes a third connection portion S3 extending along the first direction Y toward the side away from the binding region BB. One of the second initialization signal line Vinit2 and the third initialization signal line Vinit3 is electrically connected to the third connection portion S3.

[0140] refer to Figure 3 , Figure 5F and Figure 8For example, the third connection portion S3 overlaps with the second initialization signal line Vinit2 in a direction perpendicular to the substrate, so as to be electrically connected to the second initialization signal line Vinit2 through the third connection portion S3. For example, the third connection portion S3 and the second initialization signal line Vinit2 are electrically connected through a via EBB in the interlayer insulating layer. For example, the second initialization signal line Vinit2 and the third connection portion S3 are close to each other in a direction perpendicular to the substrate, thereby facilitating the electrical connection between the second connection line 220 and the second initialization signal line Vinit2.

[0141] refer to Figure 8 For example, two third connection portions S3 are respectively connected to the same side of a second connection line 220 located in the first direction Y, and the two third connection portions S3 are spaced apart from each other in the second direction X, so as to be connected one-to-one with the two connection portions of the second initialization signal line Vinit2 extending along the first direction Y. For example, the two third connection portions S3 can also be electrically connected to the second initialization compensation line located between them through a sub-connection portion S31, and the two sub-connection portions S31 are roughly in a figure-eight shape. It can be understood that in the circuit row where the second connection line is located, the connection portion in the first source-drain metal layer for connecting to signal lines such as the second power supply voltage lead is disconnected from the second connection line.

[0142] refer to Figure 3 , Figure 5F and Figure 9 For example, the third connection portion S3 overlaps with the third initialization signal line Vinit3 in a direction perpendicular to the substrate, so as to be electrically connected to the third initialization signal line Vinit3 through the third connection portion S3. For example, the third connection portion S3 and the third initialization signal line Vinit3 are electrically connected through a via EBB in the interlayer insulating layer. For example, the third initialization signal line Vinit3 and the third connection portion S3 are close to each other in a direction perpendicular to the substrate, thereby facilitating the electrical connection between the second connection line 220 and the third initialization signal line Vinit3.

[0143] refer to Figure 9For example, a third connection portion S3 is provided at each end of two adjacent second connection lines 220 in the second direction X, close to each other. The two third connection portions S3 are located on the same side of the second connection lines 220 in the first direction Y, and are thus connected to the same connection portion of the third initialization signal line Vinit3 extending along the first direction Y towards the bonding edge. The two third connection portions S3 have a roughly V-shaped structure. For example, the third connection portion S3 can be connected to the connection portion of the third initialization signal line Vinit3 via a sub-connection portion S32 extending along the second direction X to improve connection reliability. The sub-connection portion S32 can overlap with the connection portion of the third initialization signal line Vinit3 in a direction perpendicular to the substrate. It is understood that in the circuit row where the second connection lines are located, the connection portions in the first source / drain metal layer used for connecting to signal lines such as the second power supply voltage lead are disconnected from the second connection lines.

[0144] refer to Figure 2 and Figure 3 In some examples, the display substrate further includes a third transmission line 130 located in the second sub-display area 02 and extending along the second direction X. The extension direction of the third transmission line 130 is on the same straight line as the extension direction of the first transmission line 110 and they are disconnected from each other by a fifth break OP5. For example, the third transmission line 130 and the first transmission line 110 are both located in the first source / drain metal layer SD1, and the third transmission line 130 and a corresponding first transmission line 110 are located in the same row of the pixel circuit 10. For example, the endpoint of the third transmission line 130 near the boundary line L is adjacent to the first transmission line 110 closest to that endpoint and they are disconnected from each other by the fifth break OP5.

[0145] refer to Figure 2 , Figure 3 and Figure 5D The fifth break OP5 at least partially overlaps with the first initialization signal line Vinit1 in a direction perpendicular to the substrate. For example, in a direction perpendicular to the substrate, the first initialization signal line Vinit1 may completely cover the fifth break OP5. Alternatively, the first initialization signal line may only cover a portion of the fifth break, and this disclosure is not limiting in this regard.

[0146] refer to Figures 2 to 4The display substrate also includes a second power supply voltage lead VSS and a light-emitting element 20. A third transmission line 130 is electrically connected to the second power supply voltage lead VSS, and the second power supply voltage lead VSS is electrically connected to the cathode of the light-emitting element 20. Connecting the third transmission line 130 to the second power supply voltage lead VSS allows a constant voltage signal to be applied to the third transmission line 130 through the second power supply voltage lead VSS, preventing the third transmission line 130 from being in a floating state. For example, the second power supply voltage lead VSS is configured to provide a constant low-level signal. For example, the voltage output by the second power supply voltage lead VSS is a ground voltage.

[0147] refer to Figures 2 to 4 In some examples, the display substrate further includes a fourth transmission line 140 located in the second sub-display area 02 and extending along the first direction Y. For example, a portion of the fourth transmission line 140 is located in the first source / drain metal layer SD1, and another portion is located in the second source / drain metal layer SD2. For example, the entire fourth transmission line 140 extends along the first direction Y. For example, the orthographic projection of the fourth transmission line 140 on the substrate 1 extends along the first direction Y. The orthographic projection of the fourth transmission line 140 on the substrate 1 lies between the orthographic projections of two adjacent first data signal lines DA1 on the substrate 1, to facilitate the wiring arrangement in the display substrate. For example, there are no other first data signal lines between two adjacent first data signal lines DA1.

[0148] refer to Figures 2 to 4 The display substrate also includes a second power supply voltage lead VSS and a light-emitting element 20. The fourth transmission line 140 is electrically connected to the second power supply voltage lead VSS, and the second power supply voltage lead VSS is electrically connected to the cathode of the light-emitting element 20. By electrically connecting the fourth transmission line 140 to the second power supply voltage lead VSS, a constant voltage signal can be applied to the fourth transmission line 140 through the second power supply voltage lead VSS, preventing the fourth transmission line 140 from being in a floating state.

[0149] refer to Figures 2 to 4 For example, the portions of the third transmission line 130 and the fourth transmission line 140 located in the first source-drain metal layer SD1 are directly connected. For example, the portion of the fourth transmission line 140 located in the second source-drain metal layer SD2 can be electrically connected to the portion located in the first source-drain metal layer SD1 via an adapter. For example, at least a portion of the third transmission line 130 and at least a portion of the fourth transmission line 140 are located within the normal display area N.

[0150] At least one embodiment of this disclosure provides a display device, which includes the display substrate described in the above embodiments. Since the display device according to the embodiments of this disclosure uses the aforementioned display substrate, it also possesses corresponding beneficial technical effects, which will not be elaborated upon here.

[0151] The following points need to be explained:

[0152] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0153] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0154] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: The display area and the binding area located on one side of the display area along the first direction; The size of the display area along the second direction perpendicular to the first direction is greater than the size of the binding area along the second direction. The edge of the display area near the binding area is the binding edge. The display area includes a first sub-display area that at least partially overlaps with the binding area in the first direction and a second sub-display area located on at least one side of the first sub-display area and not overlapping with the binding area in the first direction. Multiple data signal lines, at least partially located within the display area, extend along the first direction and are arranged along the second direction, the multiple data signal lines including a first data signal line located within the first sub-display area and a second data signal line located within the second sub-display area; A data transmission line is connected to the second data signal line and extends to the bonding area. At least a portion of the data transmission line includes a first transmission line and a second transmission line, the first transmission line extending along the second direction and the second transmission line extending along the first direction. Wherein, the first end of the first transmission line is connected to the second data signal line to form a first connection point; The display substrate further includes a substrate, and the data signal line and the data transmission line are both disposed on the substrate; the display substrate further includes an insulating layer located between the first transmission line and the second transmission line, and the second end of the first transmission line and one end of the second transmission line are connected through a first via in the insulating layer to form a second connection point; the first connection point and the second connection point are both located within the display area; The second end of the first transmission line and the first via at least partially overlap in a direction perpendicular to the substrate.

2. The display substrate according to claim 1, wherein, The data signal line is disposed on a different layer from the first transmission line; The second transmission line includes a first transmission sublayer and a second transmission sublayer. The first transmission sublayer is disposed on the same layer as the first transmission line, and the second transmission sublayer is disposed on the same layer as the data signal line. The first transmission sublayer and the second transmission sublayer are electrically connected through a second via in the insulating layer. The distance between the center of the orthographic projection of the second via on the substrate and the center of the orthographic projection of the first via on the substrate is the first distance, and the distance between the orthographic projection of the second via on the substrate and the orthographic projection of the first transmission line on the substrate in the first direction is the second distance. The ratio of the first distance to the second distance is 0.9-1.

1.

3. The display substrate according to claim 2, wherein, The data transmission line includes multiple data transmission lines to be connected to a corresponding number of second data signal lines, and the multiple data transmission lines are respectively provided with multiple first connection points and multiple second connection points. The plurality of first connection points are located in the second sub-display area, and the plurality of second connection points are located in the first sub-display area. The plurality of first connection points, along with their corresponding second data signal lines, move further away from the first sub-display area and closer to the edge of the second sub-display area away from the first sub-display area, and further away from the binding edge. Similarly, the plurality of second connection points, along with their corresponding second data signal lines, move further away from the second sub-display area, further away from the boundary line between the first and second sub-display areas, and further away from the binding edge. The area where the first transmission line is located is the first fan-out area, and the area where the second transmission line is located is the second fan-out area. Within the first fan-out area, the length of the first transmission line of the plurality of data transmission lines increases sequentially in the direction away from the binding edge. Within the second fan-out area, the length of the second transmission line of the plurality of data transmission lines increases sequentially in the direction away from the boundary line between the first sub-display area and the second sub-display area.

4. The display substrate according to claim 3, wherein, The first transmission line of the plurality of data transmission lines is arranged along the first direction, and the second transmission line of the plurality of data transmission lines is arranged along the second direction.

5. The display substrate according to claim 3, further comprising a first connecting line located in the first fan-out area and extending along the first direction, wherein the first connecting line is disconnected from the data transmission line; The display substrate includes a first source / drain metal layer and a second source / drain metal layer, wherein the first source / drain metal layer is located between the second source / drain metal layer and the substrate. The display substrate further includes a first power supply voltage lead, the first transmission line is located in the first source-drain metal layer, and the second data signal line and at least a portion of the first power supply voltage lead are located in the second source-drain metal layer. The first connection line is electrically connected to the first power supply voltage lead, which is configured to provide a high-level signal.

6. The display substrate according to claim 5, wherein, The second transmission sublayer includes a plurality of sub-parts spaced apart in the first direction, and each sub-part has a contact pad at at least one end in the first direction; The contact pad and the second via at least partially overlap in a direction perpendicular to the substrate, so that the contact pad is electrically connected to the first source / drain metal layer through the second via.

7. The display substrate according to claim 5, wherein, The first connecting line includes a first part and a second part that are electrically connected; The first portion is located in the first source / drain metal layer, and the second portion is located in the second source / drain metal layer. The orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the second portion on the substrate.

8. The display substrate according to claim 7, wherein, The first part includes a connecting body portion and a first connecting portion connected to at least one side of the connecting body portion along the second direction, the first connecting portion being electrically connected to the first power supply voltage lead.

9. The display substrate according to claim 5, wherein, At least a portion of the first connecting line extends in the same straight line as at least a portion of the second transmission line; The first connecting line located between two adjacent first transmission lines is disconnected from the corresponding first transmission line at both ends in the first direction through a first break. The first connecting line and the second transmission line, which are adjacent to each other in the first direction, are disconnected from each other by the second break.

10. The display substrate according to claim 5 further includes a driving transistor and a power control transistor, wherein the first terminal of the power control transistor is electrically connected to the first power supply voltage lead, and the second terminal of the power control transistor is electrically connected to the first terminal of the driving transistor.

11. The display substrate according to claim 7, further comprising a second connecting line located in the second fan-out area and extending along the second direction, the second connecting line being disconnected from the data transmission line; The display substrate further includes a gate metal layer, which is located between the substrate and the first source / drain metal layer; The first transmission line and the second connection line are located in the first source-drain metal layer, the second data signal line is located in the second source-drain metal layer, and the gate metal layer further includes a plurality of initialization signal lines extending along the second direction and arranged along the first direction; The second connection line is electrically connected to the initialization signal line; The extension direction of the second connecting line is on the same straight line as the extension direction of the first transmission line; adjacent second connecting lines and first transmission lines in the second direction are disconnected from each other through a third break, and the two ends of the second connecting line located between two adjacent second transmission lines in the second direction are disconnected from the second transmission lines through a fourth break.

12. The display substrate according to claim 11, wherein, The gate metal layer includes a first gate metal layer, and the initialization signal line includes a first initialization signal line located on the first gate metal layer and extending along a first direction; the second connection line includes a second connection portion extending along the first direction toward a side away from the bonding region, the second connection portion at least partially overlapping the first initialization signal line in a direction perpendicular to the substrate, and the second connection portion being electrically connected to the first initialization signal line.

13. The display substrate according to claim 12, wherein, At least one of the third break and the fourth break overlaps at least partially with the first initialization signal line in a direction perpendicular to the substrate.

14. The display substrate according to claim 11, wherein, The second source / drain metal layer further includes multiple initialization compensation lines arranged along the second direction. Each initialization compensation line extends along the first direction and is disposed between two adjacent first power supply voltage leads. The initialization compensation line is electrically connected to the initialization signal line. The second transmission line is located between two adjacent second data signal lines, and the first power supply voltage lead is located on the side of the second data signal line away from the second transmission line.

15. The display substrate according to claim 14, wherein, The sub-pixel includes a compensation transistor and a first reset transistor. The first terminal of the compensation transistor is electrically connected to the second terminal of the driving transistor, and the second terminal of the compensation transistor is electrically connected to the gate of the driving transistor. The first terminal of the first reset transistor is electrically connected to the corresponding first initialization signal line, and the second terminal of the first reset transistor is electrically connected to the second terminal of the driving transistor.

16. The display substrate according to claim 15, wherein, The gate metal layer includes a second gate metal layer; the second gate metal layer includes a plurality of second initialization signal lines extending along the second direction and arranged in the first direction, and a plurality of third initialization signal lines; One of the second initialization signal line and the third initialization signal line is electrically connected to the corresponding second connection line.

17. The display substrate according to claim 16, wherein, The second connecting line is electrically connected to the second initialization signal line. The second connecting line includes a third connecting portion extending along the first direction toward a side away from the binding region. One of the second initialization signal line and the third initialization signal line is electrically connected to the third connecting portion.

18. The display substrate according to claim 16, wherein, The initialization compensation line includes a first initialization compensation line, a second initialization compensation line, and a third initialization compensation line located in the second source / drain metal layer. The first initialization compensation line is electrically connected to the first initialization signal line, the second initialization compensation line is electrically connected to the second initialization signal line, and the third initialization compensation line is electrically connected to the third initialization signal line. The first initialization compensation line, the second initialization compensation line, and the third initialization compensation line are arranged sequentially along the second direction.

19. The display substrate according to claim 16, wherein, The sub-pixel includes a second reset transistor and a light-emitting element. The first terminal of the second reset transistor is electrically connected to the corresponding second initialization signal line, and the second terminal of the second reset transistor is electrically connected to the anode of the light-emitting element.

20. The display substrate according to claim 19, further comprising a second reset signal line, wherein the gate of the first reset transistor is coupled to the corresponding second reset signal line; the second reset signal line and the second initialization signal line are disposed on different layers and at least partially overlap in a direction perpendicular to the substrate. The first break includes a first sub-break and a second sub-break opposite each other in the first direction, wherein the first sub-break is further away from the binding edge than the second sub-break; The first sub-port at least partially overlaps with the second reset signal line in a direction perpendicular to the substrate. At least one of the second sub-mouth and the second break overlaps at least partially with the anode of the light-emitting element in a direction perpendicular to the substrate.

21. The display substrate according to claim 19, wherein, The sub-pixel further includes a third reset transistor, the first terminal of which is electrically connected to the corresponding third initialization signal line, and the second terminal of which is electrically connected to the first terminal of the driving transistor.

22. The display substrate according to claim 2, wherein, The first transmission line includes a main body portion and a connecting portion connected to each other, the main body portion extending along the second direction and the connecting portion extending along the first direction; The end of the connecting portion away from the main body includes the first connecting point, which is closer to the binding area in the first direction than the main body.

23. The display substrate according to claim 10, further comprising a third transmission line located in the second sub-display area and extending along the second direction, wherein the extension direction of the third transmission line is on the same straight line as the extension direction of the first transmission line and is disconnected from each other by a fifth break. The display substrate further includes a second power supply voltage lead and a light-emitting element. The second power supply voltage lead is configured to provide a low-level signal. The third transmission line is electrically connected to the second power supply voltage lead, and the second power supply voltage lead is electrically connected to the cathode of the light-emitting element.

24. The display substrate according to claim 23, wherein, The fifth break point overlaps at least partially with the first initialization signal line in a direction perpendicular to the substrate.

25. The display substrate according to claim 2, further comprising a fourth transmission line located in the second sub-display area and extending along the first direction, wherein the orthographic projection of the fourth transmission line on the substrate is located between the orthographic projections of two adjacent first data signal lines on the substrate. The display substrate further includes a second power supply voltage lead and a light-emitting element. The second power supply voltage lead is configured to provide a low-level signal. The fourth transmission line is electrically connected to the second power supply voltage lead, and the second power supply voltage lead is electrically connected to the cathode of the light-emitting element.

26. A display device comprising the display substrate according to any one of claims 1-25.

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