Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure. According to the manufacturing method of the semiconductor structure, a groove is formed in the top face of a provided middle structure, an isolation material layer is generated on the middle structure, the isolation material layer covers the top face of the middle structure and fills the groove, and the isolation material layer comprises a first part located over the groove and a second part located on the side edge of the groove; the first part is annealed, and the second part is not annealed, so that the grinding rate of the first part is smaller than that of the second part; and the patterned first hard mask layer is used for carrying out chemical mechanical grinding on the isolation material layer and is stopped on the middle structure. In this way, the sinking problem in chemical mechanical polishing can be solved, a chemical mechanical polishing process window is expanded, and particularly the problem that deep sinking is prone to occurring in a graph sparse area in chemical mechanical polishing can be solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Technology

[0002] In the field of semiconductor technology, chemical mechanical polishing (CMP), as a global planarization technique, suffers from pattern sensitivity. Dishing in CMP is caused by the different polishing removal rates in different areas. Compared with densely patterned areas, sparsely patterned areas are more prone to dishing, and the more sparse the pattern, the greater the potential depth of dishing.

[0003] Figures 1 to 3 This is a schematic diagram illustrating a process for fabricating a semiconductor structure. The method for fabricating this semiconductor structure includes the following steps: (Refer to...) Figure 1 As shown, a hard mask layer 13 is formed on a semiconductor substrate 10; the hard mask layer 13 and the semiconductor substrate 10 are etched to form a plurality of shallow trenches 11 in the semiconductor substrate 10, the plurality of shallow trenches 11 defining a plurality of fins; Reference Figure 2 As shown, an isolation material layer 12 is formed on the semiconductor substrate 10, the isolation material layer 12 covers the hard mask layer 13 and fills a plurality of shallow trenches 11; Reference Figure 3 As shown, the isolation material layer 12 is chemically and mechanically polished and then stopped at the hard mask layer 13.

[0004] For chemical mechanical polishing of shallow trench isolation (STI) structures, refer to Figure 3 As shown, after chemical mechanical polishing (CMP), the isolation material layer retained in the sparser pattern region II is prone to significant dishing compared to the denser pattern region I. Excessive dishing can lead to residual dishing in subsequent CMP processes of polysilicon and interlayer dielectric (ILD). To control dishing during CMP, the over-polishing time after polishing to the surface of the hard mask layer 13 cannot be too long; however, too short an over-polishing time can easily result in residual isolation material on the fins. Therefore, the CMP process for shallow trench isolation (STI) structures has a relatively small process window. Summary of the Invention

[0005] One of the objectives of this invention is to provide a method for fabricating a semiconductor structure that can improve the depression problem in chemical mechanical polishing (CMP) and expand the CMP process window. In particular, it can improve the problem that deep depressions are easily generated in sparse areas of the pattern in CMP.

[0006] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor structure comprising: providing an intermediate structure having a trench on its top surface and a patterned first hard mask layer on the intermediate structure, the patterned first hard mask layer covering the intermediate structure on the side of the trench and exposing the trench; forming an isolation material layer on the intermediate structure, the isolation material layer covering the top surface of the intermediate structure and filling the trench, the isolation material layer comprising a first portion located directly above the trench and a second portion located on the side of the trench; annealing the first portion and not annealing the second portion, such that the polishing rate of the isolation material layer of the first portion is less than the polishing rate of the isolation material layer of the second portion; and performing chemical mechanical polishing on the isolation material layer and stopping at the patterned first hard mask layer.

[0007] Optionally, the method for annealing the first portion includes: forming a second hard mask material layer on the isolation material layer; patterning the second hard mask material layer to form a patterned second hard mask layer, the patterned second hard mask layer covering the second portion and exposing the first portion; and selectively annealing the isolation material layer of the first portion using laser annealing.

[0008] Optionally, the same mask is used to pattern the second hard mask material layer as the mask used to form the trench.

[0009] Optionally, the method for annealing the first part includes: providing a laser annealing mask that covers the second part and exposes the first part; and selectively annealing the insulating material layer of the first part by laser annealing under the shielding of the laser annealing mask.

[0010] Optionally, the insulating material layer on top of the first part can be annealed using laser annealing.

[0011] Optionally, the intermediate structure includes a semiconductor substrate, and the trench is located in the semiconductor substrate.

[0012] Optionally, the method of providing the intermediate structure includes: forming a first hard mask material layer on a semiconductor substrate, the first hard mask material layer covering the top surface of the semiconductor substrate; patterning the first hard mask material layer to form a patterned first hard mask layer; and using the patterned first hard mask layer as a mask, etching the semiconductor substrate to form a plurality of trenches, the plurality of trenches defining a plurality of fins.

[0013] Optionally, the second portion is located directly above the fin.

[0014] Optionally, the intermediate structure includes a semiconductor substrate and a first material layer located on the semiconductor substrate, wherein the trench is located in the first material layer.

[0015] Optionally, the top surface of the intermediate structure has a plurality of grooves, and the pattern on the top surface of the intermediate structure is defined by the plurality of grooves; the intermediate structure includes a pattern-dense region and a pattern-sparse region; within a unit area, the area of ​​all the first portions of the pattern-dense region is smaller than the area of ​​all the first portions of the pattern-sparse region.

[0016] In the semiconductor structure fabrication method provided by this invention, a patterned first hard mask layer is provided on the intermediate structure. The patterned first hard mask layer covers the intermediate structure on the side of the trench and exposes the trench. In the isolation material layer covering the intermediate structure and filling the trench, the polishing rate of the first part is less than that of the second part. Thus, during chemical mechanical polishing, the removal rate of the second part can be greater than that of the first part, and the polishing of the second part can stop on the patterned first hard mask layer without easily causing depressions. This ensures that the isolation material layer on the patterned first hard mask layer is effectively removed and can reduce or even avoid depressions in the isolation material layer in the trench. This can improve the depression problem in chemical mechanical polishing, improve the planarization effect of chemical mechanical polishing, and expand the process window of chemical mechanical polishing and subsequent polishing processes.

[0017] Furthermore, the pattern on the top surface of the intermediate structure is defined by multiple grooves. When the intermediate structure has dense and sparse pattern areas, the area of ​​all the first parts of the dense pattern area is smaller than the area of ​​all the first parts of the sparse pattern area per unit area. Thus, during chemical mechanical polishing, the first part with a small polishing rate and large area on the sparse pattern area can reduce the removal rate of the isolation material layer in the sparse pattern area. This can offset the conventional characteristic that the polishing rate of the sparse pattern area is greater than that of the dense pattern area during chemical mechanical polishing, which helps to improve the problem of large depression depth in the sparse pattern area and improve the planarization effect of chemical mechanical polishing. Attached Figure Description

[0018] Figures 1 to 3 This is a schematic diagram of a process for fabricating an existing semiconductor structure.

[0019] Figure 4 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0020] Figures 5 to 10 This is a step-by-step structural diagram of a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures: 10-Semiconductor substrate; 11-Shallow trench; 12-Isolation material layer; 101-Semiconductor substrate; 102-Trench; 103-Fin; 104-Pad oxide layer; 105-Patterned first hard mask layer; 106-Isolation material layer; 106a-First portion; 106b-Second portion; 107a-Second hard mask material layer; 107-Patterned second hard mask layer. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0023] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0024] Figure 4 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention. (See reference...) Figure 4 As shown, the method for fabricating the semiconductor structure provided in this embodiment includes:

[0025] Step S1, providing an intermediate structure, the top surface of which has a trench, and the intermediate structure having a patterned first hard mask layer, the patterned first hard mask layer covering the intermediate structure on the side of the trench and exposing the trench;

[0026] Step S2: An isolation material layer is generated on the intermediate structure. The isolation material layer covers the top surface of the intermediate structure and fills the trench. The isolation material layer includes a first part located directly above the trench and a second part located on the side of the trench.

[0027] Step S3: Anneal the first portion but not the second portion, such that the grinding rate of the insulating material layer in the first portion is less than the grinding rate of the insulating material layer in the second portion; and

[0028] Step S4: Perform chemical mechanical polishing on the isolation material layer and stop on the patterned first hard mask layer.

[0029] Figures 5 to 10 This is a step-by-step structural diagram illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention. The following is in conjunction with... Figure 4 , Figures 5 to 10 The method for fabricating the semiconductor structure of this application is described.

[0030] In step S1, the top surface of the provided intermediate structure has a groove 102, and the intermediate structure has a patterned first hard mask layer 105, which covers the intermediate structure on the side of the groove 102 and exposes the groove 102.

[0031] In this embodiment, the intermediate structure can be a semiconductor substrate 101, and the trench 102 is located in the semiconductor substrate 101. The material of the semiconductor substrate 101 can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, gallium nitride, or indium gallium nitride, etc., or it can be silicon-on-insulator, germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In other embodiments, the intermediate structure can include the semiconductor substrate 101 and a first material layer located on the semiconductor substrate 101, and the trench 102 can be located in the first material layer; for example, the first material layer can be a metal layer or a polycrystalline silicon material layer, etc.

[0032] The following description takes a semiconductor substrate 101 as the intermediate structure and the trench 102 located in the semiconductor substrate 101 as an example.

[0033] For example, a method for providing an intermediate structure may include: referencing Figure 5 As shown, a first hard mask material layer is formed on a semiconductor substrate 101, and the first hard mask material layer covers the top surface of the semiconductor substrate 101; the first hard mask material layer is patterned to form a patterned first hard mask layer 105; using the patterned first hard mask layer 105 as a mask, the semiconductor substrate is etched to form a plurality of trenches 102, and the plurality of trenches 102 define a plurality of fins 103.

[0034] In this embodiment, the top surface of the semiconductor substrate 101 may have a plurality of trenches 102, and the pattern of the top surface of the semiconductor substrate 101 is defined by the plurality of trenches 102. (See reference...) Figure 5As shown, the semiconductor substrate 101 includes a patterned dense region I and a patterned sparse region II. The number of trenches in the patterned dense region I is greater than the number of trenches in the patterned sparse region II, and the opening width of the trenches in the patterned dense region I is smaller than the opening width of the trenches in the patterned sparse region II. For example, the width of the trenches 102 in the patterned dense region I can be 20nm~50nm, that is, the spacing between the fins 103 can be 20nm~50nm; the opening width of the trenches 102 in the patterned sparse region II can be greater than or equal to 50µm, for example, the opening of the trenches 102 in the patterned sparse region II is 50µm×50µm, but is not limited thereto.

[0035] In some embodiments of this application, the material of the first hard mask material layer, or the patterned first hard mask layer 105, includes, but is not limited to, silicon nitride. The first hard mask material layer can be formed by a suitable deposition process such as chemical vapor deposition or atomic layer deposition.

[0036] The method for patterning the first hard mask material layer to form a patterned first hard mask layer 105 may include: coating photoresist on the first hard mask material layer to form a first photoresist layer; exposing the first photoresist layer using a mask; developing the exposed first photoresist layer to form a patterned first photoresist layer; and etching the first hard mask material layer using the patterned first photoresist layer as a mask to form the patterned first hard mask layer 105.

[0037] A pad oxide layer 104 may also be formed between the first hard mask material layer and the semiconductor substrate 101. The material of the pad oxide layer 104 may include silicon oxide. Since the stress of the first hard mask material layer is relatively large, dislocations are easily generated on the surface of the semiconductor substrate 101 when the first hard mask material layer is formed directly on the semiconductor substrate 101. The pad oxide layer 104 is used to provide a buffer when forming the first hard mask material layer, avoiding the problem of dislocations generated when forming the first hard mask material layer directly on the semiconductor substrate 101. In addition, the pad oxide layer 104 can also serve as an etching stop layer when etching to form the patterned first hard mask layer 105 and a stop layer for removing the patterned first hard mask layer 105.

[0038] In step S2, refer to Figure 5 As shown, an isolation material layer 106 is formed on a semiconductor substrate 101. The isolation material layer 106 covers the top surface of the semiconductor substrate 101 and fills a plurality of trenches 102. The isolation material layer 106 includes a first portion 106a located directly above the trenches 102 and a second portion 106b located on the side of the trenches 102.

[0039] In this embodiment, the first portion 106a is located directly above the groove 102, and the second portion 106b is located directly above the fin 103. (See reference...) Figure 5As shown, the contour of the isolation material layer 106 undulates with the contour of the groove 102, the top surface of the second part 106b is higher than the top surface of the first part 106a, and the second part 106b protrudes with the protrusion of the fin 103.

[0040] The material of the isolation layer 106 includes silicon oxide. The isolation layer 106 can be formed by deposition processes such as high-density plasma chemical vapor deposition (HDP-CVD), high aspect ratio process (HARP), low-pressure CVD (LPCVD), sub-atmospheric pressure CVD (SACVD), or flowable CVD (FCVD).

[0041] In step S3, refer to Figure 8 As shown, the first part 106a is annealed, but the second part 106b is not annealed, so that the grinding rate of the isolation material layer of the first part 106a is less than the grinding rate of the isolation material layer of the second part 106b.

[0042] In this embodiment, reference Figure 8 As shown, within a unit area (or in other words, within the same area), the area of ​​all the first parts 106a of the dense region I is smaller than the area of ​​all the first parts 106a of the sparse region II.

[0043] In one embodiment of this application, the method for annealing the first portion 106a may include: referring to Figure 6 As shown, a second hard mask material layer 107a is formed on the isolation material layer 106; Reference Figure 7 As shown, the second hard mask material layer 107a is patterned to form a patterned second hard mask layer 107, which covers the second portion 106b and exposes the first portion 106a; Reference Figure 8 As shown, the isolation material layer of the first part 106a is selectively annealed by laser annealing.

[0044] It should be noted that laser annealing is a rapid thermal annealing (RTA) process that directly utilizes a laser to rapidly increase the surface temperature of a material. Compared with traditional annealing processes, rapid thermal annealing has a faster heating rate and higher temperature. Furthermore, because laser annealing uses a laser beam to anneal the material, and the laser beam can selectively irradiate a designated area, it allows for selective annealing of that area. In this embodiment, when the isolation material layer of the first portion 106a is selectively annealed using laser annealing, the second portion 106b is not irradiated by the laser beam due to the blocking effect of the patterned second hard mask layer 107, and therefore does not undergo annealing.

[0045] It should be noted that when the isolation material layer 106 includes silicon oxide, annealing the first portion 106a of the isolation material layer 106 can promote the Si-O-Si bonding of the isolation material in the first portion 106a, making the isolation material in the first portion 106a more dense, and thus the grinding rate of the isolation material layer in the first portion 106a is lower than that of the isolation material layer in the second portion 106b. More specifically, taking tetraethyl orthosilicate (TEOS) as the silicon source gas and silicon oxide as the silicon oxide isolation material layer 106 generated by the HARP process as an example, the isolation material layer 106 contains certain hydroxyl groups. When the first portion 106a of the isolation material layer 106 is annealed, the hydroxyl groups in the isolation material in the first portion 106a can combine and release moisture, promoting the Si-O-Si bonding, making the isolation material in the first portion 106a more dense, and thus the grinding rate of the isolation material layer in the first portion 106a is lower than that of the isolation material layer in the second portion 106b.

[0046] For example, a method for patterning the second hard mask material layer 107a may include: coating photoresist on the second hard mask material layer 107a to form a second photoresist layer; exposing the second photoresist layer using a mask; developing the exposed second photoresist layer to form a patterned second photoresist layer; and etching the second hard mask material layer 107a using the patterned second photoresist layer as a mask to form a patterned second hard mask layer 107. In this embodiment, the same mask is used to expose both the second and first photoresist layers, meaning the mask used to form the patterned second hard mask layer 107 and the mask used to form the trench 102 can be the same, which helps save on mask usage and manufacturing costs.

[0047] In one embodiment of this application, if the generated second hard mask material layer 107a is relatively thick, the second hard mask material layer 107a can be ground to make its top surface flat, and then patterned. This helps to improve the patterning accuracy of the second hard mask material layer 107a, that is, to improve the accuracy of subsequent photolithography processes on the second hard mask material layer 107a. In another embodiment of this application, if the generated second hard mask material layer 107a is relatively thin, patterning can be performed directly after the second hard mask material layer 107a is generated.

[0048] After laser annealing of the first part 106a, refer to Figure 9 As shown, the second hard mask layer 107 of the pattern is removed.

[0049] In another embodiment of this application, the method for annealing the first portion 106a may include: providing a laser annealing mask that covers the second portion 106b and exposes the first portion 106a; and selectively annealing the isolation material layer of the first portion 106a by laser annealing under the shielding of the laser annealing mask. This can save the deposition, photolithography, and etching processes required to form the patterned second hard mask layer 107.

[0050] In the embodiments of this application, reference is made to Figure 8 As shown, the isolation material layer at the top of the first part 106a can be annealed by laser annealing, while the isolation material layer at the bottom of the first part 106a can remain in an unannealed state, just like the second part 106b. The depth of laser annealing of the first part 106a can be adjusted as needed.

[0051] For example, when the first part 106a is annealed by laser annealing, the area of ​​the first part 106a that needs to be annealed (such as the top) can reach a set temperature range and be maintained within the set temperature range for a set time; the set temperature range can be 1100℃~1200℃, for example 1150℃; the set time can be 350µs~450µs, for example 400µs.

[0052] In step S4, refer to Figure 9 and Figure 10 As shown, the isolation material layer 106 is chemically and mechanically polished and stops at the patterned first hard mask layer 105.

[0053] Since the grinding rate of the unannealed second part 106b is greater than that of the annealed first part 106a, the removal rate of the second part 106b during chemical mechanical polishing can be greater than that of the first part 106a. Furthermore, the grinding of the second part 106b can stop on the patterned first hard mask layer 105 without easily causing dishing. This ensures that the isolation material layer 106 on the patterned first hard mask layer 105 is effectively removed and can reduce or even avoid dishing of the isolation material layer 106 in the trench 102. In other words, it can reduce or even avoid dishing after grinding the first part 106a, improve the dishing problem in chemical mechanical polishing, enhance the planarization effect of chemical mechanical polishing, and expand the process window of chemical mechanical polishing and subsequent polishing processes.

[0054] Furthermore, within a unit area, the area of ​​all the first portions 106a of the pattern-dense region I is smaller than the area of ​​all the first portions 106a of the pattern-sparse region II. That is, the annealed area of ​​the pattern-dense region I is smaller than the annealed area of ​​the pattern-sparse region II. During chemical mechanical polishing, the first portions 106a of the pattern-sparse region II, which have a smaller polishing rate and a larger area, can reduce the removal rate of the isolation material layer of the pattern-sparse region II. This can offset the conventional characteristic that the polishing rate of the pattern-sparse region is greater than that of the pattern-dense region during chemical mechanical polishing. This helps to improve the problem of the large depression depth in the pattern-sparse region II and improve the planarization effect of chemical mechanical polishing.

[0055] Tests revealed that, taking an original isolation material layer thickness of 6100 Å and a grinding removal amount of 2500 Å as an example, if the isolation material layer is ground directly without selective annealing, the depression depth of the isolation material layer retained in the groove 102 of the pattern sparse region II is approximately 80 Å to 100 Å. After annealing a portion of the isolation material layer with a flat top surface and then performing chemical mechanical polishing, when the grinding removal amount of the isolation material layer is 1915 Å, the grinding removal amount in the annealed area is 113 Å less than that in the unannealed area, which is already greater than 100 Å. This proves that annealing the first part 106a of the isolation material layer without annealing the second part 106b can make the grinding rate of the isolation material layer in the first part 106a lower than that in the second part 106b. Furthermore, by controlling the annealing depth at the top of the first part 106a, the depressions caused by the faster grinding rate in the pattern sparse region II in conventional processes can be offset, thus improving the depression problem in chemical mechanical polishing.

[0056] In one embodiment of this application, reference is made to... Figure 10 As shown, the isolation material layer 106 retained in the trench 102 in the patterned dense region I serves as an isolation structure for isolating the fin 103. The isolation structure is, for example, a shallow trench isolation structure (STI). The isolation material layer 106 retained in the trench 102 in the patterned sparse region II can serve as a measuring pad for measuring the thickness of the retained isolation material layer 106. That is, the remaining thickness of the isolation material layer 106 after grinding is determined by measuring the isolation material layer 106 retained in the trench 102 in the patterned sparse region II. The semiconductor structure fabrication method provided in this application can improve the problem of large depressions in the measuring pad.

[0057] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: An intermediate structure is provided, the top surface of which has a trench, and a patterned first hard mask layer is provided on the intermediate structure, the patterned first hard mask layer covering the intermediate structure on the side of the trench and exposing the trench; An isolation material layer is formed on the intermediate structure, the isolation material layer covers the top surface of the intermediate structure and fills the trench, the isolation material layer includes a first portion located directly above the trench and a second portion located on the side of the trench; The first part is annealed, but the second part is not annealed, such that the grinding rate of the isolation material layer of the first part is less than the grinding rate of the isolation material layer of the second part. as well as The isolation material layer is chemically and mechanically polished and then stopped at the patterned first hard mask layer.

2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The method for annealing the first part includes: A second hard mask material layer is formed on the isolation material layer; The second hard mask material layer is patterned to form a patterned second hard mask layer, which covers the second portion and exposes the first portion; and The first part of the insulating material layer is selectively annealed using laser annealing.

3. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The same mask is used to pattern the second hard mask material layer as the mask used to form the trench.

4. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The method for annealing the first part includes: Provide a laser annealing mask that covers the second portion and exposes the first portion; and Under the shielding of the laser annealing mask, the first part of the isolation material layer is selectively annealed by laser annealing.

5. The method for fabricating a semiconductor structure as described in claim 2 or 4, characterized in that, The insulating material layer on top of the first part is annealed using laser annealing.

6. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The intermediate structure includes a semiconductor substrate, and the trench is located in the semiconductor substrate.

7. The method for fabricating a semiconductor structure as described in claim 6, characterized in that, Methods for providing intermediate structures include: A first hard mask material layer is formed on a semiconductor substrate, the first hard mask material layer covering the top surface of the semiconductor substrate; The first hard mask material layer is patterned to form a patterned first hard mask layer; and Using the patterned first hard mask layer as a mask, the semiconductor substrate is etched to form multiple trenches, and the multiple trenches define multiple fins.

8. The method for fabricating a semiconductor structure as described in claim 7, characterized in that, The second part is located directly above the fin.

9. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The intermediate structure includes a semiconductor substrate and a first material layer located on the semiconductor substrate, wherein the trench is located in the first material layer.

10. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The top surface of the intermediate structure has multiple grooves, and the pattern on the top surface of the intermediate structure is defined by the multiple grooves; the intermediate structure includes a pattern-dense region and a pattern-sparse region. Within a unit area, the area of ​​all the first portions of the dense region of the graphic is smaller than the area of ​​all the first portions of the sparse region of the graphic.

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