Semiconductor structure, preparation method, bonding method and semiconductor device

Abstract

The invention relates to the technical field of semiconductors, and particularly discloses a semiconductor structure, a preparation method, a bonding method and a semiconductor device.The preparation method of the semiconductor structure comprises the steps that a semiconductor substrate with a metal interconnection layer is provided; forming a dielectric layer on the semiconductor substrate; etching the dielectric layer to form a groove; conformally forming an air suction layer in the groove and then filling the groove with a protection layer; etching the protective layer, the air suction layer and the dielectric layer to form a through hole which penetrates through the groove and is connected to the metal interconnection layer; filling a metal material layer in the through hole; and a bonding surface is formed after thinning treatment. Wherein the gas suction layer can adsorb gas generated by condensation and other reactions of the dielectric layer in the bonding annealing process, and the risk that a cavity is formed in a bonding interface is reduced; when the alignment of the bonding surface of the wafer has tiny deviation, the protective layer can prevent metal atoms from diffusing to the dielectric layer of the wafer on the opposite side; meanwhile, the air suction layer can buffer stress generated by expansion of the metal columns, and stress damage to the dielectric layer at the bonding interface is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, preparation method, bonding method and semiconductor device. Background Technology

[0002] As integrated circuit technology advances towards smaller size, higher performance, and three-dimensional integration, hybrid bonding technology has become a key technology for achieving ultra-high-density interconnection and stacking of chips. This technology abandons traditional bumps or solder balls, embedding metal pillars (such as copper pillars) on the wafer surface and performing surface treatment to make the copper pillars and surrounding insulating dielectrics (such as silicon dioxide, silicon carbonitride, etc.) on both wafers flat, clean, and highly reactive. The two wafers are aligned and bonded, relying on van der Waals forces and hydrogen bonding on the wafer surfaces to complete pre-bonding. Subsequently, high-temperature annealing forms covalent bonds, thus achieving permanent copper-copper and dielectric-dielectric bonding. However, current hybrid bonding technologies have the following problems: First, during high-temperature annealing, copper atoms tend to diffuse into the surrounding medium. Especially when there is a slight misalignment in the wafer bonding planes, the copper pillar surfaces of the two wafers may not coincide, causing part of the copper interface to adhere to the dielectric interface of the opposite wafer (e.g., ...). Figure 1 (The area indicated by the red dashed circle). This increases the risk of copper diffusing into the dielectric layer, thus affecting the insulation performance of the dielectric layer.

[0003] Secondly, the coefficients of thermal expansion of copper and the dielectric (such as silicon dioxide) that constitute the hybrid bonding interface differ significantly. During high-temperature annealing, the volume expansion of copper is much greater than that of the surrounding dielectric layer. This uneven expansion generates huge local stress at the copper-dielectric interface, causing copper to be squeezed and potentially dislodging or damaging the dielectric layer, introducing mechanical defects such as microcracks or delamination at the interface.

[0004] Furthermore, the final strength and density of the mixed bond depend on the high-temperature annealing process. During this process, active groups (such as hydroxyl groups) on the surface of the dielectric layer (such as silica) undergo dehydration condensation reactions to form strong covalent bonds. However, this chemical reaction releases water vapor as a byproduct; at the closed bonding interface, this water vapor may further react with materials such as silicon at high temperatures to generate hydrogen gas. If these gases cannot be removed or absorbed in a timely and effective manner at the interface, they will accumulate locally, leading to voids or micro-gaps at the bonding interface, severely affecting the quality of the bonding interface. Summary of the Invention

[0005] One of the purposes of this application is to provide a semiconductor structure and preparation method to improve the problems of copper diffusion, thermomechanical stress damage, and voids caused by bonding annealing byproduct gases in hybrid bonding technology.

[0006] Another objective of this application is to provide a bonding method based on the semiconductor structure prepared above, so as to improve the bonding interface quality.

[0007] To solve the above-mentioned technical problems, the technical solution adopted in this application is as follows: In a first aspect, this application provides a method for preparing a semiconductor structure, comprising the following steps: Provide a semiconductor substrate with a metal interconnect layer; A dielectric layer is formed on the semiconductor substrate; The dielectric layer is etched to form a groove; A getter layer is first conformally deposited on the dielectric layer, followed by a protective layer, until the groove is filled. The protective layer, the air-absorbing layer, and the dielectric layer are etched to form a through-hole that extends from the groove and connects to the metal interconnect layer. A layer of metal material is filled into the through hole; The thinning process stops at the top of the groove to form a bonding surface, which includes a metal pillar and a protective layer, a getter layer, and a dielectric layer surrounding the metal pillar.

[0008] Furthermore, the air-absorbing layer is a porous structure with plastic deformation capability.

[0009] Furthermore, the air intake layer is one or more of a porous metal layer, a porous alloy layer, and a porous metal oxide layer.

[0010] Furthermore, the porosity of the air-absorbing layer ranges from 20% to 60%.

[0011] Furthermore, the protective layer has a dense structure and a low metal diffusion coefficient.

[0012] Furthermore, after the thinning process, the top dimension of the metal column is X1, and the top outer perimeter dimension of the protective layer is X2, and X1 satisfies... <X2<3X1。

[0013] Furthermore, the same photomask is used for the photolithography process of forming the groove and the through hole, and the photoresist pattern is pulled back during the photolithography process of forming the groove.

[0014] Furthermore, before filling the through-hole with a layer of metallic material, an anti-diffusion layer is deposited within the through-hole.

[0015] Secondly, this application provides a semiconductor structure, comprising: A semiconductor substrate having a metal interconnect layer therein; A dielectric layer is formed on the semiconductor substrate; Metal pillars are formed within the dielectric layer, and the bottom of the metal pillars is connected to the metal interconnect layer; A groove is formed around the metal pillar on the inner surface of the dielectric layer; An air-absorbing layer, conformally formed on the inner surface of the groove; and A protective layer is used to fill the groove where the air-absorbing layer is formed.

[0016] Furthermore, a buffer layer is provided between the dielectric layer and the semiconductor substrate.

[0017] Furthermore, the metal pillar is also surrounded by an anti-diffusion layer.

[0018] Thirdly, this application provides a bonding method for semiconductor structures, including preparing a first semiconductor structure and a second semiconductor structure based on the above-described semiconductor structure using the above-described preparation method. The bonding method includes the following steps: Pretreatment: The first semiconductor structure and the second semiconductor structure are subjected to vacuum heating and surface plasma activation treatment to activate the getter layer; Pre-bonding: Align and bond the bonding surfaces of the pre-treated first and second semiconductor structures, and apply pressure for pre-bonding; Annealing: The pre-bonded semiconductor structure is heat-treated in an inert gas or vacuum environment to complete the bonding.

[0019] Fourthly, this application provides a semiconductor device prepared using the above-described bonding method.

[0020] The unexpected technical effects of this application include: By embedding an getter layer in the dielectric layer near the bonding interface, byproduct gases such as water vapor and hydrogen generated by the condensation reaction of the dielectric layer can be adsorbed during the bonding annealing process. This reduces the accumulation of gases at the interface, lowers the risk of voids forming at the bonding interface, and helps to improve bonding strength, uniformity and yield.

[0021] By setting a protective layer on the outer periphery of the top of the metal pillar, when there is a slight deviation in the alignment of the wafer bonding faces, causing the metal pillar surfaces of the two wafers to not overlap, the protective layer forms a protective barrier at the bonding interface, preventing the metal pillar from directly contacting the dielectric interface of the opposite wafer. This effectively blocks the diffusion of metal atoms into the dielectric layer of the opposite wafer during high-temperature bonding and subsequent processes, thereby improving the reduction in dielectric insulation performance caused by metal contamination.

[0022] To address stress damage caused by alignment misalignment and the difference in thermal expansion coefficients between the metal and dielectric layers, this application provides a dual mitigation mechanism: on the one hand, the protective layer itself possesses good mechanical strength, serving as the first line of defense against the expansion and compression of the metal; on the other hand, the porous getter layer has plastic deformation capability at the high temperature of bonding annealing. When subjected to compressive stress from the metal pillar, the getter layer can undergo micro-deformation to buffer the stress, preventing stress concentration from causing the dielectric layer at the bonding interface to be forcibly squeezed open, resulting in defects such as cracks or delamination. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a hybrid bonding interface in the prior art; Figure 2 This is a flowchart of the method for fabricating the semiconductor structure in Embodiment 1 of this application; Figure 3 This is a schematic diagram of the semiconductor substrate in Embodiment 1 of this application; Figure 4 This is a schematic diagram of forming a dielectric layer on a semiconductor substrate in Embodiment 1 of this application; Figure 5 This is a schematic diagram of the first photoresist layer on the dielectric layer after development in Embodiment 1 of this application; Figure 6 This is a schematic diagram of the grooves etched on the dielectric layer in Embodiment 1 of this application; Figure 7 This is a schematic diagram of the formation of an air-absorbing layer and a protective layer on the dielectric layer in Embodiment 1 of this application; Figure 8 This is a schematic diagram of the formation of a transition layer on the protective layer and the development of the second photoresist layer in Embodiment 1 of this application; Figure 9 This is a schematic diagram of the etched through-hole in Embodiment 1 of this application; Figure 10 This is a schematic diagram of the formation of an anti-diffusion layer in the through-hole in Embodiment 1 of this application; Figure 11 This is a schematic diagram of filling the through hole with a layer of metal material in Embodiment 1 of this application; Figure 12 This is a schematic diagram of the thinning process in Embodiment 1 of this application; Figure 13 This is a schematic diagram of wafer bonding in Embodiment 2 of this application; Figure 14 This is a partial schematic diagram of the wafer bonding interface in Embodiment 2 of this application; Figure 15 This is a partial schematic diagram of the wafer bonding interface during the expansion of the metal pillar in Embodiment 2 of this application.

[0024] Reference numerals: 10, semiconductor substrate; 11, metal interconnect layer; 20, buffer layer; 21, dielectric layer; 22, trench; 30, first photoresist layer; 31, first slot; 40, gas-absorbing layer; 50, protective layer; 60, transition layer; 70, second photoresist layer; 71, second slot; 80, through-hole; 81, anti-diffusion layer; 90, metal material layer; 91, metal pillar. Detailed Implementation

[0025] The following is in conjunction with the appendix Figure 2-15 This application will be described in further detail.

[0026] Example 1 This application discloses a method for fabricating a semiconductor structure. (Refer to...) Figure 2 The method for fabricating a semiconductor structure includes the following steps: Step S100: Provide a semiconductor substrate 10 having a metal interconnect layer 11; Step S200: Form a dielectric layer 21 on the semiconductor substrate 10; Step S300: Etch dielectric layer 21 to form groove 22; Step S400: First, conformally deposit the getter layer 40 on the dielectric layer 21, and then deposit the protective layer 50 until the groove 22 is filled; Step S500: Etch the protective layer 50, the gas-absorbing layer 40 and the dielectric layer 21 to form a through hole 80 that extends from the groove 22 and connects to the metal interconnect layer 11; Step S600: Fill the through hole 80 with a metal material layer 90; Step S700: The thinning process stops at the top of the groove 22 to form a bonding surface, which includes a metal pillar and a protective layer 50, a getter layer 40, and a dielectric layer 21 surrounding the metal pillar.

[0027] Reference Figure 3 In step S100, the semiconductor substrate 10 is a wafer that has completed front-end processing (FEOL) and partial back-end processing (BEOL). Partial back-end processing refers to the completion of the fabrication of the metal interconnect layer 11. The metal interconnect layer 11 is located on the front side of the wafer, surrounded by an interlayer dielectric (ILD) layer. Below the metal interconnect layer 11 is a semiconductor structure containing transistors, all fabricated using existing technologies, which will not be elaborated further in this application. The metal interconnect layer 11 typically uses copper (Cu) or aluminum (Al) as the conductive substrate to enable electrical signal connectivity between devices within the wafer. In the subsequent hybrid bonding process, the front side of this wafer will be bonded to the front side of another wafer to achieve three-dimensional integration between the two wafers.

[0028] In step S200, the surface of the semiconductor substrate 10 is first cleaned to remove impurity particles or other contaminants. After cleaning, a dielectric layer 21 is deposited on the surface of the semiconductor substrate 10, such as... Figure 4 As shown, the dielectric layer 21 is the core functional layer for wafer bonding, and its functions include providing a bonding interface, ensuring bonding strength, and achieving inter-wafer insulation.

[0029] The dielectric layer 21 may be made of at least one of the following materials: silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbide (SiC) and their derivative variants; the dielectric layer 21 may also be a multilayer composite structure composed of the above materials.

[0030] The bonding reaction mechanisms of different dielectric materials differ significantly: when the dielectric layer 21 is SiO2, a dehydration condensation reaction occurs at the bonding interface, and the surface -OH groups form Si-O-Si bonds during annealing, releasing H2O. When the dielectric layer 21 is SiCN, a dehydrogenation condensation reaction occurs at the bonding interface, and the surface Si-H groups react with NH bonds to form Si-N bonds, releasing H2. Because the bonding strength of SiCN is higher than that of SiO2, SiCN is generally used as the dielectric layer 21.

[0031] Considering that SiCN may have insufficient adhesion when directly deposited on the semiconductor substrate 10, this embodiment adopts a double-layer stacked structure of buffer layer 20 and dielectric layer 21: first, SiO2 is deposited on the semiconductor substrate 10 as buffer layer 20 with a thickness of 50-200nm; then, SiCN is deposited on buffer layer 20 as dielectric layer 21 with a thickness of 200-500nm.

[0032] The role of SiO2 as a buffer layer 20 is that it has excellent interfacial compatibility with the semiconductor substrate 10, and can form a stable transition bond with the SiCN dielectric layer 21. This allows it to act as a transitional adhesion between the dielectric layer 21 and the semiconductor substrate 10, effectively relieving film stress, ensuring the mechanical integrity of the entire stacked structure, and avoiding defects such as film peeling and cracking during subsequent bonding or annealing processes.

[0033] The process of depositing a buffer layer 20 on the semiconductor substrate 10 and depositing a dielectric layer 21 on the buffer layer 20 can be any one of plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, low-pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, and atmospheric pressure chemical vapor deposition.

[0034] Reference Figure 5 and Figure 6 In step S300, the method of forming the groove 22 on the dielectric layer 21 includes the following steps: S310: Photoresist is coated onto the dielectric layer 21 to form a first photoresist layer 30. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, photolithography processes such as photomask exposure and development are used to pattern the first photoresist layer 30, exposing the first groove 31, such as... Figure 5 As shown.

[0035] S320: The first slot 31 is enlarged using a pull-back process. The purpose of this enlargement is to allow the same photomask to be used in step S310 and the subsequent step S510. The pull-back process is performed in an ashing machine or a reactive ion etching machine. The reactive oxygen free radicals generated by the oxygen plasma have strong oxidizing properties and can react with the photoresist to generate volatile gases such as CO2 and H2O. Under conditions of low bias power (50-150W) and relatively high cavity pressure (e.g., 200-500mTorr), gas molecule collisions are frequent, the directionality of the plasma is weakened, and chemical reactions dominate, allowing reactive oxygen free radicals to attack the photoresist from all directions. Therefore, the sidewalls of the first slot 31 and the top of the first photoresist layer 30 are etched at nearly the same rate, resulting in uniform retreat of the sidewalls and increasing the size of the first slot 31. Figure 5 As shown. The size increment of the first slot 31 can be controlled by adjusting the pull-back process time.

[0036] S330: Using the first photoresist layer 30 after the pull-back process as a mask layer, the dielectric layer 21 is etched to form a groove 22. The groove 22 can be formed by plasma dry etching. The etching gas includes at least one of carbon tetrafluoride and sulfur hexafluoride, and also includes inert gases such as argon. After etching, the first photoresist layer 30 is removed by an ashing process. Figure 6 As shown.

[0037] Reference Figure 7 In step S400, the method of conformally depositing the getter layer 40 on the dielectric layer 21 and then depositing the protective layer 50 includes the following steps: S410: Conformally deposited getter layer 40, which covers the bottom wall and sidewalls of the groove 22 and the surface of the dielectric layer 21, such as Figure 7 As shown. The gas-absorbing layer 40 has a porous structure and plastic deformation capability, with a porosity ranging from 20% to 60%. The porous structure enables the gas-absorbing layer 40 to adsorb gases generated during bonding annealing; the plastic deformation capability allows the gas-absorbing layer 40 to buffer the stress generated by the thermal expansion of the copper pillar.

[0038] The getter layer 40 can be one or more of porous metal layers, porous alloy layers, and porous metal oxide layers, specifically porous nickel, porous titanium, porous palladium, porous titanium-based alloys, porous zirconium-based alloys, porous alumina, porous zirconium oxide, etc. Methods for depositing the getter layer 40 include physical vapor deposition (including co-sputtering, pulsed laser deposition, etc.) and chemical vapor deposition (including metal-organic chemical vapor deposition, atomic layer deposition, etc.).

[0039] The getter layer 40 in this application uses porous nickel. Taking co-sputtering as an example, the deposition method is as follows: a nickel target and an immiscible sacrificial material target (such as a carbon target or a carbon-based polymer target) are used simultaneously in the sputtering chamber, or a carbon source is introduced into the reaction gas. Nickel and the sacrificial material are co-deposited on the dielectric layer 21 to form a nickel-carbon composite film. Subsequently, the sacrificial material (such as carbon) is removed by low-temperature oxidation and ashing, leaving a porous nickel framework. By adjusting the sputtering power ratio of the nickel target to the sacrificial material target, the ratio of nickel to sacrificial material can be adjusted, thereby controlling the porosity of the getter layer 40; the higher the proportion of sacrificial material, the greater the porosity of the getter layer 40. By adjusting the sputtering time, the deposition thickness of the getter layer 40 can be controlled.

[0040] An exemplary process is as follows: I. Example Parameters of Co-sputtering Process Equipment and Targets Sputtering equipment: magnetron sputtering system equipped with at least two independent radio frequency (RF) or direct current (DC) target positions.

[0041] Target selection: Nickel target: purity ≥99.95%, diameter 2-4 inches (common size); Sacrificial material targets: high-purity graphite targets (carbon targets) or polymer-based composite targets (such as polytetrafluoroethylene targets).

[0042] Substrate: A wafer with a pre-deposited dielectric layer 21.

[0043] Splashing preparation Cavity vacuum: Evacuated to a background vacuum ≤5×10 -6 Torr (approximately 6.7 × 10⁻⁶) -4 Pa); Substrate treatment: Argon ion cleaning (e.g., RF bias power 50W, time 5 minutes) to remove surface contaminants.

[0044] Key parameters of co-sputtering Working gas: Argon (Ar), purity ≥ 99.999%; Gas flow rate: 20-30 sccm, maintaining chamber pressure at 2-5 mTorr (approximately 0.27-0.67 Pa); Nickel target power: DC power supply, power 100-200W (corresponding to a deposition rate of about 1-2 nm / min). Carbon target power: RF power supply, power 50-150W (adjust key parameters for carbon content). Power ratio adjustment: By adjusting the power ratio of the carbon target to the nickel target (e.g., 1:2 to 1:1), the proportion of carbon in the nickel-carbon composite film can be controlled (the carbon content can usually be adjusted within the range of 20%-50% atomic ratio). Substrate temperature: room temperature to 100℃ (avoid high temperatures that could cause premature carbon decomposition or nickel grain coarsening). Deposition time: Set according to the target thickness. For example, when the deposition thickness is 100nm, the time is about 50-100 minutes (depending on the deposition rate). Substrate rotation: 5-20 rpm, to ensure uniformity of film composition and thickness.

[0045] II. Post-processing (low-temperature oxidation and ashing) Equipment: Tube furnace or plasma ashing system.

[0046] Process conditions: Atmosphere: Oxygen (O2) or oxygen-containing gas mixture (e.g., O2 / Ar=1:1); Temperature: 300-400℃ (low temperature should be avoided to prevent excessive oxidation of nickel or structural collapse); Time: 30-60 minutes (adjust according to carbon content to ensure complete carbon removal); Gas flow rate: 100-200 sccm, atmospheric pressure or low vacuum (e.g., 1-10 Torr). Expected results: Carbon is oxidized to CO / CO2 and volatilized, forming a porous nickel framework with a porosity of approximately 30%-60% (depending on the initial carbon content).

[0047] III. Key Control Points Porosity control: The higher the carbon target power, the greater the carbon content, and the higher the final porosity.

[0048] Structural integrity: The oxidation temperature needs to be below the significant oxidation threshold of nickel (about 400°C) to avoid the formation of too much NiO, which would lead to embrittlement of the framework.

[0049] Thickness uniformity: Porous structures may cause changes in the effective refractive index, so ellipsometry or profilometer can be used to monitor thickness and uniformity (e.g., intra-sheet non-uniformity ≤ 5%).

[0050] IV. Typical Example Parameter Combinations Nickel target power DC: 150W, deposition rate approximately 1.5 nm / min; Carbon target power RF: 75W, carbon content approximately 30% (atomic ratio); A power ratio of C:Ni:1:2 corresponds to a medium porosity (approximately 40%). Deposition time: 60 minutes, target thickness approximately 90 nm; Oxidation temperature: 350℃, hold for 45 minutes; The final porous nickel thickness is approximately 60 nm, with a thickness reduction rate of approximately 33% (due to decarburization densification).

[0051] S420: After the getter layer 40 is deposited, a protective layer 50 is deposited on the getter layer 40. The protective layer 50 covers the getter layer 40 and completely fills the groove 22. Figure 7 As shown. The protective layer 50 has a dense structure and a low copper diffusion coefficient, and can be any one of tantalum, titanium, tantalum nitride, titanium nitride, silicon nitride, silicon carbide, or a multilayer composite structure composed of these materials.

[0052] Taking a titanium / tantalum / silicon nitride composite structure as an example, the titanium layer, tantalum layer, and silicon nitride layer can be deposited layer by layer using physical vapor deposition or atomic layer deposition. The titanium layer acts as an adhesion layer, exhibiting good adhesion to the getter layer 40; the tantalum layer acts as a core diffusion barrier layer, preventing copper and other metal atoms from migrating from the copper pillars to the dielectric layer 21; the silicon nitride layer acts as a sealing and protective layer 50, preventing the tantalum layer from being oxidized in subsequent processes and providing an additional barrier. Since the tantalum layer is the primary diffusion barrier in the protective layer 50, it should be the thickest layer within the protective layer 50.

[0053] The following is an example of common process parameters based on the combination of physical vapor deposition and plasma-enhanced chemical vapor deposition: Process sequence: deposit Ti layer, deposit Ta layer, deposit SiN layer in sequence.

[0054] 1. Titanium layer Process method: Physical vapor deposition (PVD) - DC magnetron sputtering; Temperature: Room temperature - 100℃ (to prevent copper recrystallization or excessive diffusion); Chamber pressure: 1-5 mTorr (argon atmosphere); Sputtering power: 1-5 kW (DC); Deposition rate: 10-50 Å / s; Target thickness: 50-150 Å (5-15 nm). This layer does not need to be too thick; it only needs to be thick enough to ensure adhesion. Excessive thickness will increase the overall resistance.

[0055] 2. Tantalum layer Process method: Physical vapor deposition (PVD) - DC magnetron sputtering; Temperature: Room temperature - 150℃; Chamber pressure: 1-5 mTorr (argon atmosphere); Sputtering power: 3-10 kW (DC, generally higher than Ti sputtering power); Deposition rate: 5-30 Å / s; Target thickness: 200-500 Å (20-50 nm), its thickness directly determines the barrier lifetime and mechanical strength.

[0056] 3. Silicon nitride layer Process method: Plasma-enhanced chemical vapor deposition (PECVD); Temperature: 300℃-400℃ (typical temperature for PECVD, which helps to obtain dense films). Chamber pressure: 1-3 Torr; Reaction gases: SiH4 (silane) + NH3 (ammonia) + N2 (nitrogen); RF power: 300-800 W (13.56 MHz); Deposition rate: 500-1500 Å / min; Target thickness: 500-1000 Å (50-100 nm). Although the thickness value may seem larger than that of the Ti layer, its density is low and it is a dielectric. In terms of functional thickness and barrier performance, the core is still the middle Ta layer. The main function of the SiN layer is sealing and protection.

[0057] Reference Figure 8 and Figure 9 In step S500, the method of etching the protective layer 50, the gas-absorbing layer 40, and the dielectric layer 21 to form the via 80 includes the following steps: S510: SiO2 is deposited on the protective layer 50 as a transition layer 60, and then photoresist is coated on the transition layer 60 to form a second photoresist layer 70. Through photolithography processes such as photomask exposure and development, the second photoresist layer 70 is patterned, exposing the second groove 71, as shown below. Figure 8 As shown. The photomask used in this step is the same as the photomask used in step S310, which can save on photomask costs.

[0058] S520: Using the second photoresist layer 70 as a mask layer, the protective layer 50, the absorbent layer 40, and the dielectric layer 21 are etched up to the semiconductor substrate 10 to form a via 80 connected to the connection points on the metal interconnect layer 11. That is, the connection points of the metal interconnect layer 11 are exposed at the bottom of the via 80. After etching, the second photoresist layer 70 is removed using an ashing process. The resulting via 80 has sloping sidewalls and a gradually increasing radial dimension; specifically, its radial dimension gradually increases from the bottom to the top. Figure 9 As shown.

[0059] The etching method for the via 80 can be plasma dry etching. Since this step requires etching multiple layers of different materials, and considering that different materials are suited to different etching gases, a staged etching method can be adopted. For example, boron trichloride and carbon tetrafluoride can be used as etching gases to etch the protective layer 50, chlorine and boron trichloride can be used as etching gases to etch the getter layer 40, and carbon tetrafluoride and trifluoromethane can be used as etching gases to etch the dielectric layer 21.

[0060] Since the same photomask is used, the through hole 80 formed in step S520 and the groove 22 formed in step S330 are technically self-aligned. At the same time, through the flaring process of the pull-back process in step S320, the size (diameter) of the through hole 80 passing through the groove 22 is smaller than the size (width or diameter) of the groove 22.

[0061] After etching the via 80, in order to prevent metal atoms (such as copper atoms) in the metal material layer 90 (such as a copper layer) subsequently filled within the via 80 from diffusing into the surrounding dielectric layer 21 and buffer layer 20, an anti-diffusion layer 81 can be deposited within the via 80. Figure 10 As shown. The performance requirements that the anti-diffusion layer 81 needs to meet include: having an extremely low copper diffusion coefficient, which can effectively block the penetration of copper atoms; and having excellent conductivity to ensure that a stable and low-loss conductive path is formed between the subsequent metal pillars and the metal interconnect layer 11 in the semiconductor substrate 10.

[0062] Considering the above performance requirements, and taking into account the material's anti-diffusion effect, conductivity, process compatibility, and cost, the anti-diffusion layer 81 can be any one of tantalum (Ta), ruthenium (Ru), or cobalt (Co), or a composite layer structure composed of two or more of these materials. Based on the size and aspect ratio of the via 80 and the material properties of the anti-diffusion layer 81, the deposition method can employ processes such as physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0063] Reference Figure 11 In step S600, an electrochemical electroplating process is used to fill the through hole 80 with a metal material layer 90. In this embodiment, the filled metal material layer 90 is a copper layer; in other feasible embodiments, the metal material layer 90 can also be a metal such as tungsten (W), aluminum (Al), or silver (Ag). The electrochemical electroplating process specifically includes the following steps: S610, Pretreatment: A copper seed layer is deposited in the via 80 with an anti-diffusion layer 81 formed by physical vapor deposition or atomic layer deposition. The copper seed layer is the substrate for subsequent copper electroplating adhesion and growth. Before electroplating, the wafer is cleaned to remove surface oxides and organic matter to ensure the activity of the seed layer. The cleaning steps include acid cleaning, organic cleaning, pure water cleaning and drying treatment in sequence.

[0064] S620, Electroplating solution immersion: The wafer is immersed in an electroplating solution containing additives. The main components of the electroplating solution include copper source (copper sulfate), acid (sulfuric acid and hydrochloric acid), accelerator (sodium 3-mercapto-1-propanesulfonate or sodium dithiodipropanesulfonate and other sulfur-containing compounds, which are adsorbed on the seed layer surface at the bottom of the through hole 80 to accelerate the reduction and deposition of copper ions and promote the growth of the copper layer from bottom to top), inhibitor (polyethylene glycol or polyvinylpyrrolidone and other high molecular polymers, which are used to inhibit the deposition rate of copper ions and prevent the top of the through hole 80 from closing prematurely), and leveling agent (nitrogen-containing macromolecules, which are adsorbed on the protruding parts of the plating surface to inhibit copper deposition on the protruding parts and promote deposition on the recessed parts, so as to make the copper layer surface smooth).

[0065] S630, Electrochemical Deposition: After applying current, various additives work synergistically with copper ions to achieve bottom-up filling of the metal material layer 90 within the via 80, such as... Figure 11 As shown.

[0066] S640, Post-processing: The wafer is cleaned and dried to remove residual plating solution and additives; then annealing is performed to release the internal stress generated during the copper layer deposition process, increase the density of the copper layer, refine the copper grains, reduce resistivity, enhance the interfacial bonding between the copper layer and the anti-diffusion layer 81, and prevent peeling during subsequent packaging.

[0067] Reference Figure 12 In step S700, a thinning process is performed by chemical mechanical polishing, which stops at the top of the groove 22 (or the top of the dielectric layer 21) to form a bonding surface. The bonding surface includes a metal pillar 91 and a protective layer 50, a getter layer 40, and a dielectric layer 21 surrounding the metal pillar 91.

[0068] Prepared using the above method Figure 12 The semiconductor structure shown includes: Semiconductor substrate 10, having a metal interconnect layer 11 therein; Dielectric layer 21 is formed on semiconductor substrate 10; Metal pillar 91 is formed within dielectric layer 21, and the bottom of metal pillar 91 is connected to metal interconnect layer 11; Grooves 22 are formed around metal pillars 91 on the inner surface of dielectric layer 21; The air intake layer 40 is formed on the inner surface of the groove 22; and A protective layer 50 is used to fill the groove 22 where the air-absorbing layer 40 is formed.

[0069] Furthermore, in order to provide adhesion and stress relief between the dielectric layer 21 and the semiconductor substrate 10, a buffer layer 20 is provided between the dielectric layer 21 and the semiconductor substrate 10. To prevent metal atoms of the metal pillar 91 from diffusing into the surrounding dielectric layer 21 and buffer layer 20, an anti-diffusion layer 81 is provided around the metal pillar 91.

[0070] Example 2 This application discloses a bonding method for a semiconductor structure, using the semiconductor structure prepared in Example 1, including the following steps: Pretreatment: The first semiconductor structure and the second semiconductor structure prepared in Example 1 were subjected to vacuum heating and surface plasma activation treatment to activate the gas-absorbing layer 40.

[0071] The vacuum level is set to 1×10. -3 Pa-5×10 -3 Pa, this vacuum range can effectively prevent impurities such as oxygen and water vapor in the air from reacting with the surface of the semiconductor structure and the getter layer 40, thus preventing the getter layer 40 from failing prematurely; the vacuum heating temperature range is 100℃-300℃, the vacuum heating time range is 10 minutes-30 minutes, and the heating time is matched with the heating temperature.

[0072] Immediately after vacuum heating treatment, surface plasma activation treatment is performed to prevent contamination of the semiconductor structure bonding surface and getter layer 40 by contact with air. The power of plasma activation treatment is 25W-60W. If the power is too low, the activation effect will be insufficient and it will be unable to remove contaminants and inert layers from the bonding surface. If the power is too high, it will damage the surface of the semiconductor structure.

[0073] After the above pretreatment, a large number of unsaturated bonds and active adsorption sites are formed on the surface of the activated getter layer 40, which has higher chemical activity, thereby helping to improve the adsorption efficiency of the getter layer 40 for gases such as hydrogen and water vapor.

[0074] Pre-bonding: The bonding faces of the pretreated first and second semiconductor structures are aligned and bonded together, and a slight pressure (e.g., 1-10 kN) is applied. The pressure is applied uniformly through surface contact at a rate of 0.5 kN / min-1 kN / min. Pre-bonding is completed at room temperature using van der Waals forces and hydrogen bonds on the wafer surface. This ensures that the semiconductor structure will not misalign during subsequent annealing processes and guarantees that the pre-bonded structure possesses sufficient mechanical strength to meet the operational requirements of transport, transfer, and subsequent annealing processes.

[0075] Annealing: The pre-bonded semiconductor structure is heat-treated in an inert gas or vacuum environment by step heating method, including: (1) Heating stage: from room temperature to 200℃-250℃ at a heating rate of 5℃ / min-10℃ / min, and held for 30 minutes-60 minutes. The main purpose of this stage is to slowly remove the trace amount of water vapor and adsorbed impurity gas remaining at the pre-bonding interface, and at the same time to allow the active groups on the surface of the dielectric layer 21 to diffuse fully, in preparation for the subsequent condensation reaction. (2) Isothermal reaction stage: Continue heating to 350℃-450℃ at a heating rate of 3℃ / min-5℃ / min, and hold for 60 minutes-120 minutes. This stage is the core stage of the bonding reaction. The active groups at the interface of dielectric layer 21 undergo condensation reaction at high temperature to form strong covalent bonds. The metal atoms (copper atoms) at the interface of metal pillar 91 (copper pillar) diffuse and recrystallize with each other at high temperature, so that the two independent metal pillars 91 (copper pillar) fuse into a single conductor, thereby realizing the permanent bonding of copper-copper and dielectric-dielectric. (3) Cooling stage: Cool slowly to room temperature at a cooling rate of 2℃ / min-5℃ / min to avoid thermal stress inside the semiconductor structure caused by excessive cooling, prevent defects such as cracks and delamination at the bonding interface, and ensure the stability of the bonding structure.

[0076] During the annealing process, the gas-absorbing layer 40 can adsorb the gas generated by the condensation reaction of the medium layer 21, thereby reducing the accumulation of gas at the interface and reducing the risk of voids forming at the bonding interface.

[0077] In some cases, due to process variations, there may be slight misalignment between the bonding faces of the two wafers, such as... Figure 13 and Figure 14 As shown, the surfaces of the metal pillars 91 on the two wafers do not overlap. The semiconductor structure fabrication method provided in this application forms a protective layer 50 on the outer periphery of the top of the metal pillar 91. When the surfaces of the metal pillars 91 on the two wafers do not overlap, the protective layer 50 forms a protective barrier at the bonding interface, preventing the surface of the metal pillar 91 from directly contacting the dielectric layer 21 of the opposite wafer. This effectively blocks the diffusion of metal atoms from the metal pillar 91 into the dielectric layer 21 of the opposite wafer during high-temperature bonding and subsequent processes, thereby improving the insulation performance of the dielectric layer 21 caused by metal contamination.

[0078] Furthermore, refer to Figure 14, the top size of the metal pillar 91 is X1 (illustrated with the attitude of the semiconductor structure at the bottom), the outer peripheral size of the top of the protective layer 50 is X2, and X1 < X2 < 3X1 is satisfied. Within this range, the larger X2 is, the greater the distance that the metal pillar 91 is allowed to be misaligned, that is, the better the fault tolerance. However, if X2 is too large, it will cause material waste and excessive occupation of space by the protective layer 50. Therefore, as a preferred range, 1.5X1 < X2 < 2X1 needs to be satisfied, which has sufficient fault tolerance and will not cause a large space occupation.

[0079] The protective layer and getter layer composite structure provided by the present application can not only improve the problems of voids caused by the above-mentioned metal diffusion and by-products of bonding annealing gas, but also improve the problem of thermo-mechanical stress damage at high temperatures, as follows: Due to the significant difference in the thermal expansion coefficients of the metal pillar 91 and the dielectric layer 21, during the high-temperature annealing process, the volume expansion degree of the metal is much greater than that of the surrounding dielectric layer 21, as Figure 15 shown by the red dotted line area in. This non-uniform expansion will generate huge local stress at the copper-dielectric interface, causing the copper to extrude and possibly push open or damage the dielectric layer 21, introducing mechanical defects such as micro-cracks or delamination at the interface. To address this problem, the protective layer and getter layer composite structure of the present application provides a dual mitigation mechanism.

[0080] On the one hand, the protective layer 50 itself has good mechanical strength and can serve as the first line of defense against the expansion extrusion of the metal. On the other hand, the porous getter layer 40 has plastic deformation ability at the high temperature of bonding annealing. When subjected to the extrusion stress from the metal pillar 91, the getter layer 40 can undergo micro-deformation to buffer the stress, as shown by the blue dotted line area in Figure 15 . In this way, it avoids the dielectric layer 21 at the bonding interface being rigidly pushed open due to stress concentration, resulting in defects such as cracks or delamination.

[0081] In summary, the unexpected technical effects of the present application include: the getter layer 40 can adsorb the gas generated by the condensation reaction of the dielectric layer 21 during the bonding annealing process, reducing the risk of void formation at the bonding interface. When there is a slight deviation in the alignment of the wafer bonding surface, the protective layer 50 can block the diffusion of metal atoms to the dielectric layer 21 of the opposite wafer. At the same time, the getter layer 40 can buffer the stress generated by the expansion of the metal pillar 91, avoiding stress damage to the dielectric layer 21 at the bonding interface. By using the semiconductor structure preparation method and bonding method provided by the present application, the prepared semiconductor device has a high bonding interface quality.

[0082] The above are all the preferred embodiments of the present application, and the protection scope of the present application is not limited thereby. Therefore, all equivalent changes made according to the structure, shape, and principle of the present application should be covered within the protection scope of the present application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that: Includes the following steps: Provide a semiconductor substrate with a metal interconnect layer; A dielectric layer is formed on the semiconductor substrate; The dielectric layer is etched to form a groove; A getter layer is first conformally deposited on the dielectric layer, followed by a protective layer, until the groove is filled. The protective layer, the air-absorbing layer, and the dielectric layer are etched to form a through-hole that extends from the groove and connects to the metal interconnect layer. A layer of metal material is filled into the through hole; The thinning process stops at the top of the groove to form a bonding surface, which includes a metal pillar and a protective layer, a getter layer, and a dielectric layer surrounding the metal pillar.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The air-absorbing layer is a porous structure with plastic deformation capability.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The air intake layer is one or more of the following: a porous metal layer, a porous alloy layer, and a porous metal oxide layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The porosity of the air-absorbing layer ranges from 20% to 60%.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that: The protective layer has a dense structure and a low metal diffusion coefficient.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that: After the thinning process, the top dimension of the metal column is X1, and the top outer perimeter dimension of the protective layer is X2, and X1 satisfies... <X2<3X1。 7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The same photomask is used for the photolithography process that forms the groove and the through hole, and the photoresist pattern is pulled back during the photolithography process that forms the groove.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before filling the through-hole with a layer of metallic material, an anti-diffusion layer is deposited inside the through-hole.

9. A semiconductor structure, characterized in that: include: A semiconductor substrate having a metal interconnect layer therein; A dielectric layer is formed on the semiconductor substrate; Metal pillars are formed within the dielectric layer, and the bottom of the metal pillars is connected to the metal interconnect layer; A groove is formed around the metal pillar on the inner surface of the dielectric layer; An air-absorbing layer, conformally formed on the inner surface of the groove; and A protective layer is used to fill the groove where the air-absorbing layer is formed.

10. The semiconductor structure according to claim 9, characterized in that: A buffer layer is also provided between the dielectric layer and the semiconductor substrate.

11. The semiconductor structure according to claim 9, characterized in that: The metal pillar is also surrounded by an anti-diffusion layer.

12. A bonding method for a semiconductor structure, comprising a first semiconductor structure and a second semiconductor structure prepared by the preparation method according to any one of claims 1-8 or based on the semiconductor structure according to any one of claims 9-11, characterized in that, Includes the following steps: Pretreatment: The first semiconductor structure and the second semiconductor structure are subjected to vacuum heating and surface plasma activation treatment to activate the getter layer; Pre-bonding: Align and bond the bonding surfaces of the pre-treated first and second semiconductor structures, and apply pressure for pre-bonding; Annealing: The pre-bonded semiconductor structure is heat-treated in an inert gas or vacuum environment to complete the bonding.

13. A semiconductor device, characterized in that: It was prepared using the bonding method described in claim 12.

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