A package of a semiconductor die and a method of manufacturing the same

Abstract

The application relates to a semiconductor die package and a manufacturing method thereof. In the manufacturing method of the semiconductor die package, in the process of preparing an initial packaging substrate, a second insulating layer and a second metal layer are respectively arranged on two first conductive circuit layers, the lower second metal layer is subjected to a patterning treatment, a first shielding layer is formed, the first shielding layer is located below the conductive pad, a second shielding layer is formed at the bottom of the second groove, the second shielding layer, the first conductive block and the first shielding layer are electrically connected, the first shielding layer and the second shielding layer effectively surround the first semiconductor die, and the first semiconductor die can be effectively prevented from being interfered by electromagnetic waves.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a package for a semiconductor die and a method for manufacturing the same. Background Technology

[0002] Semiconductor packaging, a crucial step in integrated circuit manufacturing, is a core technology that enables electrical connection, mechanical support, and environmental protection between chips and external circuits. It not only provides physical protection for delicate and fragile chips, preventing damage from external moisture, dust, and mechanical impacts, but also achieves efficient signal transmission and power supply between the chip and the printed circuit board (PCB) through structures such as metal leads, solder balls, or bumps. As semiconductor technology evolves towards higher density, higher performance, and lower power consumption, packaging technology has developed from traditional lead-based packaging (such as DIP) to advanced forms such as ball grid arrays (BGA), chip-scale packaging (CSP), system-in-package (SiP), and 3D packaging. These technologies play an irreplaceable role in improving integration, reducing size, optimizing heat dissipation, and lowering signal delay, becoming a vital support for the miniaturization, intelligence, and multifunctionality of electronic devices. With the miniaturization of semiconductor packaging, optimizing the manufacturing process to improve the electromagnetic shielding performance of semiconductor packaging has attracted widespread attention in the industry. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a semiconductor die package and its manufacturing method.

[0004] To achieve the above objectives, the present invention provides a method for manufacturing a package of a semiconductor die, comprising the following steps:

[0005] A first core board is provided, the first core board including a core board body and conductive circuit layers covering the upper and lower surfaces of the core board body, and a first conductive block covering the middle region of the lower surface of the core board body.

[0006] A first insulating layer and a first metal layer are stacked on both the upper and lower surfaces of the first core board. The two first metal layers are patterned to form first conductive circuit layers. Multiple conductive pads are formed on the first insulating layer on the lower surface of the first core board, and the multiple conductive pads are correspondingly arranged with the first conductive block.

[0007] Next, a second insulating layer and a second metal layer are stacked on the two first conductive line layers respectively. The two second metal layers are patterned to form a second conductive line layer and a first shielding layer. The first shielding layer is located below the conductive pad.

[0008] Next, multiple conductive structures are formed, each of which is electrically connected to the first shielding layer and the first conductive block to form an initial packaging substrate.

[0009] The initial packaging substrate is perforated to form a first groove that exposes the conductive pads, and a portion of the first conductive block is removed during the formation of the first groove.

[0010] A first semiconductor die is disposed in the first groove, the first semiconductor die is electrically connected to the conductive pad, and a first encapsulation layer is formed in the first groove to cover the first semiconductor die.

[0011] Next, a second groove is formed, and multiple through holes are formed at the bottom of the second groove to expose the first conductive block.

[0012] Next, a second shielding layer is formed at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected.

[0013] Next, a second encapsulation layer is formed to fill the second groove.

[0014] In a preferred embodiment, a first conductive via is formed in the core board body, and the first conductive via is electrically connected to the conductive circuit layers on the upper and lower surfaces of the core board body.

[0015] In a preferred embodiment, before the first metal layer is formed on the upper and lower surfaces of the first core board, a through hole is formed in the first insulating layer, and then a second conductive through hole is formed in the first insulating layer during the formation of the first metal layer.

[0016] In a preferred embodiment, a pad protection layer covering the conductive pads is formed before the second insulating layer and the second metal layer are respectively stacked on the two first conductive lines.

[0017] In a preferred embodiment, a second semiconductor die is further formed on the second conductive line layer; then a third encapsulation layer is formed, which encapsulates the second semiconductor die.

[0018] In a preferred embodiment, a third semiconductor die is disposed on the second packaging layer, and a fourth packaging layer is formed on the third semiconductor die, such that the upper surface of the fourth packaging layer is flush with the upper surface of the second insulating layer above.

[0019] In a preferred embodiment, a third conductive line layer is formed on the upper surface of the fourth encapsulation layer and on the upper surface of the second insulating layer above, such that the third conductive line layer is electrically connected to the third semiconductor die.

[0020] In a preferred embodiment, when a second semiconductor die is formed on the second conductive line layer, a fourth semiconductor die is formed on the third conductive line layer.

[0021] As a preferred embodiment, a passivation protective layer is formed on the first shielding layer.

[0022] The present invention also proposes a package for a semiconductor die, wherein the package for the semiconductor die is manufactured using the above-described manufacturing method.

[0023] Compared with the prior art, the semiconductor die package and its manufacturing method of the present invention have the following advantages:

[0024] In the manufacturing method of the semiconductor die package of the present invention, during the preparation of the initial package substrate, a second insulating layer and a second metal layer are respectively stacked on the two first conductive line layers, and the lower second metal layer is patterned to form a first shielding layer. The first shielding layer is located below the conductive pad, and then a second shielding layer is formed at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected, so that the first shielding layer and the second shielding layer effectively surround the first semiconductor die, thereby effectively preventing the first semiconductor die from electromagnetic interference. In addition, by integrating the first, second, third and fourth semiconductor dies on the package substrate during the formation of the package substrate, the packaging process is simplified and the miniaturization trend of packaging is realized. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the first core board in the manufacturing method of the semiconductor die package of the present invention.

[0026] Figure 2 This is a schematic diagram of the structure forming a first conductive line layer and multiple conductive pads in the manufacturing method of the semiconductor die package of the present invention.

[0027] Figure 3 This is a schematic diagram of the structure in which the second conductive line layer and the first shielding layer are formed in the manufacturing method of the semiconductor die package of the present invention.

[0028] Figure 4 This is a schematic diagram of the structure for forming the first groove in the manufacturing method of the semiconductor die package of the present invention.

[0029] Figure 5 This is a schematic diagram of the structure of forming a first semiconductor die and a first encapsulation layer in the manufacturing method of the semiconductor die package of the present invention.

[0030] Figure 6 This is a schematic diagram of the structure for forming the second groove and the second shielding layer in the manufacturing method of the semiconductor die package of the present invention.

[0031] Figure 7 This is a schematic diagram of the structure forming a second packaging layer, a third semiconductor die, a fourth packaging layer, and a third conductive line layer in the manufacturing method of the semiconductor die package of the present invention.

[0032] Figure 8 This is a schematic diagram of the structure forming a second semiconductor die, a fourth semiconductor die, and a third packaging layer in the manufacturing method of the semiconductor die package of the present invention. Detailed Implementation

[0033] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0035] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0036] like Figures 1 to 8 As shown, this embodiment provides a method for manufacturing a package of a semiconductor die, the method comprising the following steps:

[0037] like Figure 1 As shown, a first core board is provided, the first core board including a core board body 100 and conductive circuit layers 101 covering the upper and lower surfaces of the core board body 100, and a first conductive block 102 covering the middle region of the lower surface of the core board body 100.

[0038] In a specific embodiment, the first chip is made of resin, ceramic or glass, and the conductive line layer 101 and the first conductive block 102 can be a copper metal layer. More specifically, the copper metal layer can be formed by electroplating or copper plating, and then the conductive line layer 101 and the first conductive block 102 can be formed by patterning.

[0039] In a specific embodiment, a first conductive via 103 is formed in the core board body 100. The first conductive via 103 is electrically connected to the conductive circuit layer 101 on the upper and lower surfaces of the core board body 100. More specifically, the core board body 100 is opened before the copper metal layer is formed, and then the first conductive via 103 is formed during the process of forming the copper metal layer.

[0040] like Figure 2 As shown, a first insulating layer 201 and a first metal layer are stacked on both the upper and lower surfaces of the first core board. The two first metal layers are patterned to form a first conductive line layer 202. A plurality of conductive pads 203 are formed on the first insulating layer 201 on the lower surface of the first core board. The plurality of conductive pads 203 are correspondingly arranged with the first conductive block 102.

[0041] In a specific embodiment, silicon oxide, silicon nitride, or silicon oxynitride is deposited as a first insulating layer 201 using a PECVD process. Then, a layer of metallic copper is deposited on the first insulating layer 201 using electroplating, evaporation, or magnetron sputtering. The metallic copper layer is then patterned to form a first conductive circuit layer 202. A plurality of conductive pads 203 are formed on the first insulating layer 201 on the lower surface of the first core board, and the first conductive circuit layer 202 and the conductive pads 203 are electrically connected (not shown). In other embodiments, prepreg and copper foil are laminated on the upper and lower surfaces of the first core board, and then patterned to form the first insulating layer 201, the first conductive circuit layer 202, and the conductive pads 203.

[0042] In a specific embodiment, before the first metal layer is disposed on the upper and lower surfaces of the first core board, a through hole is formed in the first insulating layer 201. Then, during the formation of the first metal layer, a second conductive through hole 204 is formed in the first insulating layer, thereby making the conductive line layer 101 on the upper and lower surfaces of the core board body 100 electrically connected to the corresponding first conductive line layer 202.

[0043] In a specific embodiment, a pad protection layer (not shown) is then formed covering the conductive pad 203. Specifically, a dense aluminum oxide layer is formed on the surface of the conductive pad 203 using a mask as the pad protection layer.

[0044] like Figure 3 As shown, a second insulating layer 301 and a second metal layer are then stacked on the two first conductive line layers 202 respectively. The two second metal layers are patterned to form a second conductive line layer 302 and a first shielding layer 303. The first shielding layer 303 is located below the conductive pad 203.

[0045] In a specific embodiment, silicon oxide, silicon nitride, or silicon oxynitride is deposited as a second insulating layer 301 using a PECVD process. Then, a copper layer is deposited on the second insulating layer 301 using electroplating, evaporation, or magnetron sputtering. The copper layer is then patterned to form a second conductive line layer 302 and a first shielding layer 303. The second conductive line layer is located above the first core board, while the first shielding layer 303 is located below the conductive pads 203.

[0046] In a specific embodiment, a third conductive via 304 is formed in the second insulating layer 301, and the third conductive via 304 electrically connects the second conductive line layer 302 and the first conductive line layer 202.

[0047] In a specific embodiment, a plurality of conductive structures 400 are then formed, all of which are electrically connected to the first shielding layer 303 and the first conductive block 102. A passivation protective layer 401 is then formed on the first shielding layer 303 to form an initial packaging substrate.

[0048] In a specific embodiment, the first shielding layer 303, the second insulating layer 301 and the first insulating layer 201 are etched to form a plurality of through holes exposing the first conductive block 102, and then conductive material, specifically copper, is deposited in the through holes to form a plurality of conductive structures 400. Then, a dense aluminum oxide layer is deposited to form a passivation protective layer 401.

[0049] like Figure 4 As shown, the initial packaging substrate is subjected to an opening process to form a first groove 500, which exposes the conductive pad 203. During the formation of the first groove 500, a portion of the first conductive block 102 is removed.

[0050] In a specific embodiment, the first groove 500 is formed by a wet etching process or a dry etching process. More specifically, the first groove 500 is formed by a step-by-step etching process. The core board body 100, the second insulating layer 301, and the first insulating layer 201 above the first conductive block 102 are removed by a laser ablation process. Then, the middle area of ​​the first conductive block 102 is removed by a wet etching process, so that the first conductive block 102 becomes a ring structure. Then, the first insulating layer 201 is removed by a hook ablation process to expose the conductive pad 203.

[0051] like Figure 5As shown, a first semiconductor die 501 is disposed in the first groove 500, the first semiconductor die 501 is electrically connected to the conductive pad 203, and a first encapsulation layer 502 is formed in the first groove 500 to cover the first semiconductor die 501.

[0052] In a specific embodiment, the first encapsulation layer 502 is also formed by transfer molding or slot coating. The first encapsulation layer 502 can be an epoxy resin layer, and during the formation of the first encapsulation layer 502, the epoxy resin material fills the gap between the first semiconductor die 501 and the first groove 500.

[0053] like Figure 6 As shown, a second groove 600 is then formed, and a plurality of through holes exposing the first conductive block 102 are formed at the bottom of the second groove 600. Next, a second shielding layer 601 is formed at the bottom of the second groove 600, so that the second shielding layer 601, the first conductive block 102, and the first shielding layer 303 are electrically connected.

[0054] In a specific embodiment, the second groove 600 is formed by a dry etching process or a wet etching process, and a plurality of through holes exposing the first conductive block 102 are formed at the bottom of the second groove 600 by a laser ablation process. Then, copper metal is deposited by an electroplating or chemical plating process to serve as the second shielding layer 601, and a portion of the second shielding layer 601 fills the through holes to electrically connect the first conductive block 102.

[0055] like Figure 7 As shown, a second encapsulation layer 701 is then formed to fill the second groove 600. A third semiconductor die 702 is disposed on the second encapsulation layer 701. A fourth encapsulation layer 703 is formed on the third semiconductor die 702, such that the upper surface of the fourth encapsulation layer 703 is flush with the upper surface of the upper second insulating layer 301. A third conductive line layer 704 is formed on the upper surface of the fourth encapsulation layer 703 and the upper surface of the upper second insulating layer 301, such that the third conductive line layer 704 is electrically connected to the third semiconductor die 702.

[0056] In a specific embodiment, the second encapsulation layer 701 is also formed by transfer molding or slot coating. The second encapsulation layer 701 can be an epoxy resin layer. During the process of setting the third semiconductor die 702 on the second encapsulation layer 701, the conductive terminals of the third semiconductor die 702 are positioned away from the second encapsulation layer 701.

[0057] In a specific embodiment, the fourth encapsulation layer 703 is also formed by transfer molding or slot coating. The fourth encapsulation layer 703 can be an epoxy resin layer. During the formation of the fourth encapsulation layer 703, the epoxy resin material fills the gap between the third semiconductor die 702 and the second groove 600, thereby making the upper surface of the fourth encapsulation layer 703 flush with the upper surface of the upper second insulating layer 301.

[0058] In a specific embodiment, a copper layer is deposited by electroplating or chemical plating, and the copper layer is patterned to form the third conductive line layer 704, so that the third conductive line layer 704 is electrically connected to the third semiconductor die 702.

[0059] like Figure 8 As shown, a second semiconductor die 801 is then formed on the second conductive line layer 302, and a fourth semiconductor die 802 is formed on the third conductive line layer 704. Then, a third encapsulation layer 803 is formed, which encapsulates the second semiconductor die 801 and the fourth semiconductor die 802.

[0060] In a specific embodiment, a second semiconductor die 801 is formed on the second conductive line layer 302, such that the second semiconductor die 801 is electrically connected to the second conductive line layer 302. At the same time, a fourth semiconductor die 802 is formed on the third conductive line layer 704, such that the fourth semiconductor die 802 is electrically connected to the third semiconductor die 702 through the third conductive line layer 704.

[0061] In a specific embodiment, the third encapsulation layer 803 is also formed by transfer molding or slot coating. The fourth encapsulation layer 803 can be an epoxy resin layer. The third encapsulation layer 803 encapsulates the second semiconductor die 801 and the fourth semiconductor die 802.

[0062] like Figure 8 As shown, the present invention also proposes a package for a semiconductor die, wherein the package for the semiconductor die is manufactured using the above-described manufacturing method.

[0063] In other embodiments, the present invention also provides a method for manufacturing a package of a semiconductor die, comprising the following steps:

[0064] A first core board is provided, the first core board including a core board body and conductive circuit layers covering the upper and lower surfaces of the core board body, and a first conductive block covering the middle region of the lower surface of the core board body.

[0065] A first insulating layer and a first metal layer are stacked on both the upper and lower surfaces of the first core board. The two first metal layers are patterned to form first conductive circuit layers. Multiple conductive pads are formed on the first insulating layer on the lower surface of the first core board, and the multiple conductive pads are correspondingly arranged with the first conductive block.

[0066] Next, a second insulating layer and a second metal layer are stacked on the two first conductive line layers respectively. The two second metal layers are patterned to form a second conductive line layer and a first shielding layer. The first shielding layer is located below the conductive pad.

[0067] Next, multiple conductive structures are formed, each of which is electrically connected to the first shielding layer and the first conductive block to form an initial packaging substrate.

[0068] The initial packaging substrate is perforated to form a first groove that exposes the conductive pads, and a portion of the first conductive block is removed during the formation of the first groove.

[0069] A first semiconductor die is disposed in the first groove, the first semiconductor die is electrically connected to the conductive pad, and a first encapsulation layer is formed in the first groove to cover the first semiconductor die.

[0070] Next, a second groove is formed, and multiple through holes are formed at the bottom of the second groove to expose the first conductive block.

[0071] Next, a second shielding layer is formed at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected.

[0072] Next, a second encapsulation layer is formed to fill the second groove.

[0073] According to a preferred embodiment of the present invention, a first conductive via is formed in the core board body, and the first conductive via is electrically connected to the conductive circuit layers on the upper and lower surfaces of the core board body.

[0074] According to a preferred embodiment of the present invention, before the first metal layer is disposed on the upper and lower surfaces of the first core board, a through hole is formed in the first insulating layer, and then a second conductive through hole is formed in the first insulating layer during the formation of the first metal layer.

[0075] According to a preferred embodiment of the present invention, a pad protection layer covering the conductive pads is formed before the second insulating layer and the second metal layer are respectively stacked on the two first conductive lines.

[0076] According to a preferred embodiment of the present invention, a second semiconductor die is further formed on the second conductive line layer, and then a third encapsulation layer is formed, wherein the third encapsulation layer encapsulates the second semiconductor die.

[0077] According to a preferred embodiment of the present invention, a third semiconductor die is disposed on the second packaging layer, and a fourth packaging layer is formed on the third semiconductor die, such that the upper surface of the fourth packaging layer is flush with the upper surface of the second insulating layer above.

[0078] According to a preferred embodiment of the present invention, a third conductive line layer is formed on the upper surface of the fourth encapsulation layer and on the upper surface of the second insulating layer above, such that the third conductive line layer is electrically connected to the third semiconductor die.

[0079] According to a preferred embodiment of the present invention, when a second semiconductor die is formed on the second conductive line layer, a fourth semiconductor die is formed on the third conductive line layer.

[0080] According to a preferred embodiment of the present invention, a passivation protective layer is formed on the first shielding layer.

[0081] According to a preferred embodiment of the present invention, the present invention also provides a package for a semiconductor die, the package for the semiconductor die being manufactured using the above-described manufacturing method.

[0082] In the manufacturing method of the semiconductor die package of the present invention, during the preparation of the initial package substrate, a second insulating layer and a second metal layer are respectively stacked on the two first conductive line layers, and the lower second metal layer is patterned to form a first shielding layer. The first shielding layer is located below the conductive pad, and then a second shielding layer is formed at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected, so that the first shielding layer and the second shielding layer effectively surround the first semiconductor die, thereby effectively preventing the first semiconductor die from electromagnetic interference. In addition, by integrating the first, second, third and fourth semiconductor dies on the package substrate during the formation of the package substrate, the packaging process is simplified and the miniaturization trend of packaging is realized.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a package of a semiconductor die, characterized in that: Includes the following steps: A first core board is provided, the first core board including a core board body and conductive circuit layers covering the upper and lower surfaces of the core board body, and a first conductive block covering the middle region of the lower surface of the core board body; A first insulating layer and a first metal layer are stacked on both the upper and lower surfaces of the first core board. The two first metal layers are patterned to form first conductive circuit layers. Multiple conductive pads are formed on the first insulating layer on the lower surface of the first core board, and the multiple conductive pads are correspondingly arranged with the first conductive block. Next, a second insulating layer and a second metal layer are stacked on the two first conductive line layers respectively. The two second metal layers are patterned to form a second conductive line layer and a first shielding layer. The first shielding layer is located below the conductive pad. Next, multiple conductive structures are formed, and each of the multiple conductive structures is electrically connected to the first shielding layer and the first conductive block to form an initial packaging substrate; The initial packaging substrate is perforated to form a first groove, the first groove exposing the conductive pads, and a portion of the first conductive block is removed during the formation of the first groove; A first semiconductor die is disposed in the first groove, the first semiconductor die is electrically connected to the conductive pad, and a first encapsulation layer is formed in the first groove to cover the first semiconductor die; Next, a second groove is formed, and multiple through holes are formed at the bottom of the second groove to expose the first conductive block; Next, a second shielding layer is formed at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected. Next, a second encapsulation layer is formed to fill the second groove.

2. The method for manufacturing a package of a semiconductor die according to claim 1, characterized in that: A first conductive via is formed in the core board body, and the first conductive via is electrically connected to the conductive circuit layers on the upper and lower surfaces of the core board body.

3. The method for manufacturing a package of a semiconductor die according to claim 1, characterized in that: Before the first metal layer is formed on the upper and lower surfaces of the first core board, a through hole is formed in the first insulating layer, and then a second conductive through hole is formed in the first insulating layer during the formation of the first metal layer.

4. The method for manufacturing a package of a semiconductor die according to claim 1, characterized in that: Before the second insulating layer and the second metal layer are respectively stacked on the two first conductive lines, a pad protection layer covering the conductive pads is formed.

5. The method for manufacturing a package of a semiconductor die according to claim 1, characterized in that: Furthermore, a second semiconductor die is formed on the second conductive line layer; then a third encapsulation layer is formed, which encapsulates the second semiconductor die.

6. The method for manufacturing a package of a semiconductor die according to claim 5, characterized in that: A third semiconductor die is disposed on the second packaging layer, and a fourth packaging layer is formed on the third semiconductor die, such that the upper surface of the fourth packaging layer is flush with the upper surface of the second insulating layer above.

7. The method for manufacturing a package of a semiconductor die according to claim 6, characterized in that: A third conductive line layer is formed on the upper surface of the fourth encapsulation layer and on the upper surface of the second insulating layer above, such that the third conductive line layer is electrically connected to the third semiconductor die.

8. The method for manufacturing a package of a semiconductor die according to claim 7, characterized in that: When a second semiconductor die is formed on the second conductive line layer, a fourth semiconductor die is formed on the third conductive line layer.

9. The method for manufacturing a package of a semiconductor die according to claim 1, characterized in that: A passivation protective layer is formed on the first shielding layer.

10. A package for a semiconductor die, characterized in that: The package of the semiconductor die is manufactured using the manufacturing method of any one of claims 1-9.

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