Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate, the substrate comprises a display area, a first non-display area located on one side of the display area and used for being bound with the driving circuit, a second non-display area located in the display area and away from the first non-display area, and a third non-display area connected with the first non-display area and the second non-display area. The common electrode bus at least partially surrounds the display area; the feedback line extends from the first non-display area to the second non-display area through the third non-display area, and the feedback line is electrically connected with the common electrode bus in the second non-display area.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high image quality, no radiation and portability, and has been rapidly developed in recent years. It has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupies a dominant position in the current flat panel display market. Currently, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal televisions, high-definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigation instruments, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, instruments, public displays and virtual reality displays, etc.

[0003] SUMMARY

[0004] The array substrate, the display panel and the display device provided by the present disclosure have the following specific solutions:

[0005] In one aspect, the present disclosure provides an array substrate, comprising:

[0006] a substrate, comprising a display area, a first non-display area located on one side of the display area and used for binding with a driving circuit, a second non-display area located away from the first non-display area, and a third non-display area connecting the first non-display area and the second non-display area;

[0007] a common electrode bus, at least partially surrounding the display area;

[0008] a feedback line, extending from the first non-display area to the second non-display area through the third non-display area, and electrically connected with the common electrode bus in the second non-display area.

[0009] In some embodiments, in the above array substrate provided by the present disclosure, the feedback line is electrically connected with the common electrode bus in the middle area of the second non-display area.

[0010] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a short-circuit ring located in the second non-display area, and the feedback line is electrically connected with the common electrode bus across the short-circuit ring.

[0011] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a short-circuit ring located in the second non-display area, and the short-circuit ring comprises a break; and the feedback line is electrically connected with the common electrode bus through the break.

[0012] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of electrostatic discharge structures electrically connected with the short-circuit ring, and the feedback line is electrically connected with the electrostatic discharge structures.

[0013] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of electrostatic discharge structures electrically connected with the short-circuit ring, and the feedback line is electrically connected with the electrostatic discharge structures.

[0014] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line electrically connected with the common electrode bus in the first non-display area.

[0015] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line electrically connected with the common electrode bus in the first non-display area.

[0016] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line electrically connected with the common electrode bus in the first non-display area.

[0017] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line electrically connected with the common electrode bus in the first non-display area.

[0018] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line electrically connected with the common electrode bus in the first non-display area.

[0019] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line electrically connected with the common electrode bus in the first non-display area.

[0020] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line electrically connected with the common electrode bus in the first non-display area.

[0021] The two feedback lines are symmetric about a central axis along which the display region extends in a first direction, and an even number of the first common electrode lines are symmetric about a central axis along which the display region extends in the first direction, the first direction being the arrangement direction of the first non-display region and the second non-display region.

[0022] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first common electrode lines are multiple, and at least part of the first common electrode lines share one operational amplifier.

[0023] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a dummy line is further included, the dummy line being symmetric about a central axis along which the display region extends in a first direction with at least part of the feedback lines, the first direction being the arrangement direction of the first non-display region and the second non-display region.

[0024] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the third non-display region includes a gate driving circuit region.

[0025] The array substrate further includes a shielding line and a clock signal line arranged in the gate driving circuit region, the shielding line extending between the clock signal line and the feedback line to between the gate driving circuit region and the common electrode bus.

[0026] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the impedance of the feedback line is smaller than the impedance of the shielding line; and in the second non-display region, the line width of the feedback line is greater than the line width of the shielding line.

[0027] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of second common electrode lines and a plurality of data lines are further included in the display region, each two adjacent data lines being a group, and the second common electrode line being arranged between each group of data lines.

[0028] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a plurality of pixel electrodes arranged in an array in the display region are further included.

[0029] The data lines are arranged at part of the column gaps of the pixel electrodes, and the second common electrode line is arranged at the column gap between each group of data lines.

[0030] The column gap width of the column gap where the data line and the second common electrode line are arranged is greater than the column gap width of the pixel electrode between the two data lines in the group.

[0031] In another aspect, the display panel provided by the embodiments of the present disclosure includes an array substrate and an opposite substrate, wherein the array substrate is the array substrate provided by the embodiments of the present disclosure.

[0032] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the opposite substrate includes a black matrix, and the black matrix includes a first black matrix strip and a second black matrix strip; wherein,

[0033] The first black matrix strip covers the data line and the second common electrode line, and the first black matrix strip is located in the column gap of the data line and the second common electrode line.

[0034] The second black matrix strip is located in the column gap of the pixel electrode between the two data lines in the group, and the width of the first black matrix strip is greater than the width of the second black matrix strip.

[0035] In another aspect, the display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure, and a backlight module located on the light side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0036] FIG. 1 is a structural schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0037] FIG. 2 is a schematic diagram in which the feedback line fb in FIG. 1 is coupled with the clock signal line CLK;

[0038] FIG. 3 is another schematic diagram in which the feedback line fb in FIG. 1 is coupled with the clock signal line CLK;

[0039] FIG. 4 is a mechanism of generating a coarse line in an 8CLK architecture;

[0040] FIG. 5 is a CT1 crosstalk diagram;

[0041] FIG. 6 is a schematic diagram of pixel & polarity arrangement of a product corresponding to FIG. 5;

[0042] FIG. 7 is a schematic diagram of coupling state of a common voltage signal in FIG. 6;

[0043] FIG. 8 is a CT2 crosstalk diagram;

[0044] FIG. 9 is another structural schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0045] FIG. 10 is another structural schematic diagram of an array substrate provided by the embodiments of the present disclosure;

[0046] FIG. 11 is an enlarged structural schematic diagram of a Z region in FIG. 10;

[0047] FIG. 12 is another enlarged structural schematic diagram of the Z region in FIG. 10;

[0048] Fig. 13 is another schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0049] Fig. 14 is another schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0050] Fig. 15 is another schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0051] Fig. 16 is another schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0052] Fig. 17a is a schematic diagram of a structure of 2*12 sub-pixels in an array substrate according to an embodiment of the present disclosure;

[0053] Fig. 17b is a schematic diagram of a structure of a gate metal layer in Fig. 17a;

[0054] Fig. 17c is a schematic diagram of a structure of a source-drain metal layer in Fig. 17a;

[0055] Fig. 17d is a schematic diagram of a structure of an active layer in Fig. 17a;

[0056] Fig. 17e is a schematic diagram of a structure of a layer in which a pixel electrode is located in Fig. 17a;

[0057] Fig. 17f is a schematic diagram of a structure of a layer in which a common electrode is located in Fig. 17a;

[0058] Fig. 18 is an enlarged schematic diagram of a column gap of a pixel electrode in which a second common electrode line is located;

[0059] Fig. 19 is an enlarged schematic diagram of a column gap of a pixel electrode between two data lines in a group;

[0060] Fig. 20 is a schematic diagram of a structure of a display panel according to an embodiment of the present disclosure;

[0061] Fig. 21 is a schematic diagram of a structure of a first black matrix strip according to an embodiment of the present disclosure;

[0062] Fig. 22 is a schematic diagram of a structure of a second black matrix strip according to an embodiment of the present disclosure;

[0063] Fig. 23 is a schematic diagram of a structure of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be described with reference to the drawings of the embodiments of the present disclosure. In the drawings, the thicknesses of layers, films, panels, regions and the like are exaggerated for clarity. In the present disclosure, example embodiments are described with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described in the present disclosure are not to be construed as being limited to the particular shapes of regions as illustrated but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features; an illustrated sharp angle can be rounded, etc. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not reflective of the true scale or proportions of a region. Like numbers refer to like or similar elements throughout.

[0065] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as is commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are used to distinguish one element from another, and the terms "comprises", "comprising", "includes", "including" and the like can be used herein and mean including but not limited to as set out herein. The terms "connected", "coupled", and the like, can be used herein and mean one or more elements or components connected or coupled at least indirectly together, whether connected or coupled directly together or connected or coupled indirectly together, via one or more interposed elements or components. The terms "inner", "outer", "upper", "lower", and the like, can be used herein and mean relative positions for the purposes of illustration only, and can be reversed when the positions of the described objects are changed.

[0066] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, or be directly connected to the other element or layer, or intervening elements or layers can be present. When an element or layer is referred to as being "on one side of" another element or layer, it can be directly on the side of the other element or layer, or be directly connected to the other element or layer, or intervening elements or layers can be present. When an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. The term "and / or" includes any and all combinations of one or more of the associated listed items. The various embodiments of the present disclosure can be combined with each other, without conflict, if not incompatible.

[0067] Current display products are developing towards low cost, so the development of Dual Gate products is constantly improving. The current Dual Gate product design generally has a horizontal crosstalk (H-Crosstalk, H-CT) problem, which seriously affects the image quality of the Dual Gate product. The inventors have studied the mechanism of horizontal crosstalk, as follows:

[0068] FIG. 1 is a schematic diagram of a structure of an array substrate provided by an embodiment of the present disclosure, FIG. 2 is a schematic diagram of a feedback line (fb) being coupled by a clock signal line (CLK) in FIG. 1, FIG. 3 is another schematic diagram of the feedback line (fb) being coupled by the clock signal line (CLK) in FIG. 1, and FIG. 4 is a mechanism of generating coarse lines in an 8CLK architecture. As can be seen from FIGS. 1 to 4, since the feedback line fb is close to the gate driving circuit area GOA (which can include the clock signal line), the feedback line fb is easily coupled by the clock signal line (CLK). The coupling of the feedback line (fb) causes the pixels connected by the G1, G2, G3, and G4 gate lines to be dark, and the pixels connected by the G5, G6, G7, and G8 gate lines to be bright. Therefore, in the four rows, the first and second rows of pixels controlled by the G1, G2, G3, and G4 gate lines display dark lines, and the third and fourth rows of pixels controlled by the G5, G6, G7, and G8 gate lines display bright lines, which macroscopically appears as coarse line crosstalk.

[0069] FIG. 5 is another horizontal crosstalk CT1 diagram, FIG. 6 is a schematic diagram of pixel & polarity arrangement corresponding to FIG. 5, and FIG. 7 is a schematic diagram of coupling state of a common voltage signal in FIG. 6. As shown in FIGS. 5 to 7, the mechanism of this horizontal crosstalk is as follows: from the perspective of the circuit, the same color pixel positive and negative polarities are unbalanced, the same row of green pixels has a positive polarity + that continuously accumulates without negative polarity - to offset, and the common electrode line (VCOM) is coupled by the data line (Data line) connected by the green pixels to cause crosstalk; from the perspective of the panel (Panel), the Panel has poor recovery ability; and from the perspective of the Dual Gate architecture, the Dual Gate product is a vertical compensation architecture, and the 1H time is short, so the coupled VCOM cannot be completely recovered within the 1H time.

[0070] FIG. 8 is another horizontal crosstalk CT2 diagram, and the related product requires that the Excel table has no crosstalk in the static, dragging, zooming in, and zooming out states; the principle of the static state and the zooming in state is the same as that of the CT1 crosstalk shown in FIG. 5, when the Excel table is in the zooming out state, only part of the compensation points can compensate the common voltage, resulting in that the crosstalk degree in the central region is heavy and the crosstalk degree in the edge region is light, so the crosstalk phenomenon outside the Excel small window is serious, and the crosstalk phenomenon of the large window is relatively light.

[0071] To at least improve the above technical problems, the array substrate provided by the embodiments of the present disclosure can include:

[0072] The substrate 101 includes a display area AA, a first non-display area DP located on one side of the display area AA and used for binding with a driving circuit, a second non-display area DPO located away from the first non-display area DP of the display area AA, and a third non-display area GL&GR connecting the first non-display area DP and the second non-display area DPO. In some embodiments, a flexible circuit board FPC can be arranged in the first non-display area DP in a chip on film (COF) manner, or a data chip Source IC and other driving circuits can be arranged in the first non-display area DP in a chip on glass (COG) manner. The flexible circuit board FPC or the data chip Source IC and other driving circuits can provide data signals for data lines (Data line) through fan-out lines (FL).

[0073] A common electrode bus line 102 is arranged at least partially around the display area AA, and the common electrode bus line 102 is arranged around the display area AA in an optional manner. The common electrode bus line 102 provides a common voltage signal for the common electrode of the display area AA.

[0074] The feedback line 103 extends from the first non-display area DP to the second non-display area DPO through the third non-display area GL and / or GR, and the feedback line 103 is electrically connected to the common electrode bus line 102 in the second non-display area DPO. Compared with the third non-display area GL&GR, the second non-display area DPO has less wiring, and therefore the path wiring of the feedback line 103 can be increased in width. The increased impedance is smaller than that of the feedback line (FB) shown in FIG. 1, so that the common voltage waveform in the screen can be more truly fed back.

[0075] In some embodiments, Table 1 shows the display effects when the six points FB, V1-V5 on the common electrode bus (BL) in FIG. 1 are respectively taken as feedback points, wherein FB is located at 1 / 12-1 / 4 (e.g. 1 / 6) of the common electrode bus 102 close to the second non-display area DPO, V1 is located at the corner of the common electrode bus 102 on the side of the second non-display area DPO, V2 is located at 2 / 5-3 / 5 (e.g. 1 / 2) of the common electrode bus 102 away from the second non-display area DPO, V3 is located at the corner of the common electrode bus 102 on the side of the first non-display area DP, V4 is located between the adjacent COFs of the common electrode bus 102 close to the side of the third non-display area GL&GR, and V5 is located at 1 / 4-1 / 2 (e.g. 1 / 3) of the common electrode bus 102 close to the side of the third non-display area GL&GR.

[0076] As can be seen from Table 1, when the connection point FB of the feedback line (fb) and the common electrode bus (BL) shown in FIG. 1 is taken as a feedback point, thick lines and poor CT1 crosstalk occur, when V1, V2 and V5 are taken as feedback points, not only thick lines do not occur, but also CT1 crosstalk is reduced by about 3 levels, and CT1 crosstalk is significantly reduced. Therefore, V1, V2 and V5 can be taken as feedback points to replace the feedback line (fb).

[0077] Table 1

[0078] In addition, since the second non-display area DPO where V1 and V5 are located has fewer wirings, the peripheral trace (which can be taken as the feedback line 103 of the present disclosure) connected to V1 and V5 can have an increased width in the second non-display area DPO, so as to ensure that the impedance of the feedback line 103 of the present disclosure is small, and thus the common voltage waveform can be more truly fed back. Based on this, the present disclosure provides that the feedback line 103 is electrically connected to the common electrode bus 102 in the second non-display area DPO. Specifically, FIG. 9 of the present disclosure takes an example in which the feedback line 103 is electrically connected to the common electrode bus 102 at the end region (e.g. the V1 point of the end region) of the second non-display area DPO, and FIG. 10 takes an example in which the feedback line 103 is electrically connected to the common electrode bus 102 at the middle region (e.g. the V5 point of the middle region) of the second non-display area DPO.

[0079] In some embodiments, FIG. 11 is a schematic diagram of an enlarged structure of the Z region in FIG. 10, and FIG. 12 is another schematic diagram of an enlarged structure of the Z region in FIG. 10. As shown in FIG. 11 and FIG. 12, the array substrate provided by the embodiments of the present disclosure can further include a short ring 104 located in the second non-display area DPO. Optionally, in FIG. 11, the feedback line 103 is electrically connected to the common electrode bus 102 by crossing the short ring 104; in FIG. 12, the short ring 104 includes a break F, and the feedback line 103 is electrically connected to the common electrode bus 102 by passing through the break F. In some embodiments, the feedback line 103 is located in the gate metal layer, and the short ring 104 with the break F is located in the gate metal layer; the short ring 104 crossed by the feedback line 103 can include a connection part ITO of the same layer and the same material as the common electrode or the pixel electrode, and a wiring part GM located in the gate metal layer, and the connection part ITO can be connected to the wiring part GM by punching, and the feedback line 103 crosses the connection part ITO to avoid short circuit between the feedback line 103 and the short ring 104.

[0080] Continuing to refer to FIG. 12, the array substrate provided by the embodiments of the present disclosure can further include a plurality of electrostatic discharge structures 105 electrically connected to the short ring 104, and the electrostatic discharge structure 105 can be electrically connected to the data line (Data line) one by one through the fan-out line FL, and the feedback line 103 can be electrically connected to the electrostatic discharge structure 105 close to the break F. Since the feedback line 103 of the present disclosure is electrically connected to the common electrode bus 102, the electrostatic discharge structure 105 of the present disclosure can be connected to the common electrode bus 102 through the feedback line 103 for electrostatic discharge, thereby increasing the electrostatic discharge path and improving the anti-static effect.

[0081] In some embodiments, the common electrode bus 102 can adopt double-layer wiring, one layer of which is located in the gate metal layer, and the other layer of which is located in the layer where the common electrode or the pixel electrode is located. Optionally, in order to reduce the coupling of the fan-out line FL to the common electrode bus 102, the present disclosure can be provided with the common electrode bus 102 including a plurality of first hollow structures OW1 which overlap with the fan-out line FL, as shown in FIG. 11 and FIG. 12. In addition, in order to enhance the curing effect of the sealant, the wider feedback line 103 can also be provided with a plurality of second hollow structures OW2, as shown in FIG. 11.

[0082] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 9 and 10, a first common electrode line 106 can also be included, which is electrically connected with the common electrode bus 102 in the first non-display area DP. Optionally, the first common electrode line 106 includes a first sub-common electrode line 1061, which is electrically connected with the common electrode bus 102 in the middle area (for example, the V4 point in the middle area) of the first non-display area DP. In some embodiments, the first common electrode line 106 can also include a second sub-common electrode line 1062, which is electrically connected with the common electrode bus 102 in the end area (for example, the V3 point in the end area) close to the first non-display area DP. The first sub-common electrode line 1061 and the second sub-common electrode line 1062 can serve as compensation lines to compensate the common voltage signal, so as to improve the uniformity of the common voltage signal.

[0083] In some embodiments, the present disclosure can mark V4 as point A, V3 as point B, V2 as point C, FB as point D, V1 as point E, V5 as point F, and set the center point of the panel as point O, and then take the sum of the impedance between two points, to obtain the values shown in Table 2. As can be seen from FIG. 1 and Table 2, due to the characteristics of the Dual Gate vertical structure, the horizontal impedance 3MΩ through point C to point O, while the vertical impedance through point F or point A to point O is much smaller than the horizontal direction, only 1KΩ, so theoretically, it can be concluded that: (1) V1 effect: negative effect, the impedance of V1→V5 is only 9Ω, and V1 compensation will offset the waveform feedback when V5 feeds back; (2) V2 effect: no effect, the Dual Gate product is a vertical VCOM structure, and the horizontal connection line is ITO (MΩ level), so the horizontal compensation effect is weak; (3) V3&V4 effect: positive effect, the single-pixel vertical connection line is Cu (Ω level), so the vertical compensation point has the best compensation effect. Therefore, the second sub-common electrode line 1062 and the first sub-common electrode line 1061 connected with V3 and V4 can be used as compensation lines for compensation.

[0084] Table 2

[0085] Table 3

[0086] Table 4

[0087] The disclosure also adopts the control variable method to verify the compensation effect of single variable and combined variable. The single variable compensation effect is shown in Table 3, and the combined variable compensation effect is shown in Table 4. From Table 3, it can be concluded that the compensation combination of V2&V3&V4 is the best, and the compensation of V1 even aggravates H-Crosstalk. From Table 4, it can be concluded that the compensation combination of V3&V4 is the best, which is consistent with the conclusion of single variable and consistent with the theoretical derivation. Therefore, the second sub-common electrode line 1062 connected with V3 and the first sub-common electrode line 1061 connected with V4 can be used as the compensation line together in the disclosure.

[0088] Table 5

[0089] Table 6

[0090] Table 7

[0091] In some embodiments, as shown in FIG. 10 and Table 5, the feedback line 103 is set at the V5 point for feedback in the disclosure, and the peripheral wiring connected with V1 and V2 is not required; as shown in FIG. 9 and Table 6, the feedback line 103 is set at the V1 point in the disclosure, and the peripheral wiring connected with V2 and V5 is not required. Therefore, the number of wirings can be reduced. In some embodiments, Table 7 shows the parameters of the peripheral wiring connected with the FB point and the V1-V5 points in the disclosure. As shown in Table 7, at least 87 μm of wiring space can be saved when the peripheral wiring of V1 and V2 is omitted in the disclosure; at least 75 μm of wiring space can be saved when the peripheral wiring of V2 and V5 is omitted in the disclosure. The saved wiring space can be effectively used in the GOA area, the AA area, the Output compensation line, the GND, the VCOM, etc., to increase the overall performance of the Panel in terms of ESD prevention, charge release, compensation ability, etc.

[0092] In some embodiments, FIG. 13 to FIG. 16 are schematic diagrams of another array substrate provided by embodiments of the present disclosure. As shown in FIG. 9, FIG. 10, FIG. 13 to FIG. 16, in the array substrate provided by embodiments of the present disclosure, the feedback line 103 can also be electrically connected to the first common electrode line 106 through an operational amplifier (OP) 107 of an external circuit board (for example, a printed circuit board (PCB)). Optionally, the first common electrode line 106 is in plural, and different first common electrode lines 106 are electrically connected to different operational amplifiers 107. For example, in FIG. 9 and FIG. 10, the feedback line 103 is in two, the first common electrode line 106 is in even number (for example, including two first sub-common electrode lines 1061 and two second sub-common electrode lines 1062), and the number of the operational amplifiers 107 is the same as the number of the first common electrode lines 106, and each first common electrode line 106 is correspondingly electrically connected to one operational amplifier 107. Optionally, the two feedback lines 103 can be symmetric about the center axis MN along the first direction Y extending through the display area AA, and the even number of first common electrode lines 106 can be symmetric about the center axis MN along the first direction Y extending through the display area AA. The first direction Y is the arrangement direction of the first non-display area DP and the second non-display area DPO. The position of the operational amplifier 107 on the circuit board (for example, the printed circuit board (PCB)) is random or placed according to the position of other structures of the circuit board.

[0093] In some embodiments, as shown in FIG. 15 and FIG. 16, in order to reduce the number of operational amplifiers 107 and save costs, at least part of the first common electrode lines 106 (for example, two first sub-common electrode lines 1061) can share one operational amplifier 107. It should be noted that in FIG. 15 and FIG. 16, when two first sub-common electrode lines 1061 share one operational amplifier 107, the feedback line 103 can be only one, and the array substrate can also include a dummy line 103', which is symmetric about the center axis MN along the first direction Y extending through the display area AA with at least part of the feedback line 103. That is, one of the feedback lines 103 in FIG. 9, FIG. 10, FIG. 13 and FIG. 14 can be used as the dummy line 103', so that the mask of the layer where the feedback line 103 is located can be used. In some embodiments, in order to save wiring space, the present disclosure can also not set the dummy line 103', and the present disclosure is not limited in this regard.

[0094] In some embodiments, as can be seen from Table 2 and Table 7, the V3 corresponds to a Bus line impedance of 37Ω, and the output driving capability of the power management chip PMIC can effectively drive V3, so that, as shown in FIGS. 13-16, the second sub-common electrode line 1062 of the present disclosure can be externally connected to the power management chip PMIC, so that the power management chip PMIC supplies power to the Bus line (i.e., the common voltage bus 102) through the second sub-common electrode line 1062 and the V3 point in turn, which can also avoid setting the operational amplifier 107 electrically connected to the second sub-common electrode line 1062, thereby reducing the cost.

[0095] In some embodiments, Table 8 shows the improvement effect of the array substrate shown in FIG. 13 on H-crosstalk, and Table 9 shows the improvement effect of the array substrate shown in FIG. 14 on H-crosstalk. In Table 8 and Table 9, Vcom represents the voltage provided by the power management chip PMIC, and Vcom is 4V-6V. As can be seen from Table 8 and Table 9, the array substrate shown in FIGS. 13 and 14 effectively improves or even eliminates CT1 crosstalk, CT2 crosstalk, and coarse lines.

[0096] Table 8

[0097] Table 9

[0098] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 9, 10, 13-16, a shielding line 108 can also be included, which extends between the gate drive circuit region GOA and the feedback line 103 to between the gate drive circuit region GOA and the common electrode bus 102. Optionally, the impedance of the feedback line 103 is less than the impedance of the shielding line 108, the line width of the feedback line 103 in the second non-display area DPO is greater than the line width of the shielding line 108 (for example, the line width of the feedback line 103 in the second non-display area DPO is more than 5 times the line width of the shielding line 108), and the line width of the feedback line 103 in the third non-display area GL&GR can be greater than, less than, or equal to the line width of the shielding line 108. In some embodiments, the gate drive circuit region GOA can be provided with a gate drive circuit and a gate drive circuit signal line electrically connected to the gate drive circuit, which includes but is not limited to a frame start signal line, a total reset signal line, a clock signal line, a low-level signal line, etc. Optionally, the feedback line (fb) of FIG. 1 can be used as the shielding line 108, which can be arranged between the clock signal line CLK and the feedback line 103, and the shielding line 108 is not electrically connected to the common electrode bus (BL), so as to prevent the clock signal line CLK from coupling to the feedback line 103 through the shielding line 103.

[0099] In some embodiments, FIG. 17a is a structural schematic diagram of 2*12 sub-pixels in an array substrate provided by embodiments of the present disclosure, FIG. 17b to FIG. 17f are structural schematic diagrams of each single film layer in FIG. 17a, FIG. 18 is an enlarged structural schematic diagram of the column gap of the pixel electrode where the second common electrode line is located, and FIG. 19 is an enlarged structural schematic diagram of the column gap of the pixel electrode between two data lines in a group. As shown in FIG. 17a to FIG. 17f, FIG. 18 and FIG. 19, in the above-mentioned array substrate provided by embodiments of the present disclosure, a plurality of second common electrode lines 109, a plurality of data lines 110 and a plurality of pixel electrodes 111 located in the display area AA can also be included, each adjacent two data lines 110 form a group, the second common electrode line 109 is located between each group of data lines 110, optionally, the data line 110 is located at part of the column gap of the pixel electrode 111, the second common electrode line 109 is arranged at the column gap between each group of data lines 110, the column gap width W1 where the data line 110 and the second common electrode line 109 are located is greater than the column gap width W2 of the pixel electrode 111 between two data lines 110 in a group. Compared with the scheme that the data line 110 and the second common electrode line 109 are alternately arranged in the column gap of the pixel electrode 111, the present disclosure can reduce the number of second common electrode lines 109 by half, and the column gap width where the second common electrode line 109 is not arranged is reduced, thereby increasing the transmittance and improving the aperture ratio by 1.5%.

[0100] As can be further known from FIG. 17a to FIG. 17f, in the present disclosure, two gate lines 112 can be arranged at the same row gap of the pixel electrode 111, so that the technical scheme of the present disclosure can be applied to Dual Gate products. Optionally, the array substrate provided by the present disclosure can also include a common electrode 113 electrically connected with the second common electrode line 109, and a transistor 114 electrically connected with the data line 110, the pixel electrode 111 and the gate line 112. In some embodiments, the pixel electrode 111 can be a block electrode, and the common electrode 113 can be a slit electrode; or the pixel electrode 111 is a slit electrode, and the common electrode 113 is a block electrode, which is not limited in the present disclosure. In addition, the gate electrode g of the transistor 114 in the present disclosure can be integrally arranged with the gate line 112, the first electrode s of the transistor 114 is integrally arranged with the data line 110, the second electrode d of the transistor 114 is electrically connected with the pixel electrode 111 through the switching electrode 115 of the layer where the common electrode 113 is located, and the active layer a of the transistor 114 can be polycrystalline silicon, amorphous silicon, indium gallium zinc oxide, etc. The other essential components in the array substrate should be understood by those skilled in the art, which will not be described here and should not be regarded as a limitation on the present disclosure.

[0101] Based on the same inventive concept, the display panel provided by the embodiments of the present disclosure is provided. FIG. 20 is a structural schematic diagram of a display panel provided by the embodiments of the present disclosure. As shown in FIG. 20, the display panel of the present disclosure can include an array substrate 001 and an opposite substrate 002 opposite to each other, wherein the array substrate 001 is the array substrate 001 provided by the embodiments of the present disclosure.

[0102] In some embodiments, the opposite substrate 002 can include a black matrix BM, which is a grid structure. The second common electrode line 109, the data line 110, the transistor 113 and the gate line 112 are located in the region of the black matrix BM. Optionally, FIG. 21 shows a structural schematic diagram of a first black matrix strip BM1 of the black matrix BM, and FIG. 22 shows a structural schematic diagram of a second black matrix strip BM2 of the black matrix BM. The first black matrix strip BM covers the data line 110 and the second common electrode line 109, and is located in the column gap with a width of W1 where the data line 110 and the second common electrode line 109 are located. The second black matrix strip BM2 is located in the column gap with a width of W2 between two data lines 110 in a group. Since the first black matrix strip BM1 needs to cover the data line 110 and the second common electrode line 109, the width of the first black matrix strip BM1 is greater than the width of the second black matrix strip BM2. In addition, color resist CF can be arranged in the grid of the black matrix BM. The color resist includes red color resist, blue color resist, green color resist, etc. In some embodiments, the color resist can also be arranged on the array substrate, which is not limited by the present disclosure.

[0103] In some embodiments, as shown in FIG. 20, the display panel provided by the embodiments of the present disclosure can further include a liquid crystal layer 003 between the array substrate 001 and the opposite substrate 002, a first polarizer 004 located on the side of the array substrate 001 away from the opposite substrate 002, and a second polarizer 005 located on the side of the opposite substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 is perpendicular to the polarization direction of the second polarizer 005. The other indispensable components of the display panel should be understood by those skilled in the art, and are not described here. They should not be regarded as a limitation on the present disclosure.

[0104] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure includes the display panel PNL provided by the embodiments of the present disclosure and a backlight module BLU located on the light-in side of the display panel PNL, as shown in FIG. 23. The backlight module BLU can be a direct backlight module or a side backlight module. Optionally, the side backlight module can include a lamp bar, a reflector sheet, a light guide plate, a diffusion sheet, a prism group and the like, and the lamp bar is located on one side of the light guide plate in the thickness direction. The direct backlight module can include a matrix light source, a reflector sheet, a diffusion plate and a brightness enhancement film and the like which are stacked on the light-out side of the matrix light source, and the reflector sheet includes an opening which is located opposite to the position of each lamp bead in the matrix light source. The lamp bead in the lamp bar and the lamp bead in the matrix light source can be a light emitting device (LED), such as a quantum dot light emitting device.

[0105] In some embodiments, the lamp bead can also be a micro light emitting device (such as Mini LED, Micro LED) and the like. The micro light emitting device in the order of sub-millimeter or even micrometer and the organic light emitting device (OLED) are all self-luminous devices. Like the organic light emitting device, the micro light emitting device has a series of advantages such as high brightness, ultra-low delay, ultra-large viewing angle and the like. In addition, since the inorganic light emitting device emits light based on the metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life and better resistance to high and low temperatures compared with the organic light emitting device which emits light based on organic matter. When the micro light emitting device is used as a backlight source, it can realize more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0106] In some embodiments, the display device provided by the embodiments of the present disclosure can be a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any product or component having a display function. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), or the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate arrays, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate arrays, programmable array logic, programmable logic devices, and the like. In addition, the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or different component arrangements.

[0107] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who understand the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0108] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The application relates to a substrate, which comprises a display area, a first non-display area on one side of the display area and used for binding with a driving circuit, a second non-display area on the display area away from the first non-display area, and a third non-display area connecting the first non-display area and the second non-display area; a common electrode bus arranged at least partially around the display area; a feedback line extending from the first non-display area to the second non-display area through the third non-display area, and the feedback line being electrically connected with the common electrode bus in the second non-display area. The feedback line is electrically connected with the common electrode bus in the middle area of the second non-display area. The feedback line is electrically connected with the common electrode bus in the end area of the second non-display area. The application further comprises a first common electrode line, which is electrically connected with the common electrode bus in the first non-display area.

2. The array substrate of claim 1, wherein, The first common electrode line comprises a first sub-common electrode line, which is electrically connected with the common electrode bus in the middle area of the first non-display area.

3. The array substrate of claim 2, wherein, The first common electrode line comprises a second sub-common electrode line, which is electrically connected with the common electrode bus in the end area of the first non-display area.

4. The array substrate of claim 2, wherein, The second sub-common electrode line circumscribes a power management chip.

5. The array substrate of claim 4, wherein, The feedback line is electrically connected with the first common electrode line through an external operational amplifier.

6. The array substrate of claim 1, wherein, The first common electrode line is a plurality of lines, and different first common electrode lines are electrically connected with different operational amplifiers.

7. The array substrate according to any one of claims 1 to 6, wherein, The feedback line is two lines, and the first common electrode line is an even number of lines.

8. The array substrate of claim 7, wherein, The two feedback lines are symmetric about a central axis extending in a first direction of the display area, and the even number of first common electrode lines are symmetric about the central axis extending in the first direction of the display area, and the first direction is the arrangement direction of the first non-display area and the second non-display area.

9. The array substrate of claim 7 or 8, wherein, The first common electrode line is a plurality of lines, and at least part of the first common electrode lines share one operational amplifier.

10. The array substrate of claim 9, wherein, The application further comprises a dummy line, which is symmetric about a central axis extending in a first direction of the display area with at least part of the feedback line, and the first direction is the arrangement direction of the first non-display area and the second non-display area.

11. The array substrate according to any one of claims 7 to 9, wherein, The third non-display area comprises a gate driving circuit area.

12. The array substrate of claim 11, wherein, The array substrate further comprises a shielding line and a clock signal line arranged in the gate driving circuit area, and the shielding line extends between the clock signal line and the feedback line to between the gate driving circuit area and the common electrode bus.

13. The array substrate of claim 12, wherein, ​ ​ 14. The array substrate of claim 11, wherein, ​ 15. The array substrate of claim 14, wherein, ​ 16. The array substrate of any one of claims 1 to 15, wherein, ​ ​ 17. The array substrate of claim 16, wherein, The feedback line has an impedance less than that of the shielding line, and in the second non-display area, the feedback line has a line width greater than that of the shielding line.

18. The array substrate of any one of claims 1 to 17, wherein, A plurality of second common electrode lines and a plurality of data lines are further included in the display area, each two adjacent data lines form a group, and the second common electrode line is located between each group of data lines.

19. The array substrate of claim 18, wherein, A plurality of pixel electrodes arranged in an array in the display area are further included. The data lines are located at part of the column gaps of the pixel electrodes, and the second common electrode line is located at the column gap between each group of data lines. The column gap width of the data line and the second common electrode line is greater than the column gap width of the pixel electrode between the two data lines in a group.

20. A display panel, wherein, The display panel comprises an array substrate and an opposite substrate, wherein the array substrate is the array substrate as claimed in any one of claims 1-19.

21. The display panel of claim 20, wherein, The opposite substrate comprises a black matrix, and the black matrix comprises a first black matrix strip and a second black matrix strip. The first black matrix strip covers the data line and the second common electrode line, and the first black matrix strip is located in the column gap of the data line and the second common electrode line. The second black matrix strip is located in the column gap of the pixel electrode between the two data lines in a group, and the width of the first black matrix strip is greater than that of the second black matrix strip.

22. A display device comprising: The display panel comprises the display panel as claimed in claim 20 or 21, and a backlight module located on the light entering side of the display panel.

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