Shifting register unit, display driving circuit and display device

Abstract

The invention discloses a shift register unit, a display driving circuit and a display device, and belongs to the technical field of display. The shift register unit comprises an input control circuit (01) and an output control circuit (02), wherein the input control circuit (01) can control connection and disconnection between an input signal end (INn) and an input node (Qn) based on a first clock signal provided by a first clock line (CB) and a second clock signal provided by a second clock line (CKn); the output control circuit (02) can control the potential of the output signal end (OUTn) based on the potential of the input node (Qn), an enable signal provided by the enable line (EN) and a reset control signal provided by the reset line (Trst), so that the output signal end (OUTn) can be reset by flexibly setting the enable signal, the clock signal and the reset control signal. And enabling the shift register unit to output a signal matched with the P-type transistor and / or the N-type transistor in the pixel. The output control circuit (02) and the input control circuit (01) are arranged in the first direction (X1) and in the direction close to the pixels, and signal lines connected with the output control circuit (02) and the input control circuit (01) extend in the second direction (Y1) intersecting with the first direction (X1), so that the narrow frame design of the display device can be facilitated.

Description

Shift register unit, display driver circuit and display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register unit, a display driver circuit, and a display device. Background Technology

[0002] With the development of display technology, gate driver on array (GOA) technology can now be used to integrate display driver circuits such as gate driver circuits and light-emitting driver circuits onto the display panel, facilitating narrow bezel designs. Correspondingly, the display driver circuit is also referred to as a GOA circuit.

[0003] Currently, GOA circuits typically include multiple cascaded shift register units (also called GOA units). Each GOA unit generally includes multiple transistors, which are connected to multiple signal lines and pixels on the display panel, and are used to output the required display drive signals to the pixels based on the signals provided by the multiple signal lines, so as to drive the pixels to emit light.

[0004] However, the current GOA unit has a relatively complex structure and many connected signal lines, which does not make good use of the narrow bezel design of the display panel.

[0005] Summary of the Invention

[0006] A shift register unit, a display driver circuit, and a display device are provided. The technical solution is as follows:

[0007] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0008] An input control circuit is connected to a first clock line, a second clock line, an input signal terminal, and an input node, respectively, and is used to control the connection and disconnection of the input signal terminal and the input node in response to a first clock signal provided by the first clock line and a second clock signal provided by the second clock line.

[0009] An output control circuit is connected to the input node, reset control line, enable line, and output signal terminal respectively, and is used to control the potential of the output signal terminal based on the potential of the input node, the enable signal provided by the enable line, and the reset control signal provided by the reset control line.

[0010] Furthermore, the output control circuit and the input control circuit are arranged along the first direction and in the direction closer to the pixel;

[0011] The reset control line, the first clock line, the second clock line, and the enable line are arranged along the first direction and in a direction close to the pixel, and extend along the second direction; wherein the second direction intersects the first direction.

[0012] Optionally, the output control circuit includes:

[0013] The first output control sub-circuit is connected to the input node, the reset control line and the first intermediate node respectively, and is used to control the potential of the first intermediate node based on the potential of the input node and the reset control signal;

[0014] The second output control sub-circuit is connected to the first intermediate node and the second intermediate node respectively, and is used to control the potential of the second intermediate node based on the potential of the first intermediate node.

[0015] The third output control sub-circuit is connected to the second intermediate node, the enable line and the output signal terminal respectively, and is used to control the potential of the output signal terminal based on the potential of the second intermediate node and the enable signal.

[0016] Furthermore, the first output control sub-circuit and the input control circuit in the output control circuit are arranged along the first direction and in a direction close to the pixel;

[0017] Furthermore, the first output control sub-circuit, the second output control sub-circuit, and the third output control sub-circuit are arranged along the first direction and in a direction close to the pixel; the second output control sub-circuit and the input control circuit are arranged along the second direction.

[0018] Optionally, the shift register unit further includes:

[0019] A latching circuit is connected to the third clock line, the fourth clock line, the second intermediate node, and the input node, respectively, and is used to control the on / off state of the second intermediate node and the input node in response to the third clock signal provided by the third clock line and the fourth clock signal provided by the fourth clock line. The potential of the second intermediate node is opposite to the potential of the first intermediate node.

[0020] A switch control circuit is connected between the enable line and the third output control sub-circuit, and is also connected to the first control terminal and the second control terminal respectively. It is used to control the on / off state of the enable line and the third output control sub-circuit in response to the first control signal provided by the first control terminal and the second control signal provided by the second control terminal.

[0021] A drive enhancement circuit is connected between the third output control sub-circuit and the output signal terminal, and is used to invert the potential of the output signal of the third output control sub-circuit at least once before outputting it to the output signal terminal.

[0022] Furthermore, the latch circuit, the switch control circuit, and the drive enhancement circuit are arranged along the first direction and in a direction close to the pixel; the latch circuit and the input control circuit are arranged along the second direction and located between the input control circuit and the second output control sub-circuit; the switch control circuit and the third output control sub-circuit are arranged along the second direction.

[0023] The third clock line and the fourth clock line are located between the reset control line and the enable line, and are arranged along the first direction and along the direction close to the pixel, and extend along the second direction.

[0024] Optionally, the input control circuit includes: a first transmission gate; the first output control sub-circuit includes: a first NOR gate; the second output control sub-circuit includes: a first NOT gate; the third output control sub-circuit includes: a second NOR gate; the latch circuit includes: a second transmission gate; the switch control circuit includes: a third transmission gate; and the drive enhancement circuit includes: a second NOT gate, a third NOT gate, and a fourth NOT gate connected in series.

[0025] The first transmission gate is connected between the input signal terminal and the input node, and is also connected to the first clock line and the second clock line respectively; the two input terminals of the first NOR gate are connected to the reset control line and the input node respectively, and the output terminal of the first NOR gate is connected to the first intermediate node; the input terminal of the first NOT gate is connected to the first intermediate node, and the output terminal of the first NOT gate is connected to the second intermediate node; of the two input terminals of the second NOR gate, one input terminal is connected to the second intermediate node, and the other input terminal is connected to the enable line through the third transmission gate, and the third transmission gate is also connected to the first control terminal and the second control terminal respectively; the output terminal of the second NOR gate is connected to the output signal terminal through the second NOT gate, the third NOT gate and the fourth NOT gate connected in series; the second transmission gate is connected between the second intermediate node and the input node, and is also connected to the third clock line and the fourth clock line respectively; the shift register unit further includes: a voltage stabilizing capacitor connected between the ground terminal and the other input terminal of the second NOR gate;

[0026] Furthermore, the first NOR gate includes a first group of circuits comprising the first transmission gate, the second transmission gate, and the first NOT gate; a second group of circuits comprising the second NOR gate and the third transmission gate; and a third group of circuits comprising the second NOT gate and the voltage-stabilizing capacitor. The third NOT gate and the fourth NOT gate are arranged along the first direction and in a direction close to the pixel. In the first group of circuits, the first transmission gate, the second transmission gate, and the first NOT gate are arranged along the second direction. In the second group of circuits, the second NOR gate and the third transmission gate are arranged along the second direction, and the third transmission gate is farther away from the first transmission gate relative to the second NOR gate. In the third group of circuits, the second NOT gate and the voltage-stabilizing capacitor are arranged along the second direction, and the voltage-stabilizing capacitor is farther away from the second NOR gate relative to the second NOT gate.

[0027] Optionally, the shift register unit is located on the substrate and along the second direction:

[0028] At least two of the following circuits on the substrate have equal lengths in their orthogonal projections: the first NOR gate, the first group of circuits, the second group of circuits, the third group of circuits, the third NOT gate, and the fourth NOT gate.

[0029] And / or, the lengths of the second NOR gate and the orthogonal projection of the second NOT gate onto the substrate are equal;

[0030] And / or, at least two of the circuits in the first transmission gate, the second transmission gate, the first NOT gate, the third transmission gate, and the voltage regulator capacitor have equal lengths of their orthogonal projections onto the substrate.

[0031] Optionally, the shift register unit is located on the substrate and along the first direction:

[0032] In the first group of circuits, at least two of the circuits among the first transmission gate, the second transmission gate, and the first NOT gate have equal widths in their orthographic projections onto the substrate;

[0033] And / or, in the second set of circuits, the width of the orthogonal projection of the second NOR gate and the third transmission gate onto the substrate is equal;

[0034] And / or, in the third set of circuits, the width of the second NOT gate is equal to the width of the orthogonal projection of the Zener capacitor onto the substrate.

[0035] Optionally, the first NOR gate, the second NOR gate, the first NOT gate, the second NOT gate, and the third NOT gate are connected to the first set of power lines and are used to operate based on the power signal provided by the first set of power lines; the fourth NOT gate is connected to the second set of power lines and is used to operate based on the power signal provided by the second set of power lines.

[0036] Among them, in the first group of power lines and the second group of power lines, each group of power lines includes a first power line and a second power line with different potentials of the provided power signals.

[0037] The first power line and the second power line included in the first group of power lines are located on both sides of at least one of the enable line and the reset control line in the first direction, and the first power line and the second power line included in any group of power lines extend along the second direction.

[0038] Along the first direction, at least the width of the first power line and the width of the second power line included in the second group of power lines are both greater than the width of the reset control line and both are greater than the width of the enable line; and the width of the first power line included in the second group of power lines is greater than the width of the first power line included in the first group of power lines, and the width of the second power line included in the second group of power lines is greater than the width of the second power line included in the first group of power lines.

[0039] Optionally, the first clock line, the second clock line, the third clock line, the fourth clock line, the enable line, the reset control line, and at least three adjacent signal lines from the first power line and the second power line included in any set of power lines are arranged at equal intervals in the first direction.

[0040] Optionally, the first transmission gate includes: a first P-type transistor and a first N-type transistor;

[0041] The gate of the first P-type transistor and the gate of the first N-type transistor are respectively connected to the first clock line and the second clock line. The first terminal of the first P-type transistor and the first terminal of the first N-type transistor are both connected to the input signal terminal. The second terminal of the first P-type transistor and the second terminal of the first N-type transistor are both connected to the input node.

[0042] Furthermore, the first P-type transistor and the first N-type transistor are arranged along the first direction and in a direction close to the second NOR gate.

[0043] Optionally, the first NOR gate includes: a second P-type transistor, a second N-type transistor, a third P-type transistor, and a third N-type transistor;

[0044] The gates of the second P-type transistor and the third N-type transistor are both connected to the reset control line. The first terminal of the second P-type transistor is connected to the first power supply line. The second terminal of the second P-type transistor is connected to the first terminal of the third P-type transistor. The second terminals of the third P-type transistor, the second terminals of the second N-type transistor, and the second terminals of the third N-type transistor are all connected to the first intermediate node. The first terminals of the second N-type transistor and the first terminals of the third N-type transistor are all connected to the second power supply line. The gates of the third P-type transistor and the second N-type transistor are both connected to the input node.

[0045] Furthermore, the third P-type transistor and the second P-type transistor are arranged and connected in series along the second direction; the second N-type transistor is located on the side of the third P-type transistor away from the second P-type transistor, and the second N-type transistor is closer to the first transmission gate relative to the third P-type transistor; the third N-type transistor is located on the side of the second P-type transistor away from the third P-type transistor, and the third N-type transistor is closer to the first NOT gate relative to the second P-type transistor.

[0046] Optionally, the first NOT gate includes a fourth P-type transistor and a fourth N-type transistor, wherein the fourth N-type transistor is a dual-gate transistor;

[0047] The gate of the fourth P-type transistor and the gate of the fourth N-type transistor are both connected to the first intermediate node. The first terminal of the fourth P-type transistor and the first terminal of the fourth N-type transistor are respectively connected to the first power line and the second power line. The second terminal of the fourth P-type transistor and the second terminal of the fourth N-type transistor are both connected to the second intermediate node.

[0048] Furthermore, the fourth N-type transistor and the fourth P-type transistor are arranged along the first direction and in a direction close to the third transmission gate.

[0049] Optionally, the second transmission gate includes: a fifth P-type transistor and a fifth N-type transistor;

[0050] The gate of the fifth P-type transistor and the gate of the fifth N-type transistor are respectively connected to the third clock line and the fourth clock line. The first terminal of the fifth P-type transistor and the first terminal of the fifth N-type transistor are both connected to the first intermediate node. The second terminal of the fifth P-type transistor and the second terminal of the fifth N-type transistor are both connected to the input node.

[0051] Furthermore, the fifth P-type transistor and the fifth N-type transistor are arranged along the first direction and in a direction close to the second NOR gate.

[0052] Optionally, the third transmission gate includes: a sixth P-type transistor and a sixth N-type transistor;

[0053] The gate of the sixth P-type transistor and the gate of the sixth N-type transistor are respectively connected to the first control terminal and the second control terminal. The first terminal of the sixth P-type transistor and the first terminal of the sixth N-type transistor are both connected to the enable line. The second terminal of the sixth P-type transistor and the second terminal of the sixth N-type transistor are both connected to the other input terminal of the second NOR gate.

[0054] Furthermore, the sixth N-type transistor and the sixth P-type transistor are arranged along the first direction and in a direction close to the voltage regulator capacitor.

[0055] Optionally, the second NOR gate includes: a seventh P-type transistor, a seventh N-type transistor, an eighth P-type transistor, and an eighth N-type transistor;

[0056] The gates of the seventh P-type transistor and the eighth N-type transistor are both connected to the third transmission gate. The gates of the eighth P-type transistor and the seventh N-type transistor are both connected to the second intermediate node. The first terminal of the seventh P-type transistor is connected to the first power supply line. The second terminal of the seventh P-type transistor is connected to the first terminal of the eighth P-type transistor. The second terminals of the eighth P-type transistor, the seventh N-type transistor, and the eighth N-type transistor are all connected to the input terminal of the second NOT gate. The first terminals of the seventh N-type transistor and the eighth N-type transistor are both connected to the second power supply line.

[0057] Furthermore, the eighth P-type transistor and the seventh N-type transistor are arranged along the second direction and in a direction close to the third transmission gate, the seventh P-type transistor and the eighth N-type transistor are arranged along the second direction and in a direction close to the third transmission gate, the seventh N-type transistor and the eighth N-type transistor are arranged along the first direction and in a direction close to the second NOT gate, and the eighth P-type transistor and the seventh P-type transistor are arranged along the first direction and in a direction close to the second NOT gate.

[0058] Optionally, the second NOT gate includes a ninth P-type transistor and a ninth N-type transistor; the third NOT gate includes a tenth P-type transistor and a tenth N-type transistor; and the fourth NOT gate includes an eleventh P-type transistor and an eleventh N-type transistor.

[0059] The gates of the ninth P-type transistor and the ninth N-type transistor are both connected to the output terminal of the second NOR gate. The gates of the tenth P-type transistor and the tenth N-type transistor are both connected to the second terminals of the ninth P-type transistor and the ninth N-type transistor. The gates of the eleventh P-type transistor and the eleventh N-type transistor are both connected to the second terminals of the tenth P-type transistor and the tenth N-type transistor. The second terminals of the eleventh P-type transistor and the eleventh N-type transistor are both connected to the output signal terminal. The first terminals of the ninth P-type transistor, the tenth P-type transistor, and the eleventh P-type transistor are all connected to the first power supply line. The first terminals of the ninth N-type transistor, the tenth N-type transistor, and the eleventh N-type transistor are all connected to the second power supply line.

[0060] Furthermore, the ninth P-type transistor and the ninth N-type transistor are arranged along the second direction and in a direction close to the voltage regulator capacitor; the tenth P-type transistor and the tenth N-type transistor are arranged along the second direction, and the tenth N-type transistor is closer to the voltage regulator capacitor relative to the tenth P-type transistor; the eleventh P-type transistor and the eleventh N-type transistor are arranged along the first direction and in a direction close to the pixel, or the eleventh P-type transistor and the eleventh N-type transistor are arranged along the second direction, and the eleventh N-type transistor is closer to the voltage regulator capacitor relative to the eleventh P-type transistor.

[0061] Optionally, the transistors included in the second NOT gate, the third NOT gate, and the fourth NOT gate are progressively larger in size, and the transistor included in the second NOT gate is larger than the transistor included in at least one of the circuits of the first NOR gate, the first transmission gate, the second transmission gate, the first NOT gate, the second NOR gate, and the third transmission gate.

[0062] Optionally, the transistor in the shift register unit includes: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a first source-drain metal layer, and a second source-drain metal layer located on one side of the substrate, wherein the first active layer is used as the active layer of the P-type transistor in the shift register unit, and the second active layer is used as the active layer of the N-type transistor in the shift register unit.

[0063] Furthermore, when the materials of the first active layer and the second active layer are different, the first active layer and the second active layer are located in different layers, and the first active layer, the first gate metal layer, the second gate metal layer, the second active layer, the first source / drain metal layer and the second source / drain metal layer are stacked sequentially in a direction away from the substrate.

[0064] When the material of the first active layer is the same as that of the second active layer, the first active layer and the second active layer are located in the same layer and are stacked sequentially with the first gate metal layer, the second gate metal layer, the second active layer, the first source / drain metal layer and the second source / drain metal layer in a direction away from the substrate.

[0065] Optionally, at least a portion of the first source / drain metal layer is reused with at least one of the first active layer, the first gate metal layer, and the second active layer to reduce the overlap area between the first source / drain metal layer and the second source / drain metal layer.

[0066] On the other hand, a display driving circuit is provided, the display driving circuit comprising: a plurality of cascaded shift register units as described in the above aspect.

[0067] In another aspect, a display device is provided, the display device comprising: a display panel, and a display driving circuit as described in the other aspect above;

[0068] The display panel includes multiple pixels arranged in an array. The display driving circuit is connected to the multiple pixels and is used to transmit display driving signals to the multiple pixels to drive the multiple pixels to emit light.

[0069] Optionally, the display driving circuit includes: a P-type gate driving circuit for transmitting gate driving signals to P-type transistors in the plurality of pixels, an N-type gate driving circuit for transmitting gate driving signals to N-type transistors in the plurality of pixels, a reset driving circuit for transmitting reset signals to transistors in the plurality of pixels, and a light-emitting driving circuit for transmitting light-emitting control signals to transistors in the plurality of pixels.

[0070] Furthermore, the P-type gate driving circuit includes two sets of P-type gate driving circuits located on both sides of the multi-row pixels in the pixel row direction. Each set of the P-type gate driving circuits includes multiple cascaded shift register units, and the multiple shift register units included in each set of the P-type gate driving circuits are connected one-to-one with the multi-row pixels.

[0071] The N-type gate driving circuit includes two sets of N-type gate driving circuits located on both sides of the multiple rows of pixels in the pixel row direction. Each set of N-type gate driving circuits includes multiple cascaded shift register units. Among the multiple shift register units included in each set of N-type gate driving circuits, one shift register unit is connected to two adjacent rows of pixels, and different shift register units are connected to different rows of pixels.

[0072] The light-emitting driving circuit and the reset driving circuit are respectively located on both sides of the multiple rows of pixels in the direction of the pixel rows. The light-emitting driving circuit and the reset driving circuit each include multiple cascaded shift register units. Among the multiple shift register units included in the light-emitting driving circuit, one shift register unit is connected to two adjacent rows of pixels, and different shift register units are connected to pixels in different rows. Among the multiple shift register units included in the reset driving circuit, one shift register unit is connected to two adjacent rows of pixels, and different shift register units are connected to pixels in different rows. Attached Figure Description

[0073] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this disclosure;

[0075] Figure 2 is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure;

[0076] Figure 3 is a schematic diagram of the working timing of a pixel circuit provided in an embodiment of this disclosure;

[0077] Figure 4 is a schematic diagram of the structural layout of a shift register unit provided in an embodiment of this disclosure;

[0078] Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this disclosure;

[0079] Figure 6 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this disclosure;

[0080] Figure 7 is a schematic diagram of the circuit structure layout of a shift register unit provided in an embodiment of this disclosure;

[0081] Figure 8 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this disclosure;

[0082] Figure 9 is a schematic circuit layout diagram of a shift register unit provided in an embodiment of this disclosure;

[0083] Figure 10 is a schematic layout diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0084] Figure 11 is a schematic layout diagram of another portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0085] Figure 12 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0086] Figure 13 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0087] Figure 14 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0088] Figure 15 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0089] Figure 16 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0090] Figure 17 is a schematic diagram of a portion of the film layer of a shift register unit provided in an embodiment of this disclosure;

[0091] Figure 18 is a schematic circuit layout of another shift register unit provided in an embodiment of this disclosure;

[0092] Figure 19 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0093] Figure 20 is a schematic diagram of another portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0094] Figure 21 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0095] Figure 22 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0096] Figure 23 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0097] Figure 24 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0098] Figure 25 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0099] Figure 26 is a schematic circuit layout of another shift register unit provided in an embodiment of this disclosure;

[0100] Figure 27 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of the present disclosure;

[0101] Figure 28 is a schematic diagram of another portion of the film layer of a shift register unit provided in an embodiment of the present disclosure;

[0102] Figure 29 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0103] Figure 30 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0104] Figure 31 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0105] Figure 32 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0106] Figure 33 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0107] Figure 34 is a schematic circuit layout of another shift register unit provided in an embodiment of this disclosure;

[0108] Figure 35 is a schematic layout diagram of a portion of the film layer of another shift register unit provided in an embodiment of the present disclosure;

[0109] Figure 36 is a schematic diagram of another portion of the film layer of a shift register unit provided in an embodiment of the present disclosure;

[0110] Figure 37 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of this disclosure;

[0111] Figure 38 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of the present disclosure;

[0112] Figure 39 is a schematic diagram of a portion of the film layer of another shift register unit provided in an embodiment of the present disclosure;

[0113] Figure 40 is a flowchart illustrating a method for driving a shift register unit according to an embodiment of this disclosure;

[0114] Figure 41 is a schematic diagram of the driving timing of a shift register unit provided in an embodiment of this disclosure;

[0115] Figure 42 is a schematic diagram of a display driving circuit provided in an embodiment of this disclosure;

[0116] Figure 43 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure;

[0117] Figure 44 is a schematic diagram of the structure of a display driving circuit in a display device provided in an embodiment of the present disclosure;

[0118] Figure 45 is a schematic diagram of the structure of a display driving circuit in another display device provided in an embodiment of this disclosure. Detailed Implementation

[0119] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0120] It is understood that the transistors used in the embodiments of this application can all be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Furthermore, based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle line of the transistor is designated as the control electrode, which can also be called the gate; the signal input terminal is the source; and the signal output terminal is the drain. In addition, the switching transistors used in the embodiments of this application can include any of P-type transistors and N-type transistors. A P-type transistor conducts when the gate is low and is cut off when the gate is high, while an N-type transistor conducts when the gate is high and is cut off when the gate is low. Furthermore, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two states and do not represent that the first potential or the second potential has a specific value throughout the text.

[0121] This application provides a shift register unit with a simple structure that is beneficial for narrow bezel design of display panels. As shown in Figure 1, the shift register unit includes an input control circuit 01 and an output control circuit 02.

[0122] The input control circuit 01 is connected to the first clock line CB, the second clock line CKn, the input signal terminal IN_n, and the input node Q_n, respectively, and is used to control the on / off state of the input signal terminal IN_n and the input node Q_n in response to the first clock signal provided by the first clock line CB and the second clock signal provided by the second clock line CKn.

[0123] For example, the input control circuit 01 can control the input signal terminal IN_n to be connected to the input node Q_n when the potential of the first clock signal provided by the first clock line CB is the first potential and the potential of the second clock signal provided by the second clock line CKn is the first potential, so that the input signal provided by the input signal terminal IN_n is transmitted to the input node Q_n, thereby controlling the potential of the input node Q_n to be the potential of the input signal; and the input control circuit 01 can control the input signal terminal IN_n to be disconnected from the input node Q_n when the potential of the first clock signal is the second potential and / or the potential of the second clock signal is the second potential.

[0124] It is understandable that "n" indicates that the shift register unit is the nth level shift register unit, and correspondingly, "nm" indicates the first m levels of shift register units cascaded with this shift register unit, and "n+m" indicates the last m levels of shift register units cascaded with this shift register unit. n can be an integer greater than 1, and m can be an integer less than n but greater than 1. For example, m can be 1, meaning that, except for the first level shift register unit, each level shift register unit can be cascaded with both the preceding and following level shift register units. The following embodiments all use m=1 as an example. Furthermore, generally, multi-level shift register units can be connected one-to-one with multiple rows of pixels. However, this is not limited to a one-to-one connection. For example, each level shift register unit can be connected with at least two rows of pixels.

[0125] Optionally, in this embodiment, the first potential can be an effective potential, and the second potential can be an ineffective potential. Furthermore, for a P-type transistor in a pixel, the first potential can be low (low, L) relative to the second potential. For an N-type transistor in a pixel, the first potential can be high (high, H) relative to the second potential. Correspondingly, a reset signal output to a P-type transistor means controlling the potential of the signal output to the P-type transistor to be high (H); a reset signal output to an N-type transistor means controlling the potential of the signal output to the N-type transistor to be low (L). Additionally, a high potential can be represented by binary "1", and a low potential can be represented by binary "0".

[0126] Referring again to Figure 1, the output control circuit 02 is connected to the input node Q_n, the reset control line Trst, the enable line EN, and the output signal terminal OUT_n, respectively. It is used to control the potential of the output signal terminal OUT_n based on the potential of the input node Q_n, the enable signal provided by the enable line EN, and the reset control signal provided by the reset control line Trst.

[0127] It is understandable that the output signal terminal OUT_n can be used to connect to a pixel. The output control circuit 02 can control the potential of the output signal terminal OUT_n to output the required display driving signal to the connected pixel through the output signal terminal OUT_n, so as to drive the pixel to emit light.

[0128] Optionally, the display driving signal may include at least one of a gate driving signal, a reset signal, and a light emission control signal. That is, the output control circuit 02 can output a gate driving signal to the data writing transistor in the pixel via the output signal terminal OUT_n. Alternatively, the output control circuit 02 can output a reset signal to the reset transistor in the pixel via the output signal terminal OUT_n. Or, the output control circuit 02 can output a light emission control signal to the light emission control transistor in the pixel via the output signal terminal OUT_n.

[0129] For example, the output control circuit 02 can control the output signal terminal OUT_n to a low potential 0 when the input node Q_n has a high potential 1, and / or the reset control signal provided by the reset control line Trst has a high potential 1, and simultaneously the enable signal provided by the enable line EN has a high potential 1; and the output control circuit 02 can also control the output signal terminal OUT_n to a high potential 1 when the input node Q_n has a high potential 1, and / or the reset control signal has a high potential 1, and simultaneously the enable signal has a low potential 0. In this way, a display driving signal (e.g., a gate driving signal) including a high potential 1 and a low potential 0 (i.e., including a first potential and a second potential) can be output through the output signal terminal OUT_n, which can realize the output of the required timing pulses to the P-type transistors and / or N-type transistors in the pixel, satisfying the driving requirements of PMOS switching pixels, or NMOS switching pixels, or CMOS switching pixels.

[0130] It is understood that, in the embodiments of this application, output reset and refresh rate control can be achieved by flexibly setting the enable signal provided by the enable line EN. For example, in normal output or high refresh rate zone, the potential of the enable signal can be set to a high potential 1 to enable the output control circuit 02 to work normally; while in the reset phase or low refresh rate zone, the potential of the enable signal can be set to a low potential 0 to enable the output control circuit 02 to control the output signal to an invalid potential, thus completing the reset. Low refresh rate zone and high refresh rate zone refer to display partitions with relatively low refresh rates (e.g., refresh rate less than or equal to 60Hz) and relatively high refresh rates (e.g., refresh rate greater than 60Hz). Generally, the display area can be divided into multiple display partitions, and different refresh rates can be used for different display partitions.

[0131] For example, for the N-type transistor connected to the output signal terminal OUT_n in the pixel, during the Porch period (or when the display panel is powered on / off), the potential of the enable signal provided by the enable line EN can be set to a high potential of 1, that is, the potential of the enable signal is set high. This causes the output control circuit 02 to control the potential of the output signal terminal OUT_n to a low potential of 0, thereby resetting the display drive signal output to the N-type transistor. The same applies to the P-type transistor, and will not be elaborated further.

[0132] It's also understandable that, in addition to setting the enable line EN, a reset control line Trst is also set. This allows for flexible configuration of the reset control signal provided by the Trst line during power-on or power-off of the display panel, or during Porch periods (or when the display panel is powered on / off). This controls the potential of the output signal terminal OUT_n to be an invalid potential, effectively resetting the output display drive signal and improving the reliability of power-on / off operations. This also avoids drive anomalies during the switch between low and high refresh rates in partial refresh scenarios and further reduces the drive power consumption of the shift register unit.

[0133] It's understandable that a PMOS switching pixel refers to a pixel whose pixel circuitry includes multiple P-type transistors; an NMOS switching pixel refers to a pixel whose pixel circuitry includes multiple N-type transistors; and a CMOS switching pixel refers to a pixel whose pixel circuitry includes at least one P-type transistor and at least one N-type transistor. MOS is short for metal-oxide-semiconductor, meaning the transistors in the pixel circuitry can be MOS transistors. Additionally, the transistors can also be thin-film transistors (TFTs). That is, the transistors in the pixel circuitry can be MOS TFTs; P-type transistors can be called PMOS TFTs, and N-type transistors can be called NMOS TFTs. Of course, this is just an illustrative explanation.

[0134] Optionally, taking a CMOS switch-type pixel as an example, Figure 2 shows a schematic diagram of the circuit structure of a pixel provided in an embodiment of this application. As shown in Figure 2, the pixel may include a pixel circuit and a light-emitting element. The pixel circuit may include nine transistors T1 to T9 and one storage capacitor Cst, that is, a 9T1C structure circuit. The light-emitting element may be, for example, an organic light-emitting diode (OLED). The connection method of each part is shown in Figure 2 and will not be described again. In addition, the signal terminals connected to the pixel include: gate signal terminals Gate_N and Gate_P, reset signal terminals Reset1_P, Reset2_P and Reset3_P, data signal terminal Data, reset power lines Vinit1, Vinit2 and Vinit3, light-emitting control terminal EM_P, pull-up power supply terminal VDD, and pull-down power supply terminal VSS. Of course, in some other embodiments, the pixel circuit may also be other structures, such as an 8T1C structure. The light-emitting element L1 may also be other types, such as a micro-LED, also known as an MLED. This application embodiment does not limit this.

[0135] For PMOS switching pixels, all nine transistors T1 to T9 can be PMOS TFTs; for NMOS switching pixels, all nine transistors T1 to T9 can be NMOS TFTs; and for CMOS switching pixels, as shown in Figure 2, T9 can be an NMOS TFT, while the other transistors T1 to T8 can all be PMOS TFTs. Correspondingly, taking the gate signal terminal as an example, the signal terminals connected to N-type transistors are marked with "_N" in the figure, and the signal terminals connected to P-type transistors are marked with "_P".

[0136] Taking the gate drive signal as an example, for a PMOS switching pixel, since the transistors receiving the gate drive signal are all PMOS TFTs, the same or similar P-type gate drive signal can be used to drive the PMOS TFT. For an NMOS switching pixel, since the transistors receiving the gate drive signal are all NMOS TFTs, the same or similar N-type gate drive signal can be used to drive the NMOS TFT. However, for the CMOS switching pixel shown in Figure 2, since transistors T2 and T4 receiving the gate drive signal are PMOS TFTs and T9 is an NMOS TFT, inverted P-type and N-type gate drive signals are needed to drive the PMOS TFT and NMOS TFT respectively. As mentioned earlier, the P-type gate drive signal refers to a gate drive signal with a first potential of low potential 0 and a second potential of high potential 1; the N-type gate drive signal refers to a gate drive signal with a first potential of high potential 1 and a second potential of low potential 0.

[0137] Optionally, taking the pixel circuit shown in Figure 2 as an example, Figure 3 shows a driving timing diagram of a pixel circuit. As shown in Figure 3, the driving timing may include stages t1 to t5 executed sequentially.

[0138] In stage t1: the potential of the light-emitting control signal provided by the light-emitting control terminal EM_P can be high. Accordingly, transistors T5 and T6 can be turned off. Furthermore, the connection between the pull-up power supply terminal VDD and the pull-down power supply terminal VSS can be disconnected, thereby turning off the light emission of the light-emitting element L1.

[0139] In stage t2, the gate drive signal provided by the gate signal terminal Gate_N can be at a high potential, while the reset signal provided by the reset signal terminals Reset1_P / Reset3_P can both be at a low potential. Correspondingly, transistors T1, T7, and T9 can all be turned on. Furthermore, the reset power supply terminal Vinit1 can sequentially output reset power signals to nodes N5 and N3 via the turned-on transistors T1 and T9, respectively, to reset nodes N5 and N3 to the potential V10 of the reset power supply signal provided by Vinit1, causing the potential of node N2 to gradually become V10 - Vth_Td, where Vth_Td refers to the threshold voltage of transistor T3 (also called the driving transistor Td). Additionally, the reset power supply terminal Vinit2 can output a reset power signal to node N4 (i.e., the anode of the OLED) via the turned-on transistor T7, to reset node N4 to the potential of the reset power supply signal provided by Vinit2.

[0140] In stage t3, the reset signal provided by the reset signal terminals Reset1_P / Reset3_P can both be at a high potential, the gate drive signal provided by the gate signal terminal Gate_N can be maintained at a high potential, and the gate drive signal provided by the gate signal terminal Gate_P can be at a low potential. Correspondingly, transistors T1 and T7 can be turned off, and transistors T2, T3, and T9 can all be turned on. Furthermore, the data signal terminal Data can transmit the data signal to node N2 via the turned-on transistor T4, thereby charging the potential of node N2 to the potential Vdata0 of the data signal, and charging nodes N3, N1, and N5 to a potential of Vdata0 + Vth_Td.

[0141] In stage t4, the potential of the gate drive signal provided by the gate signal terminal Gate_N becomes low, and the potential of the gate drive signal provided by the gate signal terminal Gate_P becomes high, while the potential of the reset signal provided by the reset signal terminal Reset2_P is low. Accordingly, transistors T2, T4, and T9 can all be turned off, and transistor T8 can be turned on. Furthermore, the reset power supply terminal Vinit3 can output a reset power supply signal to node N2 via the turned-on transistor T8, resetting node N2 to the potential V30 of the reset power supply signal provided by Vinit3. If V30 > Vdata0, the potential of node N3 can become V30 + Vth_Td; otherwise, the potential of node N3 remains Vdata0 + Vth_Td.

[0142] In stage t5, the reset signal provided by the Reset2_P terminal becomes high, and the light-emitting control signal provided by the EM_P terminal becomes low. Correspondingly, transistor T8 is turned off, and transistors T5 and T6 are both turned on. Furthermore, due to the storage effect of the storage capacitor Cst, the potential of node B1 remains at the potential of the previous stage, keeping transistor T3 on. This allows a path to be formed between the pull-up power supply terminal VDD and the pull-down power supply terminal VSS, enabling the light-emitting element L1 to emit light. The luminous current Id, which is positively correlated with the luminous intensity, can be determined by the potentials of node P1 and node P2. The potential of node P1 is Vdata0 + Vth_Td, and the potential of node P2 is the potential VDD0 of the pull-up power supply signal provided by the pull-up power supply terminal VDD. Accordingly, based on the current calculation formula, Id = K(Vdata0 - VDD0). 2K is determined by the inherent characteristics of transistor T8, such as its width-to-length ratio W / L, capacitance Cox, and mobility μ. That is, the luminous current transmitted from the pixel circuit to the light-emitting element L1 can be independent of the threshold voltage Vth_Td of the driving transistor. Therefore, the drift of the threshold voltage Vth_Td of transistor T8 will not affect the luminous brightness of the light-emitting element L1, ensuring a good luminous effect.

[0143] It is understandable that, based on the above introduction to the driving principle, transistors T2, T4, and T9 can be called data writing transistors, transistors T1, T7, and T8 can be called reset transistors, transistors T5 and T6 can be called light-emitting control transistors, and transistor T3 can be called driving transistors.

[0144] Based on this, as described above, the output signal terminal OUT_n of the shift register unit can be connected to the gate signal terminal of the pixel circuit (e.g., Gate_N and / or Gate_P as shown in Figure 2) and used to provide the required gate drive signal to the connected gate signal terminal. For example, providing the inverted P-type gate drive signal / N-type gate drive signal shown in Figure 3 to reliably drive transistors T4 and T9 in Figure 2, respectively. Of course, in some other embodiments, the output signal terminal OUT_n of the shift register unit can be connected to the reset signal terminal of the pixel circuit (e.g., Reset_P) and used to provide the required reset signal to the reset signal terminal, such as the reset signal shown in Figure 3. Alternatively, the output signal terminal OUT_n of the shift register unit can be connected to the light emission control terminal of the pixel circuit (e.g., EM_P) and used to provide the required light emission control signal to the light emission control terminal, such as the light emission control signal shown in Figure 3. Of course, it is not limited to satisfying the timing shown in Figure 3.

[0145] Next, referring to the circuit layout diagram shown in Figure 4, it can be seen that in the layout, the output control circuit 02 and the input control circuit 01 are arranged along the first direction X1 and in the direction closer to the pixel. The reset control line Trst, the first clock line CB, the second clock line CKn, and the enable line EN are arranged along the first direction X1 and in the direction closer to the pixel, and extend along the second direction Y1.

[0146] In this context, the second direction Y1 intersects with the first direction X1. For example, in a display panel comprising multiple pixels arranged in an array, the first direction X1 can refer to the pixel row direction, the second direction Y1 can refer to the pixel column direction, and the first direction X1 and the second direction Y1 can be perpendicular to each other.

[0147] Optionally, the arrangement described in the embodiments of this application may refer to "arranged sequentially in order of priority". For example, taking the arrangement of the output control circuit 02 and the input control circuit 01 along the first direction X1 and in the direction closer to the pixel as an example, the output control circuit 02 and the input control circuit 01 may be arranged sequentially along the first direction X1 and in the direction closer to the pixel. That is, in the first direction X1, the output control circuit 02 is farther away from the pixel relative to the input control circuit 01, and the input control circuit 01 is closer to the pixel relative to the output control circuit 02. The output control circuit 02, the input control circuit 01, and the pixel are arranged sequentially from left to right according to the direction shown in FIG. 4. The arrangement of other signal lines and other circuits is similar, and will not be described in detail below.

[0148] It is understandable that the layout shown in Figure 4 not only facilitates the connection between signal lines and circuits, but also allows for a relatively concentrated and compact arrangement of various circuits without wasting space, thus benefiting the narrow bezel design of the display device. Specifically, the output signal terminal OUT_n of the shift register unit shown in Figure 4 is connected to the gate signal terminal Gate_P in the nth row of pixels to output the P-type gate drive signal GP_n.

[0149] In summary, this application provides a shift register unit. The input control circuit controls the potential of the input node. The output control circuit controls the potential of the output signal terminal based on the potential of the input node, the enable signal provided by the enable line, and the reset control signal provided by the reset control line, so as to output a display drive signal to the pixel through the output signal terminal. Thus, by flexibly setting the enable signal, clock signal, and reset control signal, the shift register unit can output signals matching the P-type transistors and / or N-type transistors in the pixel. Furthermore, since the output control circuit and the input control circuit are arranged along a first direction and in a direction close to the pixel, and the signal lines connecting the output control circuit and the input control circuit are arranged along the first direction and in a direction close to the pixel, and all signal lines extend along a second direction intersecting the first direction, it also facilitates the narrow bezel design of the display device. This shift register unit has a simple structure and requires fewer signal lines.

[0150] Optionally, Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 5, the output control circuit 02 may include: a first output control sub-circuit 021, a second output control sub-circuit 022, and a third output control sub-circuit 023.

[0151] The first output control sub-circuit 021 can be connected to the input node Q_n, the reset control line Trst, and the first intermediate node Q1_n respectively, and can be used to control the potential of the first intermediate node Q1_n based on the potential of the input node Q_n and the reset control signal.

[0152] For example, the first output control sub-circuit 021 can control the potential of the first intermediate node Q1_n to be low potential 0 when the potential of the input node Q_n is high potential 1 and / or the potential of the reset control signal is high potential 1; and the first output control sub-circuit 021 can control the potential of the first intermediate node Q1_n to be high potential 1 when the potential of the input node Q_n is low potential 0 and the potential of the reset control signal is low potential 0.

[0153] The second output control sub-circuit 022 can be connected to the first intermediate node Q1_n and the second intermediate node Q2_n respectively, and can be used to control the potential of the second intermediate node Q2_n based on the potential of the first intermediate node Q1_n.

[0154] For example, the second output control sub-circuit 022 can invert the potential of the first intermediate node Q1_n and output it to the second intermediate node Q2_n, that is, it can control the potential of the second intermediate node Q2_n to be opposite to the potential of the first intermediate node Q1_n.

[0155] The third output control sub-circuit 023 can be connected to the second intermediate node Q2_n, the enable line EN, and the output signal terminal OUT_n respectively, and can be used to control the potential of the output signal terminal OUT_n based on the potential of the second intermediate node Q2_n and the enable signal.

[0156] For example, the third output control sub-circuit 023 can control the output signal terminal OUT_n to a low potential 0 when the potential of the second intermediate node Q2_n is high potential 1 and / or the potential of the enable signal is high potential 1; and the third output control sub-circuit 023 can control the output signal terminal OUT_n to a high potential 1 when the potential of the second intermediate node Q2_n is low potential 0 and the potential of the enable signal is low potential 0.

[0157] Of course, in some other embodiments, the connection method shown in FIG5 is not limited. For example, the second output control sub-circuit 022 may also be connected to the reset control line Trst.

[0158] Based on Figure 5, and continuing to refer to the layout shown in Figure 4, it can be seen that the first output control sub-circuit 021 and the input control circuit 01 in the output control circuit 02 can be arranged along the first direction X1 and towards the pixel (e.g., arranged sequentially). Furthermore, the first output control sub-circuit 021, the second output control sub-circuit 022, and the third output control sub-circuit 023 can be arranged along the first direction X1 and towards the pixel (e.g., arranged sequentially). The second output control sub-circuit 022 and the input control circuit 01 can be arranged along the second direction Y1 (e.g., arranged sequentially). This facilitates the connection between signal lines and circuits and is beneficial for the narrow bezel design of the display device. Furthermore, referring to Figure 4, it can also be seen that, relative to the previous stage (e.g., n-1 stage) shift register unit, the input control circuit 01 and the second output control sub-circuit 022 can be arranged sequentially from top to bottom in a direction away from the previous stage shift register unit.

[0159] Optionally, referring further to Figure 5, it can be seen that the shift register unit provided in the embodiments of this application may also include: latch circuit 03, switch control circuit 04, and drive enhancement circuit 05.

[0160] The latch circuit 03 can be connected to the third clock line CK, the fourth clock line CBn, the second intermediate node Q2_n, and the input node Q_n, respectively. It can be used to control the switching of the second intermediate node Q2_n and the input node Q_n in response to the third clock signal provided by the third clock line CK and the fourth clock signal provided by the fourth clock line CBn. The potential of the second intermediate node Q2_n is opposite to the potential of the first intermediate node Q1_n. That is, as described above, the second output control sub-circuit 022 can be used to invert the potential of the first intermediate node Q1_n and output it to the second intermediate node Q2_n, so that the latch circuit 03 outputs a potential opposite to the potential of the first intermediate node Q1_n to the input node Q_n.

[0161] For example, the latch circuit 03 can control the second intermediate node Q2_n to conduct with the input node Q_n when the potential of the third clock signal provided by the third clock line CK is the first potential and the potential of the fourth clock signal provided by the fourth clock line CBn is the first potential, so that the potential of the second intermediate node Q2_n is transmitted to the input node Q_n; and the latch circuit 03 can control the second intermediate node Q2_n to disconnect from the input node Q_n when the potential of the third clock signal is the second potential or the potential of the fourth clock signal is the second potential. Because the potential of the second intermediate node Q2_n is opposite to the potential of the first intermediate node Q1_n, after passing through the latch circuit 03, the potential of the input node Q_n can be made the same as the potential of the first intermediate node Q1_n, thus achieving the purpose of latching the potential of the input node Q_n. Alternatively, it can be said that the latch circuit 03 can store the potential of the input node Q_n, preventing leakage of the potential of the input node Q_n.

[0162] Optionally, in some embodiments, the first clock line CB and the fourth clock line CBn can be shared, and the second clock line CKn and the third clock line CK can be shared. For example, the first clock line CB and the fourth clock line CBn can both be the fourth clock line CBn, and the second clock line CKn and the third clock line CK can both be the second clock line CKn. That is, in one implementation, two sets of clock lines (i.e., two sets of clock signals) can be used: CK and CB. Alternatively, in another implementation, four sets of clock lines (i.e., four sets of clock signals) can be used: CKn, CK, CBn, and CB.

[0163] Optionally, the period of the four clock signals can be 2H, and the clock signals provided by clock line CK and clock line CB can differ by 1H. The clock signals provided by clock line CKn and clock line CB can be inverted signals, and the clock signals provided by clock line CBn and clock line CK can be inverted signals. Furthermore, the pulse width of the low potential 0 of the clock signals provided by clock line CK and clock line CB is generally 0 to 2 microseconds (μs) shorter than 1H, and can be selected based on the load resistor RC. This is to eliminate the influence of clock delay and avoid the risk of competition between different circuits during state switching caused by the simultaneous control of the two connected lines by input control circuit 01 and latch circuit 03. Here, "H" can refer to one line period and can be flexibly adjusted according to the number of cascaded shift register units.

[0164] Referring again to Figure 5, the switch control circuit 04 can be connected between the enable line EN and the third output control sub-circuit 023, and can also be connected to the first control terminal Con1 and the second control terminal Con2 respectively. It can be used to control the on / off state of the enable line EN and the third output control sub-circuit 023 in response to the first control signal provided by the first control terminal Con1 and the second control signal provided by the second control terminal Con2. That is, the output control circuit 02 and the enable line EN do not need to be directly connected, but are indirectly connected through the switch control circuit 04. Of course, this refers to the third output control sub-circuit 023 included in the output control circuit 02.

[0165] For example, when the potential of the first control signal provided by the first control terminal Con1 is the first potential, and the potential of the second control signal provided by the second control terminal Con2 is the first potential, the switch control circuit 04 controls the enable line EN to be connected to the third output control sub-circuit 023, thereby enabling the enable signal provided by the enable line EN to be transmitted to the third output control sub-circuit 023. This can also be considered as connecting the enable line EN to the third output control sub-circuit 023 in the output control circuit 02. Conversely, when the potential of the first control signal provided by the first control terminal Con1 is the second potential, and / or the potential of the second control signal provided by the second control terminal Con2 is the second potential, the switch control circuit 04 controls the enable line EN to be disconnected from the third output control sub-circuit 023. This can also be considered as not connecting the enable line EN to the third output control sub-circuit 023 in the output control circuit 02.

[0166] Optionally, the first control terminal Con1 and the second control terminal Con2 can be connected to the second intermediate node Q2_n and the first intermediate node Q1_n of the current stage shift register unit, respectively. This is the connection method shown in Figure 5, schematically illustrating the connection of the switch control circuit 04 to one first control terminal Con1 and one second control terminal Con2. In some other embodiments, the switch control circuit 04 can also be connected to multiple corresponding first control terminals Con1 and multiple corresponding second control terminals Con2. For example, the switch control circuit 04 can be connected to two corresponding first control terminals Con1 and two corresponding second control terminals Con2. In this scenario, of the two corresponding first control terminals Con1 and two corresponding second control terminals Con2, one first control terminal Con1 and one second control terminal Con2 can be connected to the second intermediate node Q2_n-1 and the first intermediate node Q1_n-1 of the previous stage shift register unit, respectively. The other corresponding first control terminal Con1 and the other second control terminal Con2 can be connected to the first intermediate node Q1_n and the second intermediate node Q2_n of the current stage shift register unit, respectively. Therefore, the signals at the first intermediate node Q1_n and the second intermediate node Q2_n can be used as cascading signals to drive the cascaded shift register units.

[0167] Based on this and the preceding description, it can be seen that by connecting the enable line EN to the third output control sub-circuit 023 in the output control circuit 02, the output control circuit 02 can control the potential of the output signal terminal OUT_n based on the enable signal provided by the enable line EN and the potential of the second intermediate node Q2_n, so as to output a display drive signal to the pixel. Thus, by flexibly setting the first control signal and the second control signal, the output of the shift register unit can be controlled by selecting whether the enable line EN is connected to or not in the output control circuit 02, thereby providing good drive flexibility.

[0168] Furthermore, by controlling the switch control circuit 04 with the cascading signals of adjacent shift register units, the enable line EN can be connected stage by stage. This allows the shift register unit to reset only the GOA unit at the cascading start boundary, without resetting GOA units that have started but not yet completed shifting, until the shifting is complete. This not only satisfies the driving requirement of consistent pixel-wide refresh output pulse width but also saves power consumption compared to resetting all outputs. For example, for the switch control circuit 04, the switch control circuit 04 only controls the enable line EN to conduct with the output control circuit 02 when the potentials of the first intermediate node Q1_n-1 and the second intermediate node Q2_n-1 controlled by the previous stage shift register unit are both valid potentials, and the potentials of the first intermediate node Q1_n and the second intermediate node Q2_n controlled by the previous stage shift register unit are also valid potentials. Only then does the output control circuit 02 control the output signal potential based on the enable signal provided by the enable line EN. Of course, in the embodiment shown in Figure 5, where the switch control circuit 04 is connected to a first control terminal Con1 and a second control terminal Con2 in a one-to-one correspondence, different cascaded shift register units can be connected to different enable lines EN respectively, so as to achieve the same technical effect by flexibly setting the enable signals provided by the different enable lines EN. For example, this embodiment of the application takes the current stage shift register unit connected to enable line EN1 and another cascaded shift register unit connected to enable line EN2 as an example for explanation.

[0169] Referring again to Figure 5, the drive enhancement circuit 05 can be connected between the third output control sub-circuit 023 and the output signal terminal OUT_n, and can be used to invert the potential of the output signal of the third output control sub-circuit 023 at least once before outputting it to the output signal terminal OUT_n. In this way, the driving capability of the shift register unit can be enhanced.

[0170] Optionally, in one implementation, the drive enhancement circuit 05 can invert the potential of the output signal of the third output control sub-circuit 023 in the output control circuit 02 an odd number of times before outputting it to the output signal terminal OUT_n. That is, the drive enhancement circuit 05 can control the potential of the output signal terminal OUT_n to be opposite to the potential of the output signal of the third output control sub-circuit 023 in the output control circuit 02.

[0171] Alternatively, in another implementation, the drive enhancement circuit 05 can also invert the potential of the output signal of the third output control sub-circuit 023 in the output control circuit 02 an even number of times before outputting it to the output signal terminal OUT_n. That is, the drive enhancement circuit 05 can control the potential of the output signal terminal OUT_n to be the same as the potential of the output signal of the third output control sub-circuit 023 in the output control circuit 02.

[0172] Alternatively, in another implementation, the output signal terminal OUT_n may include a first output signal terminal OUTN_n and a second output signal terminal OUTP_n, and the potentials of the first output signal terminal OUTN_n and the second output signal terminal OUTP_n may be opposite at the same time. For example, referring to Figure 2, both the first output signal terminal OUTN_n and the second output signal terminal OUTP_n can be connected to the gate signal terminal Gate_N connected to the N-type transistor T9 in the pixel, and can be used to provide gate drive signals with opposite potentials to the gate signal terminal Gate_N respectively. Of course, the gate drive signals with opposite potentials will not be provided to the N-type transistor T9 simultaneously. Alternatively, referring to Figure 2, the first output signal terminal OUTN_n and the second output signal terminal OUTP_n can be connected to the gate signal terminal Gate_N connected to the N-type transistor T9 and the gate signal terminal Gate_P connected to the P-type transistor T2 respectively, and can be used to provide gate drive signals with opposite potentials to the gate signal terminals Gate_N and Gate_P respectively. Accordingly, the drive enhancement circuit 05 may include two drive enhancement sub-circuits. One drive enhancement sub-circuit can be connected between the third output control sub-circuit 023 and the first output signal terminal OUTN_n, and can be used to invert the potential of the output signal of the third output control sub-circuit 023 an even number of times before outputting it to the first output signal terminal OUTN_n. The other drive enhancement sub-circuit can be connected between the third output control sub-circuit 023 and the second output signal terminal OUTP_n, and can be used to invert the potential of the output signal of the third output control sub-circuit 023 an odd number of times before outputting it to the second output signal terminal OUTP_n.

[0173] Optionally, based on Figure 5 and referring to the layout shown in Figure 4, the latch circuit 03, switch control circuit 04, and drive enhancement circuit 05 can be arranged along the first direction X1 and towards the pixel (e.g., arranged sequentially). The latch circuit 03 and input control circuit 01 can be arranged along the second direction Y1 (e.g., arranged sequentially) and can be located between the input control circuit 01 and the second output control sub-circuit 022. The switch control circuit 04 and the third output control sub-circuit 023 can be arranged along the second direction Y1 (e.g., arranged sequentially). The third clock line CK and the fourth clock line CBn can be located between the reset control line Trst and the enable line EN (i.e., EN1), and arranged along the first direction X1 and towards the pixel (e.g., arranged sequentially), and can extend along the second direction Y1. This facilitates the connection between signal lines and circuits and allows for narrow bezel design of the display device.

[0174] Furthermore, referring to Figure 4, it can be seen that, relative to the previous stage shift register unit, the input control circuit 01 and the latch circuit 03 can be arranged sequentially from top to bottom in a direction away from the previous stage shift register unit, and the second output control sub-circuit 022 can be located between the input control circuit 01 and the latch circuit 03. Moreover, the third output control sub-circuit 023 and the switch control circuit 04 can also be arranged sequentially from top to bottom in a direction away from the previous stage shift register unit. This facilitates the connection between the various circuits.

[0175] Optionally, based on the structure shown in Figure 5, Figure 6 illustrates a circuit structure diagram of a shift register unit. As shown in Figure 6, the input control circuit 01 may include: a first transmission gate Tg1. The first output control sub-circuit 021 may include: a first NOR gate NOR1. The second output control sub-circuit 022 may include: a first NOT gate INV1. The third output control sub-circuit 023 may include: a second NOR gate NOR2. The latch circuit 03 may include: a second transmission gate Tg2. The switch control circuit 04 may include: a third transmission gate Tg3. The drive enhancement circuit 05 may include: a second NOT gate INV2, a third NOT gate INV3, and a fourth NOT gate INV4 connected in series. It is understood that a NOT gate can also be called an inverter, and a transmission gate can also be called a transmission switch.

[0176] Specifically, the first transmission gate Tg1 can be connected between the input signal terminal IN_n and the input node Q_n, and can also be connected to the first clock line CB and the second clock line CKn respectively. The two input terminals of the first NOR gate NOR1 can be connected to the reset control line Trst and the input node Q_n respectively, and the output terminal of the first NOR gate NOR1 can be connected to the first intermediate node Q1_n. The input terminal of the first NOT gate INV1 can be connected to the first intermediate node Q1_n, and the output terminal of the first NOT gate INV1 can be connected to the second intermediate node Q2_n. Of the two inputs of the second NOR gate NOR2, one input can be connected to the second intermediate node Q2_n, and the other input can be connected to the enable line EN (i.e., EN1) through the third transmission gate Tg3. The third transmission gate Tg3 can also be connected to the first control terminal Con1 and the second control terminal Con2, respectively. The output of the second NOR gate NOR2 can be connected to the output signal terminal OUT_n through the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4 connected in series. The second transmission gate Tg2 can be connected between the second intermediate node Q2_n and the input node Q_n, and can also be connected to the third clock line CK and the fourth clock line CBn, respectively. Furthermore, the shift register unit also includes a voltage regulator capacitor C1 (not shown in Figure 6) connected between ground GND and the other input of the second NOR gate NOR2. This voltage regulator capacitor C1 can be used to stabilize the potential of the input of the second NOR gate NOR2 so that the potential remains stable even when there is no signal at the input of the second NOR gate NOR2.

[0177] It is understandable that the logic principle of a NOR gate is: all 0s output 1, any 1 outputs 0; that is, when the potentials of all received signals are low (0), the potential of the output signal can be controlled to be high (1); otherwise, as long as the potential of any received signal is high (1), the potential of the output signal is controlled to be low (0). The logic principle of a INV gate is: inverting 1 results in 0, and inverting 0 results in 1. Based on this, we can know that:

[0178] The first output control sub-circuit 021, including the first NOR gate NOR1, can control the potential of the first intermediate node Q1_n to be low (0) when the potential of the input node Q_n is high (1) and / or the potential of the reset control signal provided by the reset control line Trst is high (1); and can control the potential of the first intermediate node Q1_n to be high (1) when the potential of the input node Q_n is low (0) and the potential of the reset control signal provided by the reset control line Trst is low (0).

[0179] The second output control sub-circuit 022, including the first NOT gate INV2, can control the potential of the second intermediate node Q2_n to be high 1 when the potential of the first intermediate node Q1_n is low 0; and can control the potential of the second intermediate node Q2_n to be low 0 when the potential of the first intermediate node Q1_n is high 1.

[0180] The third output control sub-circuit 023, including the second NOR gate NOR2, can output a low-potential signal 0 to the drive enhancement circuit 05 when the potential of the second intermediate node Q2_n is high potential 1 and / or the potential of the enable signal provided by the enable line EN is high potential 1; and can also output a low-potential signal 0 to the drive enhancement circuit 05 when the potential of the second intermediate node Q2_n is low potential 0 and the potential of the enable signal provided by the enable line EN is low potential 0.

[0181] The drive enhancement circuit 05, which includes three NOT gates (INV2, INV3, and INV4), can output a high-potential signal (1) to the output signal terminal OUT_n when the third output control sub-circuit 023 outputs a low-potential signal (0); and can output a low-potential signal (0) to the output signal terminal OUT_n when the third output control sub-circuit 023 outputs a high-potential signal (1).

[0182] That is, based on the structure shown in Figure 6, the shift register unit shown includes a drive enhancement circuit 05, and this drive enhancement circuit 05 includes three NOT gates: a second NOT gate INV2, a third NOT gate INV3, and a fourth NOT gate INV4. Correspondingly, this drive enhancement circuit 05 can be used to invert the potential of the output signal of the third output control sub-circuit 023 an odd number of times (three times) and then output it to the output signal terminal OUT_n. Here, the second NOT gate INV2 can refer to the first NOT gate included in the drive enhancement circuit 05, and the fourth NOT gate INV4 can refer to the last NOT gate included in the drive enhancement circuit 05. Furthermore, in this embodiment, the output signal terminal OUT_n is connected to the gate signal terminal Gate_P, and a P-type gate drive signal is provided to the gate signal terminal Gate_P as an example. Based on this, it can also be determined that in embodiments where the drive enhancement circuit 05 inverts the potential of the output signal of the third output control sub-circuit 023 an even number of times, the drive enhancement circuit 05 can be configured to include an even number of NOT gates. For example, the drive enhancement circuit 05 can be configured to include two NOT gates: a second NOT gate INV2 and a third NOT gate INV3. The embodiments of this application do not limit the number of NOT gates included in the drive enhancement circuit 05. Furthermore, in embodiments where the drive enhancement circuit 05 includes two drive enhancement sub-circuits to perform odd-numbered and even-numbered inversion processing on the potential of the output signal of the third output control sub-circuit 023, respectively, the two drive enhancement sub-circuits can each include an odd number of NOT gates and an even number of NOT gates. Of course, in some embodiments, the two drive enhancement sub-circuits can also share NOT gates.

[0183] Understandably, by configuring the drive enhancement circuit 05 to include multiple NOT gates connected in series (e.g., three NOT gates: the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4), the driving capability of the output signal at the output signal terminal OUT_n can be amplified step by step, thus significantly enhancing the driving capability. Correspondingly, each NOT gate included in the drive enhancement circuit 05 can also be called an amplifier (AMP).

[0184] Furthermore, referring to the structure shown in Figure 6, it can be seen that in this embodiment, the latch circuit 03 includes the second transmission gate Tg2 on the premise that the second output control sub-circuit 022 includes a first NOT gate INV1 for inverting the potential of the first intermediate node Q1_n. In some other embodiments, the second output control sub-circuit 022 may also include other gate circuits besides the NOT gate (e.g., NOR gate) to control the potential of the second intermediate node Q2_n based on the potential of the first intermediate node Q1_n. Based on this, the latch circuit 03 may also include a NOT gate connected to the second transmission gate Tg2 and the first intermediate node Q1_n separately. Of course, based on the second output control sub-circuit 022 including the first NOT gate INV1, in some other embodiments, the latch circuit 03 may also include a NOT gate connected to the second transmission gate Tg2 and the first intermediate node Q1_n separately, that is, the second output control sub-circuit 022 and the latch circuit 03 may not share a NOT gate. Alternatively, the second output control sub-circuit 022 and the latch circuit 03 can share an NOT gate, meaning that the first NOT gate INV1 included in the second output control sub-circuit 022 can also be considered as part of the latch circuit 03. Furthermore, based on including multiple first control terminals Con1 and multiple second control terminals Con2, the switch control circuit 04 can include the same number of multiple third transmission gates Tg3.

[0185] Optionally, for the scenario where the output signal terminal OUT_n and the gate signal terminal Gate_P are connected, and a gate drive signal is provided to the gate signal terminal Gate_P, as shown in Figure 6, the output signal terminal OUT_n can be identified as GP_n, the first intermediate node Q1_n can be identified as GNc_n, and the second intermediate node Q2_n can be identified as GPc_n. Correspondingly, based on the first control terminal Con1 and the second control terminal Con2 being connected to the second intermediate node Q2_n and the first intermediate node Q1_n respectively, the first control terminal Con1 can also be identified as GPc_n, and the second control terminal Con2 as GNc_n. The input signal terminal IN_n of each shift register unit can be connected to the second intermediate node Q2_n of the cascaded shift register unit (e.g., the second intermediate node Q2_n-1 of the cascaded previous shift register unit, also called GPc_n-1). Of course, the input signal terminal IN_1 of the first-stage shift register unit needs to be connected to the enable signal line STV to receive the enable signal from the enable signal line STV.

[0186] Furthermore, based on Figure 6, referring to another layout shown in Figure 7, it can be seen that the first NOR gate NOR1 includes a first group of circuits including a first transmission gate Tg1, a second transmission gate Tg2 and a first NOT gate INV1, a second group of circuits including a second NOR gate NOR2 and a third transmission gate Tg3, a third group of circuits including a second NOT gate INV2 and a voltage regulator capacitor C1, and the third NOT gate INV3 and the fourth NOT gate INV4 can be arranged along the first direction X1 and along the direction closer to the pixel (e.g., arranged sequentially).

[0187] Furthermore, in the first group of circuits, the first transmission gate Tg1, the second transmission gate Tg2, and the first NOT gate INV1 can be arranged along the second direction Y1 (e.g., arranged sequentially). In the second group of circuits, the second NOR gate NOR2 and the third transmission gate Tg3 can be arranged along the second direction Y1 (e.g., arranged sequentially), and the third transmission gate Tg3 can be located away from the first transmission gate Tg1 relative to the second NOR gate NOR2. In the third group of circuits, the second NOT gate INV2 and the voltage regulator capacitor C1 can be arranged along the second direction Y1 (e.g., arranged sequentially), and the voltage regulator capacitor C1 can be located away from the second NOR gate NOR2 relative to the second NOT gate INV2.

[0188] Optionally, referring to FIG7, it can also be seen that the shift register unit described in the embodiments of this application can be located on substrate 00. Furthermore, along the second direction Y1:

[0189] At least two of the circuits in the first NOR gate NOR1, the first group of circuits, the second group of circuits, the third group of circuits, the third NOT gate INV3, and the fourth NOT gate INV4 have the same length l1 of orthogonal projection onto the substrate 00. For example, referring to Figure 7, in the shift register unit shown therein, the length l1 of the orthogonal projection of each of the five circuits in the first NOR gate NOR1, the first group of circuits, the second group of circuits, the third group of circuits, the third NOT gate INV3, and the fourth NOT gate INV4 onto the substrate 00 is equal.

[0190] And / or, the length l1 of the orthogonal projection of the second NOR gate NOR2 and the second NOT gate INV2 on the substrate 00 can be equal.

[0191] And / or, the length l1 of the orthogonal projection of at least two of the circuits in the first transmission gate Tg1, the second transmission gate Tg2, the first NOT gate INV1, the third transmission gate Tg3, and the voltage regulator capacitor C1 on the substrate 00 can be equal. For example, referring to Figure 7, in the shift register unit shown therein, the length l1 of the orthogonal projection of each of the circuits in the first transmission gate Tg1, the second transmission gate Tg2, the first NOT gate INV1, the third transmission gate Tg3, and the voltage regulator capacitor C1 on the substrate 00 is equal.

[0192] Alternatively, referring further to Figure 7, it can be seen that along the first direction X1:

[0193] In the first group of circuits, the width d1 of the orthogonal projection of at least two of the circuits in the first transmission gate Tg1, the second transmission gate Tg2, and the first NOT gate INV1 on the substrate 00 can be equal. For example, referring to Figure 7, in the shift register unit shown therein, the length l1 of the orthogonal projection of each circuit in the first transmission gate Tg1, the second transmission gate Tg2, and the first NOT gate INV1 on the substrate 00 is equal.

[0194] And / or, in the second set of circuits, the width d1 of the orthogonal projection of the second NOR gate NOR2 and the third transmission gate Tg3 on the substrate 00 can be equal.

[0195] And / or, in the third group of circuits, the width d1 of the orthogonal projection of the second NOT gate INV2 and the Zener capacitor C1 on the substrate 00 can be equal.

[0196] Of course, the equality of lengths l1 and d1 mentioned above can refer to approximate equality rather than strict equality. Furthermore, in addition to the situations described above, other equal relationships can also be included. For example, along the first direction X1, the width d1 of the first NOR gate NOR1 can be equal to that of the width of the first group of circuits.

[0197] Optionally, referring to Figure 7, it can also be seen that among the three NOT gates included in the drive enhancement circuit 05, the sizes of the second NOT gate INV2 to the fourth NOT gate INV4 can be increased sequentially, that is, from the first NOT gate to the last NOT gate, the size of each NOT gate can be increased sequentially. In this way, the driving capability can be improved step by step.

[0198] It is understood that, in conjunction with Figures 4 and 7, the arrangement provided in this application embodiment can make good use of limited space to centrally set up multiple circuit components, thereby effectively reducing the width of the frame and thus improving the driving capability and stability of the shift register unit.

[0199] Optionally, based on Figure 6, Figure 8 shows a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application. Referring to Figure 8, it can be seen that the first NOR gate NOR1, the second NOR gate NOR2, the first NOT gate INV1, the second NOT gate INV2, and the third NOT gate INV3 can be connected to the first set of power lines and can be used to operate based on the power signal provided by the first set of power lines; the fourth NOT gate INV4 can be connected to the second set of power lines and can be used to operate based on the power signal provided by the second set of power lines.

[0200] In this diagram, either the first group of power lines or the second group of power lines can include a first power line VGH and a second power line VGL with different potentials for the power signals they provide. For example, the potential of the power signal provided by the first power line VGH can be greater than the potential of the power signal provided by the second power line VGL. For distinction, the first power line VGH and the second power line VGL included in the first group of power lines are labeled VGH1 and VGL1, respectively, while the first power line VGH and the second power line VGL included in the second group of power lines are labeled VGH2 and VGL2, respectively. That is, the first power line VGH and the second power line VGL connected to all gate circuits except the last NOT gate (e.g., the fourth NOT gate INV4) are labeled VGH1 and VGL1, respectively, while the first power line VGH and the second power line VGL connected to the last NOT gate (e.g., the fourth NOT gate INV4) are labeled VGH2 and VGL2, respectively.

[0201] Optionally, the first power line VGH1 and the second power line VGL1 included in the first group of power lines may be located on both sides of at least one of the enable line EN (e.g., EN1) and the reset control line Trst in the first direction X1, and the first power line VGH1 / VGH2 and the second power line VGL1 / VGL2 included in any group of power lines may extend along the second direction Y1.

[0202] For example, referring to a layout diagram as shown in Figures 7 and 9, in the first direction X1, for the first NOR gate NOR1, the first power line VGH1 and the second power line VGL1 in the first group of power lines it connects to can be located on the left and right sides of the reset control line Trst. For the second NOR gate NOR2, the first power line VGH1 and the second power line VGL1 in the first group of power lines it connects to can be located on the left and right sides of the enable line EN. That is, part of the first power line VGH1 and part of the second power line VGL1 in the first group of power lines can be interspersed between the reset control line Trst and the enable line EN. And for each NOT gate, the first power line VGH1 / VGH2 and the second power line VGL1 / VGL2 it connects to can be adjacent to each other.

[0203] Optionally, as described above and as shown in Figure 9, the enable line EN may include different enable lines connected to different cascaded shift register units (e.g., EN1 and EN2 connected to the nth stage GOAn and the (n+1th)th stage GOAn+1, respectively). Furthermore, as shown in Figure 9, in some embodiments, the enable lines EN1 and EN2 may be arranged along the first direction X1 and in a direction closer to the pixel (e.g., arranged sequentially and adjacently).

[0204] Optionally, continuing with Figure 9, along the first direction X1, at least the widths of the first power line VGH2 and the second power line VGL2 included in the second group of power lines are both greater than the width of the reset control line Trst, and both are greater than the width of the enable line EN. Of course, if an enable signal line STV is set, the width can also be greater than the width of the enable signal line STV. Furthermore, the width of the first power line VGH2 included in the second group of power lines is greater than the width of the first power line VGH1 included in the first group of power lines, and the width of the second power line VGL2 included in the second group of power lines is greater than the width of the second power line VGL1 included in the first group of power lines.

[0205] That is, in some embodiments, the width of the reset control line Trst, the width of the enable line EN, and the width of the enable signal line STV can all be at least smaller than the width of the first power line VGH2 in the second group of power lines, and can all be at least smaller than the width of the second power line VGL2 in the second group of power lines. Of course, in other embodiments, the width of the reset control line Trst, the width of the enable line EN, and the width of the enable signal line STV can all be smaller than the width of the first power line VGH1 in the first group of power lines, and can all be smaller than the width of the second power line VGL1 in the first group of power lines. Furthermore, the width of the first power line VGH2 connected to the last NOT gate (e.g., the fourth NOT gate INV4) can be greater than the width of the first power line VGH1 connected to other gate circuits other than the fourth NOT gate INV4, and the width of the second power line VGL2 connected to the last NOT gate (e.g., the fourth NOT gate INV4) can be greater than the width of the second power line VGL1 connected to other gate circuits other than the fourth NOT gate INV4. In other words, the power line (including the first power line VGH2 and the second power line VGL2) connected to the last NOT gate that is directly connected to the output signal terminal OUT_n has the widest width.

[0206] Optionally, in some embodiments, the widths of the reset control line Trst, the enable line EN, and the power-on signal line STV may be similar or equal. The widths of the first power line VGH1 / VGH2 and the second power line VGL1 / VGL2 in any set of power lines may be similar or equal.

[0207] For example, the width of the reset control line Trst can be 3 to 10 micrometers (μm). For instance, the width of the reset control line Trst can be 4 μm. The widths of the first power line VGH1 / VGH2 and the second power line VGL1 / VGL2 in any group of power lines can generally be 5 to 30 μm. For example, in the drive enhancement circuit 05, the widths of the first power line VGH1 and the second power line VGL1 in the first group of power lines connected to the first NOT gate (e.g., the second NOT gate INV2) and the second NOT gate (e.g., the third NOT gate INV3) can both be 10 μm, while the widths of the first power line VGH2 and the second power line VGL2 in the second group of power lines connected to the last NOT gate (e.g., the fourth NOT gate INV4) can both be 30 μm.

[0208] Understandably, by making the widths of the first power lines VGH1 / VGH2 and the second power lines VGL1 / VGL2 wider, the driving capability of the corresponding gate circuits can be enhanced. Furthermore, since the last NOT gate in the drive enhancement circuit 05 is directly connected to the pixel through its output signal terminal OUT_n, making the power line connected to the last NOT gate the widest possible enhances its driving capability. Also, by separating the power line connected to the last NOT gate from the power lines connected to other NOT gates, the problem of abnormal output caused by the negative bias of the threshold voltage Vth of the N-type transistor can be solved. For example, when the threshold voltage Vth of the N-type transistor is negatively biased, the power signal provided by the second power line VGL connected to the last NOT gate can be adjusted individually to ensure the normal output of the N-type transistor.

[0209] Optionally, in some embodiments, among the multiple NOT gates included in the drive enhancement circuit 05, the potential of the power signal provided by the first power line VGH2 in the second group of power lines connected to the last NOT gate (e.g., the fourth NOT gate INV4) can be greater than or equal to the potential of the power signal provided by the first power line VGH1 in the first group of power lines connected to the other NOT gates (e.g., the second NOT gate INV2 and the third NOT gate INV3). And / or, the potential of the power signal provided by the second power line VGL2 in the second group of power lines connected to the last NOT gate can be less than or equal to the potential of the power signal provided by the second power line VGL1 in the first group of power lines connected to the other NOT gates. It is understood that this can refer to the magnitude of the absolute value of the potential. In this way, the charging and discharging speed of the last NOT gate directly connected to the output signal terminal OUT_n can be accelerated, thereby further improving the driving capability of the shift register unit and reducing leakage current, saving power consumption.

[0210] That is, in one embodiment, dual VGH and dual VGL power supply can be used. However, it is not limited to dual VGH and dual VGL power supply. Furthermore, in some embodiments, single VGH and single VGL power supply can also be used, meaning only one set of power lines, including a first power line VGH and a second power line VGL, is provided for connecting the various circuits in the shift register unit. In other words, any NOT gate in the shift register unit can be connected to the same first power line VGH and second power line VGL.

[0211] Optionally, at least three adjacent signal lines from the first clock line CB, the second clock line CKn, the third clock line CK, the fourth clock line CBn, the enable line EN, the reset control line Trst, and any set of power lines including the first power lines VGH1 / VGH2 and the second power lines VGL1 / VGL2 are arranged at equal intervals in the first direction. That is, the spacing between any two adjacent signal lines among the at least three adjacent signal lines can be a fixed spacing. For example, the fixed spacing can be greater than or equal to 3μm. For example, in some embodiments, the spacing between any two adjacent signal lines from the first clock line CB, the second clock line CKn, the third clock line CK, the fourth clock line CBn, the enable line EN, the reset control line Trst, the first power lines VGH1 / VGH2, and the second power lines VGL1 / VGL2 can be a fixed spacing.

[0212] Optionally, based on the foregoing description, the shift register unit provided in this application embodiment can actually be divided into three modules: an input shift module, a transmission and control module, and a drive enhancement module. The shift register unit may also include a voltage regulator capacitor C1. The input shift module may include a first transmission gate Tg1, a first NOR gate NOR1, a second transmission gate Tg2, and a first NOT gate INV1. The transmission and control module may include a second NOR gate NOR2 and a third transmission gate Tg3. The drive enhancement module may include a second NOT gate INV2, a third NOT gate INV3, and a fourth NOT gate INV4.

[0213] Furthermore, referring to Figures 4 and 7, it can be seen that, relative to the pixel's location, the input shifting module can be located at the very front of the layout (e.g., the far left), the driving enhancement module can be located at the very back of the layout (e.g., the far right), and the transmission and control module can be located between the input shifting module and the driving enhancement module. Also, the first NOR gate NOR1 in the input shifting module can be located at the far left. The first transmission gate Tg1, the second transmission gate Tg2, and the first NOT gate INV1 (i.e., the first group of circuits) in the input shifting module can be located on the side of the first NOR gate NOR1 closest to the pixel, and can be arranged sequentially from top to bottom, i.e., vertically. The second NOR gate NOR2 and the third transmission gate Tg3 in the transmission and control module can be located on the side of the first group of circuits closest to the pixel, and can be arranged sequentially from top to bottom, i.e., vertically. The second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4 in the driving enhancement module can be arranged sequentially from left to right towards the side closest to the pixel, i.e., horizontally. The voltage regulator capacitor C1 can be located around the third transmission gate Tg3 and the second NOT gate INV3. For example, the voltage regulator capacitor C1 can be located below the second NOT gate INV2, arranged sequentially from top to bottom with the second NOT gate INV2. In this way, wiring and transmission paths can be effectively reduced, minimizing the width of the shift register unit.

[0214] Of course, the above arrangement is only illustrative, and any arrangement that can achieve the above effect can be applied to the embodiments of this application. For example, in some embodiments, the second NOR gate NOR2 and the third transmission gate Tg3 in the transmission and control module can also be arranged horizontally. The second NOT gate INV2 and the third NOT gate INV3 can also be arranged vertically.

[0215] Optionally, referring to Figure 8, the first transmission gate Tg1 may include a first P-type transistor Tp_1 and a first N-type transistor Tn_1.

[0216] The gates of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can be connected to the first clock line CB and the second clock line CKn, respectively. The first terminals of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can both be connected to the input signal terminal IN_n. The second terminals of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 can both be connected to the input node Q_n.

[0217] Optionally, referring to Figure 8, the first NOR gate NOR1 may include: a second P-type transistor Tp_2, a second N-type transistor Tn_2, a third P-type transistor Tp_3, and a third N-type transistor Tn_3.

[0218] The gates of the second P-type transistor Tp_2 and the third N-type transistor Tn_3 can both be connected to the reset control line Trst. The first terminal of the second P-type transistor Tp_2 can be connected to the first power supply line VGH. The second terminal of the second P-type transistor Tp_2 can be connected to the first terminal of the third P-type transistor Tp_3. The second terminals of the third P-type transistor Tp_3, the second terminals of the second N-type transistor Tn_2, and the second terminals of the third N-type transistor Tn_3 can all be connected to the first intermediate node Q1_n. The first terminals of the second N-type transistor Tn_2 and the first terminals of the third N-type transistor Tn_3 can all be connected to the second power supply line VGL. The gates of the third P-type transistor Tp_3 and the second N-type transistor Tn_2 can both be connected to the input node Q_n.

[0219] Optionally, referring to Figure 8, the first NOT gate INV1 may include a fourth P-type transistor Tp_4 and a fourth N-type transistor Tn_4, and the fourth N-type transistor Tn_4 may be a dual-gate transistor.

[0220] The gates of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can both be connected to the first intermediate node Q1_n. The first terminals of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can be connected to the first power line VGH and the second power line VGL, respectively. The second terminals of the fourth P-type transistor Tp_4 and the fourth N-type transistor Tn_4 can both be connected to the second intermediate node Q2_n.

[0221] Understandably, by setting the fourth N-type transistor Tn_4 as a dual-gate transistor, leakage current during the output hold phase can be reduced, thereby reducing the power consumption of the shift register unit. Of course, other transistors can also be set as dual-gate transistors in the same way.

[0222] Optionally, referring to Figure 8, the second transmission gate Tg2 may include a fifth P-type transistor Tp_5 and a fifth N-type transistor Tn_5.

[0223] The gates of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can be connected to the third clock line CK and the fourth clock line CBn, respectively. The first terminals of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can both be connected to the first intermediate node Q1_n. The second terminals of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can both be connected to the input node Q_n.

[0224] Alternatively, referring to Figure 8, the third transmission gate Tg3 may include: a sixth P-type transistor Tp_6 and a sixth N-type transistor Tn_6.

[0225] The gates of the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6 can be connected to the first control terminal Con1 and the second control terminal Con2, respectively. The first terminals of the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6 can both be connected to the enable line EN (e.g., EN1). The second terminals of the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6 can both be connected to the other input terminal of the second NOR gate NOR2.

[0226] Alternatively, referring to Figure 8, the second NOR gate NOR2 may include: a seventh P-type transistor Tp_7, a seventh N-type transistor Tn_7, an eighth P-type transistor Tp_8, and an eighth N-type transistor Tn_8.

[0227] The gates of the seventh P-type transistor Tp_7 and the eighth N-type transistor Tn_8 can both be connected to the third transmission gate Tg3 (that is, the second terminals of the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6). The gates of the eighth P-type transistor Tp_8 and the seventh N-type transistor Tn_7 can both be connected to the second intermediate node Q2_n. The first terminal of the seventh P-type transistor Tp_7 can be connected to the first power supply line VGH. The second terminal of the seventh P-type transistor Tp_7 can be connected to the first terminal of the eighth P-type transistor Tp_8. The second terminals of the eighth P-type transistor Tp_8, the seventh N-type transistor Tn_7, and the eighth N-type transistor Tn_8 can all be connected to the input terminal of the second NOT gate INV2. The first terminals of the seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8 can all be connected to the second power supply line VGL.

[0228] Optionally, referring to Figure 8, the second NOT gate INV2 may include: a ninth P-type transistor Tp_9 and a ninth N-type transistor Tn_9. The third NOT gate INV3 may include: a tenth P-type transistor Tp_10 and a tenth N-type transistor Tn_10. The fourth NOT gate INV4 may include: an eleventh P-type transistor Tp_11 and an eleventh N-type transistor Tn_11.

[0229] The gates of the ninth P-type transistor Tp_9 and the ninth N-type transistor Tn_9 can both be connected to the output terminal of the second NOR gate NOR2 (i.e., the second terminals of the seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8). The gates of the tenth P-type transistor Tp_10 and the tenth N-type transistor Tn_10 can both be connected to the second terminals of the ninth P-type transistor Tp_9 and the ninth N-type transistor Tn_9. The gates of the eleventh P-type transistor Tp_11 and the eleventh N-type transistor Tn_11 can both be connected to the second terminals of the tenth P-type transistor Tp_10 and the tenth N-type transistor Tn_10. The second terminals of the eleventh P-type transistor Tp_11 and the eleventh N-type transistor Tn_11 can both be connected to the output signal terminal OUT_n. The first terminals of the ninth P-type transistor Tp_9, the tenth P-type transistor Tp_10, and the eleventh P-type transistor Tp_11 can all be connected to the first power supply line VGH. The first terminals of the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the eleventh N-type transistor Tn_11 can all be connected to the second power supply line VGL.

[0230] That is, the shift register unit provided in some embodiments of this application may include 11 PMOS TFTs, 11 NMOS TFTs (a total of 22 TFTs), and 1 capacitor. That is, the shift register unit provided in the embodiments of this application can be a 22T1C structure. Of course, it is not limited to a 22T1C structure. That is, the shift register unit provided in the embodiments of this application can be derived by combining and reducing basic modules.

[0231] Optionally, taking the structure shown in Figure 8 as an example, Figure 9 shows a layout schematic of one shift register unit. Based on Figure 9, Figures 10 to 17 show structural schematics of different films in the shift register unit. Figure 18 shows a layout schematic of another shift register unit. Based on Figure 18, Figures 19 to 25 show structural schematics of different films in the shift register unit. Figure 26 shows yet another layout schematic of a shift register unit. Based on Figure 26, Figures 27 to 33 show structural schematics of different films in the shift register unit. Figure 34 shows yet another layout schematic of a shift register unit. Based on Figure 34, Figures 35 to 39 show structural schematics of different films in the shift register unit. Furthermore, the layouts shown in Figures 9, 18, 26, and 34 are all layouts of two adjacent shift register units (e.g., the nth-level shift register unit GOAn and the (n+1)th-level shift register unit GOAn+1). Referring to Figures 9, 18, 26, and 34, it can be seen that:

[0232] The first P-type transistor Tp_1 and the first N-type transistor Tn_1 can be arranged along the first direction X1 and along the direction close to the second NOR gate NOR2 (e.g., arranged in sequence).

[0233] The third P-type transistor Tp_3 and the second P-type transistor Tp_2 can be arranged along the second direction Y1 (e.g., arranged sequentially) and connected in series. The second N-type transistor Tn_2 can be located on the side of the third P-type transistor Tp_3 away from the second P-type transistor Tp_2, and the second N-type transistor Tn_2 can be closer to the first transmission gate Tg1 relative to the third P-type transistor Tp_3. The third N-type transistor Tn_3 can be located on the side of the second P-type transistor Tp_2 away from the third P-type transistor Tp_3, and the third N-type transistor Tn_3 can be closer to the first NOT gate INV1 relative to the second P-type transistor Tp_2.

[0234] The fourth N-type transistor Tn_4 and the fourth P-type transistor Tp_4 can be arranged sequentially along the first direction X1 and along the direction close to the third transmission gate Tg3 (e.g., arranged sequentially).

[0235] The fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 can be arranged sequentially along the first direction X1 and along the direction close to the second NOR gate NOR2 (e.g., arranged sequentially).

[0236] The sixth N-type transistor Tn_6 and the sixth P-type transistor Tp_6 can be arranged along the first direction X1 and along the direction close to the voltage regulator capacitor C1 (e.g., arranged in sequence).

[0237] The eighth P-type transistor Tp_8 and the seventh N-type transistor Tn_7 can be arranged along the second direction Y1 and along the direction close to the third transmission gate Tg3 (e.g., arranged sequentially). The seventh P-type transistor Tp_7 and the eighth N-type transistor Tn_8 can be arranged along the second direction Y1 and along the direction close to the third transmission gate Tg3 (e.g., arranged sequentially). The seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8 can be arranged along the first direction X1 and along the direction close to the second NOT gate INV2 (e.g., arranged sequentially). The eighth P-type transistor Tp_8 and the seventh P-type transistor Tp_7 can be arranged along the first direction X1 and along the direction close to the second NOT gate INV2 (e.g., arranged sequentially).

[0238] The ninth P-type transistor Tp_9 and the ninth N-type transistor Tn_9 can be arranged along the second direction Y1 and in a direction close to the voltage regulator capacitor C1 (e.g., arranged sequentially). The tenth P-type transistor Tp_10 and the tenth N-type transistor Tn_10 can be arranged along the second direction Y1 (e.g., arranged sequentially), and the tenth N-type transistor Tn_10 can be closer to the voltage regulator capacitor C1 than the tenth P-type transistor Tp_10.

[0239] Referring to Figures 8 and 19, it can also be seen that, in one embodiment, the eleventh P-type transistor Tp_11 and the eleventh N-type transistor Tn_11 can be arranged along the first direction X1 and along the direction closer to the pixel (e.g., arranged sequentially).

[0240] Referring to Figures 26 and 34, it can be seen that in another embodiment: the eleventh P-type transistor Tp_11 and the eleventh N-type transistor Tn_11 can be arranged along the second direction Y1 (e.g., arranged sequentially), and the eleventh N-type transistor Tn_11 can be closer to the voltage regulator capacitor C1 than the eleventh P-type transistor Tp_11.

[0241] That is, as can be seen from Figures 9, 18, 26, and 34, in the embodiments of this application:

[0242] The first NOR gate NOR1 includes four TFTs that can be arranged vertically, with two P-type TFTs connected in series and two N-type TFTs located above and below the two P-type TFTs. The reset control line Trst can be located near the top of the first NOR gate NOR1 for connection.

[0243] Based on the vertical arrangement of the first transmission gate Tg1 and the second transmission gate Tg2, TFTs of the same type (i.e., of the same type: P-type or N-type) can be located on the same side and arranged vertically, while TFTs of different types can be arranged horizontally to facilitate connection between TFTs. The first clock line CB, the second clock line CKn, the third clock line CK, and the fourth clock line CBn can be located above and near the P-type TFT and the N-type TFT to facilitate connection between the first transmission gate Tg1 and the second transmission gate Tg2.

[0244] The first NOT gate INV1 can be located on the side of the second transmission gate Tg2 away from the first transmission gate Tg1, that is, below the other cascaded shift register units, to facilitate transmission to the next stage. Furthermore, the N-type TFTs and P-type TFTs can be arranged horizontally, and as mentioned earlier, the N-type TFTs can be a dual-gate design to reduce leakage current, thereby reducing the power consumption of the shift register unit.

[0245] Based on the vertical arrangement of the second NOR gate NOR2 and the third transmission gate Tg3, the orthogonal projection of the second NOR gate NOR2 onto the substrate 0000 can be square, and the two P-type TFTs in the second NOR gate NOR2 can be arranged horizontally, and can be placed in an L-shape as shown in Figure 8. The two N-type TFTs can be arranged horizontally, and can be placed parallel as shown in Figure 8. Here, the L-shape placement can mean that the active layers of the two P-type TFTs extend along the first direction X1 and the second direction Y1 respectively, and the parallel placement can mean that the active layers of the two N-type TFTs both extend along the same first direction X1. The same applies to other transistors. The enable line EN (e.g., EN1) can be located near the bottom of the third transmission gate Tg3 so that the third transmission gate Tg3 can be connected.

[0246] Furthermore, the drive enhancement circuit 05 includes three NOT gates, with the first NOT gate (i.e., the second NOT gate INV2), the second NOT gate (i.e., the third NOT gate INV3), and the last NOT gate (i.e., the fourth NOT gate INV4) arranged horizontally from left to right:

[0247] In one embodiment, as shown in Figures 9 and 18, the P-type TFTs and N-type TFTs in the second NOT gate INV2 can be arranged vertically; the P-type TFTs and N-type TFTs in the third NOT gate INV3 can be arranged vertically; and the P-type TFTs and N-type TFTs in the fourth NOT gate INV4 can be arranged horizontally.

[0248] In another embodiment, as shown in Figures 26 and 34, the P-type TFTs and N-type TFTs in the second NOT gate INV2 can be arranged vertically top to bottom; the P-type TFTs and N-type TFTs in the third NOT gate INV3 can be arranged vertically top to bottom; and the P-type TFTs and N-type TFTs in the fourth NOT gate INV4 can be arranged vertically top to bottom, with the vertical arrangement of each NOT gate being the same. Here, vertical arrangement means that the P-type TFTs and N-type TFTs are placed in the same position. For example, referring to Figures 26 and 34, it can be seen that in each NOT gate, the P-type TFT is on top and the N-type TFT is on the bottom. This not only achieves the purpose of making reasonable use of vertical space, thus facilitating the design of narrow bezels, but also ensures good uniformity of characteristics of the same type of transistors in the manufacturing process, thereby improving the display quality of the display panel. Of course, in some other embodiments, the arrangement of each NOT gate can be different, even if they are arranged vertically top to bottom. For example, some NOT gates have P-type TFTs on top and N-type TFTs on the bottom; while other NOT gates have P-type TFTs on the bottom and N-type TFTs on top.

[0249] Optionally, referring to Figure 9, it can also be seen that the transistors included in the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4 can be progressively larger in size. That is, corresponding to the drive enhancement circuit 05 described above, the sizes of the first NOT gate to the left and right last NOT gates can be progressively larger. Here, transistors can refer to P-type transistors and / or N-type transistors.

[0250] Understandably, the channel width of a transistor can characterize its size. Taking an N-type transistor as an example, the channel width of the transistor in the first NOT gate (i.e., the second NOT gate INV2) can be 2 to 15 μm; for example, the channel width of the transistor in the second NOT gate INV2 can be 8 μm. The channel width of the transistor in the second NOT gate (i.e., the third NOT gate INV3) can be approximately 1.5 to 10 times that of the transistor in the second NOT gate INV2; for example, the channel width of the transistor in the third NOT gate INV3 can be 30 μm. The channel width of the transistor in the last NOT gate (i.e., the fourth NOT gate INV4) can be the largest and can be determined by the load of the pixels it connects to. For example, the channel width of the transistor in the fourth NOT gate INV4 can be 100 μm to 300 μm.

[0251] Of course, the N-type transistors and P-type transistors in each NOT gate included in the drive enhancement circuit 05 can have the same or different dimensions, which can be determined by the mobility. For example, taking the last NOT gate, i.e. the fourth NOT gate INV4, as an example, the mobility of its included P-type transistor (i.e., the eleventh P-type transistor Tp_11) can be 1 / 3 of the mobility of the N-type transistor (i.e., the eleventh N-type transistor Tn_11), and correspondingly, the channel width of its included P-type transistor can be 1 / 3 of the channel width of its included N-type transistor.

[0252] Optionally, referring to Figure 9, the transistor size included in the second NOT gate INV2 is larger than the transistor size included in at least one of the circuits: the first NOR gate NOR1, the first transmission gate Tg1, the second transmission gate Tg2, the first NOT gate INV1, the second NOR gate NOR2, and the third transmission gate Tg3. For example, in some embodiments, the transistor size included in the second NOT gate INV2 can be larger than the transistor size included in any one of the circuits: the first NOR gate NOR1, the first transmission gate Tg1, the second transmission gate Tg2, the first NOT gate INV1, the second NOR gate NOR2, and the third transmission gate Tg3. That is, except for the NOT gates in the drive enhancement circuit 05, the transistor sizes in other gate circuits can be relatively small. For example, the transistors in other gate circuits can be equivalent to the size of a switching transistor, and the channel width can be between 2 and 10 μm.

[0253] It is understood that the layouts shown in Figures 9, 18, 26 and 34 are merely illustrative. Any adjustments made based on these layouts to facilitate the narrow bezel design of the display panel are applicable to the embodiments of this application, as long as the layout is reasonably arranged according to the available space.

[0254] Optionally, referring to Figures 9 to 39, the transistor in the shift register unit may include: a first active layer A1, a first gate metal layer GATE1, a second gate metal layer GATE2, a second active layer A2, a first source / drain metal layer SD1, and a second source / drain metal layer SD2 located on one side of the substrate 00.

[0255] The first active layer A1 can be used as the active layer of the P-type transistor in the shift register unit, and the second active layer A2 can be used as the active layer of the N-type transistor in the shift register unit.

[0256] Optionally, in some embodiments, the materials of the first active layer A1 and the second active layer A2 can be different. For example, the first active layer A1 can be made of low-temperature polysilicon (LTPS), and the second active layer A2 can be made of indium gallium zinc oxide (IGZO). Accordingly, the first active layer A1 can also be referred to as a Poly layer, and the second active layer A2 can also be referred to as an IGZO layer.

[0257] Alternatively, in some embodiments, the materials of the first active layer A1 and the second active layer A2 can be the same. For example, the materials of the first active layer A1 and the second active layer A2 can both be LTPS materials, and the material of the first active layer A1 can be a P-type LTPS material used for fabricating an active layer of a P-type transistor, while the material of the second active layer A2 can be an N-type LTPS material used for fabricating an active layer of an N-type transistor. Accordingly, both the first active layer A1 and the second active layer A2 can be referred to as poly layers.

[0258] Furthermore, when the materials of the first active layer A1 and the second active layer A2 are different, as shown in Figures 9, 18 and 26 and their corresponding film layer schematic diagrams, the first active layer A1 and the second active layer A2 can be located in different layers, and the first active layer A1, the first gate metal layer GATE1, the second gate metal layer GATE2, the second active layer A2, the first source / drain metal layer SD1 and the second source / drain metal layer SD2 can be stacked sequentially in the direction away from the substrate 00.

[0259] When the material of the first active layer A1 is the same as that of the second active layer A2, the first active layer A1 and the second active layer A2 can be located in the same layer, and can be stacked sequentially with the first gate metal layer GATE1, the second gate metal layer GATE2, the second active layer A2, the first source / drain metal layer SD1 and the second source / drain metal layer SD2 in a direction away from the substrate 00.

[0260] It is understandable that "being in the same layer" can refer to a layer structure formed by using the same film deposition process to create a film layer for a specific pattern, and then using the same mask to pattern this film layer in a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and formed through the same single patterning process. This can save manufacturing processes and costs, and can accelerate manufacturing efficiency.

[0261] In other words, when the materials of the first active layer A1 and the second active layer A2 are the same, only one active layer needs to be set to fabricate N-type and P-type transistors. This not only simplifies the film layers and saves costs, but also eliminates the need for the connection holes between the gates of the N-type and P-type transistors, thereby further reducing the bezel width of the display panel. For example, compared to the arrangement where the materials of the first active layer A1 and the second active layer A2 are different, the bezel width can be reduced by approximately 20 to 40 μm.

[0262] It is understandable that, when the first active layer A1 and the second active layer A2 are located on different layers, taking the fourth NOT gate INV4 as an example, since the size of the P-type transistor is generally smaller than the size of the N-type transistor, it can be seen from Figure 9 that in the fourth NOT gate INV4, the size of the active layer (i.e., the first active layer A1) of the P-type transistor (i.e., the eleventh P-type transistor Tp_11) can be smaller than the size of the active layer (i.e., the second active layer A2) of the N-type transistor (i.e., the eleventh N-type transistor Tn_11). Here, the size can refer to the area of ​​the orthogonal projection of the active layer onto the substrate 00. The sizes of the active layers of the P-type transistors and N-type transistors in other gate circuits are similar and will not be elaborated further.

[0263] Optionally, a first interlayer dielectric layer (ILD) and a second interlayer dielectric layer (EBB) may be further included between the third gate metal layer (GATE3) and the first source / drain metal layer (SD1). The first interlayer dielectric layer (ILD) may have multiple vias (K1) for overlapping of the films located on both sides of the ILD. The second interlayer dielectric layer (EBB) may have multiple vias (K2) for overlapping of the films located on both sides of the EBB. It is understood that the vias (K1) in the first interlayer dielectric layer (ILD) can be used for overlapping of the films between P-type transistors. The vias (K2) in the second interlayer dielectric layer (EBB) can be used for overlapping of the films between N-type transistors. Furthermore, a passivation layer (PVX) and a planarization layer (PLN) may be sequentially stacked between the first source / drain metal layer (SD1) and the second source / drain metal layer (SD2). The passivation layer (PVX) and the planarization layer (PLN) may have multiple third vias (K3) for overlapping of the films located on both sides of the passivation layer (PVX) and the planarization layer (PLN). Correspondingly, vias K1, K2, and K3 can also be referred to as connection vias. Furthermore, it is understood that when the first active layer A1 and the second active layer A2 are located on the same layer, the first interlayer dielectric layer ILD and the second interlayer dielectric layer EBB can also be located on the same layer. Accordingly, as described above, the number of connection vias can be reduced.

[0264] Optionally, in this embodiment, each connection via can be located away from the second source / drain metal layer SD2, thereby reducing the parasitic capacitance formed between the second source / drain metal layer SD2 and other metal layers (e.g., the first source / drain metal layer SD1). Furthermore, each connection via can be staggered, meaning their orthogonal projections on the substrate 00 do not overlap.

[0265] Optionally, in some embodiments, as shown in FIG18, at least a portion of the first source / drain metal layer SD1 can be reused with at least one of the first active layer A1, the first gate metal layer GATE1, and the second active layer A2 to reduce the overlap area between the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0266] That is, the first source-drain metal layer SD1 can be replaced by any layer on the side of the first source-drain metal layer SD1 away from the second source-drain metal layer SD2, thereby reducing the overlap area between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, and thus reducing the parasitic capacitance formed between the first source-drain metal layer SD1 and the second source-drain metal layer SD2, which is beneficial to further reduce the operating power consumption of the shift register unit. Of course, in some other embodiments, the same purpose can also be achieved by reducing some of the redundant vias and redundant first source-drain metal layers SD1.

[0267] Optionally, based on Figures 9 and 18: Comparing Figures 10 and 19, it can be seen that at position S1, the original redundant via can be removed, and the connection can be made directly through the first active layer A1 (i.e., the Poly layer) to reduce the parasitic capacitance on the first power line VGH1 connected above. Also, at position S2, the Poly layer can be reused to replace the first source / drain metal layer SD1 at that position, thereby effectively reducing the parasitic capacitance on the clock line CK / CB connected above. Comparing Figures 11 and 20, it can be seen that at position S3, the first gate metal layer GATE1 can be reused to replace the first source / drain metal layer SD1 at that position, thereby effectively reducing the parasitic capacitance on the first power line VGH1 connected above, and reducing the parasitic capacitance between the second source / drain metal layer SD2 and the first source / drain metal layer SD1. Comparing Figures 13 and 22, it can be seen that at position S4, the second active layer A2 (i.e., the IGZO layer) can be reused to replace the first source-drain metal layer SD1 at that position, thereby effectively reducing the parasitic capacitance on the enable line EN connected above. All the above examples can reduce the overlap area of ​​the first source-drain metal layer SD1 and the second source-drain metal layer SD2, thereby reducing parasitic capacitance and lowering the power consumption of the shift register unit.

[0268] As can be understood from Figure 8, position S1 can refer to the connection node between the second P-type transistor Tp_2 and the third P-type transistor Tp_3 in the first NOR gate NOR1. Position S2 can refer to the connection node between the first transmission gate Tg1 and the first NOT gate INV1, such as the location of the second intermediate node Q2_n. Position S3 can refer to the connection node between the eighth P-type transistor Tp_8 and the seventh N-type transistor Tn_7 in the second NOR gate NOR2. Position S4 can refer to the connection node between the second NOR gate NOR2 and the second NOT gate INV2.

[0269] It can also be understood that, compared to the structure shown in Figure 9, the structure shown in Figure 18, at position S2, can be considered as increasing the size of the first active layer Poly to reduce the area of ​​the first source / drain metal layer SD1. At position S3, it can be considered as increasing the size of the first gate metal layer GATE1 to reduce the area of ​​the first source / drain metal layer SD1. At position S4, it can be considered as increasing the size of the IGZO layer to reduce the area of ​​the first source / drain metal layer SD1. Of course, the above methods are all illustrative. In some embodiments, other film layers can also be reused as the first source / drain metal layer SD1 to reduce the overlap area between the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0270] Optionally, taking the structure shown in Figure 9 as an example, and referring to Figures 10 and 13, it can be seen that when the first active layer A1 and the second active layer A2 are located in different layers, based on the transistor arrangement of this application embodiment, the active layer of each transistor can also satisfy the following configuration:

[0271] The first active layer A1 (i.e., the Poly layer) of the second P-type transistor Tp_2 and the third P-type transistor Tp_3 can be a single unit (i.e., they can be shared); the first active layer A1 of the first P-type transistor Tp_1 and the fifth P-type transistor Tp_5 can be shared. The second active layer A2 (i.e., the IGZO layer) of the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5 can be shared; the second active layer A2 of the third N-type transistor Tn_3 and the fourth N-type transistor Tn_4 can be shared.

[0272] Optionally, taking the structure shown in Figure 34 as an example, and referring to Figures 34 and 35, it can be seen that when the first active layer A1 and the second active layer A2 are located on the same layer, based on the transistor arrangement of this application embodiment, the active layer of each transistor can also satisfy the following configuration:

[0273] The first active layer A1 (i.e., the Poly layer) of the second P-type transistor Tp_2 and the third P-type transistor Tp_3 can be shared; the active layers (including the first active layer A1 and the second active layer A2) of the first P-type transistor Tp_1, the fifth P-type transistor Tp_5, the first N-type transistor Tn_1, and the fifth N-type transistor Tn_5 can be shared; the active layers of the fourth N-type transistor Tn_4 and the fourth P-type transistor Tp_4 can be shared; the active layers of the eighth P-type transistor Tp_8, the seventh N-type transistor Tn_7, and the seventh P-type transistor Tp_7 can be shared; the active layers of the tenth P-type transistor Tp_10 and the tenth N-type transistor Tn_10 can be shared; the active layers of the eleventh P-type transistor Tp_11 and the eleventh N-type transistor Tn_11 can be shared.

[0274] In this way, the structure can be simplified and costs can be saved while still facilitating narrow bezel design. Of course, the arrangement of other film layers can be referred to the corresponding film layer structure diagram (e.g., the arrangement of the first gate metal layer GATE1 can be determined by referring to Figures 9 and 11), and will not be described in detail here.

[0275] Based on the above description, the shift register unit provided in this application embodiment can be a CMOS PGate GOA circuit (also called PGate GOA). PGate refers to the gate signal terminal connected to the P-type transistor in the pixel, and CMOS can refer to a circuit capable of outputting the required gate drive signal to both the P-type and N-type transistors in the pixel. The N-type transistors included in the shift register unit can be responsible for low-level output, and the P-type transistors can be responsible for high-level output. Furthermore, the CMOS PGate GOA has a compact and concentrated layout, which can help reduce the bezel width and improve driving capability and circuit stability. Also, the width of the gate drive signal output by the CMOS PGate GOA through the output signal terminal OUT_n is adjustable.

[0276] In summary, this application provides a shift register unit. The input control circuit controls the potential of the input node. The output control circuit controls the potential of the output signal terminal based on the potential of the input node, the enable signal provided by the enable line, and the reset control signal provided by the reset control line, so as to output a display drive signal to the pixel through the output signal terminal. Thus, by flexibly setting the enable signal, clock signal, and reset control signal, the shift register unit can output signals matching the P-type transistors and / or N-type transistors in the pixel. Furthermore, since the output control circuit and the input control circuit are arranged along a first direction and in a direction close to the pixel, and the signal lines connecting the output control circuit and the input control circuit are arranged along the first direction and in a direction close to the pixel, and all signal lines extend along a second direction intersecting the first direction, it also facilitates the narrow bezel design of the display device. This shift register unit has a simple structure and requires fewer signal lines.

[0277] This application provides a method for driving a shift register unit, which can be used to drive the shift register unit as described above. As shown in Figure 40, the method includes:

[0278] Step 4001: In response to the first scan command, provide a first clock signal to the first clock line, provide a second clock signal to the second clock line, provide a reset control signal to the reset control line, and provide an enable signal with a first potential to the enable line.

[0279] Step 4002: In response to the second scan command, provide a first clock signal to the first clock line, provide a second clock signal to the second clock line, provide a reset control signal to the reset control line, and provide an enable signal of the second potential to the enable line.

[0280] The first and second clock signals are used to drive the input control circuit to control the switching between the input signal terminal and the input node. The reset control signal and enable signal are used to drive the output control circuit to control the potential of the output signal terminal, so as to output a display drive signal to the pixel through the output signal terminal. For example, the refresh frequency indicated by the first scan command is greater than the refresh frequency indicated by the second scan command. That is, the refresh area indicated by the first scan command can be a high refresh rate area, and the refresh area indicated by the second scan command can be a low refresh rate area.

[0281] Optionally, taking the circuit structure shown in Figure 8 as an example, and outputting a gate drive signal to the P-type transistor in the pixel, Figure 41 shows a driving timing diagram of a shift register unit, including the timing of A. high refresh region and B. low refresh region.

[0282] First, referring to Figure 41, it can be seen that it shows four sets of clock signals. Furthermore, when the display panel is powered on or off, the reset control signal provided by the reset control line Trst can be set high, i.e., the potential of the reset control signal is controlled to be high, thereby controlling the potential of the output signal terminal OUT_n (e.g., GP_n) to be an invalid potential (e.g., high potential), thus resetting the output signal. In the high refresh rate region, the enable signal provided by the enable line EN (here referring to enable line EN1; the same applies to the following embodiments, and will not be repeated) can be set low, i.e., the potential of the enable signal is controlled to be low, so that the potential of the output signal of the second NOR gate NOR2 changes with the potential of the second intermediate node Q2_n (i.e., GPc_n), thus controlling the shift register unit to output normally. In the low refresh rate region, the enable signal provided by the enable line EN can be set high, i.e., the potential of the enable signal is controlled to be high, so that the potential of the output signal of the second NOR gate NOR2 can remain high and does not change with the potential of GPc_n. Furthermore, this allows the output signal terminal GP_n to remain at a low potential, thus ensuring that the potential of the display drive signal output to the pixel is invalid and the corresponding switch in the pixel is not turned on.

[0283] Secondly, referring to Figure 41, the driving principle of the shift register unit is explained as follows:

[0284] (1) In the first stage t01 of the high refresh region, a low-level first clock signal can be provided to the first clock line CB, and a high-level second clock signal can be provided to the second clock line CKn, so that the first transmission gate Tg1 is turned on. Then, the input signal terminal IN_n can be turned on with the input node Q_n, and the input signal terminal IN_n (that is, GPc_n-1) can output an input signal to the input node Q_n. At this time, the potential of the input signal can be high. In addition, a high-level reset control signal can be provided to the reset control line Trst, which can then control the potential of the first intermediate node Q1_n (that is, GNc_n) to be low after passing through the first NOR gate NOR1, and then control the potential of the second intermediate node Q2_n (that is, GPc_n) to be high after passing through the first NOT gate INV1. Based on this, the third transmission gate Tg3 can be turned off, thereby disconnecting the enable line EN from the second NOR gate NOR2. A low-level signal can be output via the second NOR gate NOR2. This low-level signal, after passing through the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4 in series, can make the output signal terminal OUT_n (i.e., GP_n) high. That is, in the first stage t01 of the high refresh rate region, the shift register unit can output a high-level gate drive signal via the output signal terminal GP_n. Furthermore, in this first stage t01, a high-level third clock signal can be provided to the third clock line CK, and a low-level fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to turn off, thereby disconnecting node GPc_n from the input node Q_n.

[0285] It is understandable that, as shown in Figure 41, in the third clock signal provided by the third clock line CK and the first clock signal provided by the first clock line CB, the pulse width of the low-potential pulse is smaller than that of the high-potential pulse, generally about 0 to 2 μs less than 1H, which can be flexibly selected according to the load RC. Based on this setting, the influence of clock delay can be eliminated, avoiding the risk of competition between the gate circuit (e.g., the first NOR gate NOR1) in the first output control sub-circuit 021 and the first NOT gate INV1 in the second output control sub-circuit 022 when the first transmission gate Tg1 and the second transmission gate Tg2 are simultaneously turned on during the input state switching, i.e., when the potential of the input signal provided by the input signal terminal IN_n changes.

[0286] (2) In the second stage t02 of the high refresh region, a high-level first clock signal can be provided to the first clock line CB, and a low-level second clock signal can be provided to the second clock line CKn, causing the first transmission gate Tg1 to turn off, thereby disconnecting the input signal terminal IN_n from the input node Q_n. Furthermore, a low-level third clock signal can be provided to the third clock line CK, and a high-level fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to turn on, thereby turning the second intermediate node Q2_n (i.e., GPc_n) on with the input node Q_n, thus latching the potential of the input node Q_n to the high potential of node GPc_n. In addition, a low-level reset control signal can be provided to the reset control line Trst, so after passing through the first NOR gate NOR1, the potential of the first intermediate node Q1_n (i.e., GNc_n) can be controlled to be low, and after passing through the first NOT gate INV1, the potential of node GPc_n can be controlled to be high. Based on this, the third transmission gate Tg3 can be turned off, thereby disconnecting the enable line EN from the second NOR gate NOR2. A low-level signal can be output via the second NOR gate NOR2. This low-level signal, after passing through the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4 in series, can make the output signal terminal OUT_n (i.e., GP_n) high. That is, in the second stage t02 of the high refresh rate region, the shift register unit can output a high-level gate drive signal via the output signal terminal GP_n.

[0287] (3) In the third stage t03 of the high refresh region, a low-level first clock signal can be provided to the first clock line CB, and a high-level second clock signal can be provided to the second clock line CKn, so that the first transmission gate Tg1 is turned on, thereby turning on the input signal terminal IN_n and the input node Q_n. The input signal terminal IN_n can output the input signal to the input node Q_n, and the potential of the input signal can be low at this time. In addition, a low-level reset control signal can be provided to the reset control line Trst, which can then control the potential of the first intermediate node Q1_n (i.e., GNc_n) to be high after passing through the first NOR gate NOR1, and then control the potential of the second intermediate node Q2_n (i.e., GPc_n) to be low after passing through the first NOT gate INV1. Based on this, the third transmission gate Tg3 can be turned on, thereby connecting the enable line EN to the second NOR gate NOR2. The second NOR gate NOR2 can output a high-level signal. This high-level signal, after passing through the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4 in series, can make the output signal terminal OUT_n (i.e., GP_n) low. That is, in the third stage t03 of the high refresh rate region, the shift register unit can output a low-level gate drive signal through the output signal terminal GP_n. Furthermore, in this third stage t03, a high-level third clock signal can be provided to the third clock line CK, and a low-level fourth clock signal can be provided to the fourth clock line CBn, causing the second transmission gate Tg2 to turn off, thereby disconnecting node GPc_n from the input node Q_n.

[0288] (4) In the low-brush region, since the enable signal remains at a high potential, as mentioned earlier, the output signal of the second NOR gate NOR2 can remain at a low potential. As shown in Figure 41, this low-potential signal, after being sequentially connected through the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4, can make the output signal terminal OUT_n (i.e., GP_n) at a high potential. The working principles of other stages are illustrated in the timing diagram shown in Figure 41 and will not be elaborated here.

[0289] Optionally, the shift register unit can also be connected to the display driver IC (DIC) and used to receive the aforementioned signals, such as clock signals, provided by the DIC. That is, the DIC can provide the required signals to the signal terminals connected to the shift register unit so that the shift register unit can output the required display driving signals to the pixels.

[0290] It is understandable that, since the driving method of the shift register unit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the driving method of the shift register unit will not be repeated here for the sake of brevity.

[0291] This application also provides a display driving circuit. As shown in FIG42, the display driving circuit includes: a plurality of cascaded shift register units (GOAs) as described above.

[0292] For example, the shift register unit GOA shown in Figure 42 provides the gate drive signal to the gate signal terminal Gate_P connected to the P-type transistor in the pixel. That is, the output terminal OUT_P is connected to the gate signal terminal Gate_P of the pixel. Correspondingly, the display driving circuit including this PGate GOA can also be called a gate driving circuit.

[0293] Furthermore, the display driver circuit shown in Figure 42 employs four sets of clock signals (including CK, CB, CKn, and CBn, a total of four clock lines), and is powered by dual VGH and dual VGL (including first power lines VGH1 and VGH2, and second power lines VGL1 and VGL2). The cascading configuration shown is as follows: the input IN_1 of the first-stage shift register unit PGate GOA is connected to the enable signal line STV, and the inputs of other-stage shift register units PGate GOA (e.g., IN_2, IN_n-1, and IN_n) are connected to the second intermediate node Q2_n (i.e., node GPc_n) of the previous-stage shift register unit PGate GOA.

[0294] It is understandable that, since the potential of node GNc_n is opposite to that of node GPc_n, for the first-stage shift register unit, an inverter F1, also known as a NOT gate, can be added between the enable signal line STV and node GNc_1 to receive a signal with a potential opposite to that of the enable signal. For the design of other structures, please refer to the relevant descriptions of the shift register unit mentioned above; they will not be elaborated upon here.

[0295] Optionally, in some embodiments, a dummy shift register unit, i.e., a dummy GOA, may be added to the first or last line to meet the required timing requirements or drive the load.

[0296] It is understood that since the display driving circuit can have essentially the same technical effect as the shift register unit described in the previous embodiments, the technical effect of the display driving circuit will not be described again here for the sake of brevity.

[0297] This application also provides a display device. As shown in FIG43, the display device includes: a display panel 100, and a display driving circuit 000 as shown in FIG42.

[0298] The display panel 100 includes multiple pixels arranged in an array (not shown in the figure), and the display driving circuit 000 is connected to the multiple pixels and is used to transmit display driving signals to the multiple pixels to drive the multiple pixels to emit light.

[0299] Optionally, based on Figure 43 and continuing to refer to Figure 44, it can be seen that the display driving circuit 000 may include: a P-type gate driving circuit for transmitting gate driving signals to P-type transistors in multiple pixels, an N-type gate driving circuit for transmitting gate driving signals to N-type transistors in multiple pixels, a reset driving circuit for transmitting reset signals to transistors in multiple pixels, and a light-emitting driving circuit for transmitting light-emitting control signals to transistors in multiple pixels.

[0300] Optionally, based on Figure 44, referring further to Figure 45, it can be seen that it schematically shows 2376 rows of pixels Pixel_1 to Pixel_2376. Furthermore, the driving architecture of each circuit shown satisfies:

[0301] The P-type gate driving circuit may include two sets of P-type gate driving circuits located on both sides of multiple rows of pixels in the pixel row direction. Each set of P-type gate driving circuits may include multiple cascaded shift register units (also called PGate GOA). Each set of P-type gate driving circuits may be connected one-to-one with multiple rows of pixels. That is, the P-type gate driving circuit can be bilaterally driven, and in each side of the P-type gate driving circuit, one level of PGate GOA can drive one level (i.e., one row) of pixels. Correspondingly, it can be seen that, based on 2376 rows of pixels Pixel_1 to Pixel_2376, each set of P-type gate driving circuits may include 2376 levels of PGate GOA1 to PGate GOA2376.

[0302] The illustrated N-type gate driving circuit can include two sets of N-type gate driving circuits located on both sides of multiple rows of pixels in the pixel row direction. Each set of N-type gate driving circuits can include multiple cascaded shift register units (also called NGate GOA). In each set of N-type gate driving circuits, one shift register unit can be connected to two adjacent rows of pixels, and different shift register units can be connected to different rows of pixels. That is, the N-type gate driving circuit can be bilaterally driven, and in each side of the N-type gate driving circuit, one level of NGate GOA can drive two levels (i.e., two rows) of pixels. Correspondingly, it can be seen that based on 2376 rows of pixels Pixel_1 to Pixel_2376, each set of N-type gate driving circuits can include 2376 / 2 = 1188 levels of NGate GOA1&2 to NGate GOA2375&2376.

[0303] The light-emitting driving circuit and reset driving circuit shown can be located on opposite sides of multiple rows of pixels in the pixel row direction. For example, referring to Figure 45, the light-emitting driving circuit is located on the right side, and the reset driving circuit is located on the left side. Both the light-emitting driving circuit and the reset driving circuit can each include multiple cascaded shift register units. In the multiple shift register units included in the light-emitting driving circuit, one shift register unit can be connected to two adjacent rows of pixels, and different shift register units can be connected to pixels in different rows. Similarly, in the multiple shift register units included in the reset driving circuit, one shift register unit can be connected to two adjacent rows of pixels, and different shift register units can be connected to pixels in different rows. The shift register units included in the light-emitting driving circuit can also be called EM GOA; the shift register units included in the reset driving circuit can also be called Reset GOA. Furthermore, since, as shown in Figure 2, the transistors connected to the Reset signal terminal are all P-type transistors, Reset GOA can also be called PRESET GOA. That is, both the light-emitting driving circuit and the reset driving circuit can be single-sided driving, and one level of EM GOA can drive two levels (i.e., two rows) of pixels, and one level of PRESET GOA can also drive two levels (i.e., two rows) of pixels. Correspondingly, it can be seen that based on 2376 rows of pixels Pixel_1 to Pixel_2376, the light-emitting driving circuit can include 2376 / 2 = 1188 levels of EM GOA1&2 to EM GOA2375&2376. The reset driving circuit can include 2376 / 2 = 1188 levels of PRESET GOA1&2 to PRESET GOA2375&2376. Furthermore, referring to Figure 2, it can be seen that for the first row of pixels, because the previous level shift register unit needs to provide a reset signal to the reset signal terminal Reset_P connected to transistor T1, an additional PRESET GOA0 needs to be connected to the first row of pixels to provide the required reset signal.

[0304] Optionally, the shift register unit described in the foregoing embodiments can be the P-type gate drive circuit therein. That is, the embodiments of this application can be layout design optimizations for PGate GOA. Referring to Figures 8 and 45, it can also be seen that the PGate GOA can be a 22T1C 4CLK structure (i.e., a structure including 22 transistors and 1 capacitor, and using 4 sets of clock signals). Furthermore, referring to Figure 45, it can also be seen that the NGate GOA can be a 24T1C 4CLK dual VGH / VGL structure. The PReset GOA can be a 16T1C CLK dual VGH / VGL structure. The EM GOA can be a CLK dual VGH / VGL structure. And, in some embodiments, as shown in Figure 45, on the left side of both sides in the pixel row direction, the PReset GOA, NGate GOA, and PGate GOA can be arranged sequentially along the direction closer to the pixel; on the right side of both sides in the pixel row direction, the EM GOA, NGate GOA, and PGate GOA can be arranged sequentially along the direction closer to the pixel. In this way, the space on the display panel can be used efficiently, resulting in a more compact layout, which further facilitates the narrow bezel design of the display panel.

[0305] Of course, the above-described driving architecture, circuit structure, and arrangement are merely illustrative. For example, in some other embodiments, the PGate GOA can also be designed as a single PGate GOA driving two levels (i.e., two rows) of pixels. The light-emitting driving circuit can also be designed as a dual-sided driving circuit. Regarding the circuit structure, the NGate GOA can also be a 22T1C 2CLK single VGH / VGL structure. As for the arrangement, taking the left side of the two sides in the pixel row direction as an example, the NGate GOA, PRESET GOA, and PGate GOA can also be arranged sequentially along the direction closest to the pixel.

[0306] Optionally, the display device can be any product or component with display functionality, such as an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, or any other display device. Furthermore, the display device can also be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-readers.

[0307] It is understood that since the display device can have essentially the same technical effect as the shift register unit described in the various embodiments above, the technical effect of the display device will not be described again here for the sake of brevity.

[0308] It is understood that the terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0309] For example, the use of words such as "first," "second," "third," and similar terms does not indicate any order, quantity, or importance, but is merely used to distinguish different components.

[0310] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0311] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0312] The word “connection” or “link” is not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0313] "Up," "down," "left," and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0314] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0315] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

A shift register unit, the shift register unit comprising: An input control circuit is connected to a first clock line, a second clock line, an input signal terminal, and an input node, respectively, and is used to control the connection and disconnection of the input signal terminal and the input node in response to a first clock signal provided by the first clock line and a second clock signal provided by the second clock line. An output control circuit is connected to the input node, reset control line, enable line, and output signal terminal respectively, and is used to control the potential of the output signal terminal based on the potential of the input node, the enable signal provided by the enable line, and the reset control signal provided by the reset control line. Furthermore, the output control circuit and the input control circuit are arranged along the first direction and in the direction closer to the pixel; The reset control line, the first clock line, the second clock line, and the enable line are arranged along the first direction and in a direction close to the pixel, and extend along the second direction; wherein the second direction intersects the first direction. According to claim 1, the shift register unit, wherein, The output control circuit includes: The first output control sub-circuit is connected to the input node, the reset control line and the first intermediate node respectively, and is used to control the potential of the first intermediate node based on the potential of the input node and the reset control signal; The second output control sub-circuit is connected to the first intermediate node and the second intermediate node respectively, and is used to control the potential of the second intermediate node based on the potential of the first intermediate node. The third output control sub-circuit is connected to the second intermediate node, the enable line and the output signal terminal respectively, and is used to control the potential of the output signal terminal based on the potential of the second intermediate node and the enable signal. Furthermore, the first output control sub-circuit and the input control circuit in the output control circuit are arranged along the first direction and in a direction close to the pixel; Furthermore, the first output control sub-circuit, the second output control sub-circuit, and the third output control sub-circuit are arranged along the first direction and in a direction close to the pixel; the second output control sub-circuit and the input control circuit are arranged along the second direction. According to claim 2, the shift register unit, wherein, The shift register unit also includes include: A latching circuit is connected to the third clock line, the fourth clock line, the second intermediate node, and the input node, respectively, and is used to control the on / off state of the second intermediate node and the input node in response to the third clock signal provided by the third clock line and the fourth clock signal provided by the fourth clock line. The potential of the second intermediate node is opposite to the potential of the first intermediate node. A switch control circuit is connected between the enable line and the third output control sub-circuit, and is also connected to the first control terminal and the second control terminal respectively. It is used to control the on / off state of the enable line and the third output control sub-circuit in response to the first control signal provided by the first control terminal and the second control signal provided by the second control terminal. A drive enhancement circuit is connected between the third output control sub-circuit and the output signal terminal, and is used to invert the potential of the output signal of the third output control sub-circuit at least once before outputting it to the output signal terminal. Furthermore, the latch circuit, the switch control circuit, and the drive enhancement circuit are arranged along the first direction and in a direction close to the pixel; the latch circuit and the input control circuit are arranged along the second direction and located between the input control circuit and the second output control sub-circuit; the switch control circuit and the third output control sub-circuit are arranged along the second direction. The third clock line and the fourth clock line are located between the reset control line and the enable line, and are arranged along the first direction and along the direction close to the pixel, and extend along the second direction. According to claim 3, the shift register unit, wherein, The input control circuit includes: a first transmission gate; the first output control sub-circuit includes: a first NOR gate; the second output control sub-circuit includes: a first NOT gate; the third output control sub-circuit includes: a second NOR gate; the latch circuit includes: a second transmission gate; the switch control circuit includes: a third transmission gate; the drive enhancement circuit includes: a second NOT gate, a third NOT gate, and a fourth NOT gate connected in series. The first transmission gate is connected between the input signal terminal and the input node, and is also connected to the first clock line and the second clock line respectively; the two input terminals of the first NOR gate are connected to the reset control line and the input node respectively, and the output terminal of the first NOR gate is connected to the first intermediate node; the input terminal of the first NOT gate is connected to the first intermediate node, and the output terminal of the first NOT gate is connected to the second intermediate node; of the two input terminals of the second NOR gate, one input terminal is connected to the second intermediate node, and the other input terminal is connected to the enable gate through the third transmission gate. The shift register unit is further connected to the input node and the second control terminal, respectively. The output terminal of the second NOR gate is connected to the output signal terminal through the second NOT gate, the third NOT gate, and the fourth NOT gate connected in series. The second transmission gate is connected between the second intermediate node and the input node, and is also connected to the third clock line and the fourth clock line, respectively. The shift register unit also includes a voltage regulator capacitor connected between the ground terminal and another input terminal of the second NOR gate. Furthermore, the first NOR gate comprises a first group of circuits including the first transmission gate, the second transmission gate, and the first NOT gate; a second group of circuits including the second NOR gate and the third transmission gate; and a third group of circuits including the second NOT gate and the voltage-stabilizing capacitor. The third NOT gate and the fourth NOT gate are arranged along the first direction and in a direction close to the pixel. In the first group of circuits, the first transmission gate, the second transmission gate, and the first NOT gate are arranged along the second direction. In the second group of circuits, the second NOR gate and the third transmission gate are arranged along the second direction, and the third transmission gate is farther away from the first transmission gate relative to the second NOR gate. In the third group of circuits, the second NOT gate and the voltage-stabilizing capacitor are arranged along the second direction, and the voltage-stabilizing capacitor is farther away from the second NOR gate relative to the second NOT gate. The shift register unit according to claim 4, wherein, The shift register unit is located on the substrate and along the second direction: At least two of the following circuits on the substrate have equal lengths in their orthogonal projections: the first NOR gate, the first group of circuits, the second group of circuits, the third group of circuits, the third NOT gate, and the fourth NOT gate. And / or, the lengths of the second NOR gate and the orthogonal projection of the second NOT gate onto the substrate are equal; And / or, at least two of the circuits in the first transmission gate, the second transmission gate, the first NOT gate, the third transmission gate, and the voltage regulator capacitor have equal lengths of their orthogonal projections onto the substrate. The shift register unit according to claim 4 or 5, wherein, The shift register unit is located on the substrate and along the first direction: In the first group of circuits, at least two of the circuits among the first transmission gate, the second transmission gate, and the first NOT gate have equal widths in their orthographic projections onto the substrate; And / or, in the second set of circuits, the width of the orthogonal projection of the second NOR gate and the third transmission gate onto the substrate is equal; And / or, in the third set of circuits, the width of the second NOT gate is equal to the width of the orthogonal projection of the Zener capacitor onto the substrate. The shift register unit according to any one of claims 4 to 6, wherein, The first NOR gate, the second NOR gate, the first NOT gate, the second NOT gate, and the third NOT gate are connected to the first set of power lines and are used to operate based on the power signal provided by the first set of power lines; the fourth NOT gate is connected to the second set of power lines and is used to operate based on the power signal provided by the second set of power lines. Among them, in the first group of power lines and the second group of power lines, each group of power lines includes a first power line and a second power line with different potentials of the provided power signals. The first power line and the second power line included in the first group of power lines are located on both sides of at least one of the enable line and the reset control line in the first direction, and the first power line and the second power line included in any group of power lines extend along the second direction. Along the first direction, at least the width of the first power line and the width of the second power line included in the second group of power lines are both greater than the width of the reset control line and both are greater than the width of the enable line; and the width of the first power line included in the second group of power lines is greater than the width of the first power line included in the first group of power lines, and the width of the second power line included in the second group of power lines is greater than the width of the second power line included in the first group of power lines. The shift register unit according to claim 7, wherein, The first clock line, the second clock line, the third clock line, the fourth clock line, the enable line, the reset control line, and at least three adjacent signal lines from the first power line and the second power line included in any set of power lines are arranged at equal intervals in the first direction. The shift register unit according to any one of claims 4 to 8, wherein, The first transmission gate includes: a first P-type transistor and a first N-type transistor; The gate of the first P-type transistor and the gate of the first N-type transistor are respectively connected to the first clock line and the second clock line. The first terminal of the first P-type transistor and the first terminal of the first N-type transistor are both connected to the input signal terminal. The second terminal of the first P-type transistor and the second terminal of the first N-type transistor are both connected to the input node. Furthermore, the first P-type transistor and the first N-type transistor are along the first direction and adjacent to each other. Arranged in the direction closest to the second NOR gate. The shift register unit according to any one of claims 4 to 9, wherein, The first NOR gate includes: a second P-type transistor, a second N-type transistor, a third P-type transistor, and a third N-type transistor; The gates of the second P-type transistor and the third N-type transistor are both connected to the reset control line. The first terminal of the second P-type transistor is connected to the first power supply line. The second terminal of the second P-type transistor is connected to the first terminal of the third P-type transistor. The second terminals of the third P-type transistor, the second terminals of the second N-type transistor, and the second terminals of the third N-type transistor are all connected to the first intermediate node. The first terminals of the second N-type transistor and the first terminals of the third N-type transistor are all connected to the second power supply line. The gates of the third P-type transistor and the second N-type transistor are both connected to the input node. Furthermore, the third P-type transistor and the second P-type transistor are arranged and connected in series along the second direction; the second N-type transistor is located on the side of the third P-type transistor away from the second P-type transistor, and the second N-type transistor is closer to the first transmission gate relative to the third P-type transistor; the third N-type transistor is located on the side of the second P-type transistor away from the third P-type transistor, and the third N-type transistor is closer to the first NOT gate relative to the second P-type transistor. The shift register unit according to any one of claims 4 to 10, wherein, The first NOT gate includes a fourth P-type transistor and a fourth N-type transistor, wherein the fourth N-type transistor is a dual-gate transistor; The gate of the fourth P-type transistor and the gate of the fourth N-type transistor are both connected to the first intermediate node. The first terminal of the fourth P-type transistor and the first terminal of the fourth N-type transistor are respectively connected to the first power line and the second power line. The second terminal of the fourth P-type transistor and the second terminal of the fourth N-type transistor are both connected to the second intermediate node. Furthermore, the fourth N-type transistor and the fourth P-type transistor are arranged along the first direction and in a direction close to the third transmission gate. The shift register unit according to any one of claims 4 to 11, wherein, The second transmission gate includes: a fifth P-type transistor and a fifth N-type transistor; The gate of the fifth P-type transistor and the gate of the fifth N-type transistor are respectively connected to the third clock line and the fourth clock line. The first terminal of the fifth P-type transistor and the first terminal of the fifth N-type transistor are both connected to the first intermediate node. The second terminal of the fifth P-type transistor and the second terminal of the fifth N-type transistor are both connected to the input node. Furthermore, the fifth P-type transistor and the fifth N-type transistor are arranged along the first direction and in a direction close to the second NOR gate. The shift register unit according to any one of claims 4 to 12, wherein, The third transmission gate includes: a sixth P-type transistor and a sixth N-type transistor; The gate of the sixth P-type transistor and the gate of the sixth N-type transistor are respectively connected to the first control terminal and the second control terminal. The first terminal of the sixth P-type transistor and the first terminal of the sixth N-type transistor are both connected to the enable line. The second terminal of the sixth P-type transistor and the second terminal of the sixth N-type transistor are both connected to the other input terminal of the second NOR gate. Furthermore, the sixth N-type transistor and the sixth P-type transistor are arranged along the first direction and in a direction close to the voltage regulator capacitor. The shift register unit according to any one of claims 4 to 13, wherein, The second NOR gate includes: a seventh P-type transistor, a seventh N-type transistor, an eighth P-type transistor, and an eighth N-type transistor; The gates of the seventh P-type transistor and the eighth N-type transistor are both connected to the third transmission gate. The gates of the eighth P-type transistor and the seventh N-type transistor are both connected to the second intermediate node. The first terminal of the seventh P-type transistor is connected to the first power supply line. The second terminal of the seventh P-type transistor is connected to the first terminal of the eighth P-type transistor. The second terminals of the eighth P-type transistor, the seventh N-type transistor, and the eighth N-type transistor are all connected to the input terminal of the second NOT gate. The first terminals of the seventh N-type transistor and the eighth N-type transistor are both connected to the second power supply line. Furthermore, the eighth P-type transistor and the seventh N-type transistor are arranged along the second direction and in a direction close to the third transmission gate; the seventh P-type transistor and the eighth N-type transistor are arranged along the second direction and in a direction close to the third transmission gate; the seventh N-type transistor and the eighth N-type transistor are arranged along the first direction and in a direction close to the second NOT gate. The eight P-type transistors and the seventh P-type transistor are arranged along the first direction and in a direction close to the second NOT gate. The shift register unit according to any one of claims 4 to 14, wherein, The second NOT gate includes: a ninth P-type transistor and a ninth N-type transistor; the third NOT gate includes: a tenth P-type transistor and a tenth N-type transistor; the fourth NOT gate includes: an eleventh P-type transistor and an eleventh N-type transistor; The gates of the ninth P-type transistor and the ninth N-type transistor are both connected to the output terminal of the second NOR gate. The gates of the tenth P-type transistor and the tenth N-type transistor are both connected to the second terminals of the ninth P-type transistor and the ninth N-type transistor. The gates of the eleventh P-type transistor and the eleventh N-type transistor are both connected to the second terminals of the tenth P-type transistor and the tenth N-type transistor. The second terminals of the eleventh P-type transistor and the eleventh N-type transistor are both connected to the output signal terminal. The first terminals of the ninth P-type transistor, the tenth P-type transistor, and the eleventh P-type transistor are all connected to the first power supply line. The first terminals of the ninth N-type transistor, the tenth N-type transistor, and the eleventh N-type transistor are all connected to the second power supply line. Furthermore, the ninth P-type transistor and the ninth N-type transistor are arranged along the second direction and in a direction close to the voltage regulator capacitor; the tenth P-type transistor and the tenth N-type transistor are arranged along the second direction, and the tenth N-type transistor is closer to the voltage regulator capacitor relative to the tenth P-type transistor; the eleventh P-type transistor and the eleventh N-type transistor are arranged along the first direction and in a direction close to the pixel, or the eleventh P-type transistor and the eleventh N-type transistor are arranged along the second direction, and the eleventh N-type transistor is closer to the voltage regulator capacitor relative to the eleventh P-type transistor. The shift register unit according to any one of claims 4 to 15, wherein, The transistors included in the second NOT gate, the third NOT gate, and the fourth NOT gate have progressively larger sizes, and the transistor included in the second NOT gate has a larger size than the transistor included in at least one of the circuits of the first NOR gate, the first transmission gate, the second transmission gate, the first NOT gate, the second NOR gate, and the third transmission gate. The shift register unit according to any one of claims 1 to 16, wherein, The transistor in the shift register unit includes: a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a first source-drain metal layer, and a second source-drain metal layer located on one side of the substrate. The first active layer is used as the active layer of the P-type transistor in the shift register unit, and the second active layer is used as the active layer of the N-type transistor in the shift register unit. Furthermore, when the materials of the first active layer and the second active layer are different, the first active layer and the second active layer are located in different layers, and the first active layer, the first gate metal layer, the second gate metal layer, the second active layer, the first source / drain metal layer and the second source / drain metal layer are stacked sequentially in a direction away from the substrate. When the material of the first active layer is the same as that of the second active layer, the first active layer and the second active layer are located in the same layer and are stacked sequentially with the first gate metal layer, the second gate metal layer, the second active layer, the first source / drain metal layer and the second source / drain metal layer in a direction away from the substrate. The shift register unit according to claim 17, wherein, At least a portion of the first source / drain metal layer is reused with at least one of the first active layer, the first gate metal layer, and the second active layer to reduce the overlap area between the first source / drain metal layer and the second source / drain metal layer. A display driving circuit, the display driving circuit comprising: A cascaded plurality of shift register units as described in any one of claims 1 to 18. A display device, the display device comprising: The display panel, and the display driving circuit as described in claim 19; The display panel includes multiple pixels arranged in an array. The display driving circuit is connected to the multiple pixels and is used to transmit display driving signals to the multiple pixels to drive the multiple pixels to emit light. The display device according to claim 20, wherein, The display driving circuit includes: a P-type gate driving circuit for transmitting gate driving signals to P-type transistors in the plurality of pixels; an N-type gate driving circuit for transmitting gate driving signals to N-type transistors in the plurality of pixels; a reset driving circuit for transmitting reset signals to transistors in the plurality of pixels; and a reset driving circuit for transmitting gate driving signals to the plurality of pixels. A light-emitting drive circuit in which transistors in each pixel transmit light-emitting control signals; Furthermore, the P-type gate driving circuit includes two sets of P-type gate driving circuits located on both sides of the multi-row pixels in the pixel row direction. Each set of the P-type gate driving circuits includes multiple cascaded shift register units, and the multiple shift register units included in each set of the P-type gate driving circuits are connected one-to-one with the multi-row pixels. The N-type gate driving circuit includes two sets of N-type gate driving circuits located on both sides of the multiple rows of pixels in the pixel row direction. Each set of N-type gate driving circuits includes multiple cascaded shift register units. Among the multiple shift register units included in each set of N-type gate driving circuits, one shift register unit is connected to two adjacent rows of pixels, and different shift register units are connected to different rows of pixels. The light-emitting driving circuit and the reset driving circuit are respectively located on both sides of the multiple rows of pixels in the direction of the pixel rows. The light-emitting driving circuit and the reset driving circuit each include multiple cascaded shift register units. Among the multiple shift register units included in the light-emitting driving circuit, one shift register unit is connected to two adjacent rows of pixels, and different shift register units are connected to pixels in different rows. Among the multiple shift register units included in the reset driving circuit, one shift register unit is connected to two adjacent rows of pixels, and different shift register units are connected to pixels in different rows.

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