Source driving circuit, display panel, display device and driving method

Abstract

A source driving circuit, a display panel, a display device and a driving method, comprising: a first input sub-circuit (301), a second input sub-circuit (302), a node control sub-circuit (303) and an output sub-circuit (304), the first input sub-circuit (301) comprising a first input sub-unit (3011), a second input sub-unit (3012) and a third input sub-unit (3013), the first input subunit (3011) provides a scanning start signal to a first node (N1) and provides a signal of a first reference signal end (VGH) to a second node (N2), the second input subunit (3012) provides a signal of the first reference signal end (VGH) to the second node (N2), and the third input subunit (3013) provides a signal of a third control signal end (SW3) to the second node (N2). And the second input sub-circuit (302) provides the signal of the second control signal end (SW2) to the third node (N3), so that the local refreshing of the middle column of the display panel can be realized, and the power consumption is saved.

Description

Source drive circuit, display panel, display device and driving method

[0001] This application claims priority to PCT patent application filed on August 30, 2024, with application number PCT / CN2024 / 115895 and entitled "A source driving circuit, display panel, display device and driving method", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a source driving circuit, display panel, display device, and driving method. Background Technology

[0003] Currently, existing display panels need to initialize and write the data voltage of all pixels within one frame when updating the screen. However, in certain special screen conditions (such as static screens, screens with infrequent updates, and screens that only require updating a few columns), the data voltage of most pixels on the screen does not need to be updated. In this case, the original display brightness can be maintained by low-leakage transistors. Repeatedly writing and updating these pixels results in some wasted power consumption. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a source drive circuit, a display panel, a display device, and a driving method to reduce the power consumption of the display panel during the display process.

[0006] On one hand, embodiments of this disclosure provide a source drive circuit, including: a first input sub-circuit, a second input sub-circuit, a node control sub-circuit, and an output sub-circuit, wherein the first input sub-circuit includes a first input sub-unit, a second input sub-unit, and a third input sub-unit;

[0007] The first input subunit is configured to provide a scan start signal from the data signal to a first node and a signal from a first reference signal to a second node in response to an effective voltage signal in the signal of the first control signal terminal, and to provide the scan start signal from the data signal terminal to the first node in response to an effective voltage signal in the signal of the first control signal terminal within one frame display time, wherein the signal of the first control signal terminal includes one effective voltage signal and the signal of the data signal terminal includes a scan start signal and a data voltage signal that appear sequentially.

[0008] The second input subunit is configured to provide the signal from the first reference signal terminal to the second node in response to the signal from the pull-up node and the signal from the second control signal terminal;

[0009] The third input subunit is configured to provide a signal from the third control signal terminal to the second node in response to a signal from the first node.

[0010] The second input sub-circuit is configured to provide the signal from the second control signal terminal to the third node in response to the signal from the first clock signal terminal;

[0011] The node control subcircuit is configured to control the signals of the pull-up node and the pull-down node based on the signals of the second node and the third node;

[0012] The output sub-circuit is configured to provide a signal from the first reference signal terminal to the drive output terminal in response to a signal from the pull-up node; and to provide a signal from the second reference signal terminal to the drive output terminal in response to a signal from the pull-down node.

[0013] On the other hand, embodiments of this disclosure also provide a display panel, including:

[0014] The display area includes multiple sub-pixels, multiple column refresh lines, and multiple data lines. Each sub-pixel includes a light-emitting device and a pixel driving circuit connected to the light-emitting device. One column refresh line is connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels, and one data line is connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels.

[0015] The non-display area includes multiple source control lines and multiple source drive circuits as described in any embodiment of this disclosure. The multiple source control lines include a first source control line and a second source control line, or a first source control line, a second source control line, and a third source control line. The drive output terminal of one of the multiple source drive circuits is connected to one of the multiple column refresh lines. The data signal terminal of one of the multiple source drive circuits is connected to one of the multiple data lines. The first control signal terminal of one of the multiple source drive circuits is connected to one of the first source control lines. The second control signal terminal of one of the multiple source drive circuits is connected to one of the second source control lines. The third control signal terminal of one of the multiple source drive circuits is connected to one of the second or third source control lines.

[0016] On the other hand, this disclosure also provides a display device, including: a display panel as described above and at least one source chip;

[0017] The source chip is coupled to at least some of the data lines and at least some of the source control lines of the display panel. The source chip is configured to sequentially output a scan start signal and a data voltage signal to the data lines connected to it within one frame display time, and to output an effective voltage signal to the first source control line, and to output corresponding control signals to the second source control line, or the second source control line and the third source control line.

[0018] On the other hand, embodiments of this disclosure also provide a first driving method applied to the source driving circuit of any of the above, comprising:

[0019] The first input sub-unit, in response to the effective voltage signal in the signal of the first control signal terminal, provides the first scan start signal in the signal of the data signal terminal to the first node and provides the signal of the first reference signal terminal to the second node; the second input sub-circuit, in response to the signal of the first clock signal terminal, provides the invalid level signal in the signal of the second control signal terminal to the third node; the node control sub-circuit controls the signals of the pull-up node and the pull-down node to be in a sustain state according to the signals of the second node and the third node;

[0020] The second input sub-unit, in response to the signal from the pull-up node and the signal from the second control signal terminal, provides the signal from the first reference signal terminal to the second node; the second input sub-circuit, in response to the signal from the first clock signal terminal, provides the valid level signal from the signal from the second control signal terminal to the third node; the node control sub-circuit controls the signal from the pull-up node to be in a valid state according to the signals from the second node and the third node; and the output sub-circuit, in response to the signal from the pull-up node, provides the signal from the first reference signal terminal to the drive output terminal.

[0021] On the other hand, embodiments of this disclosure also provide a second driving method applied to the source drive circuit of any of the above, comprising:

[0022] The first input sub-unit, in response to the effective voltage signal in the signal of the first control signal terminal, provides the second scan start signal in the signal of the data signal terminal to the first node and provides the signal of the first reference signal terminal to the second node; the second input sub-circuit, in response to the signal of the first clock signal terminal, provides the invalid level signal in the signal of the second control signal terminal to the third node; the node control sub-circuit controls the signals of the pull-up node and the pull-down node to be in a sustain state according to the signals of the second node and the third node;

[0023] The third input sub-unit responds to the signal of the first node by providing the signal of the third control signal terminal to the second node; the node control sub-circuit controls the signal of the pull-down node to be in an active state according to the signal of the second node; and the output sub-circuit responds to the signal of the pull-down node by providing the signal of the second reference signal terminal to the drive output terminal.

[0024] In summary, this disclosure provides a source driving circuit, a display panel, a display device, and a driving method. The source driving circuit includes a first input sub-circuit, a second input sub-circuit, a node control sub-circuit, and an output sub-circuit. The first input sub-circuit includes a first input sub-unit, a second input sub-unit, and a third input sub-unit. The first input sub-unit is configured to, in response to an effective voltage signal in a signal at a first control signal terminal, provide a first scan start signal in a signal at a data signal terminal to a first node and provide a signal at a first reference signal terminal to a second node. During one frame of display time, the signal at the first control signal terminal includes one effective voltage signal, and the signal at the data signal terminal includes a scan start signal and a data voltage signal appearing sequentially. The second input sub-unit is configured to, in response to a signal from a pull-up node and a second... The control signal terminal provides the first reference signal terminal signal to the second node; the third input sub-unit is configured to provide the third control signal terminal signal to the second node in response to the first node signal; the second input sub-circuit is configured to provide the second control signal terminal signal to the third node in response to the first clock signal terminal signal; the node control sub-circuit is configured to control the signals of the pull-up node and pull-down node according to the signals of the second node and the third node; the output sub-circuit is configured to provide the first reference signal terminal signal to the drive output terminal in response to the pull-up node signal, and to provide the second reference signal terminal signal to the drive output terminal in response to the pull-down node signal. Through the above source drive circuit settings, partial refresh of some columns in the display panel can be realized, thereby saving power consumption while ensuring display effect.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0026] Overview of the attached figures

[0027] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0028] Figure 1 is an equivalent circuit diagram of a pixel driving circuit in an embodiment of this disclosure;

[0029] Figure 2 is a schematic diagram of the driving timing of a pixel driving circuit for bidirectional row and column control in an embodiment of this disclosure;

[0030] Figure 3 is a schematic diagram of the structure of the first source drive circuit in the embodiment of this disclosure;

[0031] Figure 4 is a schematic diagram of the structure of the second type of source drive circuit in the embodiment of this disclosure;

[0032] Figure 5 is an equivalent circuit diagram of the first source drive circuit in the embodiments of this disclosure;

[0033] Figure 6 is a schematic diagram of the third type of source drive circuit in the embodiments of this disclosure;

[0034] Figure 7 is an equivalent circuit diagram of the second type of source drive circuit in the embodiments of this disclosure;

[0035] Figure 8 is a schematic diagram of the fourth source drive circuit in the embodiments of this disclosure;

[0036] Figure 9 is an equivalent circuit diagram of the third source drive circuit in the embodiments of this disclosure;

[0037] Figure 10 is a schematic diagram of the fifth source drive circuit in the embodiments of this disclosure;

[0038] Figure 11 is an equivalent circuit diagram of the fourth source drive circuit in the embodiments of this disclosure;

[0039] Figure 12 is an equivalent circuit diagram of the fifth source drive circuit in the embodiments of this disclosure;

[0040] Figure 13 is an equivalent circuit diagram of the sixth source drive circuit in the embodiments of this disclosure;

[0041] Figure 14 is an equivalent circuit diagram of the seventh source drive circuit in the embodiments of this disclosure;

[0042] Figure 15 is an equivalent circuit diagram of the eighth source drive circuit in the embodiments of this disclosure;

[0043] Figure 16 is a timing diagram of a source drive circuit according to an embodiment of the present disclosure;

[0044] Figure 17 is a first simulation waveform diagram of a source drive circuit in an embodiment of this disclosure;

[0045] Figure 18 is a timing diagram of another source drive circuit in an embodiment of this disclosure;

[0046] Figure 19 is a second simulation waveform diagram of a source drive circuit according to an embodiment of the present disclosure;

[0047] Figure 20 is a schematic diagram of the connection of a display panel according to an embodiment of the present disclosure;

[0048] Figure 21 is a connection diagram of a display device according to an embodiment of the present disclosure;

[0049] Figure 22 is a connection diagram of another display device in an embodiment of this disclosure;

[0050] Figure 23 is a flowchart illustrating a driving method for a source drive circuit according to an embodiment of this disclosure;

[0051] Figure 24 is a flowchart illustrating another source drive circuit driving method in an embodiment of this disclosure.

[0052] Detailed Explanation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0054] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0055] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0056] In related technologies, when a display panel updates its image, it needs to initialize and write the data voltage of all pixels within one frame. However, in certain special image conditions (e.g., static images, images with infrequent updates, and images that only require updating a few columns), the data voltage of most pixels on the screen does not need to be updated. In this case, the original display brightness can be maintained by low-leakage transistors. Repeatedly writing and updating these pixels results in some wasted power consumption.

[0057] The following describes a pixel driving circuit adapted to the source driving circuit in the embodiments of this disclosure. Unlike the pixel driving circuits of related technologies, the adapted pixel driving circuit includes a control sub-circuit, which includes at least two switching transistors. The at least two switching transistors control whether the data voltage is written to the control terminal of the driving transistor.

[0058] For example, the pixel driving circuit adapted to the source driving circuit in the embodiments of this disclosure includes: a driving sub-circuit 101, a data writing sub-circuit 102, a conduction control sub-circuit 103, a control sub-circuit 104, a compensation sub-circuit 105, and a light-emitting device.

[0059] The driving sub-circuit 101 is coupled to the first node n1, the second node n2 and the third node n3 respectively, and is configured to provide driving current to the light-emitting device under the control of the signals of the first node n1 and the second node n2.

[0060] The data writing sub-circuit 102 is coupled to the first scan signal terminal P_Gate, the data signal terminal Data, and the second node n2, respectively, and is configured to write the signal of the data signal terminal Data to the second node n2 under the control of the signal of the first scan signal terminal P_Gate.

[0061] The conduction control sub-circuit 103 is coupled to the first node n1, the fourth node n4 and the fifth node n5 respectively, and is configured to form a path between the first node n1 and the fifth node n5 under the control of the signal of the fourth node n4.

[0062] The control sub-circuit 104 is coupled to the second scan signal terminal N_Gate, the third scan signal terminal C_Gate, the second reference signal terminal VGL, and the fourth node n4, respectively, and is configured to write the signal of the third scan signal terminal C_Gate or the signal of the second reference signal terminal VGL into the fourth node n4 under the control of the signal of the second scan signal terminal N_Gate.

[0063] The compensation sub-circuit 105 is coupled to the first scan signal terminal P_Gate, the third node n3 and the fifth node n5 respectively, and is configured to form a path between the third node n3 and the fifth node n5 under the control of the signal of the first scan signal terminal P_Gate, and to compensate the threshold voltage of the driving sub-circuit 101.

[0064] When the display panel needs to refresh the screen, both the second scan signal terminal N_Gate and the third scan signal terminal C_Gate are input with valid levels. Under the control of the signal of the second scan signal terminal N_Gate, the control sub-circuit writes the signal of the third scan signal terminal C_Gate into the fourth node n4 to conduct the conduction control sub-circuit 103. Under the control of the signal of the first scan signal terminal P_Gate, the data writing sub-circuit 102 writes the signal of the data signal terminal Data into the second node n2. The data signal of the second node n2 is written into the first node n1 through the conducted drive sub-circuit 101, the compensation sub-circuit 105, and the conduction control sub-circuit 103.

[0065] When the display panel does not need to refresh the screen, at least one of the second scan signal terminal N_Gate and the third scan signal terminal C_Gate is input with an invalid level, and the invalid level control control sub-circuit 103 of the fourth node n4 is turned off, thereby preventing the data voltage from being written into the driving sub-circuit of the pixel driving circuit corresponding to the corresponding sub-pixel.

[0066] In some exemplary embodiments, the pixel driving circuit further includes a first light-emitting control sub-circuit 1061 and a second light-emitting control sub-circuit 1062, wherein:

[0067] The first light-emitting control sub-circuit 1061 is connected to the first voltage terminal ELVDD, the light-emitting control signal terminal EM and the second node n2 respectively, and is configured to form a path between the first voltage terminal ELVDD and the second node n2 under the control of the signal of the light-emitting control signal terminal EM.

[0068] The second light-emitting control sub-circuit 1062 is connected to the light-emitting control signal terminal EM, the third node n3 and the sixth node n6 respectively, and is configured to form a path between the third node n3 and the sixth node n6 under the control of the signal of the light-emitting control signal terminal EM.

[0069] In some exemplary embodiments, one end of the light-emitting device is connected to the sixth node n6, and the other end is connected to the second voltage terminal ELVSS.

[0070] In some exemplary embodiments, the pixel driving circuit described above further includes a storage sub-circuit 107, wherein the storage sub-circuit 107 is connected to the first voltage terminal ELVDD and the first node n1 respectively, and is configured to store the voltage of the first node n1 (i.e. the control terminal of the driving sub-circuit 101).

[0071] In some exemplary embodiments, the pixel driving circuit further includes a reset sub-circuit. The reset sub-circuit is connected to a reset control signal terminal (which may be a first reset control signal terminal P_Reset or a second reset control signal terminal H_Reset), and is also connected to at least one of the fifth node n5, the sixth node n6, and the second node n2. It is configured to reset at least one of the fifth node n5, the sixth node n6, and the second node n2 under the control of the signal from the reset control signal terminal.

[0072] In some exemplary embodiments, the reset sub-circuit includes a first reset sub-circuit 1081, a second reset sub-circuit 1082, and a third reset circuit 1083, wherein:

[0073] The first reset sub-circuit 1081 is connected to the first reset control signal terminal P_Reset, the fifth node n5 and the first initial signal terminal Vinit1 respectively, and is configured to reset the fifth node n5 using the first initial voltage of the first initial signal terminal Vinit1 under the control of the signal of the first reset control signal terminal P_Reset.

[0074] The second reset sub-circuit 1082 is connected to the second reset control signal terminal H_Reset, the sixth node n6, and the second initial signal terminal Vinit2, respectively. It is configured to reset the sixth node n6 using the second initial voltage of the second initial signal terminal Vinit2 under the control of the signal of the second reset control signal terminal H_Reset.

[0075] The third reset sub-circuit 1083 is connected to the second reset control signal terminal H_Reset, the second node n2 and the third initial signal terminal Vinit3 respectively, and is configured to reset the second node n2 using the third initial voltage of the third initial signal terminal Vinit3 under the control of the signal of the second reset control signal terminal H_Reset.

[0076] In some exemplary embodiments, as shown in FIG1, the pixel driving circuit provided in the embodiments of this disclosure includes a driving sub-circuit 101 including a driving transistor M3, a data writing sub-circuit 102 including a data writing transistor M4, a conduction control sub-circuit 103 including a conduction control transistor M10, a control sub-circuit 104 including a first switching transistor M8 and a second switching transistor M9, a compensation sub-circuit 105 including a compensation transistor M11, a first light emission control sub-circuit 1061 including a first light emission control transistor M5, a second light emission control sub-circuit 1062 including a second light emission control transistor M6, a storage sub-circuit 107 including a storage capacitor Cst, a first reset sub-circuit 1081 including a first reset transistor M1, a second reset sub-circuit 1082 including a second reset transistor M7, and a third reset sub-circuit 1083 including a third reset transistor M2.

[0077] Specifically, the control terminal of driving transistor M3 is connected to the first node n1, the first terminal of driving transistor M3 is connected to the second node n2, and the second terminal of driving transistor M3 is connected to the third node n3; the control terminal of data writing transistor M4 is connected to the first scan signal terminal P_Gate, the first terminal of data writing transistor M4 is connected to the data signal terminal Data, and the second terminal of data writing transistor M4 is connected to the second node n2; the control terminal of conduction control transistor M10 is connected to the fourth node n4, the first terminal of conduction control transistor M10 is connected to the first node n1, and the second terminal of conduction control transistor M10 is connected to the fifth node n5; the control terminal of the first switching transistor M8 is connected to the first node n1 ... the first terminal of conduction control transistor M10 is connected to the first node n1, and the second terminal of conduction control transistor M10 is connected to the fifth node n5; the control terminal of the first switching transistor M8 is connected to the first node n1, the first terminal of conduction control transistor M10 is connected to the first node n1, the first terminal of conduction control transistor M10 is connected to the first node n1, and the second terminal of conduction control transistor M10 is connected to the first node The control terminal of the first switching transistor M8 is connected to the second scan signal terminal N_Gate; the first terminal of the first switching transistor M8 is connected to the third scan signal terminal C_Gate; and the second terminal of the first switching transistor M8 is connected to the fourth node n4. The control terminal of the second switching transistor M9 is connected to the second scan signal terminal N_Gate; the first terminal of the second switching transistor M9 is connected to the second reference signal terminal VGL; and the second terminal of the second switching transistor M9 is connected to the fourth node n4. The control terminal of the compensation transistor M11 is connected to the first scan signal terminal P_Gate; the first terminal of the compensation transistor M11 is connected to the third node n3; and the second terminal of the compensation transistor M11 is connected to the fifth node n5. The first light-emitting... The control terminal of the first light-emitting control transistor M5 is connected to the light-emitting control signal terminal EM. The first terminal of the first light-emitting control transistor M5 is connected to the first voltage terminal ELVDD, and the second terminal of the first light-emitting control transistor M5 is connected to the second node n2. The control terminal of the second light-emitting control transistor M6 is connected to the light-emitting control signal terminal EM. The first terminal of the second light-emitting control transistor M6 is connected to the third node n3, and the second terminal of the second light-emitting control transistor M6 is connected to the sixth node n6. One end of the storage capacitor Cst is connected to the first node n1, and the other end of the storage capacitor Cst is connected to the first voltage terminal ELVDD. The control terminal of the first reset transistor M1 is connected to the first reset control signal terminal P_Rese. The first reset transistor M1 is connected to the first initial signal terminal Vinit1, and the second terminal of the first reset transistor M1 is connected to the fifth node n5; the control terminal of the second reset transistor M7 is connected to the second reset control signal terminal H_Reset, the first terminal of the second reset transistor M7 is connected to the second initial signal terminal Vinit2, and the second terminal of the second reset transistor M7 is connected to the sixth node n6; the control terminal of the third reset transistor M2 is connected to the second reset control signal terminal H_Reset, the first terminal of the third reset transistor M2 is connected to the third initial signal terminal Vinit3, and the second terminal of the third reset transistor M2 is connected to the second node n2.

[0078] Figure 1 illustrates an exemplary structure of the driving sub-circuit 101, the data writing sub-circuit 102, the conduction control sub-circuit 103, the control sub-circuit 104, the compensation sub-circuit 105, the first light-emitting control sub-circuit 1061, the second light-emitting control sub-circuit 1062, the first reset sub-circuit 1081, the second reset sub-circuit 1082, and the third reset sub-circuit 1083. It will be readily understood by those skilled in the art that the implementation of each of the above sub-circuits is not limited to this, as long as their respective functions can be achieved.

[0079] In some exemplary embodiments, in this pixel driving circuit, transistors M1 to M9 and M11 can be low-temperature polysilicon (LTPS) thin film transistors (TFTs), and transistor M10 can be an indium gallium zinc oxide (IGZO) thin film transistor.

[0080] In this embodiment, indium gallium zinc oxide (IGZO) thin-film transistors (LTS-TFTs) generate less leakage current compared to low-temperature polycrystalline silicon (LTPS-TFTs). Therefore, using an IGS-TFT for transistor M10 significantly reduces leakage current. During low-frequency displays, the IGS-TFT can maintain the voltage of the storage capacitor for a longer period, avoiding repeated charging of the data signal lines and thus reducing the power consumption of the display panel during display. Furthermore, since transistors M1 and M11 do not need to be IGS-TFTs, and LTPS-TFTs are generally smaller than IGS-TFTs, the pixel driving circuit in this embodiment occupies less space, which is beneficial for improving the resolution of the display panel.

[0081] The pixel driving circuit of this embodiment combines the good switching characteristics of LTPS-TFT and the low leakage current characteristics of Oxide-TFT, which can realize low-frequency driving (1Hz~60Hz) and significantly reduce the power consumption of the display screen.

[0082] Within one frame period, the pixel driving circuit operates through an initialization phase, a data writing phase, and a light-emitting phase. During initialization, the signal from the first initial signal terminal Vinit1 is written to the first node n1 via the activated first reset transistor M1 and the on-control transistor M10. The signal from the second initial signal terminal Vinit2 is written to the sixth node n6 via the activated second reset transistor M7. The signal from the third initial signal terminal Vinit3 is written to the second node n2 via the activated third reset transistor M2, thus resetting the control terminal, the first terminal, and the anode of the driving transistor. During the data writing phase, the sum of the data voltage of the data signal line and the threshold voltage of the driving transistor is charged into the storage capacitor Cst via the activated data writing transistor M4, the driving transistor M3, the compensation transistor M11, and the on-control transistor M10. During the light-emitting phase, the first power supply voltage output from the first voltage terminal ELVDD provides a driving voltage to the first electrode of the light-emitting device via the activated first light-emitting control transistor M5, the driving transistor M3, and the second light-emitting control transistor M6, allowing a driving current to flow through the light-emitting device and causing it to emit light.

[0083] In this embodiment, the fourth node n4 controls the maintenance or modification of the potential of the control terminal (i.e. the first node n1) of the driving transistor M3 through the conduction control transistor M10, and works with other transistors to reset the first node n1 and / or charge the data voltage and the threshold voltage of the driving transistor M3 into the storage capacitor Cst.

[0084] In this embodiment, by adding a first switching transistor M8 and a second switching transistor M9 to the pixel driving circuit, the signal of the fourth node n4 can be selected as the signal of the third scanning signal terminal C_Gate or the signal of the second reference signal terminal VGL through the signal of the second scanning signal terminal N_Gate, thus realizing bidirectional control in both row and column directions.

[0085] For example, whether to refresh in the row direction can be determined by whether the signal of the second scan signal terminal N_Gate is at an active level, and whether to refresh in the column direction can be determined by whether the signal of the third scan signal terminal C_Gate is at an active level.

[0086] In this embodiment of the disclosure, the effective level of a certain signal terminal or a certain node can be determined according to the type of transistor connected to that signal terminal or node. For example, in Figure 1, if the conduction control transistor M10 connected to the fourth node n4 is an N-type transistor, then the effective level of the signal at the fourth node n4 is high, and the ineffective level of the signal at the fourth node n4 is low. If the driving transistor M3 connected to the first node n1 is a P-type transistor, then the effective level of the signal at the first node n1 is low, and the ineffective level of the signal at the first node n1 is high.

[0087] In this embodiment, the effective levels of the second scanning signal terminal N_Gate and the third scanning signal terminal C_Gate can be determined based on their levels when the pixel driving circuit is in a refresh frame. For example, taking the pixel driving circuit in Figure 1 as an example, since the pixel driving circuit is in a refresh frame state when the signal of the second scanning signal terminal N_Gate is low and the signal of the third scanning signal terminal C_Gate is high, the effective level of the second scanning signal terminal N_Gate in Figure 1 is low, and the effective level of the third scanning signal terminal C_Gate is high. However, this disclosure is not limiting; in other examples, the effective level of the second scanning signal terminal N_Gate can also be high, and the effective level of the third scanning signal terminal C_Gate can also be low.

[0088] In Figure 1, when the signal level of the second scan signal terminal N_Gate is invalid (e.g., high level), the first switching transistor M8 is off, the second switching transistor M9 is on, and the level of the fourth node n4 is always the low level signal of the second reference signal terminal VGL. The conduction control transistor M10 is off, and the corresponding sub-pixel is not refreshed. When the signal level of the second scan signal terminal N_Gate is valid (e.g., low level), the first switching transistor M8 is on, the second switching transistor M9 is off, and the level of the fourth node n4 is the level of the signal of the third scan signal terminal C_Gate. At this time, whether the column direction is refreshed is determined by whether the signal level of the third scan signal terminal C_Gate is valid.

[0089] When the signal level of the third scan signal terminal C_Gate is invalid (e.g., low level), the level of the fourth node n4 remains low, the conduction control transistor M10 is turned off, and the corresponding sub-pixel is not refreshed. When the signal level of the third scan signal terminal C_Gate is valid (e.g., high level), the level of the fourth node n4 becomes high, the conduction control transistor M10 is turned on, and it works with other transistors to refresh the data voltage of the first node n1.

[0090] In summary, the corresponding sub-pixel is in refresh frame state only when the signal levels of the second scan signal terminal N_Gate and the third scan signal terminal C_Gate are both valid. When the signal level of at least one of the second scan signal terminal N_Gate and the third scan signal terminal C_Gate is invalid, the corresponding sub-pixel is in hold frame state, thus realizing bidirectional control in the row and column directions, as shown in Figure 2.

[0091] In some examples, if certain columns of the display screen do not need to be refreshed, the sub-pixels of the relevant columns can be controlled not to update the data voltage. In the specific implementation, the switching of at least two switching transistors included in the control sub-circuit of the pixel driving circuit is controlled so that the data voltage is not written to the control terminal of the driving transistor during the display time of the current frame.

[0092] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0093] Referring to Figures 3 and 4, an embodiment of this disclosure proposes a source drive circuit, including: a first input sub-circuit 301, a second input sub-circuit 302, a node control sub-circuit 303, and an output sub-circuit 304, wherein the first input sub-circuit 301 includes a first input sub-unit 3011, a second input sub-unit 3012, and a third input sub-unit 3013.

[0094] The first input subunit 3011 is configured to provide a scan start signal from the data signal terminal Datain to the first node N1 in response to an effective voltage signal in the signal of the first control signal terminal SW1, and to provide a signal from the first reference signal terminal VGH to the second node N2. The signal of the first control signal terminal SW1 includes an effective voltage signal within one frame display time, and the signal of the data signal terminal Datain includes a scan start signal and a data voltage signal that appear sequentially.

[0095] During implementation, when the effective voltage signal in the signal of the first control signal terminal SW1 is input, the first input sub-unit 3011 is turned on, and the scan start signal in the signal of the data signal terminal Datain is provided to the first node N1 through the turned-on first input sub-unit 3011. The signal of the first reference signal terminal VGH is provided to the second node N2 through the turned-on first input sub-unit 3011.

[0096] In order to achieve partial refresh of the display panel in the column direction, in this embodiment of the present disclosure, before writing data voltage to the data line, the effective voltage signal and the scan start signal are used to control whether to refresh the column. Therefore, within one frame of display time, the signal of the first control signal terminal SW1 only includes one effective voltage signal. That is, when the column needs to be refreshed, the effective voltage signal provided by the first control signal terminal SW1 is input to the first input subunit 3011, and then the scan start signal provided by the data signal terminal Datain is written to the first node N1.

[0097] It should be noted that the signals of the aforementioned Datain terminal include the scan start signal and the data voltage signal that appear sequentially. However, when the aforementioned Datain terminal provides the data voltage signal, the signal of the first control signal terminal SW1 will correspond to a signal other than the effective voltage signal. That is, when the signal of the first control signal terminal SW1 is a signal other than the effective voltage signal, the signal of the Datain terminal is the data voltage signal. In other words, the aforementioned source drive circuit shields the response of the data voltage signal and controls whether the column is refreshed only based on the scan start signal before the data voltage signal appears.

[0098] For example, referring to FIG5, the first input subunit 3011 may include: a first transistor T1 and a second transistor T2.

[0099] The control terminal of the first transistor T1 is coupled to the first control signal terminal SW1, the first terminal of the first transistor T1 is coupled to the data signal terminal Datain, and the second terminal of the first transistor T1 is coupled to the first node N1.

[0100] For example, the first transistor T1 can be turned on under the control of the active level of the first control signal terminal SW1, and can be turned off under the control of the inactive level of the first control signal terminal SW1. For example, if the first transistor T1 is set as an N-type transistor, then the active level of the signal at the first control signal terminal SW1 is a high level, and the inactive level of the signal at the first control signal terminal SW1 is a low level. Alternatively, if the first transistor T1 is set as a P-type transistor, then the active level of the signal at the first control signal terminal SW1 is a low level, and the inactive level of the signal at the first control signal terminal SW1 is a high level.

[0101] Referring to Figure 5, the first transistor T1 is a P-type transistor. When the signal at the first control signal terminal SW1 is low, the first transistor T1 is turned on, and the data signal terminal Datain is connected to the first node N1 through the turned-on first transistor T1.

[0102] The control terminal of the second transistor T2 is coupled to the first control signal terminal SW1, the first terminal of the second transistor T2 is coupled to the first reference signal terminal VGH, and the second terminal of the second transistor T2 is coupled to the second node N2.

[0103] For example, the second transistor T2 can be turned on under the control of the active level of the first control signal terminal SW1, and can be turned off under the control of the inactive level of the first control signal terminal SW1. For example, if the second transistor T2 is set as an N-type transistor, then the active level of the signal at the first control signal terminal SW1 is a high level, and the inactive level of the signal at the first control signal terminal SW1 is a low level. Alternatively, if the second transistor T2 is set as a P-type transistor, then the active level of the signal at the first control signal terminal SW1 is a low level, and the inactive level of the signal at the first control signal terminal SW1 is a high level.

[0104] Referring to Figure 5, the second transistor T2 is a P-type transistor. When the signal at the first control signal terminal SW1 is low, the second transistor T2 is turned on, and the first reference signal terminal VGH is connected to the second node N2 through the turned-on second transistor T2.

[0105] The second input subunit 3012 is configured to provide the signal of the first reference signal terminal VGH to the first node N1 and the second node N2 in response to the signal of the pull-up node N4 and the signal of the second control signal terminal SW2.

[0106] During implementation, when the signal of the pull-up node N4 is valid and the signal of the second control signal terminal SW2 is a second level signal, the second input sub-unit 3012 is turned on, and the signal of the first reference signal terminal VGH is provided to the first node N1 and the second node N2 through the turned-on second input sub-unit 3012.

[0107] For example, referring to FIG5, the second input subunit 3012 includes: a third transistor T3, a fourth transistor T4 and a fifth transistor T5.

[0108] The control terminal of the third transistor T3 is coupled to the second control signal terminal SW2, the first terminal of the third transistor T3 is coupled to the second terminal of the fifth transistor T5, and the second terminal of the third transistor T3 is coupled to the first node N1.

[0109] For example, the third transistor T3 can be turned on under the control of the active level of the second control signal terminal SW2, and can be turned off under the control of the inactive level of the second control signal terminal SW2. For example, if the third transistor T3 is set as an N-type transistor, then the active level of the signal at the second control signal terminal SW2 is a high level, and the inactive level of the signal at the second control signal terminal SW2 is a low level. Alternatively, if the third transistor T3 is set as a P-type transistor, then the active level of the signal at the second control signal terminal SW2 is a low level, and the inactive level of the signal at the second control signal terminal SW2 is a high level.

[0110] Referring to Figure 5, the third transistor T3 is a P-type transistor. When the signal at the second control signal terminal SW2 is low, the third transistor T3 is turned on, and the second terminal of the fifth transistor T5 is connected to the first node N1 through the turned-on third transistor T3.

[0111] The control terminal of the fifth transistor T5 is coupled to the pull-up node (i.e., the fourth node) N4, and the first terminal of the fifth transistor T5 is coupled to the first reference signal terminal VGH.

[0112] For example, the fifth transistor T5 can be turned on under the control of the active level of the pull-up node N4, and can be turned off under the control of the inactive level of the pull-up node N4. For example, if the fifth transistor T5 is set as an N-type transistor, then the active level of the signal of the pull-up node N4 is a high level, and the inactive level of the signal of the pull-up node N4 is a low level. Alternatively, if the fifth transistor T5 is set as a P-type transistor, then the active level of the signal of the pull-up node N4 is a low level, and the inactive level of the signal of the pull-up node N4 is a high level.

[0113] Referring to Figure 5, the fifth transistor T5 is a P-type transistor. When the signal at the fourth node N4 is low, the fifth transistor T5 is turned on, and the first reference signal terminal VGH is connected to the first terminal of the third transistor T3 through the turned-on fifth transistor T5.

[0114] The control terminal of the fourth transistor T4 is coupled to the second control signal terminal SW2, the first terminal of the fourth transistor T4 is coupled to the second terminal of the fifth transistor T5, and the second terminal of the fourth transistor T4 is coupled to the second node N2.

[0115] For example, the fourth transistor T4 can be turned on under the control of the active level of the second control signal terminal SW2, and can be turned off under the control of the inactive level of the second control signal terminal SW2. For example, if the fourth transistor T4 is set as an N-type transistor, then the active level of the signal at the second control signal terminal SW2 is a high level, and the inactive level of the signal at the second control signal terminal SW2 is a low level. Alternatively, if the fourth transistor T4 is set as a P-type transistor, then the active level of the signal at the second control signal terminal SW2 is a low level, and the inactive level of the signal at the second control signal terminal SW2 is a high level.

[0116] Referring to Figure 5, the fourth transistor T4 is a P-type transistor. When the signal at the second control signal terminal SW2 is low, the fourth transistor T4 is turned on, and the second terminal of the fifth transistor T5 is connected to the second node N2 through the turned-on fourth transistor T4.

[0117] The aforementioned third input subunit 3013 is configured to provide the signal of the third control signal terminal SW3 to the second node N2 in response to the signal of the first node N1.

[0118] During implementation, when the signal of the first node N1 is valid, the third input subunit 3013 is turned on, and the signal of the third control signal terminal SW3 is provided to the second node N2 through the turned-on third input subunit 3013.

[0119] For example, referring to FIG5, the third input subunit 3013 includes: a sixth transistor T6.

[0120] The control terminal of the sixth transistor T6 is coupled to the first node N1, the first terminal of the sixth transistor T6 is coupled to the third control signal terminal SW3, and the second terminal of the sixth transistor T6 is coupled to the second node N2.

[0121] For example, the sixth transistor T6 can be turned on under the control of the active level of the first node N1, and can be turned off under the control of the inactive level of the first node N1. For example, if the sixth transistor T6 is set as an N-type transistor, then the active level of the signal of the first node N1 is a high level, and the inactive level of the signal of the first node N1 is a low level. Alternatively, if the sixth transistor T6 is set as a P-type transistor, then the active level of the signal of the first node N1 is a low level, and the inactive level of the signal of the first node N1 is a high level.

[0122] Referring to Figure 5, the sixth transistor T6 is a P-type transistor. When the signal at the first node N1 is low, the sixth transistor T6 is turned on, and the third control signal terminal SW3 is connected to the second node N2 through the turned-on sixth transistor T6.

[0123] For example, referring to FIG5, the third input subunit 3013 further includes: a first capacitor C1.

[0124] The first terminal of the first capacitor C1 is coupled to the first node N1, and the second terminal of the first capacitor C1 is coupled to the second node N2.

[0125] The first capacitor C1 can couple (raise or pull down) the potential of the second node N2 to the potential of the first node N1, or it can couple (raise or pull down) the potential of the first node N1 to the potential of the second node N2.

[0126] The second input sub-circuit 302 is configured to provide the signal of the second reference signal terminal VGL to the third node N3 in response to the signal of the first clock signal terminal CK.

[0127] During implementation, when the signal of the first clock signal terminal CK is valid, the second input sub-circuit 302 is turned on, and the signal of the second control signal terminal SW2 is provided to the third node N3 through the turned-on second input sub-circuit 302.

[0128] For example, referring to FIG5, the second input sub-circuit 302 includes a seventh transistor T7.

[0129] The control terminal of the seventh transistor T7 is coupled to the first clock signal terminal CK, the first terminal of the seventh transistor T7 is coupled to the second control signal terminal SW2, and the second terminal of the seventh transistor T7 is coupled to the third node N3.

[0130] For example, the seventh transistor T7 can be turned on under the control of the active level of the first clock signal terminal CK, and can be turned off under the control of the inactive level of the first clock signal terminal CK. For example, if the seventh transistor T7 is set as an N-type transistor, then the active level of the signal at the first clock signal terminal CK is high, and the inactive level of the signal at the first clock signal terminal CK is low. Alternatively, if the seventh transistor T7 is set as a P-type transistor, then the active level of the signal at the first clock signal terminal CK is low, and the inactive level of the signal at the first clock signal terminal CK is high.

[0131] Referring to Figure 5, the seventh transistor T7 is a P-type transistor. When the signal at the first clock signal terminal CK is low, the seventh transistor T7 is turned on, and the second control signal terminal SW2 is connected to the third node N3 through the turned-on seventh transistor T7.

[0132] The aforementioned node control sub-circuit 303 is configured to control the signals of the pull-up node (i.e., the fourth node) N4 and the pull-down node (i.e., the fifth node) N5 based on the signals of the second node N2 and the third node N3.

[0133] During implementation, the node control sub-circuit 303 controls the pull-up node N4 to an active level based on the signals from the second node N2 and the third node N3, thereby causing the output sub-circuit 304 to output the signal at the first reference signal terminal VGH. Alternatively, the node control sub-circuit 303 controls the pull-down node N5 to an active level based on the signals from the second node N2 and the third node N3, thereby causing the output sub-circuit 304 to output the signal at the second reference signal terminal VGL.

[0134] The aforementioned output sub-circuit 304 is configured to provide the signal of the first reference signal terminal VGH to the drive output terminal HOUT in response to the signal of the pull-up node N4; and to provide the signal of the second reference signal terminal VGL to the drive output terminal HOUT in response to the signal of the pull-down node N5.

[0135] During implementation, when the signal of pull-up node N4 is at an active level, output sub-circuit 304 is turned on, and the signal of the first reference signal terminal VGH is provided to the drive output terminal HOUT through the turned-on output sub-circuit 304. Alternatively, when the signal of pull-down node N5 is at an active level, output sub-circuit 304 is turned on, and the signal of the second reference signal terminal VGL is provided to the drive output terminal HOUT through the turned-on output sub-circuit 304.

[0136] For example, referring to FIG4, the node control sub-circuit 303 includes: a first control sub-unit 3031, a second control sub-unit 3032 and a third control sub-unit 3033.

[0137] The first control subunit 3031 is coupled to the second node N2, the pull-down node N5, the second reference signal terminal VGL, and the sixth node N6. The first control subunit 3031 is configured to provide the signal of the second node N2 to the pull-down node N5 in response to the signal of the second reference signal terminal VGL; and to provide the signal of the second node N2 to the sixth node N6 in response to the signal of the second reference signal terminal VGL; and to provide the signal of the sixth node N6 to the pull-down node N5 in response to the signal of the sixth node N6.

[0138] For example, referring to FIG5, the first control subunit 3031 includes: an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10.

[0139] The control terminal of the eighth transistor T8 is coupled to the second reference signal terminal VGL, the first terminal of the eighth transistor T8 is coupled to the second node N2, and the second terminal of the eighth transistor T8 is coupled to the pull-down node N5.

[0140] For example, the eighth transistor T8 can be turned on under the control of the active level of the second reference signal terminal VGL, and can be turned off under the control of the inactive level of the second reference signal terminal VGL. For example, if the eighth transistor T8 is set as an N-type transistor, then the active level of the signal at the second reference signal terminal VGL is a high level, and the inactive level of the signal at the second reference signal terminal VGL is a low level. Alternatively, if the eighth transistor T8 is set as a P-type transistor, then the active level of the signal at the second reference signal terminal VGL is a low level, and the inactive level of the signal at the second reference signal terminal VGL is a high level.

[0141] Referring to Figure 5, the eighth transistor T8 is a P-type transistor. When the signal at the second reference signal terminal VGL is low, the eighth transistor T8 is turned on, and the second node N2 is connected to the pull-down node N5 through the turned-on eighth transistor T8.

[0142] The control terminal of the ninth transistor T9 is coupled to the second reference signal terminal VGL, the first terminal of the ninth transistor T9 is coupled to the second node N2, and the second terminal of the ninth transistor T9 is coupled to the sixth node N6.

[0143] For example, the ninth transistor T9 can be turned on under the control of the active level of the second reference signal terminal VGL, and can be turned off under the control of the inactive level of the second reference signal terminal VGL. For example, if the ninth transistor T9 is set as an N-type transistor, then the active level of the signal at the second reference signal terminal VGL is a high level, and the inactive level of the signal at the second reference signal terminal VGL is a low level. Alternatively, if the ninth transistor T9 is set as a P-type transistor, then the active level of the signal at the second reference signal terminal VGL is a low level, and the inactive level of the signal at the second reference signal terminal VGL is a high level.

[0144] Referring to Figure 5, the ninth transistor T9 is a P-type transistor. When the signal at the second reference signal terminal VGL is low, the ninth transistor T9 is turned on, and the second node N2 is connected to the sixth node N6 through the turned-on ninth transistor T9.

[0145] The control terminal of the tenth transistor T10 is coupled to the sixth node N6, the first terminal of the tenth transistor T10 is coupled to the sixth node N6, and the second terminal of the tenth transistor T10 is coupled to the pull-down node N5.

[0146] For example, the tenth transistor T10 can be turned on under the control of the active level of the sixth node N6, and can be turned off under the control of the inactive level of the sixth node N6. For example, if the tenth transistor T10 is set as an N-type transistor, then the active level of the signal of the sixth node N6 is a high level, and the inactive level of the signal of the sixth node N6 is a low level. Alternatively, if the tenth transistor T10 is set as a P-type transistor, then the active level of the signal of the sixth node N6 is a low level, and the inactive level of the signal of the sixth node N6 is a high level.

[0147] Referring to Figure 5, the tenth transistor T10 is a P-type transistor. When the signal of the sixth node N6 is low, the tenth transistor T10 is turned on, and the sixth node N6 is connected to the pull-down node N5 through the turned-on tenth transistor T10.

[0148] The second control subunit 3032 is coupled to the second node N2, the third node N3, the first reference signal terminal VGH, the first clock signal terminal CK, the second clock signal terminal CB, and the sixth node N6. The second control subunit 3032 is configured to provide the signal of the first clock signal terminal CK to the third node N3 in response to the signal of the second node N2; to provide the signal of the first reference signal terminal VGH to the seventh node N7 in response to the signal of the third node N3; and to provide the second clock signal terminal CB to the seventh node N7 in response to the signal of the sixth node N6.

[0149] For example, referring to FIG5, the second control subunit 3032 includes: an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a second capacitor C2.

[0150] The control terminal of the eleventh transistor T11 is coupled to the second node N2, the first terminal of the eleventh transistor T11 is coupled to the first clock signal terminal CK, and the second terminal of the eleventh transistor T11 is coupled to the third node N3.

[0151] For example, the eleventh transistor T11 can be turned on under the control of the active level of the second node N2, and can be turned off under the control of the inactive level of the second node N2. For example, if the eleventh transistor T11 is set as an N-type transistor, then the active level of the signal at the second node N2 is a high level, and the inactive level of the signal at the second node N2 is a low level. Alternatively, if the eleventh transistor T11 is set as a P-type transistor, then the active level of the signal at the second node N2 is a low level, and the inactive level of the signal at the second node N2 is a high level.

[0152] Referring to Figure 5, the eleventh transistor T11 is a P-type transistor. When the signal at the second node N2 is low, the eleventh transistor T11 is turned on, and the first clock signal terminal CK is connected to the third node N3 through the turned-on eleventh transistor T11.

[0153] The control terminal of the twelfth transistor T12 is coupled to the third node N3, the first terminal of the twelfth transistor T12 is coupled to the seventh node N7, and the second terminal of the twelfth transistor T12 is coupled to the first reference signal terminal VGH.

[0154] For example, the twelfth transistor T12 can be turned on under the control of the active level of the third node N3, and can be turned off under the control of the inactive level of the third node N3. For example, if the twelfth transistor T12 is set as an N-type transistor, then the active level of the signal of the third node N3 is a high level, and the inactive level of the signal of the third node N3 is a low level. Alternatively, if the twelfth transistor T12 is set as a P-type transistor, then the active level of the signal of the third node N3 is a low level, and the inactive level of the signal of the third node N3 is a high level.

[0155] Referring to Figure 5, the twelfth transistor T12 is a P-type transistor. When the signal at the third node N3 is low, the twelfth transistor T12 is turned on, and the seventh node N7 is connected to the first reference signal terminal VGH through the turned-on twelfth transistor T12.

[0156] The control terminal of the thirteenth transistor T13 is coupled to the sixth node N6, the first terminal of the thirteenth transistor T13 is coupled to the second clock signal terminal CB, and the second terminal of the thirteenth transistor T13 is coupled to the seventh node N7.

[0157] For example, the thirteenth transistor T13 can be turned on under the control of the active level of the sixth node N6, and can be turned off under the control of the inactive level of the sixth node N6. For example, if the thirteenth transistor T13 is set as an N-type transistor, then the active level of the signal of the sixth node N6 is a high level, and the inactive level of the signal of the sixth node N6 is a low level. Alternatively, if the thirteenth transistor T13 is set as a P-type transistor, then the active level of the signal of the sixth node N6 is a low level, and the inactive level of the signal of the sixth node N6 is a high level.

[0158] Referring to Figure 5, the thirteenth transistor T13 is a P-type transistor. When the signal at the sixth node N6 is low, the ninth transistor T9 is turned on, and the seventh node N7 is connected to the second clock signal terminal CB through the turned-on thirteenth transistor T13.

[0159] The first terminal of the second capacitor C2 is coupled to the sixth node N6, and the second terminal of the second capacitor C2 is coupled to the seventh node N7.

[0160] The aforementioned third control subunit 3033 is coupled to the second node N2, the third node N3, the second reference signal terminal VGL, the second clock signal terminal CB, the first reference signal terminal VGH, and the pull-up node N4. The third control subunit 3033 is configured to provide the signal of the second clock signal terminal CB to the pull-up node N4 in response to the signals of the second reference signal terminal VGL, the third node N3, and the second clock signal terminal CB; and to provide the signal of the first reference signal terminal VGH to the pull-up node N4 in response to the signal of the second node N2.

[0161] For example, referring to FIG5, the third control subunit 3033 includes: a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17 and a third capacitor C3.

[0162] The control terminal of the fourteenth transistor T14 is coupled to the second reference signal terminal VGL. The first terminal of the fourteenth transistor T14 is coupled to the third node N3. The second terminal of the fourteenth transistor T14 is coupled to the eighth node N8 (i.e., the first terminal of the third capacitor C3).

[0163] For example, the fourteenth transistor T14 can be turned on under the control of the active level of the second reference signal terminal VGL, and can be turned off under the control of the inactive level of the second reference signal terminal VGL. For example, if the fourteenth transistor T14 is set as an N-type transistor, then the active level of the signal at the second reference signal terminal VGL is a high level, and the inactive level of the signal at the second reference signal terminal VGL is a low level. Alternatively, if the fourteenth transistor T14 is set as a P-type transistor, then the active level of the signal at the second reference signal terminal VGL is a low level, and the inactive level of the signal at the second reference signal terminal VGL is a high level.

[0164] Referring to Figure 5, the fourteenth transistor T14 is a P-type transistor. When the signal at the second reference signal terminal VGL is low, the fourteenth transistor T14 is turned on, and the third node N3 is connected to the first terminal of the second capacitor C2 through the turned-on fourteenth transistor T14.

[0165] The control terminal of the fifteenth transistor T15 is coupled to the eighth node N8 (i.e., the first terminal of the third capacitor C3), the first terminal of the fifteenth transistor T15 is coupled to the ninth node N9 (i.e., the second terminal of the third capacitor C3), and the second terminal of the fifteenth transistor T15 is coupled to the second clock signal terminal CB.

[0166] For example, the fifteenth transistor T15 can be turned on under the control of the effective level of the first terminal of the third capacitor C3, and can be turned off under the control of the ineffective level of the first terminal of the third capacitor C3. For example, if the fifteenth transistor T15 is set as an N-type transistor, then the effective level of the signal at the first terminal of the third capacitor C3 is a high level, and the ineffective level of the signal at the first terminal of the third capacitor C3 is a low level. Alternatively, if the fifteenth transistor T15 is set as a P-type transistor, then the effective level of the signal at the first terminal of the third capacitor C3 is a low level, and the ineffective level of the signal at the first terminal of the third capacitor C3 is a high level.

[0167] Referring to Figure 5, the fifteenth transistor T15 is a P-type transistor. When the signal at the first terminal of the third capacitor C3 is low, the fifteenth transistor T15 is turned on, and the second terminal of the third capacitor C3 is connected to the second clock signal terminal CB through the turned-on fifteenth transistor T15.

[0168] The control terminal of the sixteenth transistor T16 is coupled to the second clock signal terminal CB. The first terminal of the sixteenth transistor T16 is coupled to the ninth node N9 (i.e., the second terminal of the third capacitor C3). The second terminal of the sixteenth transistor T16 is coupled to the pull-up node N4.

[0169] For example, the sixteenth transistor T16 can be turned on under the control of the active level of the second clock signal terminal CB, and can be turned off under the control of the inactive level of the second clock signal terminal CB. For example, if the sixteenth transistor T16 is set as an N-type transistor, then the active level of the signal at the second clock signal terminal CB is a high level, and the inactive level of the signal at the second clock signal terminal CB is a low level. Alternatively, if the sixteenth transistor T16 is set as a P-type transistor, then the active level of the signal at the second clock signal terminal CB is a low level, and the inactive level of the signal at the second clock signal terminal CB is a high level.

[0170] Referring to Figure 5, the sixteenth transistor T16 is a P-type transistor. When the signal at the second clock signal terminal CB is low, the sixteenth transistor T16 is turned on, and the second terminal of the third capacitor C3 is connected to the pull-up node N4 through the turned-on sixteenth transistor T16.

[0171] The control terminal of the seventeenth transistor T17 is coupled to the second node N2, the first terminal of the seventeenth transistor T17 is coupled to the first reference signal terminal VGH, and the second terminal of the seventeenth transistor T17 is coupled to the pull-up node N4.

[0172] For example, the seventeenth transistor T17 can be turned on under the control of the active level of the second node N2, and can be turned off under the control of the inactive level of the second node N2. For example, if the seventeenth transistor T17 is set as an N-type transistor, then the active level of the signal of the second node N2 is a high level, and the inactive level of the signal of the second node N2 is a low level. Alternatively, if the seventeenth transistor T17 is set as a P-type transistor, then the active level of the signal of the second node N2 is a low level, and the inactive level of the signal of the second node N2 is a high level.

[0173] Referring to Figure 5, the seventeenth transistor T17 is a P-type transistor. When the signal of the second node N2 is low, the seventeenth transistor T17 is turned on, and the first reference signal terminal VGH is connected to the pull-up node N4 through the turned-on seventeenth transistor T17.

[0174] The first terminal of the third capacitor C3 is coupled to the eighth node N8, and the second terminal of the third capacitor C3 is coupled to the ninth node N9.

[0175] The output sub-circuit 304 is configured to provide the signal of the first reference signal terminal VGH to the drive output terminal HOUT in response to the signal of the pull-up node N4, and to provide the signal of the second reference signal terminal VGL to the drive output terminal HOUT in response to the signal of the pull-down node N5.

[0176] For example, referring to Figure 5, the output sub-circuit 304 includes: an eighteenth transistor T18, a fourth capacitor C4, and a nineteenth transistor T19.

[0177] The control terminal of the eighteenth transistor T18 is coupled to the pull-down node N5, the first terminal of the eighteenth transistor T18 is coupled to the second reference signal terminal VGL, and the second terminal of the eighteenth transistor T18 is coupled to the drive output terminal HOUT.

[0178] For example, the eighteenth transistor T18 can be turned on under the control of the active level of the pull-down node N5, and can be turned off under the control of the inactive level of the pull-down node N5. For example, if the eighteenth transistor T18 is set as an N-type transistor, then the active level of the signal of the pull-down node N5 is a high level, and the inactive level of the signal of the pull-down node N5 is a low level. Alternatively, if the eighteenth transistor T18 is set as a P-type transistor, then the active level of the signal of the pull-down node N5 is a low level, and the inactive level of the signal of the pull-down node N5 is a high level.

[0179] Referring to Figure 5, the eighteenth transistor T18 is a P-type transistor. When the signal of the pull-down node N5 is low, the eighteenth transistor T18 is turned on, and the second reference signal terminal VGL is connected to the drive output terminal HOUT through the turned-on eighteenth transistor T18.

[0180] The first terminal of the fourth capacitor C4 is coupled to the pull-up node N4, and the second terminal of the fourth capacitor C4 is coupled to the first reference signal terminal VGH.

[0181] The control terminal of the nineteenth transistor T19 is coupled to the pull-up node N4, the first terminal of the nineteenth transistor T19 is coupled to the drive output terminal HOUT, and the second terminal of the nineteenth transistor T19 is coupled to the first reference signal terminal VGH.

[0182] For example, the nineteenth transistor T19 can be turned on under the control of the active level of pull-up node N4, and can be turned off under the control of the inactive level of pull-up node N4. For example, if the nineteenth transistor T19 is set as an N-type transistor, then the active level of the signal of pull-up node N4 is a high level, and the inactive level of the signal of pull-up node N4 is a low level. Alternatively, if the nineteenth transistor T19 is set as a P-type transistor, then the active level of the signal of pull-up node N4 is a low level, and the inactive level of the signal of pull-up node N4 is a high level.

[0183] Referring to Figure 5, the nineteenth transistor T19 is a P-type transistor. When the signal at the pull-up node N4 is low, the nineteenth transistor T19 is turned on, and the first reference signal terminal VGH is connected to the drive output terminal HOUT through the turned-on nineteenth transistor T19.

[0184] Furthermore, as exemplarily shown in Figures 6, 8 and 10, the aforementioned source drive circuit also includes a first pull-down control sub-circuit 305.

[0185] The first pull-down control sub-circuit 305 is configured to provide the signal of the second reference signal terminal VGL to the sixth node N6 in response to at least one of the following: a signal from the drive output terminal HOUT (not shown), the pull-down node N5, the first node N1, or the second node N2.

[0186] During implementation, the first pull-down control sub-circuit 305 is turned on according to at least one of the following: the signals of the drive output terminal HOUT, pull-down node N5, first node N1 or second node N2 are turned on, and the signal of the second reference signal terminal VGL is provided to the sixth node N6 through the turned-on first pull-down control sub-circuit 305.

[0187] For example, referring to Figures 7, 9 and 11, the first pull-down control sub-circuit 305 includes: a twentieth transistor T20.

[0188] The control terminal of the twentieth transistor T20 is coupled to at least one of the following: drive output terminal HOUT (not shown in the figure), pull-down node N5, first node N1 or second node N2; the first terminal of the twentieth transistor T20 is coupled to the second reference signal terminal VGL; and the second terminal of the twentieth transistor T20 is coupled to the sixth node N6.

[0189] (1) For example, the twentieth transistor T20 can be turned on under the control of the active level of the pull-down node N5, and can be turned off under the control of the inactive level of the pull-down node N5. For example, if the twentieth transistor T20 is set as an N-type transistor, then the active level of the signal of the pull-down node N5 is a high level, and the inactive level of the signal of the pull-down node N5 is a low level. Alternatively, if the twentieth transistor T20 is set as a P-type transistor, then the active level of the signal of the pull-down node N5 is a low level, and the inactive level of the signal of the pull-down node N5 is a high level.

[0190] Referring to Figure 7, the twentieth transistor T20 is a P-type transistor. When the signal of the pull-down node N5 is low, the twentieth transistor T20 is turned on, and the signal of the second reference signal terminal VGL is provided to the sixth node N6 through the turned-on twentieth transistor T20.

[0191] (2) For example, the twentieth transistor T20 can be turned on under the control of the effective level of the first node N1, and can be turned off under the control of the ineffective level of the first node N1. For example, if the twentieth transistor T20 is set as an N-type transistor, then the effective level of the signal of the first node N1 is a high level, and the ineffective level of the signal of the first node N1 is a low level. Alternatively, if the twentieth transistor T20 is set as a P-type transistor, then the effective level of the signal of the first node N1 is a low level, and the ineffective level of the signal of the first node N1 is a high level.

[0192] Referring to Figure 9, the twentieth transistor T20 is a P-type transistor. When the signal at the first node N1 is low, the twentieth transistor T20 is turned on, and the signal at the second reference signal terminal VGL is provided to the sixth node N6 through the turned-on twentieth transistor T20.

[0193] (3) For example, the twentieth transistor T20 can be turned on under the control of the effective level of the second node N2, and can be turned off under the control of the ineffective level of the second node N2. For example, if the twentieth transistor T20 is set as an N-type transistor, then the effective level of the signal of the second node N2 is a high level, and the ineffective level of the signal of the second node N2 is a low level. Alternatively, if the twentieth transistor T20 is set as a P-type transistor, then the effective level of the signal of the second node N2 is a low level, and the ineffective level of the signal of the second node N2 is a high level.

[0194] Referring to Figure 11, the twentieth transistor T20 is a P-type transistor. When the signal at the second node N2 is low, the twentieth transistor T20 is turned on, and the signal at the second reference signal terminal VGL is provided to the sixth node N6 through the turned-on twentieth transistor T20.

[0195] (4) For example, the twentieth transistor T20 can be turned on under the control of the effective level of the drive output terminal HOUT, and can be turned off under the control of the ineffective level of the drive output terminal HOUT. For example, if the twentieth transistor T20 is set as an N-type transistor, then the effective level of the signal at the drive output terminal HOUT is a high level, and the ineffective level of the signal at the drive output terminal HOUT is a low level. Alternatively, if the twentieth transistor T20 is set as a P-type transistor, then the effective level of the signal at the drive output terminal HOUT is a low level, and the ineffective level of the signal at the drive output terminal HOUT is a high level.

[0196] Furthermore, as exemplarily shown in Figures 8 and 10, the aforementioned source drive circuit also includes a second pull-down control sub-circuit 306.

[0197] The first pull-down control sub-circuit 305 is coupled to the second reference signal terminal VGL via the second pull-down control sub-circuit 306. The second pull-down control sub-circuit 306 is configured to provide the signal of the second reference signal terminal VGL to the first pull-down control sub-circuit 305 in response to the signal of the drive output terminal HOUT.

[0198] During implementation, when the signal at the drive output terminal HOUT is valid, the first pull-down control sub-circuit 305 is connected to the second reference signal terminal VGL via the second pull-down control sub-circuit 306, and the signal at the second reference signal terminal VGL is provided to the first pull-down control sub-circuit 305 via the activated second pull-down control sub-circuit 306.

[0199] For example, referring to FIG9, the second pull-down control sub-circuit 306 includes: a twenty-first transistor T21.

[0200] The control terminal of the twenty-first transistor T21 is coupled to the drive output terminal HOUT, the first terminal of the twenty-first transistor T21 is coupled to the first pull-down control sub-circuit 305, and the second terminal of the twenty-first transistor T21 is coupled to the second reference signal terminal VGL.

[0201] For example, the twenty-first transistor T21 can be turned on under the control of the effective level of the drive output terminal HOUT, and can be turned off under the control of the ineffective level of the drive output terminal HOUT. For example, if the twenty-first transistor T21 is set as an N-type transistor, then the effective level of the signal at the drive output terminal HOUT is a high level, and the ineffective level of the signal at the drive output terminal HOUT is a low level. Alternatively, if the twenty-first transistor T21 is set as a P-type transistor, then the effective level of the signal at the drive output terminal HOUT is a low level, and the ineffective level of the signal at the drive output terminal HOUT is a high level.

[0202] Referring to Figure 9, the twenty-first transistor T21 is a P-type transistor. When the signal at the drive output terminal HOUT is low, the twenty-first transistor T21 is turned on. The first terminal of the first pull-down control sub-circuit 305, i.e. the twentieth transistor T20, is connected to the second reference signal terminal VGL through the turned-on twenty-first transistor T21.

[0203] For example, referring to FIG10, the above-mentioned source drive circuit also includes a reset sub-circuit 307.

[0204] The reset circuit 307 is configured to provide the signal of the first reference signal terminal VGH to the second node N2 in response to the signal of the node control signal terminal HCX.

[0205] During implementation, when the signal at the node control signal terminal HCX is valid, the reset sub-circuit 307 is turned on, and the signal at the first reference signal terminal VGH is provided to the second node N2 through the turned-on reset sub-circuit 307.

[0206] For example, referring to Figures 11 and 12, the reset sub-circuit 307 includes a twenty-second transistor T22.

[0207] The control terminal of the 22nd transistor T22 is coupled to the node control signal terminal HCX, the first terminal of the 22nd transistor T22 is coupled to the second node N2, and the second terminal of the 22nd transistor T22 is coupled to the first reference signal terminal VGH.

[0208] For example, the twenty-second transistor T22 can be turned on under the control of the active level of the node control signal terminal HCX, and can be turned off under the control of the inactive level of the node control signal terminal HCX. For example, if the twenty-second transistor T22 is set as an N-type transistor, then the active level of the signal at the node control signal terminal HCX is a high level, and the inactive level of the signal at the node control signal terminal HCX is a low level. Alternatively, if the twenty-second transistor T22 is set as a P-type transistor, then the active level of the signal at the node control signal terminal HCX is a low level, and the inactive level of the signal at the node control signal terminal HCX is a high level.

[0209] Referring to Figures 11 and 12, the twenty-second transistor T22 is configured as a P-type transistor. When the signal at the node control signal terminal HCX is low, the twenty-second transistor T22 is turned on, and the second node N2 is connected to the first reference signal terminal VGH via the turned-on twenty-second transistor T22. In this case, the second node N2 is at a high level, thereby achieving a reset of the second node N2.

[0210] For example, referring to FIG13, the second reference signal terminal includes a first sub-reference signal terminal VGL1 and a second sub-reference signal terminal VGL; the first reference signal terminal includes a first reference sub-signal terminal VGH1 and a second reference sub-signal terminal VGH.

[0211] The above-mentioned multiple reference signal terminals enable more independent setting of reference voltage, realizing a scheme where different reference signal terminals provide voltage to different transistors, thereby improving circuit stability.

[0212] In one implementation, the voltage value of the first sub-reference signal terminal VGL1 is greater than or equal to the voltage value of the second sub-reference signal terminal VGL.

[0213] During implementation, setting the voltage values ​​of the first sub-reference signal terminal VGL1 and the second sub-reference signal terminal VGL to different values ​​can save some power consumption. On the other hand, setting the voltage value of the first sub-reference signal terminal VGL1 to be greater than or equal to the voltage value of the second sub-reference signal terminal VGL can enhance the output capability of the circuit.

[0214] That is, the voltage value acting on the first sub-reference signal terminal VGL1 of the output sub-circuit 304 is greater than or equal to the voltage value acting on the second sub-reference signal terminal VGL of the second input sub-circuit 302 and the node control sub-circuit 303. In this way, the noise between the second input sub-circuit 302, the node control sub-circuit 303 and the output sub-circuit 304 can be better isolated. After the second input sub-circuit 302 inputs the signal of the second sub-reference signal terminal VGL, the node control sub-circuit 303 can better control the signals of the pull-up node N4 and the pull-down node N5. At the same time, the output sub-circuit 304 can better output the voltage value of the first sub-reference signal terminal VGL1, thereby enhancing the output capability of the circuit.

[0215] Similarly, the voltage value of the second reference sub-signal terminal VGH is greater than or equal to the voltage value of the first reference sub-signal terminal VGH1.

[0216] That is, the voltage value of the second reference sub-signal terminal VGH acting on the node control sub-circuit 303 is greater than or equal to the voltage value of the first reference sub-signal terminal VGH1 acting on the output sub-circuit 304. In this way, the noise between the node control sub-circuit 303 and the output sub-circuit 304 can be better isolated, the node control sub-circuit 303 can better control the signals of the pull-up node N4 and the pull-down node N5, and at the same time, the output sub-circuit 304 can better output the voltage value of the first reference sub-signal terminal VGH1.

[0217] In this embodiment of the present disclosure, the second control signal terminal SW2 and the third control signal terminal SW3 in the above-mentioned source drive circuit can be multiplexed into one control signal terminal. When the second control signal terminal SW2 and the third control signal terminal SW3 are multiplexed into one control signal terminal, the second control signal terminal SW2 and the third control signal terminal SW3 can be connected to one of the multiple source control lines, thereby reducing the number of source control lines and saving the routing space in the non-display area.

[0218] For example, referring to Figures 3, 4, 6, 8 and 10, the third input subunit 3013 is configured to provide the signal of the second control signal terminal SW2 to the second node N2 in response to the signal of the first node N1.

[0219] During implementation, when the signal of the first node N1 is valid, the third input subunit 3013 is turned on, and the signal of the second control signal terminal SW2 is provided to the second node N2 through the turned-on third input subunit 3013.

[0220] For example, referring to FIG14, the third input subunit 3013 includes: a sixth transistor T6.

[0221] The control terminal of the sixth transistor T6 is coupled to the first node N1, the first terminal of the sixth transistor T6 is coupled to the second control signal terminal SW2, and the second terminal of the sixth transistor T6 is coupled to the second node N2.

[0222] For example, the sixth transistor T6 can be turned on under the control of the active level of the first node N1, and can be turned off under the control of the inactive level of the first node N1. For example, if the sixth transistor T6 is set as an N-type transistor, then the active level of the signal of the first node N1 is a high level, and the inactive level of the signal of the first node N1 is a low level. Alternatively, if the sixth transistor T6 is set as a P-type transistor, then the active level of the signal of the first node N1 is a low level, and the inactive level of the signal of the first node N1 is a high level.

[0223] Referring to Figure 14, the sixth transistor T6 is a P-type transistor. When the signal at the first node N1 is low, the sixth transistor T6 is turned on, and the second control signal terminal SW2 is connected to the second node N2 through the turned-on sixth transistor T6.

[0224] The following description, using the example of a source driving circuit provided in this embodiment where the first transistor T1 to the twenty-first transistor T21 are all P-type thin-film transistors, and in conjunction with the source driving circuit shown in Figure 15 and the timing diagram shown in Figure 16 or Figure 18, details the operation of a source driving circuit within one frame period. As shown in Figure 15, the source driving circuit provided in this embodiment includes 21 transistor units (T1 to T21), 4 capacitor units (C1 to C4), 8 input signal terminals (VGH, VGL, SW1, SW2, SW3, Datain, CK, and CB), and 1 output signal terminal (HOUT). The first reference signal terminal VGH continuously provides a high-level signal, the second reference signal terminal ELVSS continuously provides a low-level signal, the first clock signal terminal CK outputs a periodically changing first clock signal, and the second clock signal terminal CB outputs a periodically changing second clock signal. The waveforms of the first clock signal and the second clock signal are not completely synchronized, and the high-level time of the first clock signal and the second clock signal are slightly longer than the low-level time. As shown in Figure 16 or Figure 18, in stage T11, the signal at the first control signal terminal SW1 is an effective voltage signal, and at this time, the signal at the data signal terminal Datain is the scan start signal. In stages other than T11, the signal at the first control signal terminal SW1 is an invalid voltage signal, and at this time, the signal at the data signal terminal Datain is the data voltage signal. As shown in Figure 16, when it is necessary to drive the output terminal HOUT to output a high level, the scan start signal in the data signal terminal Datain is a high-level signal; as shown in Figure 18, when it is necessary to drive the output terminal HOUT to output a low level, the scan start signal in the data signal terminal Datain is a low-level signal.

[0225] Referring to Figures 15, 16, and 17, when the output terminal HOUT needs to be driven to output a high level, the operation process of this source drive circuit includes:

[0226] T11 stage: The signal of the first control signal terminal SW1 is low, the signal of the second control signal terminal SW2 is high, the signal of the third control signal terminal SW3 is high, the signal of the first clock signal terminal CK is low, the signal of the second clock signal terminal CB is high, and the signal of the data signal terminal Datain is high.

[0227] Since the effective voltage signal in the first control signal terminal SW1 is low, the first transistor T1 and the second transistor T2 are turned on. At this time, the high level in the data signal terminal Datain is written to the first node N1 through the turned-on first transistor T1. The high level in the first node N1 turns off the sixth transistor T6. The high level in the first reference signal terminal VGH is written to the second node N2 through the turned-on second transistor T2. The high level in the second node N2 turns off the eleventh transistor T11 and the seventeenth transistor T17. The signal in the second control signal terminal SW2 is high, and the third transistor T3 and the fourth transistor T4 are turned off. The low level signal in the second reference signal terminal VGL turns on the eighth transistor T8 and the ninth transistor T9. Thus, the high level in the second node N2 is provided to the fifth node N5 and the sixth node N6. The high level in the fifth node N5 turns off the eighteenth transistor T18 and the twentieth transistor T20, and the high level in the sixth node N6 turns off the thirteenth transistor T13 and the tenth transistor T10. When the first clock signal terminal CK is low, the seventh transistor T7 is turned on. The high level of the second control signal terminal SW2 is written to the third node N3, and the twelfth transistor T12 is turned off. The low level of the second reference signal terminal VGL turns on the fourteenth transistor T14. The high level of the third node N3 is provided to the eighth node N8, and the fifteenth transistor T15 is turned off. The second clock signal terminal CB is high, and the sixteenth transistor T16 is turned off. The fourth node, which is also the pull-up node N4, remains at its previous high level. The nineteenth transistor T19 and the fifth transistor T5 are turned off, and the drive output terminal HOUT remains at its previous low level output state.

[0228] T12 stage: The first control signal terminal SW1 jumps to a high level, the second control signal terminal SW2 remains at a high level, the third control signal terminal SW3 jumps from a high level to a low level, the first clock signal terminal CK jumps to a high level, and the second clock signal terminal CB jumps to a low level.

[0229] When the third control signal terminal SW3 transitions from high to low, the levels of the first node N1 and the second node N2 remain high as before due to the sixth transistor T6 being turned off. When the second clock signal terminal CB transitions to low, the low level of the second clock signal terminal CB cannot be written to the seventh node N7, the ninth node N9, and the fourth node N4 because the thirteenth transistor T13 and the fifteenth transistor T15 are turned off. Therefore, the fourth node N4 and the fifth node N5 remain high, the nineteenth transistor T19 and the eighteenth transistor T18 remain off, and the drive output terminal HOUT remains low.

[0230] T13 stage: The driving timing is the same as T11 stage.

[0231] T14 stage: The driving timing is the same as T12 stage.

[0232] T15 stage: The first control signal terminal SW1 remains high, the second control signal terminal SW2 changes from high to low, the third control signal terminal SW3 remains low, the first clock signal terminal CK changes to low, and the second clock signal terminal CB changes to high.

[0233] The second control signal terminal SW2 jumps from high level to low level, the first clock signal terminal CK jumps to low level, the seventh transistor T7 is turned on, the third node N3 and the eighth node N8 are written to VGL-Vth, the fifteenth transistor T15 is turned on, and the potentials of other nodes remain unchanged.

[0234] T16 stage: The first control signal terminal SW1 remains high, the second control signal terminal SW2 remains low, the third control signal terminal SW3 remains low, the first clock signal terminal CK jumps to high, and the second clock signal terminal CB jumps to low.

[0235] When the second clock signal terminal CB jumps low, the sixteenth transistor T16 turns on, pulling the potentials of the ninth node N9 and the fourth node N4 low. Through the coupling of the third capacitor C3, the potential of the eighth node N8 is further pulled low. The low level of the fourth node N4 turns on the nineteenth transistor T19 and the fifth transistor T5. The nineteenth transistor T19 pulls the signal output terminal HOUT high to the high level of the first reference signal terminal VGH. The low level of the second control signal terminal SW2 turns on the third transistor T3 and the fourth transistor T4. The levels of the second node N2 and the first node N1 stabilize at the high level of the first reference signal terminal VGH. The high level of the second node N2 is transmitted to the fifth node N5 and the sixth node N6 through the turned-on eighth transistor T8 and ninth transistor T9. The high level of the fifth node N5 and the signal output terminal HOUT turns off the twentieth transistor T20 and the twenty-first transistor T21.

[0236] T17 stage: The first control signal terminal SW1 remains high, the second control signal terminal SW2 remains low, the third control signal terminal SW3 remains low, the first clock signal terminal CK jumps to low, and the second clock signal terminal CB jumps to high.

[0237] When the second clock signal terminal CB goes high, the potentials of the ninth node N9 and the eighth node N8 also go high. However, the high level of the second clock signal terminal CB turns off the sixteenth transistor T16, and the fourth node N4 remains low. When the first clock signal terminal CK goes low, the seventh transistor T7 turns on, and the third node N3 remains low. The high level of the second node N2 turns off the eleventh transistor T11, and the other nodes maintain the state of the previous stage, driving the output terminal HOUT to stably output a high level potential.

[0238] Referring to Figures 15, 18, and 19, the operation of this source drive circuit when the output terminal HOUT needs to be driven to output a low level includes:

[0239] K11 stage: The signal of the first control signal terminal SW1 is low, the signal of the second control signal terminal SW2 is high, the signal of the third control signal terminal SW3 is high, the signal of the first clock signal terminal CK is low, the signal of the second clock signal terminal CB is high, and the signal of the data signal terminal Datain is high.

[0240] Since the effective voltage signal in the first control signal terminal SW1 is low, the first transistor T1 and the second transistor T2 are turned on. At this time, the low level in the data signal terminal Datain (for example, between 0 and 0.5V) is written to the first node N1 through the turned-on first transistor T1, and the sixth transistor T6 is turned on. The high level in the first reference signal terminal VGH is written to the second node N2 through the turned-on second transistor T2, and the eleventh transistor T11 and the seventeenth transistor T17 are turned off. The signal in the second control signal terminal SW2 is high, and the third transistor T3 and the fourth transistor T4 are turned off. The low level signal in the second reference signal terminal VGL turns on the eighth transistor T8 and the ninth transistor T9. Thus, the high level in the second node N2 is provided to the fifth node N5 and the sixth node N6. The high level in the fifth node N5 turns off the eighteenth transistor T18 and the twentieth transistor T20, and the high level in the sixth node N6 turns off the thirteenth transistor T13 and the tenth transistor T10. When the first clock signal terminal CK is low, the seventh transistor T7 is turned on. The high level of the second control signal terminal SW2 is written to the third node N3, and the twelfth transistor T12 is turned off. The low level of the second reference signal terminal VGL turns on the fourteenth transistor T14. The high level of the third node N3 is provided to the eighth node N8, and the fifteenth transistor T15 is turned off. The second clock signal terminal CB is high, and the sixteenth transistor T16 is turned off. The fourth node, which is also the pull-up node N4, remains at its previous high level. The nineteenth transistor T19 and the fifth transistor T5 are turned off, and the drive output terminal HOUT remains at its previous high level.

[0241] K12 stage: The first control signal terminal SW1 jumps to a high level, the second control signal terminal SW2 remains at a high level, the third control signal terminal SW3 jumps from a high level to a low level, the first clock signal terminal CK jumps to a high level, and the second clock signal terminal CB jumps to a low level.

[0242] When the second clock signal terminal CB jumps to a low level, since the third node N3 and the first node N1 are at a high level, the fifteenth transistor T15 is turned off. The low level of the second clock signal terminal CB cannot be written to the ninth node N9 and the fourth node N4. Therefore, the ninth node N9 and the fourth node N4 remain at their previous high levels, the nineteenth transistor T19 and the eighteenth transistor T18 remain off, and the drive output terminal HOUT remains in its previous low-level output state. The third control signal terminal SW3 transitions from high to low. Because the sixth transistor T6 is turned on, the level of the second node N2 is pulled low. Due to the presence of the first capacitor C1, the level of the first node N1 is coupled low. The sixth transistor T6 is fully turned on, and the second node N2 is written with a low level. The low level of the second node N2 is transmitted to the fifth node N5 and the sixth node N6 through the conducting eighth transistor T8 and ninth transistor T9. The eighteenth transistor T18 is turned on, pulling the signal output terminal HOUT low to the low level of the second reference signal terminal VGL. The fifth node N5 is further pulled low by the capacitive coupling of the eighteenth transistor T18. The low level of the second node N2 turns on the seventeenth transistor T17, pulling the level of the fourth node N4 high. The nineteenth transistor T19 is turned off to avoid affecting the low level of the drive output terminal HOUT. The low level of the sixth node N6 turns on the thirteenth transistor T13. The low level of the second clock signal terminal CB is charged into the seventh node N7 through the conducting thirteenth transistor T13.

[0243] K13 stage: The first control signal terminal SW1 is at a high level, the second control signal terminal SW2 remains at a high level, the third control signal terminal SW3 is at a low level, the first clock signal terminal CK jumps to a low level, and the second clock signal terminal CB jumps to a high level.

[0244] The low level of the first clock signal terminal CK turns on the seventh transistor T7, and the third node N3 remains at a high level. The high level of the second clock signal terminal CB is written to the seventh node N7 through the turned-on thirteenth transistor T13, and the remaining nodes maintain the potential of the previous stage.

[0245] K14 stage: The first control signal terminal SW1 is at a high level, the second control signal terminal SW2 remains at a high level, the third control signal terminal SW3 is at a low level, the first clock signal terminal CK jumps to a high level, and the second clock signal terminal CB jumps to a low level.

[0246] When the first clock signal terminal CK is high, the level of the third node N3 is pulled high through the conducting eleventh transistor T11, and the level of the eighth node N8 is pulled high through the conducting fourteenth transistor T14. The fifteenth transistor T15 is turned off, and the low level of the second clock signal terminal CB cannot be written to the ninth node N9 and the fourth node N4. The low level of the sixth node N6 turns on the thirteenth transistor T13, and the low level of the second clock signal terminal CB is charged into the seventh node N7. Due to the coupling effect of the second capacitor C2, the potential of the sixth node N6 is pulled low, and the tenth transistor T10 turns on, further pulling the potential of the fifth node N5 low, fully turning on the eighteenth transistor T18, driving the output terminal HOUT to be in a fully low output state.

[0247] K15 stage: The first control signal terminal SW1 is at a high level, the second control signal terminal SW2 changes from a high level to a low level, the third control signal terminal SW3 is at a low level, the first clock signal terminal CK changes to a low level, and the second clock signal terminal CB changes to a high level.

[0248] When the second control signal terminal SW2 jumps from high to low, the first clock signal terminal CK jumps to low, the seventh transistor T7 turns on, the low level of the second control signal terminal SW2 is transmitted to the third node N3 through the turned-on seventh transistor T7, the low level of the third node N3 is transmitted to the eighth node N8 through the turned-on fourteenth transistor T14, the fifteenth transistor T15 turns on, the high level of the second clock signal terminal CB is written to the ninth node N9 and the fourth node N4 through the turned-on fifteenth transistor T15 and sixteenth transistor T16, and the nineteenth transistor T19 turns off.

[0249] K16 stage: The first control signal terminal SW1 remains high, the second control signal terminal SW2 remains low, the third control signal terminal SW3 remains low, the first clock signal terminal CK jumps to high, and the second clock signal terminal CB jumps to low.

[0250] When the first clock signal terminal CK goes high, the seventh transistor T7 turns off. The low level of the second node N2 turns on the eleventh transistor T11. The high level of the first clock signal terminal CK is provided to the third node N3 through the turned-on eleventh transistor T11. The high level of the third node N3 is transmitted to the eighth node N8 through the turned-on fourteenth transistor T14. The fifteenth transistor T15 turns off. The low level of the second clock signal terminal CB cannot be written to the ninth node N9 and the fourth node N4. The low level of the sixth node N6 turns on the thirteenth transistor T13. The low level of the second clock signal terminal CB is charged into the seventh node N7. Due to the coupling effect of the second capacitor C2, the potential of the sixth node N6 is pulled low. The tenth transistor T10 turns on, further pulling down the potential of the fifth node N5, fully turning on the eighteenth transistor T18, driving the output terminal HOUT to be in a fully low output state. The low level of the fifth node N5 turns on the twentieth transistor T20, and the low level output of the drive output terminal HOUT turns on the twenty-first transistor T21, ensuring that the level of the sixth node N6 is always low.

[0251] K17 stage: The first control signal terminal SW1 remains high, the second control signal terminal SW2 remains low, the third control signal terminal SW3 remains low, the first clock signal terminal CK jumps to low, and the second clock signal terminal CB jumps to high.

[0252] When the first clock signal terminal CK goes low, the seventh transistor T7 turns on, and the third node N3 remains low. When the second clock signal terminal CB goes high, the potentials of the ninth node N9 and the eighth node N8 also go high, but the high level of the second clock signal terminal CB turns off the sixteenth transistor T16, and the fourth node N4 remains high. The drive output terminal HOUT outputs a stable low level potential.

[0253] Based on the same inventive concept, referring to Figure 20, this disclosure provides a display panel, including: a display area, including multiple sub-pixels, multiple column refresh lines and multiple data lines, each sub-pixel including a light-emitting device and a pixel driving circuit connected to the light-emitting device, a column refresh line connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels, and a data line connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels.

[0254] In this embodiment, to achieve partial refresh of the display panel along the column direction, a matching column refresh line is provided for each data line in the display area, and this column refresh line is arranged parallel to the data line. Simultaneously, the pixel driving circuit included in each sub-pixel is connected to the column refresh line and the data line.

[0255] The non-display area includes multiple source control lines and multiple source drive circuits as described above. The multiple source control lines include a first source control line and a second source control line, or a first source control line, a second source control line, and a third source control line. The drive output terminal HOUT of one of the multiple source drive circuits is connected to one of the multiple column refresh lines. The data signal terminal Datain of one of the multiple source drive circuits is connected to one of the multiple data lines. The first control signal terminal SW1 of one of the multiple source drive circuits is connected to one of the multiple source control lines. The second control signal terminal SW2 of one of the multiple source drive circuits is connected to one of the multiple source control lines. The third control signal terminal of one of the multiple source drive circuits is connected to one of the multiple source control lines or one of the multiple source control lines.

[0256] In some examples, when the second control signal terminal SW2 and the third control signal terminal SW3 in the source drive circuit are not multiplexed as a single control signal terminal, the third control signal terminal SW3 of one of the multiple source drive circuits is connected to one of the multiple source control lines.

[0257] In other examples, when the second control signal terminal SW2 and the third control signal terminal SW3 in the source drive circuit are multiplexed into a single control signal terminal, the third control signal terminal SW3 of one of the multiple source drive circuits is connected to one of the second source control lines among the multiple source control lines.

[0258] To connect the source driver circuit and the source chip, in this embodiment, multiple source control lines are provided in the non-display area of ​​the display panel. That is, multiple source control lines are provided for each source driver circuit. The source chip sends signals to the first control signal terminal SW1, the second control signal terminal SW2, and the third control signal terminal SW3 of the source driver circuit through these source control lines. Simultaneously, the source chip also sends sequentially occurring scan start signals and data voltage signals to the data lines. These sequentially occurring scan start signals and data voltage signals are sent to the source driver circuit, allowing the data signal terminal Datain of the source driver circuit to receive them. After the drive output terminal HOUT of the source driver circuit generates a signal, it sends the signal from the drive output terminal HOUT to the pixel driver circuit through the column refresh line, exemplarily the third scan signal terminal C_Gate (i.e., the first terminal of the first switching transistor M8) shown in Figure 1. This updates the data voltage of the pixel driver circuit, thereby refreshing the display of the connected data lines.

[0259] For example, referring to FIG1, a pixel driving circuit includes: a first switching transistor M8 and a second switching transistor M9, wherein the first switching transistor M8 and the second switching transistor M9 are of different types.

[0260] Referring to Figure 1, the control terminal of the second switching transistor M9 is coupled to the second scan signal terminal N_Gate connected to the sub-pixel, the first terminal of the second switching transistor M9 is coupled to the second reference signal terminal VGL, and the second terminal of the second switching transistor M9 is coupled to the first terminal of the first switching transistor M8.

[0261] During implementation, when the signal of the second scan signal terminal N_Gate is high, the second switching transistor M9 is turned on. The signal of the second reference signal terminal VGL is provided to the control terminal of the conduction control transistor M10 through the turned-on second switching transistor M9, causing the conduction control transistor M10 to turn off. This results in the control terminal of the driving transistor M3 being disconnected from the first terminal of the driving transistor M3, preventing data voltage from being written to the control terminal of the driving transistor M3, and preventing the corresponding sub-pixel from being refreshed.

[0262] Referring to Figure 1, the control terminal of the first switching transistor M8 is coupled to the second scan signal terminal N_Gate connected to the sub-pixel, the first terminal of the first switching transistor M8 is coupled to the control terminal of the conduction control transistor M10, and the second terminal of the first switching transistor M8 is coupled to the third scan signal terminal C_Gate connected to the sub-pixel. The first terminal of the conduction control transistor M10 is coupled to the control terminal of the driving transistor M3, and the second terminal of the conduction control transistor M10 is coupled to the first terminal of the driving transistor M3.

[0263] During implementation, when the signal of the second scan signal terminal N_Gate is low, the first switching transistor M8 is turned on. The signal of the third scan signal terminal C_Gate is provided to the control terminal of the conduction control transistor M10 through the turned-on first switching transistor M8, so that the conduction control transistor M10 is turned on, thereby making the control terminal of the driving transistor M3 and the first terminal of the driving transistor M3 in a conducting state. The data voltage is written to the control terminal of the driving transistor M3, and the corresponding sub-pixel is refreshed.

[0264] It should also be noted that the aforementioned third scan signal terminal C_Gate is coupled to the column refresh line connected to the sub-pixel. That is, after the source drive circuit generates a signal, it will send the signal of the aforementioned drive output terminal HOUT to the third scan signal terminal C_Gate in the pixel drive circuit through the column refresh line, so as to control whether the corresponding sub-pixel should be updated with data voltage.

[0265] Based on the same inventive concept, referring to Figures 21 and 22, this disclosure provides a display device, including a display panel as described above and at least one source chip.

[0266] The source chip is coupled to at least some of the data lines and at least some of the source control lines of the display panel. The source chip is configured to sequentially output a scan start signal and a data voltage signal to the data lines connected to it during one frame of display time, and to output an effective voltage signal to the first source control line.

[0267] In this embodiment of the present disclosure, the source chip is connected to the display panel, and the source chip and the display panel are used in conjunction to enable the display panel to refresh in the column direction.

[0268] During implementation, within one frame of display time on the display panel, the source chip sequentially outputs a scan start signal and a data voltage signal to the data line connected to it. After being sent to the data line, these sequentially output scan start signal and data voltage signal are further sent to the aforementioned source drive circuit. In addition, the source chip also outputs an effective voltage signal to the first source control line, and this effective voltage signal is also supplied to the source drive circuit via the first source control line, thereby enabling the source drive circuit to operate.

[0269] It should be noted that the HCT pulse shown in Figure 22 is the aforementioned scan start signal. In this embodiment, the scan start signal can be either a first scan start signal or a second scan start signal. When it is necessary to drive the output terminal HOUT to output a high level, the effective level of the scan start signal is the high level of the HCT pulse, i.e., the first scan start signal; when it is necessary to drive the output terminal HOUT to output a low level, the effective level of the scan start signal is the low level of the HCT pulse, i.e., the second scan start signal.

[0270] The display device provided in the embodiments of this disclosure can be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0271] Based on the same inventive concept, referring to Figure 23, this disclosure provides a first driving method for a source driving circuit applied to any of the above claims, including:

[0272] Step 2301: Input Phase: The first input sub-unit 3011, in response to the valid voltage signal in the first control signal terminal SW1, provides the first scan start signal in the data signal terminal Datain to the first node N1, and provides the signal in the first reference signal terminal VGH to the second node N2. The second input sub-circuit 302, in response to the signal in the first clock signal terminal CK, provides the invalid level signal in the second control signal terminal SW2 to the third node N3. The node control sub-circuit 303, based on the signals from the second node N2 and the third node N3, controls the signals of the pull-up node N4 and the pull-down node N5 to maintain a holding state.

[0273] During implementation, when a valid voltage signal is input to the first control signal terminal SW1, the first input sub-unit 3011 is turned on. The scan start signal in the data signal terminal Datain is provided to the first node N1 through the turned-on first input sub-unit 3011, and the signal of the first reference signal terminal VGH is provided to the second node N2 through the turned-on first input sub-unit 3011. When the signal of the first clock signal terminal CK is at a valid level, the second input sub-circuit 302 is turned on. The invalid level signal in the signal of the second control signal terminal SW2 is provided to the third node N3 through the turned-on second input sub-circuit 302 (that is, the third node N3 is maintained at an invalid level). In this way, the node control sub-circuit 303 controls the signals of the pull-up node N4 and the pull-down node N5 to maintain a sustained state based on the signals of the second node N2 and the third node N3.

[0274] Step 2302: Output Stage: In response to the signal from pull-up node N4 and the signal from the second control signal terminal SW2, the second input sub-unit 3012 provides the signal from the first reference signal terminal VGH to the second node N2. In response to the signal from the first clock signal terminal CK, the second input sub-circuit 302 provides the valid level signal from the signal from the second control signal terminal to the third node N3 (i.e., maintains the third node N3 at a valid level). The node control sub-circuit 303 controls the signal from pull-up node N4 to be valid based on the signals from the second node N2 and the third node N3. The output sub-circuit 304, in response to the signal from pull-up node N4, provides the signal from the first reference signal terminal VGH to the drive output terminal HOUT.

[0275] During implementation, when an invalid voltage signal is input to the first control signal terminal SW1 (i.e., during any time period other than when an valid voltage signal appears within a display frame), the first input sub-unit 3011 is disconnected. However, a valid voltage signal is input to the second control signal terminal SW2, and the pull-up node remains at a valid level. The second input sub-unit 3012 then conducts, providing the signal from the first reference signal terminal VGH to the second node N2. When the signal from the first clock signal terminal CK is at a valid level, the second input sub-circuit 302 conducts, and the third node N3 remains at a valid level. Thus, the node control sub-circuit 303 controls the signal of the pull-up node N4 to be valid based on the signals from the second node N2 and the third node N3. The output sub-circuit 304, responding to the signal from the pull-up node N4, provides the signal from the first reference signal terminal VGH to the drive output terminal HOUT. Referring to Figure 17, the drive output terminal HOUT outputs a high-level signal.

[0276] Based on the same inventive concept, referring to Figure 24, this disclosure provides a second driving method for a source drive circuit applied to any of the above claims, including:

[0277] Step 2401: Input Phase: The first input sub-unit 3011, in response to the valid voltage signal in the first control signal terminal SW1, provides the second scan start signal in the data signal terminal Datain to the first node N1, and provides the signal in the first reference signal terminal VGH to the second node N2. The second input sub-circuit 302, in response to the signal in the first clock signal terminal CK, provides the invalid level signal in the second control signal terminal to the third node N3 (i.e., maintains the third node N3 at an invalid level). The node control sub-circuit 303, based on the signals of the second node N2 and the third node N3, controls the signals of the pull-up node N4 and the pull-down node N5 to be in a sustained state.

[0278] During implementation, when a valid voltage signal is input to the first control signal terminal SW1, the first input sub-unit 3011 is turned on. The scan start signal in the data signal terminal Datain is provided to the first node N1 through the turned-on first input sub-unit 3011, and the signal of the first reference signal terminal VGH is provided to the second node N2 through the turned-on first input sub-unit 3011. When the signal of the first clock signal terminal CK is at a valid level, the second input sub-circuit 302 is turned on. The invalid level signal in the signal of the second control signal terminal SW2 is provided to the third node N3 through the turned-on second input sub-circuit 302 (that is, the third node N3 is maintained at an invalid level). In this way, the node control sub-circuit 303 controls the signals of the pull-up node N4 and the pull-down node N5 to maintain a sustained state based on the signals of the second node N2 and the third node N3.

[0279] Step 2402: Output Stage: In response to the signal from the first node N1, the third input sub-unit 3013 provides the signal from the third control signal terminal SW3 to the second node N2. The node control sub-circuit 303 controls the signal from the pull-down node N5 to be active based on the signal from the second node N2. In response to the signal from the pull-down node N5, the output sub-circuit 304 provides the signal from the second reference signal terminal VGL to the drive output terminal HOUT.

[0280] During implementation, since the first node N1 is at an active level, the third input sub-unit 3013 is turned on, providing the signal of the third control signal terminal SW3 to the second node N2. The node control sub-circuit 303, based on the signal of the second node N2, controls the signal of the pull-down node N5 to be active. Simultaneously, the node control sub-circuit 303 can further pull down the level of the pull-down node N5. Thus, the output sub-circuit 304, responding to the signal of the pull-down node N5, can fully provide the signal of the second reference signal terminal VGL to the drive output terminal HOUT. Referring to Figure 19, the drive output terminal HOUT outputs a low-level signal.

[0281] In summary, this disclosure provides a source driving circuit, a display panel, a display device, and a driving method. The source driving circuit includes a first input sub-circuit, a second input sub-circuit, a node control sub-circuit, and an output sub-circuit. The first input sub-circuit includes a first input sub-unit, a second input sub-unit, and a third input sub-unit. The first input sub-unit is configured to, in response to an effective voltage signal in a signal at a first control signal terminal, provide a first scan start signal in a signal at a data signal terminal to a first node and provide a signal at a first reference signal terminal to a second node. During one frame of display time, the signal at the first control signal terminal includes one effective voltage signal, and the signal at the data signal terminal includes a scan start signal and a data voltage signal appearing sequentially. The second input sub-unit is configured to, in response to a signal at a pull-up node and a first scan start signal, provide a first scan start signal in a signal at a data signal terminal to a first node and a first scan start signal to a second node. The signal from the second control signal terminal is provided to the second node, and the signal from the first reference signal terminal is provided to the second node in response to the signal from the first node. The third input sub-unit is configured to provide the signal from the third control signal terminal to the second node in response to the signal from the first clock signal terminal. The node control sub-circuit is configured to control the signals of the pull-up node and the pull-down node according to the signals from the second node and the third node. The output sub-circuit is configured to provide the signal from the first reference signal terminal to the drive output terminal in response to the signal from the pull-up node, and to provide the signal from the second reference signal terminal to the drive output terminal in response to the signal from the pull-down node. Through the above source drive circuit settings, partial refresh of some columns in the display panel can be realized, thereby saving power consumption while ensuring display effect.

[0282] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0283] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0284] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0285] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0286] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A source drive circuit, wherein, include: The circuit comprises a first input sub-circuit, a second input sub-circuit, a node control sub-circuit, and an output sub-circuit, wherein the first input sub-circuit includes a first input sub-unit, a second input sub-unit, and a third input sub-unit; The first input subunit is configured to provide a scan start signal from the data signal to a first node and a signal from a first reference signal to a second node in response to an effective voltage signal in the signal of the first control signal terminal, and to provide the scan start signal from the data signal terminal to the first node in response to an effective voltage signal in the signal of the first control signal terminal within one frame display time, wherein the signal of the first control signal terminal includes one effective voltage signal and the signal of the data signal terminal includes a scan start signal and a data voltage signal that appear sequentially. The second input subunit is configured to provide the signal from the first reference signal terminal to the second node in response to the signal from the pull-up node and the signal from the second control signal terminal; The third input subunit is configured to provide a signal from the third control signal terminal to the second node in response to a signal from the first node. The second input sub-circuit is configured to provide the signal from the second control signal terminal to the third node in response to the signal from the first clock signal terminal; The node control subcircuit is configured to control the signals of the pull-up node and the pull-down node based on the signals of the second node and the third node; The output sub-circuit is configured to provide the signal at the first reference signal terminal to the drive output terminal in response to the signal at the pull-up node. In response to the signal from the pull-down node, the signal from the second reference signal terminal is provided to the drive output terminal.

2. The source drive circuit according to claim 1, wherein, The first input sub-unit includes: a first transistor and a second transistor; The control terminal of the first transistor is coupled to the first control signal terminal, the first terminal of the first transistor is coupled to the data signal terminal, and the second terminal of the first transistor is coupled to the first node. The control terminal of the second transistor is coupled to the first control signal terminal, the first terminal of the second transistor is coupled to the first reference signal terminal, and the second terminal of the second transistor is coupled to the second node.

3. The source drive circuit according to claim 1, wherein, The second input sub-unit includes: a third transistor, a fourth transistor, and a fifth transistor; The control terminal of the third transistor is coupled to the second control signal terminal, the first terminal of the third transistor is coupled to the second terminal of the fifth transistor, and the second terminal of the third transistor is coupled to the first node; The control terminal of the fourth transistor is coupled to the second control signal terminal, the first terminal of the fourth transistor is coupled to the second terminal of the fifth transistor, and the second terminal of the fourth transistor is coupled to the second node; The control terminal of the fifth transistor is coupled to the pull-up node, and the first terminal of the fifth transistor is coupled to the first reference signal terminal.

4. The source drive circuit according to claim 1, wherein, The third input subunit includes: a sixth transistor; The control terminal of the sixth transistor is coupled to the first node, the first terminal of the sixth transistor is coupled to the third control signal terminal, and the second terminal of the sixth transistor is coupled to the second node.

5. The source drive circuit according to claim 4, wherein, The third input subunit further includes: a first capacitor; The first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the second node.

6. The source drive circuit according to claim 1, wherein, The node control sub-circuit includes: a first control sub-unit, a second control sub-unit, and a third control sub-unit; The first control subunit is coupled to the second node, the sixth node, the second reference signal terminal and the pull-down node. The first control subunit is configured to provide the signal of the second node to the pull-down node in response to the signal of the second reference signal terminal, and to provide the signal of the second node to the sixth node in response to the signal of the second reference signal terminal, and to provide the signal of the sixth node to the pull-down node in response to the signal of the sixth node. The second control subunit is coupled to the second node, the third node, the first reference signal terminal, the first clock signal terminal, the second clock signal terminal, and the sixth node. The second control subunit is configured to provide the signal of the first clock signal terminal to the third node in response to a signal from the second node; to provide the signal of the first reference signal terminal to the seventh node in response to a signal from the third node; and to provide the signal of the second clock signal terminal to the seventh node in response to a signal from the sixth node. The third control subunit is coupled to the second node, the third node, the second reference signal terminal, the second clock signal terminal, the first reference signal terminal, and the pull-up node. The third control subunit is configured to provide the signal of the second clock signal terminal to the pull-up node in response to the signals of the second reference signal terminal, the third node, and the second clock signal terminal; and to provide the signal of the first reference signal terminal to the pull-up node in response to the signal of the second node.

7. The source drive circuit according to claim 6, wherein, The first control subunit includes: an eighth transistor, a ninth transistor, and a tenth transistor; The control terminal of the eighth transistor is coupled to the second reference signal terminal, the first terminal of the eighth transistor is coupled to the second node, and the second terminal of the eighth transistor is coupled to the pull-down node. The control terminal of the ninth transistor is coupled to the second reference signal terminal, the first terminal of the ninth transistor is coupled to the second node, and the second terminal of the ninth transistor is coupled to the sixth node. The control terminal of the tenth transistor is coupled to the sixth node, the first terminal of the tenth transistor is coupled to the sixth node, and the second terminal of the tenth transistor is coupled to the pull-down node.

8. The source drive circuit according to claim 6, wherein, The second control subunit includes: an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a second capacitor; The control terminal of the eleventh transistor is coupled to the second node, the first terminal of the eleventh transistor is coupled to the first clock signal terminal, and the second terminal of the eleventh transistor is coupled to the third node. The control terminal of the twelfth transistor is coupled to the third node, the first terminal of the twelfth transistor is coupled to the seventh node, and the second terminal of the twelfth transistor is coupled to the first reference signal terminal. The control terminal of the thirteenth transistor is coupled to the sixth node, the first terminal of the thirteenth transistor is coupled to the second clock signal terminal, and the second terminal of the thirteenth transistor is coupled to the seventh node. The first end of the second capacitor is coupled to the sixth node, and the second end of the second capacitor is coupled to the seventh node.

9. The source drive circuit according to claim 6, wherein, The third control subunit includes: a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a third capacitor; The control terminal of the fourteenth transistor is coupled to the second reference voltage signal terminal, the first terminal of the fourteenth transistor is coupled to the third node, and the second terminal of the fourteenth transistor is coupled to the first terminal of the third capacitor. The control terminal of the fifteenth transistor is coupled to the first terminal of the third capacitor, the first terminal of the fifteenth transistor is coupled to the second terminal of the third capacitor, and the second terminal of the fifteenth transistor is coupled to the second clock signal terminal. The control terminal of the sixteenth transistor is coupled to the second clock signal terminal, the first terminal of the sixteenth transistor is coupled to the second terminal of the third capacitor, and the second terminal of the sixteenth transistor is coupled to the pull-up node; The control terminal of the seventeenth transistor is coupled to the second node, the first terminal of the seventeenth transistor is coupled to the first reference signal terminal, and the second terminal of the seventeenth transistor is coupled to the pull-up node.

10. The source drive circuit according to any one of claims 1 to 9, wherein, The output sub-circuit includes: an eighteenth transistor, a fourth capacitor, and a nineteenth transistor; The control terminal of the eighteenth transistor is coupled to the pull-down node, the first terminal of the eighteenth transistor is coupled to the second reference signal terminal, and the second terminal of the eighteenth transistor is coupled to the drive output terminal. The first end of the fourth capacitor is coupled to the pull-up node, and the second end of the fourth capacitor is coupled to the first reference signal terminal. The control terminal of the nineteenth transistor is coupled to the pull-up node, the first terminal of the nineteenth transistor is coupled to the drive output terminal, and the second terminal of the nineteenth transistor is coupled to the first reference signal terminal.

11. The source drive circuit according to any one of claims 6 to 9, wherein, It also includes the first pull-down control sub-circuit; The first pull-down control subcircuit is configured to provide a signal from the second reference signal terminal to the sixth node in response to at least one of the following: a signal from the drive output terminal, the pull-down node, the first node, or the second node.

12. The source drive circuit according to claim 11, wherein, The first pull-down control sub-circuit includes: a twentieth transistor; The control terminal of the twentieth transistor is coupled to at least one of the following: the drive output terminal, the pull-down node, the first node or the second node, the first terminal of the twentieth transistor is coupled to the second reference signal terminal, and the second terminal of the twentieth transistor is coupled to the sixth node.

13. The source drive circuit according to claim 11, wherein, It also includes a second pull-down control sub-circuit; The first pull-down control sub-circuit is coupled to the second reference signal terminal via the second pull-down control sub-circuit. The second pull-down control sub-circuit is configured to provide the signal of the second reference signal terminal to the first pull-down control sub-circuit in response to the signal of the drive output terminal.

14. The source drive circuit according to claim 13, wherein, The second pull-down control sub-circuit includes: a twenty-first transistor; The control terminal of the 21st transistor is coupled to the drive output terminal, the first terminal of the 21st transistor is coupled to the first pull-down control sub-circuit, and the second terminal of the 21st transistor is coupled to the second reference signal terminal.

15. The source drive circuit according to any one of claims 1 to 14, wherein, It also includes a reset circuit; The reset sub-circuit is configured to provide a signal from the first reference signal terminal to the second node in response to a signal from the node control signal terminal.

16. The source drive circuit according to claim 15, wherein, The reset sub-circuit includes: a twenty-second transistor; The control terminal of the twelfth transistor is coupled to the node control signal terminal, the first terminal of the twelfth transistor is coupled to the second node, and the second terminal of the twelfth transistor is coupled to the first reference signal terminal.

17. The source drive circuit according to any one of claims 1 to 16, wherein, The second reference signal terminal includes a first sub-reference signal terminal and a second sub-reference signal terminal; The first reference signal terminal includes a first reference sub-signal terminal and a second reference sub-signal terminal.

18. The source drive circuit according to claim 17, wherein, The voltage value at the first sub-reference signal terminal is greater than or equal to the voltage value at the second sub-reference signal terminal.

19. The source drive circuit according to claim 17, wherein, The voltage value at the second reference sub-signal terminal is greater than or equal to the voltage value at the first reference sub-signal terminal.

20. A display panel, wherein, include: The display area includes multiple sub-pixels, multiple column refresh lines, and multiple data lines. Each sub-pixel includes a light-emitting device and a pixel driving circuit connected to the light-emitting device. One column refresh line is connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels, and one data line is connected to the pixel driving circuit of at least some sub-pixels in a column of sub-pixels. The non-display area includes multiple source control lines and multiple source drive circuits as described in any one of claims 1 to 19. The multiple source control lines include a first source control line and a second source control line, or a first source control line, a second source control line, and a third source control line. The drive output terminal of one of the multiple source drive circuits is connected to one of the multiple column refresh lines. The data signal terminal of one of the multiple source drive circuits is connected to one of the multiple data lines. The first control signal terminal of one of the multiple source drive circuits is connected to one of the first source control lines. The second control signal terminal of one of the multiple source drive circuits is connected to one of the second source control lines. The third control signal terminal of one of the multiple source drive circuits is connected to one of the second or third source control lines.

21. The display panel according to claim 20, wherein, The pixel driving circuit includes: a first switching transistor and a second switching transistor, wherein the first switching transistor and the second switching transistor are of different types; The control terminal of the first switching transistor is coupled to the second scan signal terminal connected to the sub-pixel, the first terminal of the first switching transistor is coupled to the control terminal of the turn-on control transistor, and the second terminal of the first switching transistor is coupled to the third scan signal terminal connected to the sub-pixel. The control terminal of the second switching transistor is coupled to the second scan signal terminal connected to the sub-pixel. The first terminal of the second switching transistor is coupled to the second reference signal terminal. The second terminal of the second switching transistor is coupled to the first terminal of the first switching transistor. The first terminal of the turn-on control transistor is coupled to the control terminal of the driving transistor. The second terminal of the turn-on control transistor is coupled to the first terminal of the driving transistor. The third scan signal terminal is coupled to the column refresh line connected to the sub-pixel.

22. A display device, wherein, include: The display panel and at least one source chip as described in any one of claims 20 to 21; The source chip is coupled to at least some of the data lines and at least some of the source control lines of the display panel. The source chip is configured to sequentially output a scan start signal and a data voltage signal to the data lines connected to it within one frame display time, and to output an effective voltage signal to the first source control line, and to output corresponding control signals to the second source control line, or the second source control line and the third source control line.

23. A first driving method applied to the source driving circuit as described in any one of claims 1 to 19, wherein, include: The first input sub-unit responds to the effective voltage signal in the signal of the first control signal terminal by providing the first scan start signal in the signal of the data signal terminal to the first node and providing the signal of the first reference signal terminal to the second node; the second input sub-circuit responds to the signal of the first clock signal terminal by providing the invalid level signal in the signal of the second control signal terminal to the third node; The node control sub-circuit controls the signals of the pull-up node and the pull-down node to maintain a state based on the signals of the second node and the third node; The second input sub-unit, in response to the signal from the pull-up node and the signal from the second control signal terminal, provides the signal from the first reference signal terminal to the second node; the second input sub-circuit, in response to the signal from the first clock signal terminal, provides the valid level signal from the signal from the second control signal terminal to the third node; the node control sub-circuit controls the signal from the pull-up node to be in a valid state according to the signals from the second node and the third node; and the output sub-circuit, in response to the signal from the pull-up node, provides the signal from the first reference signal terminal to the drive output terminal.

24. A second driving method applied to a driving circuit as described in any one of claims 1 to 19, wherein, include: The first input sub-unit, in response to the effective voltage signal in the signal of the first control signal terminal, provides the second scan start signal in the signal of the data signal terminal to the first node and provides the signal of the first reference signal terminal to the second node; the second input sub-circuit, in response to the signal of the first clock signal terminal, provides the invalid level signal in the signal of the second control signal terminal to the third node; the node control sub-circuit controls the signals of the pull-up node and the pull-down node to be in a sustain state according to the signals of the second node and the third node; The third input sub-unit responds to the signal of the first node by providing the signal of the third control signal terminal to the second node; the node control sub-circuit controls the signal of the pull-down node to be in an active state according to the signal of the second node; and the output sub-circuit responds to the signal of the pull-down node by providing the signal of the second reference signal terminal to the drive output terminal.

Images