Display panel and display device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-06-24
- Publication Date
- 2026-05-05
AI Technical Summary
When foldable products are displayed in full screen, noticeable display differences can easily appear at the fold, such as black lines or uneven brightness, affecting the display effect.
The display panel is divided into multiple areas, each with an independent gate drive circuit. Signal preprocessing is performed through the connection of an auxiliary gate drive circuit and a frame enable signal line to ensure the consistency of the gate drive signal in each area and reduce brightness differences at the fold.
It effectively reduces brightness unevenness at the folding position, improves display effect, reduces power consumption, and supports the full-screen display requirements of foldable screens.
Smart Images
Figure CN121986372A_ABST
Abstract
Description
Display panel and display device Technical Field
[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology
[0002] With the rapid development of mobile products (such as mobile phones and smart tablets), various forms of products have emerged in the market, among which foldable products are becoming increasingly popular. For foldable products, full-screen display is required when folded, and partial display is required when folded. In order to save power consumption when folded, the GOA (Gate Driver on Array) is generally grouped with the fold line as the boundary.
[0003] However, for foldable products with group control, when displayed in full screen, there are often obvious differences at the folding points, such as black lines or obvious brightness differences, resulting in poor display. Summary of the Invention
[0004] In view of this, this application proposes a display panel and display device to solve or partially solve the above-mentioned problems.
[0005] Based on the above objectives, in a first aspect, this application provides a display panel divided into N regions arranged sequentially along a first direction, each region including a display area and a peripheral area located on at least one side of the display area; N is an integer not less than 2; wherein, the display panel includes: N pixel subarrays, respectively located in the N display areas; each pixel subarray includes a plurality of pixels arranged in rows and columns; N gate driving circuits, respectively located in the N peripheral areas; for the gate driving circuits and the pixel subarrays located in the same region, the gate driving circuit is configured to provide a gate driving signal to the pixel subarray in response to a corresponding frame enable signal; the gate driving circuit includes a multi-stage cascaded shift register, each stage of the shift register corresponding to a row of pixels; N frame enable signal lines, each of the frame enable signals... The enable signal line is configured to provide the frame enable signal to the corresponding gate drive circuit; (N-1) auxiliary gate drive circuits, each auxiliary gate drive circuit including at least one stage of auxiliary shift register; the first frame enable signal line is connected to the signal input terminal of the first stage shift register of the first gate drive circuit; when 2≤i≤N, the i-th frame enable signal line is connected to the signal input terminal of the first stage auxiliary shift register of the (i-1)-th auxiliary gate drive circuit, and the signal output terminal of the last stage auxiliary shift register of the (i-1)-th auxiliary gate drive circuit is connected to the signal input terminal of the first stage shift register of the i-th gate drive circuit; and when the auxiliary gate drive circuit includes multiple stages of auxiliary shift registers, adjacent stages in the multiple stages of auxiliary shift registers are cascaded.
[0006] In some alternative embodiments, the i-th auxiliary gate drive circuit is located in the (i+1)-th peripheral region.
[0007] In some alternative embodiments, at least a portion of the auxiliary gate drive circuitry is located in the first peripheral region.
[0008] In some optional embodiments, the system further includes: M redundant gate drive circuits; M is an integer not less than 1; and at least a portion of the M redundant gate drive circuits are reused as the auxiliary gate drive circuit.
[0009] In some optional embodiments, at least a portion of the M redundant gate driving circuits are located in the first peripheral region and correspond to the corner region of the first display area; the auxiliary gate driving circuit located in the first peripheral region is multiplexed by the redundant gate driving circuit located in the first peripheral region.
[0010] In some alternative embodiments, for the auxiliary gate drive circuit located in the first peripheral region, each stage of the auxiliary shift register is located on the side of the first-stage shift register in the first gate drive circuit that is away from the second peripheral region.
[0011] In some alternative embodiments, for the auxiliary gate drive circuit located in the first peripheral region, each stage of the auxiliary shift register is located between multiple shift registers in the first gate drive circuit.
[0012] In some alternative embodiments, for a portion of the auxiliary gate drive circuit, the signal output of a partial-stage auxiliary shift register is connected to a compensation line.
[0013] In some alternative embodiments, the compensation line extends along the first direction and is located in the peripheral area.
[0014] In some optional embodiments, the gate driving circuit includes at least a second reset driving circuit, a scan driving circuit, and a compensation driving circuit; the auxiliary gate driving circuit includes a first auxiliary driving circuit, a second auxiliary driving circuit, and a third auxiliary driving circuit; the first auxiliary driving circuit is correspondingly connected to the second reset driving circuit, the second auxiliary driving circuit is correspondingly connected to the scan driving circuit, and the third auxiliary driving circuit is correspondingly connected to the compensation driving circuit.
[0015] In some optional embodiments, the gate driving circuit includes the first reset driving circuit; the pixel includes a pixel driving circuit, the pixel driving circuit including a first reset transistor; the display panel further includes a plurality of first reset signal lines; one first reset signal line, a first-level shift register of the first reset driving circuit, and a row of pixels are correspondingly configured; for the corresponding first reset signal line, the shift register, and the pixel, the control electrode of the first reset transistor is connected to the second end of the first reset signal line, and the first end of the first reset signal line is connected to the signal output terminal of the shift register.
[0016] In some optional embodiments, the display panel further includes: a plurality of first initial signal lines; a first terminal of the first reset transistor is connected to the first initial signal line; the first reset transistor corresponding to each first-stage shift register in the second to N gate driving circuits is called a first type transistor, and the first reset transistor corresponding to the other shift registers in the N gate driving circuits is called a second type transistor; the amplitude of the voltage signal received by the first type transistor from the first initial signal line is different from the amplitude of the voltage signal received by the first type transistor from the first initial signal line.
[0017] In some optional embodiments, the gate driving circuit includes a second reset driving circuit; the pixel includes a pixel driving circuit; the pixel driving circuit includes a second reset transistor and a third reset transistor; the display panel further includes multiple second reset signal lines; one second reset signal line is configured corresponding to a first-level shift register of the second reset driving circuit and a row of pixels; for the corresponding second reset signal line, the shift register, and the pixel, the control electrode of the second reset transistor and the third reset transistor are both connected to the second end of the second reset signal line, and the first end of the second reset signal line is connected to the signal output terminal of the shift register.
[0018] In some optional embodiments, the display panel further includes: a plurality of second initial signal lines; the first terminal of the second reset transistor is connected to the second initial signal line; the second reset transistor corresponding to each first-stage shift register in the second to N gate driving circuits is called a third type transistor, and the second reset transistor corresponding to the other shift registers in the N gate driving circuits is called a fourth type transistor; the amplitude of the voltage signal received by the third type transistor from the second initial signal line is different from the amplitude of the voltage signal received by the fourth type transistor from the second initial signal line.
[0019] In some optional embodiments, the display panel further includes: multiple third initial signal lines; the first terminal of the third reset transistor is connected to the third initial signal lines; the third reset transistor corresponding to each first-stage shift register in the second to Nth gate driving circuits is called a fifth type transistor, and the third reset transistor corresponding to the other shift registers in the N gate driving circuits is called a sixth type transistor; the amplitude of the voltage signal received by the fifth type transistor from the third initial signal lines is different from the amplitude of the voltage signal received by the sixth type transistor from the third initial signal lines.
[0020] In some optional embodiments, the gate driving circuit includes the compensation driving circuit; the pixel includes a pixel driving circuit; the pixel driving circuit includes a compensation transistor; the display panel further includes a plurality of first scan signal lines; one first scan signal line is configured corresponding to a first-level shift register of the scan driving circuit and a row of pixels; for the corresponding first scan signal line, the shift register and the pixel, the control electrode of the compensation transistor is connected to the second end of the first scan signal line, and the first end of the first scan signal line is connected to the signal output terminal of the shift register.
[0021] In some optional embodiments, the gate driving circuit includes the scan driving circuit; the pixel includes a pixel driving circuit; the pixel driving circuit includes a data writing transistor; the display panel further includes a plurality of second scan signal lines; one second scan signal line is configured corresponding to a first-level shift register of the scan driving circuit and a row of pixels; for the corresponding second scan signal line, the shift register and the pixel, the control electrode of the data writing transistor is connected to the second end of the second scan signal line, and the first end of the second scan signal line is connected to the signal output terminal of the shift register.
[0022] In some alternative embodiments, the method further includes: multiple data signal lines; the first terminal of the data writing transistor is connected to one of the data signal lines.
[0023] In some optional embodiments, the gate driving circuit includes the light-emitting driving circuit; the pixel includes a pixel driving circuit; the pixel driving circuit includes a light-emitting control transistor; the display panel further includes multiple light-emitting control signal lines; one light-emitting control signal line is configured corresponding to a first-level shift register of the light-emitting driving circuit and a row of pixels; for the corresponding light-emitting control signal line, the shift register, and the pixel, the control electrode of the light-emitting control transistor is connected to the second end of the light-emitting control signal line, and the first end of the light-emitting control signal line is connected to the signal output terminal of the shift register.
[0024] Secondly, this disclosure also provides a display device, which includes the display panel described in any embodiment of the first aspect. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 is a planar schematic diagram of the unfolded state of a double-fold display panel in the related technology.
[0027] Figure 2 is a magnified view of the area enclosed by the dashed line on the display panel shown in Figure 1.
[0028] Figure 3 is a schematic diagram of the wiring structure of the area shown in Figure 2.
[0029] Figure 4 shows the waveform diagrams of the signals received by the nth-stage shift register and the (n+1)th-stage shift register.
[0030] Figure 5 is a plan view of the display panel provided in this disclosure.
[0031] Figure 6 is a schematic diagram of a first exemplary structure of the display panel provided in Embodiment 1.
[0032] Figure 7 shows the waveforms of the signals received by the nth and (n+1)th stage shift registers after the auxiliary gate circuit is set.
[0033] Figure 8 is a schematic diagram of a second exemplary structure of the display panel provided in Embodiment 1.
[0034] Figure 9 is a schematic diagram of the compensation line.
[0035] Figure 10 shows a first exemplary structure of the display panel provided in Embodiment 2.
[0036] Figure 11 shows a second exemplary structure of the display panel provided in Embodiment 2.
[0037] Figure 12 is a schematic diagram of the redundant gate drive circuit located in the first region.
[0038] Figure 13 is a schematic diagram of the 8T1C pixel driving circuit.
[0039] Figure 14 is a schematic diagram of the modular structure of the gate drive circuit.
[0040] Figure 15 is a schematic diagram of the structure of the display panel provided in Extended Embodiment 2.
[0041] Figure 16 is a schematic diagram of the structure of the display panel provided in Extended Embodiment 3.
[0042] Figure 17 is a schematic diagram of the structure of the display panel provided in Extended Embodiment 4. Detailed Implementation
[0043] To make the objectives, technical solutions, and advantages of this specification clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0044] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element, object, or method step preceding the term covers the element, object, or method step listed after the term and its equivalents, without excluding other elements, objects, or method steps. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0045] As described in the background section, with the rise of foldable smart devices such as foldable phones, the display effect of foldable screens is receiving increasing attention. In some embodiments, for image display, the corresponding circuitry for image display on a non-foldable screen is directly transferred to a foldable screen, with foldability only applied at the folding position. For foldable displays, the display state changes before and after folding; for example, full-screen display is required when folded, while only partial display is needed after folding. For smart devices that directly apply the gate driving circuitry for image display on a non-foldable screen, partial display can be achieved by controlling the data writing to write the undisplayed portion to black, thus indirectly completing the partial display function. However, although such a design can achieve partial display, since the undisplayed portion of the GOA and pixels still function normally, the IC (Integrated Circuit, driver chip) power consumption is no different from that of full-screen display, and power saving is not achieved. It should be noted that in some embodiments, the gate driving circuit can be a GOA circuit, that is, the gate driving circuit is directly integrated into the array substrate of the display panel. The following embodiments are all illustrated using a GOA circuit as the gate driving circuit.
[0046] Before introducing the technical solution disclosed herein, we will first take a double-folded display panel as an example to introduce the structure of the gate driving circuit of the double-folded display panel in the related technology, as well as the technical problems therein.
[0047] Figure 1 is a planar schematic diagram of the unfolded state of a double-fold display panel in the related technology. As shown in Figure 1, the display panel can be divided into two regions arranged sequentially along a first direction, namely the first region Z1 and the second region Z2. Each region includes a display area AA and a peripheral area BA located on at least one side of the display area AA. For ease of description, the display area AA located in the first region Z1 and the second region Z1 are referred to as the first display area AA1 and the second display area AA2, respectively, and the peripheral area BA located in the first region Z1 and the second region Z1 are referred to as the first peripheral area BA1 and the second peripheral area BA2, respectively. In this paper, the first direction is the folding direction, the X direction, or the direction where the pixel column is located, and the second direction is the Y direction or the direction where the pixel row is located; however, it should be noted that a certain direction in this paper is not limited to a straight line trajectory in a geometric sense, but refers to the overall direction including the meandering shape.
[0048] Figure 2 is a magnified view of the area enclosed by the dashed line in Figure 1 of the display panel. As shown in Figure 2, the display panel includes two pixel subarrays and two gate driving circuits; wherein, the two pixel subarrays are a first subarray P1 located in the first display area AA1 and a second subarray P2 located in the second display area AA2; the two gate driving circuits are a first gate driving circuit G1 located in the first peripheral area BA1 and a second gate driving circuit G2 located in the second peripheral area BA2. Specifically, both the first subarray P1 and the second subarray P2 include multiple pixels 11 arranged in an array, and both the first gate driving circuit G1 and the second gate driving circuit G2 include multi-stage shift registers 21 arranged sequentially along the X direction.
[0049] Figure 3 is a schematic diagram of the wiring structure of the area shown in Figure 2. As shown in Figure 3, the display panel also includes two frame start signal lines, namely the first frame start signal line STV1 (STV stands for Start of Vertical Blanking) and the second frame start signal line STV2. Specifically, the number of stages of the shift register 21 in the first gate driving circuit G1 corresponds to the number of rows of pixels 11 in the first sub-array P1, and the number of stages of the shift register 21 in the second gate driving circuit G2 corresponds to the number of rows of pixels 11 in the second sub-array P2; moreover, the shift registers 21 of each stage in the first gate driving circuit G1 are cascaded sequentially, and the shift registers 21 of each stage in the second gate driving circuit G2 are cascaded sequentially. The signal input terminal of the first stage shift register 21 of the first gate driving circuit G1 is connected to the first frame start signal line STV1, while the signal input terminal of the first stage shift register 21 of the second gate driving circuit G2 is connected to the second frame start signal line STV2. In simple terms, the first gate drive circuit G1 is configured to provide a gate drive signal to the first subarray P1 in response to the first frame enable signal; the second gate drive circuit G2 is configured to provide a gate drive signal to the first subarray P1 in response to the second frame enable signal.
[0050] As can be seen, the aforementioned double-fold display panel includes two gate driving circuits, located on both sides of the fold line, with each gate driving circuit connected to a different frame-on signal line. However, the inventors have discovered that black lines appear near the fold line of the display panel during use, affecting normal image display.
[0051] In response, the inventors analyzed the problematic product and discovered that the "black line" might be caused by the following reason: In the X direction, the two shift registers 21 closest to the fold line on either side are the last stage shift register 21 of the first gate drive circuit G1 (assumed to be stage n, where n is an integer not less than 2) and the first stage shift register 21 of the second gate drive circuit G2 (assumed to be stage n+1). For stage n shift register 21, it receives the cascaded signal output from stage n-1 shift register 21, while for stage n+1 shift register 21, it receives the second frame enable signal, which is typically generated by an external driver chip IC. As a result, the signal waveforms received by stage n shift register 21 and stage n+1 shift register 21 are inconsistent, specifically in terms of rising edge, falling edge, and the amplitude of high and low levels.
[0052] Figure 4 shows the waveforms of the signals received by the nth and (n+1)th stage shift registers. Referring to Figure 4, the nth stage shift register 21 receives the cascaded signal output by the (n-1)th stage shift register 21, with a falling edge time of Tf1 and a rising edge time of Tr1. The (n+1)th stage shift register 21 receives the second frame enable signal, with a falling edge time of Tf2 and a rising edge time of Tr2. Clearly, Tf1 > Tf2. This results in a difference between the gate drive signal output by the nth stage shift register 21 and the gate drive signal output by the (n+1)th stage shift register. Consequently, the signals received by the nth and (n+1)th row pixels controlled by the nth and (n+1)th stage shift registers differ, affecting the operating state of the thin-film transistors in the pixel driving circuit, ultimately manifesting as a dark line in the (n+1)th row pixel.
[0053] In order to solve at least one of the above-mentioned technical problems, in one respect, this disclosure provides a display panel.
[0054] Figure 5 is a plan view of the display panel provided in this disclosure. As shown in Figure 5, the display panel provided in this disclosure can be divided into N regions (Z1 to ZN), where N is an integer not less than 2. Each region includes a display area AA and a peripheral area BA located at least on one side of the display area AA. For example, N can be 2 or 3, etc. Those skilled in the art will understand that when N is 2, it refers to a double-fold display panel; when N is 3, it refers to a triple-fold display panel.
[0055] Specifically, the display panel provided in this disclosure includes: N pixel sub-arrays, N gate driving circuits, N frame enable signal lines, and N-1 auxiliary gate driving circuits. The N gate driving circuits are located in N peripheral areas (BA); the N sub-pixel arrays are located in N display areas (AA). For gate driving circuits and pixel sub-arrays located in the same area, the gate driving circuit is configured to provide a gate driving signal to the pixel sub-array in response to its corresponding frame enable signal. The gate driving circuit specifically includes a multi-stage cascaded shift register, and the pixel sub-array includes multiple pixels arranged in an array, with each stage of the shift register corresponding to a row of pixels. In the N frame enable signal lines, each frame enable signal line is configured to provide a frame enable signal to its corresponding gate driving circuit. Each auxiliary gate driving circuit includes at least one auxiliary shift register.
[0056] For the first frame enable signal line, it is connected to the signal input terminal of the first-stage shift register of the first gate drive circuit. For the i-th frame enable signal line among the 2nd to Nth frame enable signal lines, where 2≤i≤N, the i-th frame enable signal line is connected to the signal input terminal of the first-stage auxiliary shift register of the (i-1)-th auxiliary gate drive circuit, and the signal output terminal of the last-stage auxiliary shift register of the (i-1)-th auxiliary gate drive circuit is connected to the signal input terminal of the first-stage shift register of the i-th gate drive circuit; and when the auxiliary gate drive circuit includes multiple stages of auxiliary shift registers, adjacent stages of the multiple stages of auxiliary shift registers are cascaded.
[0057] The display panel provided in this disclosure connects the signal input terminals of the first-stage shift registers of the second to Nth gate driving circuits to their corresponding auxiliary gate driving circuits. That is, for any one of the second to Nth gate driving circuits, the frame enable signal line is connected to the auxiliary shift register, and the output signal of the auxiliary shift register is used as the input of the first-stage shift register of the gate driving circuit. This is equivalent to pre-processing the frame enable signal and transmitting the processed frame enable signal to the first-stage shift register in the form of a cascaded signal. In practical applications, the first-stage shift registers of the gate driving circuits in the second to Nth regions can obtain the same "cascaded signal" instead of the initial frame enable signal. This reduces or even prevents waveform differences in the GOA at different folding areas due to different driving signal sources, and reduces or even prevents the problem of significant differences in pixel brightness caused by this. This ensures uniform display brightness at the folding position and reduces or even solves the display defects caused by display differences.
[0058] To more clearly describe the technical solution of this disclosure, the following description uses a double-folding display panel as an example to introduce several specific embodiments of this disclosure. The double-folding display panel can be divided into two regions, namely a first region Z1 and a second region Z2; the display panel includes two pixel sub-arrays (a first sub-array P1 and a second sub-array P2, respectively), two gate driving circuits (a first gate driving circuit G1 and a second gate driving circuit G2, respectively), two frame enable signal lines (a first frame enable signal line STV1 and a second frame enable signal line STV2, respectively), and an auxiliary gate driving circuit G'.
[0059] Example 1
[0060] In Example 1, the i-th auxiliary gate drive circuit G' is located in the (i+1)-th peripheral region BA.
[0061] For a double-fold display panel, N=2, the display panel includes an auxiliary gate driving circuit G', and the auxiliary gate driving circuit G' is located in the second peripheral region BA. Next, we will introduce two exemplary structures of the display panel, taking the auxiliary gate driving circuit G' including a single-stage auxiliary shift register and a multi-stage auxiliary shift register as examples.
[0062] Figure 6 is a schematic diagram of a first exemplary structure of the display panel provided in Embodiment 1. As shown in Figure 6, in this example, the first gate driving circuit G1 includes n shift registers 21 arranged sequentially along the X direction, and the second gate driving circuit G2 includes n shift registers 21 arranged sequentially along the X direction; the first subarray P1 includes n rows of pixels 11, and the second subarray P2 includes n rows of pixels 11. The shift registers 21 of the first gate driving circuit G1 are cascaded, and the signal input terminal of the first-stage shift register 21 is connected to the first frame enable signal line STV1; the shift registers 21 of the second gate driving circuit G2 are cascaded. In particular, in the display panel shown in Figure 6, the auxiliary gate driving circuit G' includes only one auxiliary shift register 31, which can be located on the side of the first-stage shift register 21 of the second gate driving circuit G2 near the first region Z1. Furthermore, the signal input terminal of the auxiliary shift register 31 is connected to the second frame enable signal line STV2, and the signal output terminal of the auxiliary shift register 31 is connected to the first stage shift register 21 of the second gate drive circuit G2.
[0063] In the example shown in Figure 6, this is equivalent to performing a pre-processing step on the second frame enable signal. This effectively reduces the difference between the signal received by the first-stage shift register 21 in the second gate drive circuit G2 and the cascaded signal received by the last-stage shift register 21 in the first gate drive circuit G2, i.e., reducing the difference between the signals received by the nth and (n+1)th stage shift registers 21. Figure 7 shows the waveforms of the signals received by the nth and (n+1)th stage shift registers after setting the auxiliary gate circuit G'. Comparing the waveforms in Figure 7 with those in Figure 4, it can be observed that after setting the auxiliary gate circuit G', the waveforms of the signals received by the nth and (n+1)th stage shift registers tend to be consistent. For example, their falling edge times Tf1 and Tf2 are almost identical, and their rising edge times Tr1 and Tr2 are also identical, thus effectively reducing pixel differences.
[0064] Figure 8 is a schematic diagram of a second exemplary structure of the display panel provided in Embodiment 1. As shown in Figure 8, the difference between this example and the example shown in Figure 6 is that the auxiliary gate driving circuit G' includes multiple stages of auxiliary shift registers 31, and all stages of auxiliary shift registers 31 are located on the side of the first stage shift register 21 of the second gate driving circuit G2 near the first region Z1. The stages of auxiliary shift registers 31 are cascaded sequentially. The signal input terminal of the first stage auxiliary shift register 31 is connected to the second frame enable signal line STV2, and the signal output terminal of the last stage auxiliary shift register 31 is connected to the signal input terminal of the first stage shift register 21 of the second gate driving circuit G2.
[0065] In the example above, it is equivalent to performing multi-level preprocessing on the second frame activation signal, which can further reduce the difference in the signals received between the nth and n+1th level shift registers 21, thereby further reducing the brightness difference near the fold line.
[0066] In other examples, in the multi-stage auxiliary shift register 31 of the auxiliary gate drive circuit G', part of it is located on the side of the first-stage shift register 21 of the second gate drive circuit G2 near the first region Z1, and part of it is located between two adjacent shift registers 21 of the second gate drive circuit G2.
[0067] In some other examples, in the multi-stage auxiliary shift register 31 of the auxiliary gate drive circuit G', any one stage of the auxiliary shift register 31 is located between two adjacent shift registers 21 of the second gate drive circuit G2.
[0068] In other examples, to make the signal output by the auxiliary shift register 31 closer to the cascaded signal, the display panel also includes a compensation line. Figure 9 is a schematic diagram of the compensation line. As shown in Figure 9, the compensation line 41 is located in the peripheral area BA and extends along the X direction, and at least part of the signal output terminal of the auxiliary shift register 31 is connected to the compensation line 41. In this example, the compensation line 41 can further compensate for the load of the output of the auxiliary shift register 114, extending the cascaded signal output by the auxiliary shift register 31 so that the cascaded signal needs to pass through the compensation line 41 before reaching the first-stage shift register 21 of the second gate drive circuit G2. By compensating in this way, the load of the cascaded signal output by the auxiliary shift register 31 is made consistent with the load of the cascaded signal output by the nth-stage shift register 21, thereby further reducing the difference between the signals received by the nth-stage and (n+1)th-stage shift registers 21.
[0069] In summary, in Embodiment 1, the auxiliary gate driving circuit G' is located in the peripheral region BA of the second region Z2, and the auxiliary gate driving circuit G' may include a single-stage auxiliary shift register 31 or multiple-stage auxiliary shift registers 31. In addition, when the auxiliary gate driving circuit G' includes multiple-stage auxiliary shift registers 31, each stage of the auxiliary shift register 31 may be continuously and sequentially distributed along the X direction, or may be alternately distributed along the X direction with the shift register 21 of the second gate driving circuit G2. Furthermore, the display panel may also include a compensation line 41, and the signal output terminal of at least one stage of the auxiliary shift register 31 is simultaneously connected to the compensation line 41 to perform load compensation on the signal output by the auxiliary shift register 31.
[0070] Example 2
[0071] In the display panel provided in Embodiment 1 above, since the auxiliary gate driving circuit G' is located in the second region Z2, as shown in Figures 6 and 8, the shift register 21 of the second gate driving circuit G2 and its corresponding pixel row cannot be on the same horizontal line. That is, the shift register 21 and its corresponding pixel row are misaligned. Moreover, the more stages the auxiliary shift register 31 of the auxiliary gate driving circuit G' has, the more serious the misalignment between the shift register 21 and its corresponding pixel row becomes. This results in the space occupied by the connection between the shift register 21 and the pixel 11 becoming larger, which is not conducive to the narrow bezel design of the display panel.
[0072] Therefore, in this embodiment, the auxiliary gate driving circuit G' of the display panel is located in the first peripheral region BA. Next, taking the auxiliary gate driving circuit G' comprising a single-stage auxiliary shift register and multiple-stage auxiliary shift registers as an example, the structure of the display panel provided in Embodiment 2 will be described.
[0073] Figure 10 shows a first exemplary structure of the display panel provided in Embodiment 2. As shown in Figure 10, in this example, the auxiliary gate driving circuit G' includes only one-stage auxiliary shift register 31, which is located on the side of the first-stage shift register 21 of the first gate driving circuit G1 away from the second region Z2. Furthermore, the signal input terminal of the auxiliary shift register 31 is connected to the second frame enable signal line STV2, and the signal output terminal of the auxiliary shift register 31 is connected to the first-stage shift register 21 of the second gate driving circuit G2.
[0074] In the above example, by setting the auxiliary shift register 31 on the side of the first-stage shift register 21 of the first gate driving circuit G1 away from the second region Z2, compared with embodiment 1, it has at least the following beneficial effects: 1. It avoids the problem of misalignment between the shift register 21 and the corresponding pixel row, so the wiring area of the peripheral area BA will not be too large, which is conducive to narrow bezels; 2. The distance between the signal output terminal of the auxiliary shift register 31 and the second gate driving circuit G2 is large, so the signal output line between the two is equivalent to the compensation line 41 in embodiment 1. That is, in this embodiment, since the auxiliary shift register 31 is set in the first region Z1, the signal output line of the auxiliary shift register 31 can bear the role of load compensation, so there is no need to set the compensation line 41 separately, which simplifies the wiring, simplifies the process and reduces the cost.
[0075] Of course, when the auxiliary gate drive circuit G' includes a multi-stage auxiliary shift register 31, the multi-stage auxiliary shift register 31 can be set on the side of the first stage shift register 21 of the first gate drive circuit G1 away from the second region Z2.
[0076] Figure 11 shows a second exemplary structure of the display panel provided in Embodiment 2. As shown in Figure 11, in this example, the auxiliary gate driving circuit G' includes a multi-stage auxiliary shift register 31, which is located between the multi-stage shift registers 21 of the first gate driving circuit G1. Furthermore, the signal input terminal of the first-stage auxiliary shift register 31 is connected to the second frame enable signal line STV2, and the signal output terminal of the last-stage auxiliary shift register 31 is connected to the first-stage shift register 21 of the second gate driving circuit G2.
[0077] Comparing Figures 11 and 10, it can be seen that in the example of Figure 10, since the topmost element is the auxiliary shift register 31, and the shift register 21 is located below it, the corresponding frame enable signal lines STV1 and STV2 are arranged in the Y-direction with STV2 first and STV2 last. In other words, for the example of Figure 10, the arrangement order of the frame enable signal lines needs to be adjusted according to the setting position of the auxiliary shift register 31. However, for the example shown in Figure 11, since the auxiliary shift register 31 is located between the multi-stage shift registers 21, the arrangement order of the corresponding frame enable signal lines STV1 and STV2 in the Y-direction can be STV1 first and STV2 last. That is, the order of the two frame enable signal lines does not need to be changed, thus improving the convenience of preparing the frame enable signal lines.
[0078] In other examples, the multi-stage auxiliary shift register 31 can be alternated with the shift register 21; of course, part of the multi-stage auxiliary shift register 31 can be set on the side of the first-stage shift register 21 away from the second region Z2, as shown in Figure 10, and another part can be set between each stage of the shift register 21, as shown in Figure 11. Other similar extended examples will not be shown here.
[0079] The above embodiments 1 and 2 respectively introduced two configuration positions of the auxiliary gate drive circuit G'. Next, based on the inventive concept of the above embodiments 1 and 2, several extended embodiments are provided.
[0080] Extended Example 1
[0081] Those skilled in the art will understand that, in order to ensure etching uniformity and stress balance between functional and non-functional areas when fabricating the gate driving circuit of a display panel, a redundant gate driving circuit (Dummy GOA) is often fabricated simultaneously with the gate driving circuit. This redundant gate driving circuit can be located between the first gate driving circuit G1 and the second gate driving circuit G2, or on the side of the first gate driving circuit G1 away from the second region Z1, or on the side of the second gate driving circuit G2 away from the first region Z1; alternatively, when the redundant gate driving circuit includes multiple levels of redundant shift registers, these multiple levels of redundant shift registers can be alternately configured with other functional shift registers.
[0082] In a first extended embodiment, the display panel of this disclosure further includes M redundant gate driving circuits, where M is an integer not less than 1. Preferably, at least a portion of the M redundant gate driving circuits is reused as an auxiliary gate driving circuit G'. This is equivalent to reusing the originally non-functional redundant gate driving circuits as auxiliary driving circuits G', thereby ensuring etching uniformity and stress balance, reducing the brightness difference between the fold line area and other display areas, simplifying the manufacturing process and reducing costs, and avoiding the occupation of additional bezel area.
[0083] Figure 12 is a schematic diagram of the redundant gate driving circuit located in the first region. As shown in Figure 12, the redundant gate driving circuit located in the first region includes a multi-level redundant shift register 51, which corresponds to the corner area of the display area of the first region Z1. This arrangement allows for flexible adjustment of the position of the shift register 21, avoiding misalignment between the corner area shift register 21 and the pixel row, which could lead to wiring chaos. Preferably, the redundant shift register 51 located in the first peripheral region BA can be used as the auxiliary shift register 31 in Embodiment 2.
[0084] In summary, the core inventive concept of Extended Embodiment 1 is to reuse the redundant gate drive circuit, which is originally formed simultaneously with the gate drive circuit during the fabrication process, as an auxiliary gate drive circuit. This eliminates the need for additional fabrication processes and additional border areas, simplifying the fabrication process and facilitating narrower borders.
[0085] To further explain the technical solution disclosed herein, the following section will elaborate on the design architecture and working process of the gate driving circuit in the display panel, taking into account the structural characteristics of the pixel driving circuit.
[0086] As a necessary technical groundwork, the structural system of the pixel driving circuit in the display panel will first be described. The pixel 11 of the display panel includes a pixel driving circuit, which can be any of 2T1C, 5T2C, 6T1C, 7T1C, and 8T1C.
[0087] Figure 13 is a schematic diagram of the 8T1C pixel driving circuit. This article will use it as an example to introduce the structure of the gate driving circuit in the display panel. As shown in Figure 13, the 8T1C pixel driving circuit includes eight transistors and one storage capacitor Cst. The eight transistors are: first reset transistor T1, compensation transistor T2, third transistor T3, data writing transistor T4, first light emission control transistor T5, second light emission control transistor T6, second reset transistor T7, and third reset transistor T8. Correspondingly, the display panel includes multiple first reset signal lines, multiple second reset signal lines, multiple light emission control signal lines, multiple first scan signal lines, and multiple second scan signal lines.
[0088] In this circuit, the control electrode of the first reset transistor T1 is connected to the first reset signal line to receive the first reset signal Reset_P; the control electrodes of the second reset transistor T7 and the third reset transistor T8 are connected to the second reset signal line to receive the second reset signal Reset_H; the control electrodes of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control signal line to receive the light-emitting control signal EM; the control electrode of the data writing transistor T4 is connected to the second scan signal line to receive the second scan signal Gate_P; and the control electrode of the compensation transistor T2 is connected to the first scan signal line to receive the first scan signal Gate_N. That is, different control signals are required for the control electrodes of different transistors. Accordingly, the gate drive circuit includes different types of gate drive circuits to provide gate drive signals for the control electrodes of different transistors.
[0089] Figure 14 is a schematic diagram of the modular structure of the gate driving circuit. As shown in Figure 14, corresponding to the 8T1C pixel driving circuit, the gate driving circuit includes a first reset driving circuit GOA_RP, a second reset driving circuit GOA_RH, a light emission driving circuit GOA_EM, a scan driving circuit GOA_GP, and a compensation driving circuit GOA_GN. Specifically, the first reset driving circuit GOA_RP is configured to output a first reset signal Reset_P to the gate of the first reset transistor T1; the second reset driving circuit GOA_RH is configured to output a second reset signal Reset_H to the second reset transistor T7 and the third reset transistor T8; the light emission driving circuit GOA_EM is configured to output a light emission control signal EM to the gates of the first light emission control transistor T5 and the second light emission control transistor T6; the scan driving circuit GOA_GP is configured to output a second scan signal Gate_P to the gate of the data writing transistor T4; and the compensation driving circuit GOA_GN is configured to output a first scan signal Gate_N to the gate of the compensation transistor T2.
[0090] Referring again to Figure 14, taking the double-folding display panel as an example, when the pixel driving circuit is 8T1C, the gate driving circuit of this disclosure specifically includes: two first reset driving circuits GOA_RP (G1_RP and G2_RP, respectively, with frame enable signal lines STV1_RP and STV2_RP, respectively), two second reset driving circuits GOA_RH (G1_RH and G2_RH, respectively, with frame enable signal lines STV1_RH and STV2_RH, respectively), two light-emitting driving circuits GOA_EM (G1_EM and G2_EM, respectively, with frame enable signal lines STV1_EM and STV2_EM, respectively), two second scan driving circuits GOA_GP (G1_GP and G2_GP, respectively, with frame enable signal lines STV1_GP and STV2_GP, respectively), and two first scan driving circuits GOA_GN (G1_GN and G2_GN, respectively, with frame enable signal lines STV1_GN and STV2_GN, respectively). The gate drive circuit mentioned in the above embodiments of this disclosure can be one or more of the five types of GOAs.
[0091] Referring again to Figure 14, in some examples, an auxiliary gate drive circuit G' can be provided for each of the five types of GOAs. For example, an auxiliary drive circuit G'_RP is provided for the first reset drive circuit GOA_RP, an auxiliary drive circuit G'_RH is provided for the second reset drive circuit GOA_RH, an auxiliary drive circuit G'_EM is provided for the light emission drive circuit GOA_EM, an auxiliary drive circuit G'_GP is provided for the second scan drive circuit GOA_GP, and an auxiliary drive circuit G'_GN is provided for the first scan drive circuit GOA_GN. That is, the input signal of the first-stage shift register of the second gate drive circuit in each type of GOA is adjusted, thereby adjusting the gate drive signal of each transistor in the pixel drive circuit corresponding to the first-stage shift register. This can minimize the brightness difference near the fold line caused by signal differences.
[0092] However, the inventors discovered that among the five types of control signals, the main factors affecting the "black line" are the second reset signal Reset_H, the second scan signal Gate_P, and the first scan signal Gate_N. Therefore, to simplify the design and fabrication process, auxiliary drive circuits G'_RH, G'_GP, and G'_GN can be set only for the second reset drive circuit GOA_RH, the second scan drive circuit GOA_GP, and the first scan drive circuit GOA_GN. For the first reset drive circuit GOA_RP and the light-emitting drive circuit GOA_EM, there is no need to set auxiliary gate drive circuits. This achieves both a reduction in brightness difference and simplifies the design and fabrication process.
[0093] Next, we will introduce extended embodiments 2-4. It should be noted that the inventive concept of extended embodiments 2-4 differs from that of the embodiments described above. The core of the embodiments described above lies in adding an auxiliary gate driving circuit to the second gate driving circuit. This auxiliary gate driving circuit receives the frame enable signal, converts it into a cascaded signal, and transmits it to the second gate driving circuit to change the gate driving signals received by each transistor in the pixel driving circuit. The core of the following extended embodiments, however, lies in changing the source driving signals received by each transistor in the pixel driving circuit. In specific implementations, one can choose the above embodiment (adding an auxiliary gate driving circuit), or one can choose extended embodiments 2-4 below (changing the source driving signals), or one can combine the above embodiments with extended embodiments 2-4 below (further changing the source driving signals based on adding an auxiliary gate driving circuit).
[0094] As necessary technical groundwork, before introducing extended embodiments 2-4, we continue with the description of the pixel driving circuit in Figure 13. Referring to Figure 13, the source of the first reset transistor T1 receives the first initial signal Vinit1. Correspondingly, the display panel also includes multiple first initial signal lines, and the source of the first reset transistor T1 is connected to the first initial signal lines. The source of the second reset transistor T7 receives the second initial signal Vinit2. Correspondingly, the display panel also includes multiple second initial signal lines, and the source of the second reset transistor T7 is connected to the second initial signal lines. The source of the third reset transistor T8 receives the third initial signal Vinit3. Correspondingly, the display panel also includes multiple third initial signal lines, and the source of the third reset transistor T8 is connected to the third initial signal lines. Furthermore, the source of the data writing transistor T4 receives the data signal Data. Correspondingly, the display panel also includes multiple data signal lines, and the source of the data writing transistor T4 is connected to the data signal lines.
[0095] Extended Example 2
[0096] For a display panel comprising N gate driving circuits, the first reset transistor T1 corresponding to each first-stage shift register 21 in the 2nd to Nth gate driving circuits is referred to as a first-type transistor T1-1, and the first reset transistor T1 corresponding to the other shift registers 21 in the N gate driving circuits is referred to as a second-type transistor T1-2. In extended embodiment 2, the amplitude of the first initial signal Vinit1 received by the first-type transistor T1-1 from the first initial signal line is different from the amplitude of the first initial signal Vinit1 received by the second-type transistor T1-2 from the first initial signal line.
[0097] Figure 15 is a schematic diagram of the display panel provided in Extended Embodiment 2. As shown in Figure 15, taking the double-fold display panel as an example, it includes two gate driving circuits. The first reset transistor T1 corresponding to the first stage shift register 21 of the second gate driving circuit G2 is called the first type transistor T1-1, and the first reset transistor T1 corresponding to the other stages of shift register 21 in the two gate driving circuits is called the second type transistor T1-2. The amplitude of the first initial signal Vinit1 received by the first type transistor T1-1 from the first initial signal line is different from the amplitude of the first initial signal Vinit1 received by the second type transistor T1-2 from the first initial signal line. In practical implementation, multiple initial signal lines can be divided into a first type signal line V1-1 and a second type signal line V1-2. The source of the first type transistor T1-1 is connected to the first type signal line to receive the first type initial signal (denoted as Vinit1-1), and the source of the second type transistor T1-2 is connected to the second type signal line to receive the second type initial signal (denoted as Vinit1-2). The amplitude of Vinit1-1 is different from that of Vinit1-2. For example, the amplitude of Vinit1-1 can be greater than that of Vinit1-2. In practice, the difference in amplitude between the signals received by the two types of transistors can be determined through adjustment. The adjustment result should make the brightness of the folded line consistent with or almost consistent with that of other display areas.
[0098] In this extended embodiment 2, by individually controlling the source drive signal of the first reset transistor T1 in the pixel driving circuit near the fold line, making it different from the source drive signal of the first reset transistor T1 at other locations, the pixel current near the fold line can be adjusted, thereby improving the black line or brightness difference at this location.
[0099] Extended Example 3
[0100] For a display panel comprising N gate drive circuits, the second reset transistor T7 corresponding to each first-stage shift register 21 in the 2nd to Nth gate drive circuits is referred to as a third-type transistor T7-1, and the second reset transistor T7 corresponding to the other shift registers 21 in the N gate drive circuits is referred to as a fourth-type transistor T7-2. In extended embodiment 3, the amplitude of the second initial signal Vinit2 received by the third-type transistor T7-1 from the second initial signal line is different from the amplitude of the second initial signal Vinit2 received by the fourth-type transistor T7-2 from the second initial signal line.
[0101] Figure 16 is a schematic diagram of the display panel provided in Extended Embodiment 3. As shown in Figure 16, taking the double-fold display panel as an example, it includes two gate driving circuits. The second reset transistor T7 corresponding to the first stage shift register 21 of the second gate driving circuit G2 is referred to as the third type transistor T7-1, and the second reset transistor T7 corresponding to the other stages of shift register 21 in the two gate driving circuits is referred to as the fourth type transistor T7-2. The amplitude of the second initial signal Vinit2 received by the third type transistor T7-1 from the second initial signal line is different from the amplitude of the second initial signal Vinit2 received by the fourth type transistor T7-2 from the second initial signal line. In practical implementation, multiple second initial signal lines can be divided into third-type signal lines V2-1 and fourth-type signal lines V2-2. The source of the third-type transistor T7-1 is connected to the third-type signal line to receive the third-type initial signal (denoted as Vinit2-1), and the source of the fourth-type transistor T7-2 is connected to the fourth-type signal line to receive the fourth-type initial signal (denoted as Vinit2-2). The amplitude of Vinit2-1 differs from that of Vinit2-2. For example, the amplitude of Vinit2-1 can be greater than that of Vinit2-2. In practice, the difference in amplitude between the signals received by the two types of transistors can be determined through adjustment. The adjustment result should ensure that the brightness of the folded lines is consistent with or nearly consistent with that of other display areas.
[0102] In this extended embodiment 3, by individually controlling the source drive signal of the second reset transistor T7 in the pixel driving circuit near the fold line, making it different from the source drive signal of the second reset transistor T7 at other locations, the pixel current near the fold line can be adjusted, thereby improving the black line or brightness difference at this location.
[0103] Extended Example 4
[0104] For a display panel comprising N gate drive circuits, the third reset transistor T8 corresponding to each first-stage shift register 21 in the 2nd to Nth gate drive circuits is referred to as the fifth type transistor T8-1, and the third reset transistor T8 corresponding to the other shift registers 21 in the N gate drive circuits is referred to as the sixth type transistor T8-2. In extended embodiment 4, the amplitude of the third initial signal Vinit3 received by the fifth type transistor T8-1 from the third initial signal line is different from the amplitude of the third initial signal Vinit3 received by the sixth type transistor T8-2 from the third initial signal line.
[0105] Figure 17 is a schematic diagram of the display panel provided in Extended Embodiment 4. As shown in Figure 17, taking the double-fold display panel as an example, it includes two gate driving circuits. The third reset transistor T8 corresponding to the first-stage shift register 21 of the second gate driving circuit G2 is referred to as the fifth type transistor T8-1, and the third reset transistor T8 corresponding to the other shift registers 21 in the two gate driving circuits is referred to as the sixth type transistor T8-2. The amplitude of the third initial signal Vinit3 received by the fifth type transistor T8-1 from the third initial signal line is different from the amplitude of the third initial signal Vinit3 received by the sixth type transistor T8-2 from the third initial signal line. In practical implementation, multiple third initial signal lines can be divided into fifth-type signal lines V3-1 and sixth-type signal lines V3-2. The source of the fifth-type transistor T8-1 is connected to the first-type signal line to receive the fifth-type initial signal (denoted as Vinit3-1), and the source of the sixth-type transistor T8-2 is connected to the sixth-type signal line to receive the sixth-type initial signal (denoted as Vinit3-2). The amplitudes of Vinit3-1 and Vinit3-2 are different. For example, the amplitude of Vinit3-1 can be greater than that of Vinit3-2. In practice, the difference in amplitude between the signals received by the two types of transistors can be determined through adjustment. The adjustment result should make the brightness of the folded lines consistent with or nearly consistent with that of other display areas.
[0106] In this extended embodiment 4, by individually controlling the source drive signal of the third reset transistor T8 in the pixel driving circuit near the fold line, making it different from the source drive signal of the third reset transistor T8 at other locations, the pixel current near the fold line can be adjusted, thereby improving the black line or brightness difference at this location.
[0107] In some embodiments, referring to Figures 6 to 10, the display panel further includes a clock signal line, and the shift register 21 in each gate drive circuit is connected to the clock signal line CLK for obtaining the clock signal during operation using the clock signal line CLK.
[0108] In summary, to address the issues of black lines or uneven brightness in foldable display panels, this disclosure provides a display panel in its first aspect and details various specific embodiments of the display panel. The core of Embodiments 1 and 2 lies in providing an auxiliary gate driving circuit for the gate driving circuit. This auxiliary gate driving circuit converts the frame enable signal into a cascaded signal, thereby reducing the difference between the gate driving signal of the pixel driving circuit in the folded region and the gate driving signal of other regions, thus reducing brightness differences. Extended Embodiment 1 is an extension of Embodiments 1 and 2, its core being the reuse of redundant gate driving circuits as auxiliary gate driving circuits to simplify the fabrication process and improve bezel utilization. The core of Extended Embodiments 2-4 lies in individually controlling the source driving signals of some transistors (T1, T7, and T8) in the pixel driving circuit of the folded region, making them different from the source driving signals of other regions, thereby reducing the difference in pixel current between the folded region and other regions, thus reducing brightness differences.
[0109] Based on the above inventive concept, this application also provides a display device, including a display panel as described in any of the foregoing embodiments.
[0110] The display device described above is used to apply the corresponding display panel in the foregoing embodiments and has the beneficial effects of the corresponding display panel embodiments, which will not be repeated here.
[0111] It is understandable that the display device is a product with image display function, and it is generally driven by multiple driving circuits. For example, it can be: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large wall area, home appliance, information query equipment (such as business query equipment of e-government, bank, hospital, power and other departments, monitor, etc.).
[0112] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.
[0113] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.
[0114] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.
[0115] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.
Claims
1. A display panel, divided into N regions arranged sequentially along a first direction, each region including a display area and a peripheral area located on at least one side of the display area; N is an integer not less than 2; in, The display panel includes: N pixel subarrays are located in the N display areas respectively; each pixel subarray includes multiple pixels arranged in rows and columns. N gate driving circuits are located in N peripheral regions respectively; for the gate driving circuit and the pixel sub-array located in the same region, the gate driving circuit is configured to provide a gate driving signal to the pixel sub-array in response to the corresponding frame enable signal; the gate driving circuit includes a multi-stage cascaded shift register, with each stage of the shift register corresponding to a row of pixels; N frame enable signal lines, each frame enable signal line being configured to provide the frame enable signal to the corresponding gate drive circuit; (N-1) auxiliary gate driving circuits, wherein each auxiliary gate driving circuit includes at least one auxiliary shift register; The first frame enable signal line is connected to the signal input terminal of the first stage shift register of the first gate drive circuit; when 2≤i≤N, the i-th frame enable signal line is connected to the signal input terminal of the first stage auxiliary shift register of the (i-1)-th auxiliary gate drive circuit, and the signal output terminal of the last stage auxiliary shift register of the (i-1)-th auxiliary gate drive circuit is connected to the signal input terminal of the first stage shift register of the i-th gate drive circuit; and when the auxiliary gate drive circuit includes multiple stages of auxiliary shift registers, adjacent stages of the multiple stages of auxiliary shift registers are cascaded.
2. The display panel according to claim 1, wherein, The i-th auxiliary gate drive circuit is located in the (i+1)-th peripheral region.
3. The display panel according to claim 1, wherein, At least a portion of the auxiliary gate drive circuit is located in the first peripheral region.
4. The display panel according to any one of claims 1-3, wherein, It also includes: M redundant gate drive circuits; M is an integer not less than 1; Of the M redundant gate drive circuits, at least a portion of the redundant gate drive circuits are reused as the auxiliary gate drive circuit.
5. The display panel according to claim 4, wherein, Of the M redundant gate driving circuits, at least a portion is located in the first peripheral region and corresponds to the corner region of the first display region; The auxiliary gate drive circuit located in the first peripheral region is multiplexed by the redundant gate drive circuit located in the first peripheral region.
6. The display panel according to claim 5, wherein, For the auxiliary gate drive circuit located in the first peripheral region, each of its auxiliary shift registers is located on the side of the first-stage shift register in the first gate drive circuit that is away from the second peripheral region.
7. The display panel according to claim 5, wherein, For the auxiliary gate drive circuit located in the first peripheral region, each of its auxiliary shift registers is located among multiple shift registers in the first gate drive circuit.
8. The display panel according to claim 1, wherein, For a portion of the auxiliary gate drive circuit, the signal output terminal of a partial stage auxiliary shift register is connected to the compensation line.
9. The display panel according to claim 8, wherein, The compensation line extends along the first direction and is located in the surrounding area.
10. The display panel according to claim 1, wherein, The gate driving circuit includes at least a second reset driving circuit, a scan driving circuit, and a compensation driving circuit; The auxiliary gate drive circuit includes a first auxiliary drive circuit, a second auxiliary drive circuit, and a third auxiliary drive circuit. The first auxiliary driving circuit is connected to the second reset driving circuit, the second auxiliary driving circuit is connected to the scan driving circuit, and the third auxiliary driving circuit is connected to the compensation driving circuit.
11. The display panel according to claim 10, wherein, The gate driving circuit further includes a first reset driving circuit. The pixel includes a pixel driving circuit, and the pixel driving circuit includes: a first reset transistor; The display panel also includes: multiple first reset signal lines; A first reset signal line, a first-level shift register of the first reset drive circuit, and a row of pixels are configured accordingly; For the corresponding first reset signal line, the shift register, and the pixel, the control electrode of the first reset transistor is connected to the second end of the first reset signal line, and the first end of the first reset signal line is connected to the signal output terminal of the shift register.
12. The display panel according to claim 11, wherein, The display panel also includes: multiple first initial signal lines; The first terminal of the first reset transistor is connected to the first initial signal line; The first reset transistor corresponding to each first-stage shift register in the second to N gate driving circuits is called a first-type transistor, and the first reset transistor corresponding to the other shift registers in the N gate driving circuits is called a second-type transistor; the amplitude of the first initial signal transmitted by the first initial signal line received by the first-type transistor is different from the amplitude of the first initial signal transmitted by the first initial signal line received by the second-type transistor.
13. The display panel according to claim 10, wherein, The pixel includes a pixel driving circuit; The pixel driving circuit includes: a second reset transistor and a third reset transistor; The display panel also includes: multiple second reset signal lines; A second reset signal line is configured to correspond to the first-level shift register of the second reset drive circuit and a row of pixels; For the corresponding second reset signal line, the shift register, and the pixel, the control electrode of the second reset transistor and the third reset transistor are both connected to the second end of the second reset signal line, and the first end of the second reset signal line is connected to the signal output terminal of the shift register.
14. The display panel according to claim 13, wherein, The display panel also includes: multiple second initial signal lines; The first terminal of the second reset transistor is connected to the second initial signal line; The second reset transistor corresponding to each first-stage shift register in the second to N gate drive circuits is called a third type transistor, and the second reset transistor corresponding to the other shift registers in the N gate drive circuits is called a fourth type transistor; the amplitude of the voltage signal received by the third type transistor from the second initial signal line is different from the amplitude of the voltage signal received by the fourth type transistor from the second initial signal line.
15. The display panel according to claim 13, wherein, The display panel also includes: multiple third initial signal lines; The first terminal of the third reset transistor is connected to the third initial signal line; The third reset transistor corresponding to each first-stage shift register in the second to Nth gate drive circuits is called a fifth type transistor, and the third reset transistor corresponding to the other shift registers in the N gate drive circuits is called a sixth type transistor; the amplitude of the voltage signal received by the fifth type transistor from the third initial signal line is different from the amplitude of the voltage signal received by the sixth type transistor from the third initial signal line.
16. The display panel according to claim 10, wherein, The pixel includes a pixel driving circuit; The pixel driving circuit includes: a compensation transistor; The display panel also includes: multiple first scan signal lines; A first scan signal line, a first-level shift register of the scan driving circuit, and a row of pixels are configured accordingly; For the corresponding first scan signal line, the shift register, and the pixel, the control electrode of the compensation transistor is connected to the second end of the first scan signal line, and the first end of the first scan signal line is connected to the signal output terminal of the shift register.
17. The display panel according to claim 10, wherein, The pixel includes a pixel driving circuit; The pixel driving circuit includes: a data writing transistor; The display panel also includes: multiple second scan signal lines; A second scan signal line is configured to correspond to the first-level shift register of the scan driving circuit and a row of pixels; For the corresponding second scan signal line, the shift register, and the pixel, the control electrode of the data write transistor is connected to the second end of the second scan signal line, and the first end of the second scan signal line is connected to the signal output terminal of the shift register.
18. The display panel according to claim 17, wherein, Also includes: Multiple data signal lines; The first terminal of the data writing transistor is connected to a data signal line.
19. The display panel according to claim 10, wherein, The gate driving circuit also includes a light-emitting driving circuit. The pixel includes a pixel driving circuit; The pixel driving circuit includes: a light-emitting control transistor; The display panel also includes: multiple light-emitting control signal lines; One of the light emission control signal lines, a first-level shift register of the light emission driving circuit, and a row of pixels are configured accordingly; For the corresponding light emission control signal line, the shift register, and the pixel, the control electrode of the light emission control transistor is connected to the second end of the light emission control signal line, and the first end of the light emission control signal line is connected to the signal output terminal of the shift register.
20. A display device, wherein, The display panel includes any one of claims 1-19.