Design of base mesh grid information in dynamic mesh coding and decoding

Abstract

A mechanism for processing video data is disclosed. The mechanism includes determining that a value of the presumed syntax element is equal to 0 when the syntax element is not present in the bitstream. The value of the syntax element plus one specifies the number of sub-grids in each grid frame. A conversion is performed between the visual media data and the bitstream based on the syntax element.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 588,788, filed October 9, 2023, which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to the generation, storage, and use of digital audio and video media information in file formats. Background Technology

[0004] Digital video accounts for the largest share of bandwidth used on the internet and other digital communication networks. As the number of connected user devices capable of receiving and displaying video increases, the bandwidth demand for digital video is likely to continue to grow. Summary of the Invention

[0005] The first aspect relates to a method for processing media data, comprising: determining, when a syntax element is not present in a bitstream, that the value of the presumed syntax element is equal to 0, wherein the value of the syntax element plus one specifies the number of subgrids in each grid frame; and performing a conversion between visual media data and a bitstream based on the value of the syntax element.

[0006] Alternatively, in any of the above aspects, another implementation of the aspect provides that the syntax element is specified as bmsi_num_submeshes_minus1.

[0007] Alternatively, in any of the foregoing aspects, another implementation of that aspect provides that the values ​​of the syntax elements are in the range of 0 to 255 (including boundary values).

[0008] Alternatively, in any of the foregoing aspects, another implementation of that aspect provides that the value of the syntax element is encoded or decoded in the bitstream as a 6-bit unsigned integer.

[0009] Alternatively, in any of the foregoing aspects, another implementation of that aspect provides encoding and decoding the values ​​of syntax elements in a bitstream using N bits, where N is an integer greater than 8.

[0010] Alternatively, in any of the foregoing aspects, another implementation of that aspect provides that the value of a syntax element is encoded or decoded in a bitstream as an N-bit unsigned integer, where N is an integer greater than 8.

[0011] Alternatively, in any of the foregoing aspects, another implementation of that aspect provides that the value of a syntax element is encoded or decoded in a bitstream as an N-bit unsigned integer, where N is one of 12, 16, 24, and 32.

[0012] Alternatively, in any of the above aspects, another implementation of that aspect provides that when there is only one subgrid, the value of the subgrid's identifier (ID) is not present in the bitstream.

[0013] Alternatively, in any of the above aspects, another implementation of the aspect provides that when there is only one subgrid, the value of the subgrid's identifier (ID) is presumed to be equal to 0.

[0014] Optionally, in any of the above aspects, another embodiment of the aspect provides that the number of bits used to represent the subgrid identifier (ID) syntax element is included in the bit stream as an incremental value between the number of bits and a fixed value, and wherein the fixed value is greater than 1.

[0015] Alternatively, in any of the above aspects, another implementation of the aspect provides a fixed value including Ceil(Log2(bmsi_num_submeshes_minus1 + 1)), where Ceil represents the upper bound function and Log2 represents the logarithmic function to the base 2.

[0016] Alternatively, in any of the above aspects, another implementation of that aspect provides that when the increment value is not present in the bitstream, the increment value is presumed to be equal to 0.

[0017] Alternatively, in any of the above aspects, another implementation of that aspect provides that the range of the increment value is from 0 to N, where N is an integer.

[0018] Alternatively, in any of the above aspects, another implementation of that aspect provides N equal to 15.

[0019] Alternatively, in any of the foregoing aspects, another implementation of that aspect provides a conversion that includes encoding media data into a bitstream.

[0020] Alternatively, in any of the above aspects, another implementation of that aspect provides a conversion that includes decoding media data from a bitstream.

[0021] The second aspect relates to an apparatus for processing video or image data, comprising: a processor; and a non-transitory memory having instructions thereon, wherein the instructions, when executed by the processor, cause the processor to perform a method of any of the disclosed embodiments.

[0022] The third aspect relates to a non-transitory computer-readable medium including a computer program product for use by a video codec apparatus, the computer program product including computer-executable instructions stored on the non-transitory computer-readable medium, causing the video codec apparatus to perform the method of any of the disclosed embodiments when executed by a processor.

[0023] The fourth aspect relates to a non-transitory computer-readable recording medium storing a bitstream of video generated by a method performed by a video processing apparatus, wherein the method includes: determining, when a syntax element is not present in the bitstream, that the value of the presumed syntax element is equal to 0, wherein the value of the syntax element plus one specifies the number of subgrids in each grid frame; and performing a conversion between visual media data and the bitstream based on the value of the syntax element.

[0024] The fifth aspect relates to a method for storing a bitstream of video, comprising: determining, when a syntax element is not present in the bitstream, that the value of the presumed syntax element is equal to 0, wherein the value of the syntax element plus one specifies the number of subgrids in each grid frame; generating a bitstream based on the syntax element; and storing the bitstream in a non-transitory computer-readable recording medium.

[0025] The sixth aspect relates to the methods, apparatus, or systems described in this disclosure.

[0026] For clarity, any of the embodiments described above may be combined with any one or more of the other embodiments described above to create new embodiments within the scope of this disclosure.

[0027] These and other features will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings and claims. Attached Figure Description

[0028] To gain a more complete understanding of this disclosure, reference is now made to the following brief description, taken in conjunction with the accompanying drawings and detailed description, wherein like reference numerals denote like parts.

[0029] Figure 1 This is a block diagram illustrating the decoder design for dynamic mesh encoding and decoding.

[0030] Figure 2 This is a block diagram illustrating the structure of the dynamic mesh encoding / decoding test model.

[0031] Figure 3 This is a block diagram illustrating an example video processing system.

[0032] Figure 4 This is a block diagram of an example video processing device.

[0033] Figure 5 This is a flowchart of an example method for video processing.

[0034] Figure 6 This is a block diagram illustrating an example video codec system.

[0035] Figure 7 This is a block diagram showing an example encoder.

[0036] Figure 8 This is a block diagram showing an example decoder.

[0037] Figure 9 This is a schematic diagram of an example encoder. Detailed Implementation

[0038] First, it should be understood that although illustrative implementations of one or more embodiments are provided below, the disclosed systems and / or methods can be implemented using any number of techniques, whether currently known or yet to be developed. This disclosure should not be limited in any way to the illustrative implementations, drawings, and techniques shown below, including the exemplary designs and implementations shown and described herein, but rather to modifications within the scope of the appended claims and the full scope of their equivalents.

[0039] 1. Preliminary Discussion

[0040] This disclosure relates to improvements in dynamic grid coding and decoding for Motion Picture Experts Group Immersive (MPEG-I) video. Specifically, it relates to the advanced syntax design of the base grid subgrid. It can also be applied to other immersive video coding and decoding standards or codecs.

[0041] 2. Further discussion

[0042] In computer graphics, three-dimensional (3D) / immersive content can typically be represented by 3D meshes and texture maps. These mesh and texture data can be generated by machines or converted from images captured by multiple cameras from different angles. Similar to two-dimensional (2D) video, the mesh and texture data also change as these 3D contents change over time, including dynamic mesh sequences. Dynamic meshes are typically large in data and difficult to store and transmit. To meet the requirements of applications using dynamic meshes, the Motion Picture Experts Group (MPEG) issued a call for proposals [1]. One of the key requirements for effectively using existing 2D codecs is to use current 2D video codec standards to compress most of the data and keep the rest simple and low in complexity. Such requirements ensure that the representation can take advantage of 2D video hardware / software systems without spending a lot of effort to redesign specific systems dedicated to dynamic meshes.

[0043] MPEG received five responses to the solicitation of proposals. Among them, proposal [2] showed better performance compared to the other proposals. Therefore, based on [2], a test model was built to develop the planned dynamic mesh coding standard.

[0044] Until the draft was published, the latest test model of Dynamic Mesh Coding (V-DMC) could be found at the following link: http: / / mpegx.int-evry.fr / software / MPEG / dmc / mpeg-vmesh-tm / - / tags / v5.0; the latest working draft (WD) document was WD 4.0 [3].

[0045] 2.1 Data Representation in Dynamic Mesh Encoding and Decoding

[0046] Figure 1 This is a block diagram illustrating the decoder design for dynamic mesh encoding and decoding. Figure 1The decoder design as described in WD 4.0 [3] is shown. It can be seen that the dynamic mesh decoder receives four bitstreams and performs decoding to reconstruct the dynamic mesh plus texture signal. The first bitstream is used to represent the base mesh, which is a decimated version of the original mesh. The second bitstream is used to represent the displacement vector between the reconstructed base mesh and the original mesh. The displacement vector is arranged as 2D video and compressed using a codec that conforms to the 2D video codec standard, or the displacement can be encoded and decoded using an arithmetic codec. The third bitstream is used to represent the texture (or attribute map). The attribute map is also arranged as 2D video and compressed using a codec that conforms to the 2D video codec standard. The design philosophy is to make the base mesh portion small enough so that the module that processes the base mesh can be easily implemented. On the other hand, the displacement vectors and attribute maps account for the majority of the volume of the entire dynamic mesh data, which can be processed using current dedicated high-efficiency 2D video codec systems. Such a design can reduce the extra effort required to implement a dynamic mesh codec system and ensure high throughput and encoding / decoding efficiency of the dynamic mesh data.

[0047] 2.2 Test Model for Dynamic Mesh Encoding and Decoding

[0048] Figure 2 This is a block diagram illustrating the structure of the dynamic mesh encoding / decoding test model. Figure 2 The structure of an example dynamic mesh codec model is shown. In this model, Draco is used to compress the base mesh, and an HEVC test model (e.g., HM) is used to compress the displacement vectors and property maps. However, it should be noted that other mesh or video codec systems can also be used for dynamic mesh codecs.

[0049] The base mesh m is generated from the original mesh using a downsampling scheme. Then, its quantized version is applied using Draco. Encoding and decoding can be performed. This can be done by... Perform inverse quantization to obtain the base mesh for reconstruction. Displacement vector It is calculated by using a subdivision scheme to compare the original mesh with... It is generated by the difference between the subdivisions.

[0050] 2.3 Basic Mesh Submesh Information Syntax and Semantics

[0051] In the example V-DMC design, the base grid subgrid information is used to indicate the number of subgrids, and an identifier (ID) is assigned to each subgrid. The relevant syntax and semantics are as follows:

[0052] H.8.1.3.2.2 Basic Mesh Sub-mesh Information

[0053]

[0054] H.8.3.2.2 Basic Mesh Sub-mesh Information

[0055] A value of 1 for `bmsi_use_single_mesh_flag` specifies that there is only one sub-mesh in each mesh frame of the reference BFPS. A value of 0 for `bmsi_use_single_mesh_flag` specifies that there can be more than one sub-mesh in each mesh frame of the reference BFPS.

[0056] Incrementing bmsi_num_submeshes_minus1 by 1 specifies the number of sub-mesh elements in each mesh frame of the reference BFPS. The value of bmsi_num_submeshes_minus1 must be in the range of 0 to 63 (inclusive). When it does not exist and bmsi_use_single_mesh_flag is equal to 1, its value is presumed to be 1.

[0057] A value of 1 for `bmsi_signalled_submesh_id_flag` specifies that the submesh ID is transmitted via signaling for each mesh frame. A value of 0 for `bmsi_signalled_tile_id_flag` specifies that the submesh ID is not transmitted via signaling.

[0058] The increment of 1 in `bmsi_signalled_submesh_id_length_minus1` specifies the number of bits used to represent the syntax element `bmsi_tile_id[i]` (if present), and the syntax element `submesh_id` is in the submesh header. The value of `bmsi_signalled_tile_id_length_minus1` must be in the range of 0 to 15 (inclusive). When it does not exist, its value is presumed to be equal to `Ceil(Log2(bmsi_num_submeshes_minus1 + 1)) - 1`.

[0059] `bmsi_submesh_id[i]` specifies the slice ID of the i-th submesh. The length of the `bmsi_submesh_id[i]` syntax element is `bmsi_signalled_submesh_id_length_minus1 + 1` bits. When it does not exist, the value of `bmsi_submesh_id[i]` is presumed to be equal to `i`, where `i` ranges from 0 to `bmsi_num_submeshes_minus1` (inclusive). For bitstream consistency, `bmsi_submesh_id[i]` should not be equal to `bmsi_submesh_id[j]` for all `i != j`. The length of the `bmsi_submesh_id[i]` syntax element is `bmsi_signalled_submesh_id_length_minus1 + 1` bits.

[0060] The variable FirstSubmeshID is calculated as follows:

[0061] FirstSubmeshID= bmsi_submesh_id[0]

[0062] for ( i = 1; i < bmsi_num_submeshes_minus1+ 1; i++ )

[0063] FirstSubmeshID = Min(FirstSubmeshID, bmsi_submesh_id[ i ])

[0064] 3. The technical problem solved by the disclosed technical solution

[0065] The example design for dynamic mesh encoding and decoding has the following problems:

[0066] First, the estimated value of bmsi_num_submeshes_minus1 is incorrect.

[0067] Second, the value of bmsi_num_submeshes_minus1 must be in the range of 0-63 and be encoded / decoded as u(8). This range does not match the number of bits. Furthermore, using 8 bits to transmit bmsi_num_submeshes_minus1 via signaling may be too limited.

[0068] Third, when there is only one subgrid, it is meaningless to transmit the ID of the unique subgrid via signaling.

[0069] Fourth, the number of bits used to transmit the submesh ID via signal is (bmsi_signalled_submesh_id_length_minus1 + 1), which is in the range of 1 to 16. Due to the constraint that each submesh must have a different ID value, this may be illegal in some cases.

[0070] 4. List of solutions and implementation examples

[0071] To address the aforementioned issues, the methods outlined below are disclosed. These projects should be considered as examples for interpreting general concepts, and not interpreted in a narrow sense. Furthermore, these designs can be applied individually or in combination in any way.

[0072] 1. To solve problem 1, one or more of the following methods are specified:

[0073] a. In one example, when it does not exist, the value of bmsi_num_submeshes_minus1 is presumed to be equal to 0.

[0074] 2. To solve problem 2, one or more of the following methods are specified:

[0075] a. In one example, the value of bmsi_num_submeshes_minus1 must be in the range of 0 to 255.

[0076] b. Alternatively, it is proposed to use u(6) to transmit bmsi_num_submeshes_minus1 via signaling.

[0077] 3. To better address problem 2, one or more of the following methods are specified:

[0078] a. In one example, N bits (N>8) can be used to transmit bmsi_num_submeshes_minus1 via signaling.

[0079] i. In one example, u(N) is used to transmit bmsi_num_submeshes_minus1 via signaling.

[0080] ii. In one example, N equals 12, 16, 24, or 32.

[0081] 4. To solve problem 3, one or more of the following methods are specified:

[0082] a. In one example, when there is only one subgrid, the ID value of that subgrid is not transmitted via signaling.

[0083] b. In one example, when there is only one subgrid, the ID value of that subgrid is presumed to be equal to 0.

[0084] 5. To solve problem 4, one or more of the following methods are specified:

[0085] a. In one example, the increment between the number of bits indicating the subgrid ID transmitted via signaling and a fixed value greater than 1.

[0086] i. In one example, the fixed value is Ceil(Log2(bmsi_num_submeshes_minus1+1)).

[0087] ii. In one example, when the increment value does not exist, the increment value is presumed to be equal to 0.

[0088] iii. In one example, the increment value ranges from 0 to N.

[0089] 1. In one example, N equals 15.

[0090] 5. Examples

[0091] The following are some example implementations of the aspects outlined in Section 4 of the previous article.

[0092] The most relevant additions or modifications are shown in bold, and some deleted parts are shown in italics. Other editable changes may exist and are therefore not indicated.

[0093] The following text changes are based on WD 4.0 with V-DMC [3].

[0094] 5.1 Example 1

[0095] This embodiment refers to item 1, which was outlined in section 4 of the previous article.

[0096] H.8.1.3.2.2 Basic Mesh Sub-mesh Information

[0097]

[0098] H.8.3.2.2 Basic Mesh Sub-mesh Information

[0099] A value of 1 for `bmsi_use_single_mesh_flag` specifies that there is only one sub-mesh in each mesh frame of the reference BFPS. A value of 0 for `bmsi_use_single_mesh_flag` specifies that there can be more than one sub-mesh in each mesh frame of the reference BFPS.

[0100] Incrementing bmsi_num_submeshes_minus1 by 1 specifies the number of sub-mesh elements in each mesh frame of the reference BFPS. The value of bmsi_num_submeshes_minus1 must be in the range of 0 to 63 (inclusive). When it does not exist and bmsi_use_single_mesh_flag is equal to 1, its value is presumed to be equal to 1.

[0101] 5.2 Example 2

[0102] This embodiment refers to item 2.a, which was outlined in section 4 of the previous article.

[0103] H.8.3.2.2 Basic Mesh Sub-mesh Information

[0104] A value of 1 for `bmsi_use_single_mesh_flag` specifies that there is only one sub-mesh in each mesh frame of the reference BFPS. A value of 0 for `bmsi_use_single_mesh_flag` specifies that there can be more than one sub-mesh in each mesh frame of the reference BFPS.

[0105] Incrementing bmsi_num_submeshes_minus1 by 1 specifies the number of sub-mesh arrays in each mesh frame of the reference BFPS. The value of bmsi_num_submeshes_minus1 must be in the range of 0 to 63,255 (inclusive). When it does not exist and bmsi_use_single_mesh_flag is equal to 1, its value is presumed to be 1.

[0106] 5.3 Example 3

[0107] This embodiment refers to item 3, which was outlined in section 4 of the previous article.

[0108] H.8.1.3.2.2 Basic Mesh Sub-mesh Information

[0109]

[0110] 5.4 Example 4

[0111] This embodiment refers to item 4, which was outlined in section 4 of the previous article.

[0112] H.8.1.3.2.2 Basic Mesh Sub-mesh Information

[0113]

[0114] H.8.3.2.2 Basic Mesh Sub-mesh Information

[0115] A value of 1 for `bmsi_use_single_mesh_flag` specifies that there is only one sub-mesh in each mesh frame of the reference BFPS. A value of 0 for `bmsi_use_single_mesh_flag` specifies that there can be more than one sub-mesh in each mesh frame of the reference BFPS.

[0116] Incrementing bmsi_num_submeshes_minus1 by 1 specifies the number of sub-mesh elements in each mesh frame of the reference BFPS. The value of bmsi_num_submeshes_minus1 must be in the range of 0 to 63 (inclusive). When it does not exist and bmsi_use_single_mesh_flag is equal to 1, its value is presumed to be 1.

[0117] A value of 1 for `bmsi_signalled_submesh_id_flag` specifies that the submesh ID is signaled for each mesh frame. A value of 0 for `bmsi_signalled_tile_id_flag` specifies that the submesh ID is not signaled. When it does not exist, the value of `bmsi_signalled_submesh_id_flag` is assumed to be 0.

[0118] The increment of 1 in `bmsi_signalled_submesh_id_length_minus1` specifies the number of bits used to represent the syntax element `bmsi_tile_id[i]` (if present), and the syntax element `submesh_id` is in the submesh header. The value of `bmsi_signalled_tile_id_length_minus1` must be in the range of 0 to 15 (inclusive). When it does not exist, its value is presumed to be equal to `Ceil(Log2(bmsi_num_submeshes_minus1 + 1)) - 1`.

[0119] `bmsi_submesh_id[i]` specifies the slice ID of the i-th submesh. The length of the syntax element `bmsi_submesh_id[i]` is `bmsi_signalled_submesh_id_length_minus1 + 1` bits. When it does not exist, for each `i` in the range from 0 to `bmsi_num_submeshes_minus1` (inclusive), the value of `bmsi_submesh_id[i]` is presumed to be equal to `i`. The requirement for bitstream consistency is that for all `i != j`, `bmsi_submesh_id[i]` should not be equal to `bmsi_submesh_id[j]`. The length of the syntax element `bmsi_submesh_id[i]` is `bmsi_signalled_submesh_id_length_minus1 + 1` bits.

[0120] The variable FirstSubmeshID is calculated as follows:

[0121] FirstSubmeshID= bmsi_submesh_id[0]

[0122] for ( i = 1; i < bmsi_num_submeshes_minus1+ 1; i++ )

[0123] FirstSubmeshID = Min(FirstSubmeshID, bmsi_submesh_id[ i ])

[0124] 5.5 Example 5

[0125] This embodiment refers to item 1, which was outlined in section 4 of the previous article.

[0126] H.8.1.3.2.2 Basic Mesh Sub-mesh Information

[0127]

[0128] H.8.3.2.2 Basic Mesh Sub-mesh Information

[0129] A value of 1 for `bmsi_use_single_mesh_flag` specifies that there is only one sub-mesh in each mesh frame of the reference BFPS. A value of 0 for `bmsi_use_single_mesh_flag` specifies that there can be more than one sub-mesh in each mesh frame of the reference BFPS.

[0130] Incrementing bmsi_num_submeshes_minus1 by 1 specifies the number of sub-mesh elements in each mesh frame of the reference BFPS. The value of bmsi_num_submeshes_minus1 must be in the range of 0 to 63 (inclusive). When it does not exist and bmsi_use_single_mesh_flag is equal to 1, its value is presumed to be 1.

[0131] A value of 1 for `bmsi_signalled_submesh_id_flag` specifies that the submesh ID is transmitted via signaling for each mesh frame. A value of 0 for `bmsi_signalled_tile_id_flag` specifies that the submesh ID is not transmitted via signaling.

[0132] `bmsi_signalled_submesh_id_delta_length_minus1` plus 1 `Ceil( Log2( bmsi_num_submeshes_minus1 + 1 ) )` specifies the number of bits used to represent the syntax element `bmsi_tile_id[ i ]` (if present), and the syntax element `submesh_id` is in the submesh header. The value of `bmsi_signalled_submesh_tile_id_delta_length_minus1` must be in the range of 0 to 15 (inclusive). When it does not exist, its value is presumed to be equal to `Ceil( Log2( bmsi_num_submeshes_minus1 + 1 ) ) – 1 0`.

[0133] `bmsi_submesh_id[i]` specifies the slice ID of the i-th submesh. The length of the syntax element `bmsi_submesh_id[i]` is `bmsi_signalled_submesh_id_length_minus1 + 1` bits. When it does not exist, for each `i` in the range from 0 to `bmsi_num_submeshes_minus1` (inclusive), the value of `bmsi_submesh_id[i]` is presumed to be equal to `i`. The requirement for bitstream consistency is that for all `i != j`, `bmsi_submesh_id[i]` should not be equal to `bmsi_submesh_id[j]`. The length of the syntax element `bmsi_submesh_id[i]` is `bmsi_signalled_submesh_id_length_minus1 + 1` bits.

[0134] The variable FirstSubmeshID is calculated as follows:

[0135] FirstSubmeshID = bmsi_submesh_id[0]

[0136] for (i = 1; i < bmsi_num_submeshes_minus1 + 1; i++)

[0137] FirstSubmeshID = Min(FirstSubmeshID, bmsi_submesh_id[i])

[0138] 6. References

[0139] [1]MPEG technical requirements, “CfP for. Dynamic Mesh Coding,” ISO / IEC JTC 1 / SC 29 / WG 2 doc.no. N145, in Oct. 2021.

[0140] [2]K. Mammou, J. Kim, A. Tourapis and D. Podborski, “[V-CG] Apple’sDynamic Mesh Coding CfP Response,” ISO / IEC JTC 1 / SC 29 / WG 7 doc. no. m59281,in Apr. 2022.

[0141] [3]MPEG output document, “WD 3.0 of V-DMC,” ISO / IEC JTC 1 / SC 29 / WG 7doc.no. N00611, in Apr. 2023.

[0142] [4]C. Huang, X. Xu, X. Zhang, J. Tian and S. Liu, “Investigation ofvideo coding of motion fields,” ISO / IEC JTC 1 / SC 29 / WG 7 doc. no. m61005, inJul. 2022.

[0143] Figure 3This is a block diagram illustrating an example video processing system 4000 in which various techniques disclosed herein may be implemented. Various implementations may include some or all of the components of system 4000. System 4000 may include an input 4002 for receiving video content. The video content may be received in a raw or uncompressed format, such as 8 or 10-bit multi-component pixel values, or it may be received in a compressed or encoded format. Input 4002 may represent a network interface, a peripheral bus interface, or a storage interface. Examples of network interfaces include wired interfaces (such as Ethernet, Passive Optical Networking (PON), etc.) and wireless interfaces (such as Wi-Fi or cellular interfaces).

[0144] System 4000 may include an encoding component 4004 capable of implementing the various encoding / decoding or encoding methods described in this disclosure. Encoding component 4004 may reduce the average bit rate from the video input 4002 to the output of encoding component 4004 to produce an encoded representation of the video. Encoding techniques are therefore sometimes referred to as video compression or video transcoding techniques. The output of encoding component 4004 may be stored or transmitted via a communication connection such as that represented by component 4006. The bitstream (or encoded) representation of the video received at input 4002, whether stored or transmitted via communication, may be used by component 4008 to generate pixel values ​​or displayable video that is sent to display interface 4010. The process of generating user-visible video from the bitstream representation is sometimes referred to as video decompression. Furthermore, although some video processing operations are referred to as “encoding” operations or tools, it is understood that encoding tools or operations are used by encoders, and corresponding decoding tools or operations that reverse the encoded result will be performed by decoders.

[0145] Examples of peripheral bus interfaces or display interfaces may include Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI), or DisplayPort. Examples of storage interfaces include Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect (PCI), Integrated Drive Electronics (IDE), etc. The technologies described in this disclosure can be embodied in a variety of electronic devices, such as mobile phones, laptops, smartphones, or other devices capable of performing digital data processing and / or video display.

[0146] Figure 4This is a block diagram of an example video processing apparatus 4100. Apparatus 4100 can be used to implement one or more methods described herein. Apparatus 4100 can be embodied in a smartphone, tablet, computer, Internet of Things (IoT) receiver, etc. Apparatus 4100 may include one or more processors 4102, one or more memories 4104, and video processing circuitry 4106. The processors 4102(s) may be configured to implement one or more methods described herein. The memories 4104(s) may be used to store data and code for implementing the methods and techniques described herein. The video processing circuitry 4106 may be used to implement some of the techniques described herein in hardware circuitry. In some embodiments, the video processing circuitry 4106 may be at least partially included in the processor 4102, such as a graphics coprocessor.

[0147] Figure 5 This is a flowchart of an example method 4200 for video processing. Method 4200 includes: in step 4202, when a syntax element is not present in the bitstream, determining that the value of the presumed syntax element is equal to 0, wherein the value of the syntax element plus one specifies the number of sub-grids in each grid frame. In one embodiment, the syntax element is specified as bmsi_num_submeshes_minus1. In step 4204, performing a conversion between visual media data and the bitstream based on the value of the syntax element. This conversion may include encoding at the encoder, decoding at the decoder, or a combination thereof.

[0148] It should be noted that method 4200 can be implemented in a means of processing video data, including a processor and a non-transitory memory having instructions thereon, such as a video encoder 4400, a video decoder 4500, and / or an encoder 4600. In this case, the instructions cause the processor to execute method 4200 when executed by the processor. Furthermore, method 4200 can be executed by a non-transitory computer-readable medium, which includes a computer program product for use by a video encoding / decoding device. The computer program product includes computer-executable instructions stored on the non-transitory computer-readable medium, such that when the computer-executable instructions are executed by a processor, the video encoding / decoding device executes method 4200.

[0149] Figure 6 This is a block diagram illustrating an example video encoding / decoding system 4300 that can utilize the techniques of this disclosure. The video encoding / decoding system 4300 may include a source device 4310 and a target device 4320. The source device 4310 generates encoded video data, and this source device 4310 may be referred to as a video encoding device. The target device 4320 can decode the encoded video data generated by the source device 4310, and this target device 4320 may be referred to as a video decoding device.

[0150] Source device 4310 may include video source 4312, video encoder 4314, and input / output (I / O) interface 4316. Video source 4312 may include sources such as video capture devices, interfaces for receiving video data from video content providers, and / or computer graphics systems for generating video data, or combinations thereof. Video data may include one or more pictures. Video encoder 4314 encodes the video data from video source 4312 to generate a bitstream. The bitstream may include a sequence of bits forming a coded representation of the video data. The bitstream may include encoded pictures and associated data. Encoded pictures are coded representations of pictures. Associated data may include sequence parameter sets, picture parameter sets, and other syntax structures. I / O interface 4316 may include a modulator / demodulator (modem) and / or a transmitter. Encoded video data may be transmitted directly to target device 4320 via network 4330 through I / O interface 4316. Encoded video data may also be stored on storage medium / server 4340 for access by target device 4320.

[0151] Target device 4320 may include I / O interface 4326, video decoder 4324, and display device 4322. I / O interface 4326 may include a receiver and / or a modem. I / O interface 4326 may acquire encoded video data from source device 4310 or storage medium / server 4340. Video decoder 4324 may decode the encoded video data. Display device 4322 may display the decoded video data to a user. Display device 4322 may be integrated with target device 4320 or may be external to target device 4320, wherein target device 4320 may be configured to interface with an external display device.

[0152] The video encoder 4314 and the video decoder 4324 can operate according to video compression standards, such as HEVC, VVC and other existing and / or further standards.

[0153] Figure 7 This is a block diagram illustrating an example of a video encoder 4400, which can be... Figure 6 The system 4300 shown includes a video encoder 4314. The video encoder 4400 can be configured to perform any or all of the techniques disclosed herein. The video encoder 4400 includes multiple functional components. The techniques described in this disclosure can be shared among the various components of the video encoder 4400. In some examples, a processor can be configured to perform any or all of the techniques described in this disclosure.

[0154] The functional components of the video encoder 4400 may include a segmentation unit 4401; a prediction unit 4402, which may include a mode selection unit 4403, a motion estimation unit 4404, a motion compensation unit 4405, and an intra-frame prediction unit 4406; a residual generation unit 4407; a transform processing unit 4408; a quantization unit 4409; an inverse quantization unit 4410; an inverse transform unit 4411; a reconstruction unit 4412; a buffer 4413; and an entropy coding unit 4414.

[0155] In other examples, the video encoder 4400 may include more, fewer, or different functional components. In one example, the prediction unit 4402 may include an intra-block copy (IBC) unit. The IBC unit can perform prediction in an IBC mode, where at least one reference picture is the picture in which the current video block is located.

[0156] Furthermore, some components such as the motion estimation unit 4404 and the motion compensation unit 4405 can be highly integrated, but for illustrative purposes, these components are represented separately in the example of the video encoder 4400.

[0157] The segmentation unit 4401 can segment an image into one or more video blocks. The video encoder 4400 and the video decoder 4500 can support various video block sizes.

[0158] The mode selection unit 4403 can select one of several encoding / decoding modes (intra-frame encoding / decoding or inter-frame encoding / decoding), for example, based on error results, and provide the resulting intra-frame or inter-frame encoded / decoded block to the residual generation unit 4407 to generate residual block data, and to the reconstruction unit 4412 to reconstruct the coded block for use as a reference image. In some examples, the mode selection unit 4403 can select an intra-frame / inter-frame joint prediction (CIIP) mode, where prediction is based on inter-frame prediction signals and intra-frame prediction signals. In the case of inter-frame prediction, the mode selection unit 4403 can also select a resolution for the block based on motion vectors (e.g., sub-pixel precision or integer pixel precision).

[0159] To perform inter-frame prediction on the current video block, motion estimation unit 4404 can generate motion information for the current video block by comparing one or more reference frames from buffer 4413 with the current video block. Motion compensation unit 4405 can determine the predicted video block for the current video block based on the motion information and decoded samples of images from buffer 4413 other than the image associated with the current video block.

[0160] The motion estimation unit 4404 and the motion compensation unit 4405 can perform different operations on the current video block, for example, depending on whether the current video block is in an I-band, P-band, or B-band.

[0161] In some examples, motion estimation unit 4404 can perform unidirectional prediction on the current video block, and can search for a reference video block for the current video block in the reference images of list 0 or list 1. Motion estimation unit 4404 can then generate a reference index indicating the reference image containing the reference video block in list 0 or list 1, and a motion vector indicating the spatial displacement between the current video block and the reference video block. Motion estimation unit 4404 can output the reference index, prediction direction indicator, and motion vector as motion information for the current video block. Motion compensation unit 4405 can generate a predicted video block for the current block based on the reference video block indicated by the motion information of the current video block.

[0162] In other examples, motion estimation unit 4404 can perform bidirectional prediction on the current video block. Motion estimation unit 4404 can search for a reference video block for the current video block in the reference images in list 0, and can also search for another reference video block for the current video block in the reference images in list 1. Motion estimation unit 4404 can then generate reference indices indicating the reference images containing the reference video blocks in lists 0 and 1, and motion vectors indicating the spatial displacement between the reference video blocks and the current video block. Motion estimation unit 4404 can output the reference index and motion vector of the current video block as motion information for the current video block. Motion compensation unit 4405 can generate a predicted video block for the current video block based on the reference video blocks indicated by the motion information of the current video block.

[0163] In some examples, the motion estimation unit 4404 can output a complete set of motion information for use in the decoder's decoding process. In some examples, the motion estimation unit 4404 may not output a complete set of motion information for the current video. Instead, the motion estimation unit 4404 can reference the motion information of another video block to transmit the motion information of the current video block via a signal. For example, the motion estimation unit 4404 may determine that the motion information of the current video block is sufficiently similar to the motion information of neighboring video blocks.

[0164] In one example, the motion estimation unit 4404 may indicate a value to the video decoder 4500 in the syntax structure associated with the current video block, which indicates that the current video block has the same motion information as another video block.

[0165] In another example, motion estimation unit 4404 may identify another video block and motion vector difference (MVD) in the syntax structure associated with the current video block. The motion vector difference indicates the difference between the motion vector of the current video block and the motion vector of the indicated video block. Video decoder 4500 may use the motion vector of the indicated video block and the motion vector difference to determine the motion vector of the current video block.

[0166] As discussed above, the video encoder 4400 can transmit motion vectors via signaling in a predictive manner. Two examples of predictive signaling techniques that can be implemented by the video encoder 4400 include Advanced Motion Vector Prediction (AMVP) and Merge Pattern Signaling.

[0167] Intra-prediction unit 4406 can perform intra-prediction on the current video block. When intra-prediction unit 4406 performs intra-prediction on the current video block, it can generate prediction data for the current video block based on decoded samples of other video blocks in the same frame. The prediction data for the current video block can include the predicted video block and various syntax elements.

[0168] The residual generation unit 4407 can generate residual data for the current video block by subtracting (or more) predicted video blocks from the current video block. The residual data for the current video block may include residual video blocks corresponding to different sample components of the samples in the current video block.

[0169] In other examples, such as in skip mode, there may be no residual data for the current video block, and the residual generation unit 4407 may not perform subtraction operations.

[0170] The transform processing unit 4408 can generate one or more transform coefficient video blocks for the current video block by applying one or more transforms to the residual video blocks associated with the current video block.

[0171] After the transform processing unit 4408 generates a transform coefficient video block associated with the current video block, the quantization unit 4409 can quantize the transform coefficient video block associated with the current video block based on one or more quantization parameter (QP) values ​​associated with the current video block.

[0172] The inverse quantization unit 4410 and the inverse transform unit 4411 can apply inverse quantization and inverse transform to the transform coefficient video block respectively to reconstruct the residual video block from the transform coefficient video block. The reconstruction unit 4412 can add the reconstructed residual video block to the corresponding sample points of one or more predicted video blocks generated by the prediction unit 4402 to produce a reconstructed video block associated with the current block for storage in the buffer 4413.

[0173] After the video block is reconstructed by reconstruction unit 4412, a loop filtering operation can be performed to reduce video block artifacts in the video block.

[0174] The entropy coding unit 4414 can receive data from other functional components of the video encoder 4400. When the entropy coding unit 4414 receives data, it can perform one or more entropy coding operations to generate entropy-coded data and output a bitstream including the entropy-coded data.

[0175] Figure 8 This is a block diagram illustrating an example of a video decoder 4500. The video decoder 4500 can be... Figure 6 The system 4300 shown includes a video decoder 4324. The video decoder 4500 can be configured to perform any or all of the techniques disclosed herein. In the example shown, the video decoder 4500 includes multiple functional components. The techniques described in this disclosure can be shared among the various components of the video decoder 4500. In some examples, a processor can be configured to perform any or all of the techniques described in this disclosure.

[0176] In the example shown, the video decoder 4500 includes an entropy decoding unit 4501, a motion compensation unit 4502, an intra-frame prediction unit 4503, an inverse quantization unit 4504, an inverse transform unit 4505, a reconstruction unit 4506, and a buffer 4507. In some examples, the video decoder 4500 can perform a decoding process that is generally contrasted with the encoding process described with respect to the video encoder 4400.

[0177] The entropy decoding unit 4501 can retrieve the encoded bitstream. The encoded bitstream may include entropy-encoded video data (e.g., encoded blocks of video data). The entropy decoding unit 4501 can decode the entropy-encoded video data, and based on the entropy-decoded video data, the motion compensation unit 4502 can determine motion information including motion vectors, motion vector precision, reference image list index, and other motion information. The motion compensation unit 4502 can determine this information, for example, by executing AMVP and Merge modes.

[0178] The motion compensation unit 4502 can generate motion compensation blocks, possibly performing interpolation based on an interpolation filter. The identifier of the interpolation filter to be used, with sub-pixel accuracy, can be included in the syntax element.

[0179] The motion compensation unit 4502 can use the interpolation filter used by the video encoder 4400 during the encoding of the video block to calculate the interpolation for sub-integer pixels of the reference block. The motion compensation unit 4502 can determine the interpolation filter used by the video encoder 4400 based on the received syntax information, and the motion compensation unit 4502 can use the interpolation filter to generate the prediction block.

[0180] The motion compensation unit 4502 may use some syntax information to determine the size of the blocks used to encode (multiple) frames and / or (multiple) stripes of the encoded video sequence, segmentation information describing how each macroblock of the image of the encoded video sequence is segmented, a mode indicating how each segment is encoded, one or more reference frames (and a list of reference frames) for each inter-frame codec block, and other information for decoding the encoded video sequence.

[0181] Intra-prediction unit 4503 can use, for example, an intra-prediction mode received in the bitstream to form prediction blocks from spatially adjacent blocks. Inverse quantization unit 4504 inverse quantizes (i.e., dequantizes) the quantized video block coefficients provided in the bitstream and decoded by entropy decoding unit 4501. Inverse transform unit 4505 applies an inverse transform.

[0182] The reconstruction unit 4506 can sum the residual block with the corresponding predicted block generated by the motion compensation unit 4502 or the intra-frame prediction unit 4503 to form a decoded block. If necessary, a deblocking filter can also be applied to filter the decoded block to remove block artifacts. The decoded video block is then stored in a buffer 4507, which provides a reference block for subsequent motion compensation / intra-frame prediction and also generates decoded video for presentation on a display device.

[0183] Figure 9 This is a schematic diagram of an example encoder 4600. Encoder 4600 is suitable for implementing VVC techniques. Encoder 4600 includes three loop filters: a deblocking filter (DF) 4602, a sample adaptive compensation (SAO) 4604, and an adaptive loop filter (ALF) 4606. Unlike DF 4602, which uses predefined filters, SAO 4604 and ALF 4606 utilize the original samples of the current image, respectively, by adding an offset and by applying a finite impulse response (FIR) filter, and by utilizing the encoded / decoded side information through signal transmission offset and filter coefficients to reduce the mean square error between the original and reconstructed samples. ALF 4606 is located in the last processing stage of each image and can be considered as a tool to attempt to capture and repair artifacts caused by previous stages.

[0184] The encoder 4600 also includes an intra-frame prediction component 4608 and a motion estimation / compensation (ME / MC) component 4610 configured to receive input video. The intra-frame prediction component 4608 is configured to perform intra-frame prediction, while the ME / MC component 4610 is configured to perform inter-frame prediction using reference images obtained from a reference image buffer 4612. Residual blocks from inter-frame or intra-frame prediction are fed into a transform (T) component 4614 and a quantization (Q) component 4616 to generate quantized residual transform coefficients, which are then fed into an entropy coding component 4618. The entropy coding component 4618 entropy-codes the prediction results and the quantized transform coefficients and transmits them to a video decoder (not shown). The quantized components output from the quantization component 4616 can be fed into an inverse quantization (IQ) component 4620, an inverse transform component 4622, and a reconstruction (REC) component 4624. REC component 4624 is able to output images to DF 4602, SAO 4604 and ALF4606 for filtering before these images are stored in reference image buffer 4612.

[0185] The following is a list of some preferred solutions.

[0186] The following solutions illustrate examples of the techniques discussed in this article.

[0187] 1. A method for processing media data, comprising: determining, when not present, that the value of bmsi_num_submeshes_minus1 is presumed to be equal to 0; and performing a conversion between visual media data and a bitstream based on bmsi_num_submeshes_minus1.

[0188] 2. The method described in Solution 1, wherein the value of bmsi_num_submeshes_minus1 must be in the range of 0 to 255.

[0189] 3. The method according to any one of solutions 1-2, wherein u(6) is used to transmit bmsi_num_submeshes_minus1 via signal transmission.

[0190] 4. The method according to any one of solutions 1-3, wherein N bits are used for signal transmission of bmsi_num_submeshes_minus1, and wherein N is greater than 8.

[0191] 5. The method according to any one of solutions 1-4, wherein u(N) is used to transmit bmsi_num_submeshes_minus1 via signal.

[0192] 6. The method according to any one of solutions 1-5, wherein N is equal to 12, 16, 24 or 32.

[0193] 7. The method according to any one of solutions 1-6, wherein when there is only one subgrid, the ID value of that subgrid is not transmitted via signal.

[0194] 8. The method according to any one of solutions 1-7, wherein when there is only one subgrid, the ID value of the subgrid is presumed to be equal to 0.

[0195] 9. The method according to any one of solutions 1-8, wherein the number of bits indicating the subgrid ID transmitted via signaling is an incremental value between a fixed value greater than 1.

[0196] 10. The method according to any one of solutions 1-9, wherein the fixed value is Ceil(Log2(bmsi_num_submeshes_minus1+1)).

[0197] 11. The method according to any one of solutions 1-10, wherein when it is not present, the increment value is presumed to be equal to 0.

[0198] 12. The method according to any one of solutions 1-11, wherein the range of the incremental value is from 0 to N.

[0199] 13. The method according to any one of solutions 1-12, wherein N equals 15.

[0200] 14. An apparatus for processing video data, comprising: a processor; and a non-transitory memory having instructions thereon, wherein the instructions, when executed by the processor, cause the processor to perform the method according to any one of solutions 1-13.

[0201] 15. A non-transitory computer-readable medium comprising a computer program product for use by a video codec apparatus, the computer program product comprising computer-executable instructions stored on the non-transitory computer-readable medium such that, when executed by a processor, the video codec apparatus performs the method according to any one of solutions 1-13.

[0202] 16. A non-transitory computer-readable recording medium storing a bitstream of video generated by a method performed by a video processing apparatus, wherein the method includes: determining, when not present, that the value of bmsi_num_submeshes_minus1 is presumed to be equal to 0; and generating the bitstream based on the determination.

[0203] 17. A method for storing a bitstream of video, comprising: determining, when not present, that the value of bmsi_num_submeshes_minus1 is presumed to be equal to 0; generating a bitstream based on the determination; and storing the bitstream in a non-transitory computer-readable recording medium.

[0204] 18. A method, apparatus or system described in this disclosure.

[0205] In the described solution, the encoder conforms to the format rules by generating an encoded representation based on those rules. In the described solution, the decoder parses the syntax elements in the encoded representation using known information about their presence or absence, based on the format rules, to generate the decoded video.

[0206] In this disclosure, the term "video processing" can refer to video encoding, video decoding, video compression, or video decompression. For example, a video compression algorithm can be applied during the conversion from a pixel representation of a video to a corresponding bitstream representation, and vice versa. For example, the bitstream representation of the current video block can correspond to bits at co-positions or propagated at different positions in the bitstream defined by the syntax. For example, a macroblock can be encoded based on the error residual value after transformation and encoding / decoding, and also using bits from the header and other fields in the bitstream. Furthermore, during the conversion, the decoder can, based on this determination, parse the bitstream knowing whether certain fields may or may not be present, as described in the solutions above. Similarly, the encoder can determine whether to include or exclude specific syntax fields and generate encoded / decoded representations accordingly by including or excluding syntax fields from the encoded / decoded representation.

[0207] The disclosed and other solutions, examples, embodiments, modules, and functional operations described herein can be implemented in digital electronic circuits, or in computer software, firmware, or hardware, including the structures disclosed herein and their structural equivalents, or in combinations thereof. The disclosed and other embodiments can be implemented as one or more computer program products, i.e., one or more computer program instruction modules encoded on a computer-readable medium for execution by or control of the operation of a data processing apparatus. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a storage device, a material composition affecting machine-readable propagation signals, or a combination thereof. The term "data processing apparatus" includes all means, devices, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the apparatus may also include code that creates an execution environment for an associated computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination thereof. Propagation signals are artificially generated signals, such as machine-generated electrical signals, optical signals, or electromagnetic signals, which are generated to encode information to be transmitted to a suitable receiver device.

[0208] Computer programs (also known as programs, software, software applications, scripts, or code) can be written in any programming language, including compiled or interpreted languages, and can be deployed in any form, including standalone programs or modules, components, subroutines, or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the related program, or in multiple co-located files (e.g., a file storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on one computer or on multiple computers located at a single site or distributed across multiple sites and interconnected by a communication network.

[0209] The processing and logic flows described in this disclosure can be executed by one or more programmable processors that execute one or more computer programs to perform functions by manipulating input data and generating outputs. The processing and logic flows can also be executed by special-purpose logic circuitry, and the apparatus can also be implemented as special-purpose logic circuitry, such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs).

[0210] Processors suitable for executing computer programs include, for example, general-purpose and special-purpose microprocessors, and any one or more processors of any type of digital computer. Typically, a processor receives instructions and data from read-only memory or random access memory, or both. The basic components of a computer are a processor that executes instructions and one or more storage devices that store the instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or receive data from or transfer data to one or more mass storage devices via operative coupling, or both. However, a computer does not necessarily have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and storage devices, including, for example, semiconductor storage devices such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable hard disks; magneto-optical disks; and CD-ROMs and DVD-ROMs. Processors and memory may be supplemented by or incorporated into special-purpose logic circuitry.

[0211] While this disclosure contains numerous details, these details should not be construed as limiting any subject matter or the scope of the claims, but rather as descriptions of features specific to particular embodiments of a particular art. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments, or in any suitable sub-combination. Furthermore, although features may function in certain combinations as described above, and even were originally claimed in this manner, in some cases one or more features in the claimed combination may be removed from that combination, and the claimed combination may be for sub-combinations or variations thereof.

[0212] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed sequentially in the particular order or sequence shown, or requiring all shown operations to be performed in order to achieve the desired result. Furthermore, the partitioning of various system components in the embodiments described in this disclosure should not be construed as requiring such partitioning in all embodiments.

[0213] Only a few implementations and examples are described, and other implementations, improvements and variations may be made based on what is described and shown in this disclosure.

[0214] When there are no intermediate components (other than lines, traces, or other media between the first and second components), the first component is directly coupled to the second component. When there are intermediate components other than lines, traces, or other media between the first and second components, the first component is indirectly coupled to the second component. The term "coupled" and its variations include direct coupling and indirect coupling. The use of the term "about" means including a range of ±10% of the following figures, unless otherwise specified.

[0215] While several embodiments have been provided in this disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of this disclosure. The present examples are to be considered illustrative rather than restrictive and are not intended to be limited to the details set forth herein. For example, various elements or components may be combined or integrated into another system, or certain features may be omitted or not implemented.

[0216] Furthermore, the technologies, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, technologies, or methods without departing from the scope of this disclosure. Other items shown or discussed as couplings may be directly connected or indirectly coupled or communicated through some interface, device, or intermediate component (whether electrical, mechanical, or other). Other examples of variations, substitutions, and modifications can be determined by those skilled in the art and may be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for processing media data, comprising: When a syntax element is not present in the bitstream, the value of the syntax element is presumed to be 0, wherein the value of the syntax element plus one specifies the number of subgrids in each grid frame; as well as The conversion between visual media data and the bitstream is performed based on the value of the syntax element.

2. The method of claim 1, wherein the syntax element is specified as bmsi_num_submeshes_minus1.

3. The method according to any one of claims 1-2, wherein the value of the syntax element is in the range of 0 to 255 (including boundary values).

4. The method according to any one of claims 1-2, wherein the value of the syntax element is encoded or decoded into a 6-bit unsigned integer in the bitstream.

5. The method according to any one of claims 1-2, wherein N bits are used to encode and decode the value of the syntax element in the bit stream, where N is an integer greater than 8.

6. The method according to any one of claims 1-2, wherein the value of the syntax element is encoded or decoded in the bitstream as an N-bit unsigned integer, where N is an integer greater than 8.

7. The method according to any one of claims 1-2, wherein the value of the syntax element is encoded or decoded in the bitstream as an N-bit unsigned integer, where N is one of 12, 16, 24, and 32.

8. The method according to any one of claims 1-7, wherein when there is only one subgrid, the value of the identifier (ID) of the subgrid is not present in the bitstream.

9. The method according to any one of claims 1-7, wherein when there is only one subgrid, the value of the subgrid's identifier (ID) is presumed to be 0.

10. The method according to any one of claims 1-9, wherein the incremental value between the number of bits used to represent the subgrid identifier (ID) syntax element and a fixed value is included in the bit stream, and the fixed value is greater than 1.

11. The method of claim 10, wherein the fixed value comprises Ceil(Log2(bmsi_num_submeshes_minus1 + 1)), where Ceil represents an upper bound function and Log2 represents a logarithmic function with base 2.

12. The method according to any one of claims 10-11, wherein when the increment value is not present in the bitstream, the increment value is presumed to be equal to 0.

13. The method according to any one of claims 10-12, wherein the range of the incremental value is from 0 to N, where N is an integer.

14. The method of claim 13, wherein N equals 15.

15. The method according to any one of claims 1-14, wherein the conversion comprises encoding the media data into the bitstream.

16. The method according to any one of claims 1-14, wherein the conversion comprises decoding the media data from the bitstream.

17. An apparatus for processing video or image data, comprising: processor; And a non-transitory memory having instructions thereon, wherein the instructions, when executed by the processor, cause the processor to perform the method according to any one of claims 1-16.

18. A non-transitory computer-readable medium comprising a computer program product for use by a video codec apparatus, the computer program product comprising computer-executable instructions stored on the non-transitory computer-readable medium such that, when executed by a processor, the video codec apparatus performs the method according to any one of claims 1-16.

19. A non-transitory computer-readable recording medium storing a bitstream of video generated by a method performed by a video processing apparatus, wherein the method includes: When a syntax element is not present in the bitstream, the value of the syntax element is presumed to be 0, wherein the value of the syntax element plus one specifies the number of subgrids in each grid frame; as well as The conversion between visual media data and the bitstream is performed based on the value of the syntax element.

20. A method for storing a bitstream of video, comprising: When a syntax element is not present in the bitstream, the value of the syntax element is presumed to be 0, wherein the value of the syntax element plus one specifies the number of subgrids in each grid frame; The bitstream is generated based on the syntax elements; as well as The bit stream is stored in a non-transitory computer-readable recording medium.

21. A method, apparatus or system described in this disclosure.

Images