Light detection device, electronic apparatus, and method of manufacturing light detection device

Abstract

Provided is a light detection device capable of reducing a chip area. The light detection device includes a semiconductor layer, a wiring layer, a terminal pad, and an element. The semiconductor layer includes a photoelectric conversion unit, and one surface is a light incident surface and the other surface is an element forming surface. The wiring layer is laminated on the element formation surface of the semiconductor layer. The terminal pad is at least partially located within the semiconductor layer and is connected to the metal wiring of the wiring layer. The element is disposed between the terminal pad and the wiring layer.

Description

Technical Field

[0001] The technology disclosed herein (the Technology) relates to a photodetector, an electronic device including a photodetector, and a method for manufacturing a photodetector. Background Technology

[0002] In solid-state imaging devices, a number of protective elements are typically arranged on the chip in a manner corresponding to each terminal pad to protect the semiconductor device from electrostatic discharge (ESD) and process-induced damage (PID). Patent Document 1 discloses a structure in which the emitter region of a protective transistor is electrically connected to the area below the terminal pad. Reference List Patent documents

[0003] Patent document 1: Japanese Patent Application Publication No. 10-335627 Summary of the Invention The problem to be solved by the present invention

[0004] In solid-state imaging devices, it is desirable to reduce chip size. However, the chip area increases because a certain number of protective components are required within the chip.

[0005] This disclosure is made in view of the foregoing, and its purpose is to provide a light detection device, an electronic device, and a method for manufacturing the light detection device that can reduce chip area. Problem Solution

[0006] One aspect of this disclosure is a photodetector comprising: a semiconductor layer including a photoelectric conversion unit, one surface of the semiconductor layer being a light incident surface and the other surface of the semiconductor layer being a component forming surface; a wiring layer stacked on the component forming surface of the semiconductor layer; terminal pads at least partially located in the semiconductor layer and connected to metal wiring of the wiring layer; and components disposed between the terminal pads and the wiring layer.

[0007] Another aspect of this disclosure is a photodetector comprising: a semiconductor layer including a photoelectric conversion unit, one surface of the semiconductor layer being a light incident surface and the other surface of the semiconductor layer being a component forming surface; a wiring layer stacked on the component forming surface of the semiconductor layer; a terminal pad located on the wiring layer side of the component forming surface of the semiconductor layer and connected to a metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, wherein a component is arranged at the location where the pad opening is formed before the pad opening is formed.

[0008] Furthermore, another aspect of this disclosure is an electronic device including a photodetector, the photodetector comprising: a semiconductor layer including a photoelectric conversion unit, one surface of the semiconductor layer being a light incident surface and the other surface of the semiconductor layer being a component forming surface; a wiring layer stacked on the component forming surface of the semiconductor layer; terminal pads at least partially located in the semiconductor layer and connected to metal wiring of the wiring layer; and components disposed between the terminal pads and the wiring layer.

[0009] Furthermore, another aspect of this disclosure is an electronic device including a photodetector, the photodetector comprising: a semiconductor layer including a photoelectric conversion unit, one surface of the semiconductor layer being a light incident surface and the other surface of the semiconductor layer being a component forming surface; a wiring layer stacked on the component forming surface of the semiconductor layer; a terminal pad located on the wiring layer side of the component forming surface of the semiconductor layer and connected to a metal wiring of the wiring layer; and a pad opening formed from the light incident surface of the semiconductor layer to the terminal pad and exposing the terminal pad from the light incident surface, wherein a component is arranged at the location where the pad opening is formed before the pad opening is formed.

[0010] Furthermore, another aspect of this disclosure is a method for manufacturing a photodetector, comprising: preparing a semiconductor chip in which a wiring layer is stacked on an element forming surface of a semiconductor layer including a photoelectric conversion unit, one surface of the semiconductor layer being a light incident surface and the other surface of the semiconductor layer being the element forming surface; forming a terminal pad in the semiconductor layer, the upper surface of the terminal pad being exposed to the outside; and connecting the lower surface of the terminal pad and the metal wiring of the wiring layer through a through-hole, such that an element disposed in the semiconductor layer is located between the lower surface of the terminal pad and the wiring layer.

[0011] Furthermore, another aspect of this disclosure is a method for manufacturing a photodetector, comprising: preparing a semiconductor chip including a photoelectric conversion unit and a wiring layer stacked on an element forming surface of a semiconductor layer, one surface of the semiconductor layer being a light incident surface and the other surface of the semiconductor layer being the element forming surface; forming terminal pads connected to metal wiring of the wiring layer on the wiring layer side of the element forming surface of the semiconductor layer; forming pad openings extending from the light incident surface of the semiconductor layer to the terminal pads and exposing the terminal pads from the light incident surface; and arranging an element at the formation location of the pad openings before forming the pad openings. Attached Figure Description

[0012] Figure 1 This is a plan view schematically illustrating a construction example of a solid-state imaging apparatus according to a first embodiment of the present disclosure. Figure 2 This is a block diagram illustrating a construction example of a solid-state imaging apparatus according to a first embodiment of the present disclosure. Figure 3 This is an equivalent circuit diagram of the pixel unit of a solid-state imaging apparatus according to a first embodiment of the present disclosure. Figure 4A This is a plan view (part 1) illustrating a schematic structural example of a solid-state imaging device according to a comparative example of a first embodiment of the present disclosure. Figure 4B This is a plan view (part 2) illustrating a schematic structural example of a solid-state imaging device according to a comparative example of a first embodiment of the present disclosure. Figure 5A It is along Figure 4A The line A-A' shown is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device. Figure 5B It is along Figure 4B The line A-A' shown is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device. Figure 6A This is a plan view (part 1) showing a schematic structural example of a solid-state imaging apparatus according to a first embodiment of the present disclosure. Figure 6B This is a plan view (part 2) showing a schematic structural example of a solid-state imaging apparatus according to a first embodiment of the present disclosure. Figure 7A It is along Figure 6A The line A-A' shown is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device. Figure 7B It is along Figure 6BThe line A-A' shown is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device. Figure 8A This is a cross-sectional view (part 1) showing the process flow of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. Figure 8B This is a cross-sectional view (part 2) showing the process flow of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. Figure 8C This is a cross-sectional view (part 3) showing the process flow of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. Figure 8D This is a cross-sectional view (part 4) showing the process flow of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. Figure 8E This is a cross-sectional view (part 5) showing the process flow of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. Figure 8F This is a cross-sectional view (part 6) showing the process flow of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. Figure 8G This is a cross-sectional view (part 7) showing the process flow of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. Figure 8H This is a cross-sectional view (part 8) showing the process flow of a method for manufacturing a solid-state imaging device according to a first embodiment of the present disclosure. Figure 9A This is a plan view (part 1) showing a schematic structural example of a solid-state imaging apparatus according to a second embodiment of the present disclosure, as observed from the element forming surface. Figure 9B This is a plan view (part 2) showing a schematic structural example of a solid-state imaging apparatus according to a second embodiment of the present disclosure, as observed from the element forming surface. Figure 10A It is along Figure 9A The line B-B' shown is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device. Figure 10B It is along Figure 9B The line B-B' shown is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device. Figure 11A This is a cross-sectional view (part 1) showing the process flow of a method for manufacturing a solid-state imaging apparatus according to a second embodiment of the present disclosure. Figure 11BThis is a cross-sectional view (part 2) showing the process flow of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. Figure 11C This is a cross-sectional view (part 3) showing the process flow of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. Figure 11D This is a cross-sectional view (part 4) showing the process flow of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. Figure 11E This is a cross-sectional view (part 5) showing the process flow of a method for manufacturing a solid-state imaging device according to a second embodiment of the present disclosure. Figure 12 This is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device according to a third embodiment of the present invention. Figure 13A This is a partial cross-sectional view (part 1) showing a schematic structural example of a solid-state imaging apparatus according to a fourth embodiment of the present disclosure. Figure 13B This is a partial cross-sectional view (part 2) showing a schematic structural example of a solid-state imaging device according to a fourth embodiment of the present disclosure. Figure 14A This is a partial cross-sectional view (part 1) showing a schematic structural example of a solid-state imaging apparatus according to a fifth embodiment of the present disclosure. Figure 14B This is a partial cross-sectional view (part 2) showing a schematic structural example of a solid-state imaging apparatus according to a fifth embodiment of the present disclosure. Figure 15 This is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device according to a sixth embodiment of the present invention. Figure 16 This is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging device according to a seventh embodiment of the present invention. Figure 17 This is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging apparatus according to an eighth embodiment of the present invention. Figure 18 This is a block diagram illustrating an example of the construction of an imaging system as an electronic device applying this technology. Figure 19 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a moving object control system to which the technology according to this disclosure can be applied. Figure 20 It is shown Figure 19 A diagram showing an example of the mounting position of the imaging unit. Detailed Implementation

[0013] Embodiments of this disclosure will now be described with reference to the accompanying drawings. In the illustrations of the drawings referenced in the following description, identical or similar components are indicated by identical or similar reference numerals to avoid redundancy. It should be noted that the drawings are schematic, and the relationship between the thickness and planar dimensions of each device or component, as well as the thickness ratio, may differ from actual conditions. Therefore, specific thicknesses and dimensions should be determined taking into account the following description. Furthermore, it is unnecessary to elaborate further, as portions with different dimensional relationships and scales are included between the drawings.

[0014] In this specification, "first conductivity type" refers to p-type or n-type, and "second conductivity type" refers to p-type or n-type different from "first conductivity type". Furthermore, adding a "+" or "−" after "n" or "p" indicates that the impurity density of the corresponding semiconductor region is higher or lower than the impurity density of the semiconductor region without the "+" or "−" added. It should be noted that even semiconductor regions with the same "n" and "n" added do not necessarily have identical impurity densities.

[0015] Furthermore, the definitions of directions such as "up" and "down" in the following description are for illustrative purposes only and are not intended to limit the technical concept of this disclosure. For example, it goes without saying that when the object is rotated 90° for observation, "up" and "down" become "left" and "right," and when the object is rotated 180° for observation, "up" and "down" are reversed. Note that the effects described in this manual are merely examples and are not limited to these; other effects may also be provided.

[0016] <First Embodiment> In this embodiment, an example will be described of applying this technology to a solid-state imaging device as a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor. The solid-state imaging device is an example of a light detection device. Besides solid-state imaging devices, light detection devices also include devices that detect only light, such as ranging devices. (Overall structure of a solid-state imaging device) First, the overall structure of the solid-state imaging device 1A will be explained. like Figure 1 As shown, the solid-state imaging device 1A according to this embodiment mainly includes a semiconductor chip 2 having a rectangular two-dimensional planar shape in a planar view. In other words, the solid-state imaging device 1A is mounted on the semiconductor chip 2. The solid-state imaging device 1A captures image light from the object being photographed through an optical lens (not shown), converts the amount of incident light formed on the imaging surface into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal.

[0017] like Figure 1As shown, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted includes a rectangular pixel region 2A disposed in the central portion of a two-dimensional plane (which includes X and Y directions that are orthogonal to each other) and a peripheral region 2B disposed outside the pixel region 2A and surrounding the pixel region 2A.

[0018] For example, pixel region 2A is a light-receiving surface that receives light converged by an optical lens. Then, in pixel region 2A, multiple pixels 3 are arranged in a matrix in a two-dimensional plane containing the X and Y directions. In other words, pixels 3 are repeatedly arranged in a two-dimensional plane along mutually orthogonal X and Y directions.

[0019] like Figure 1 As shown, a plurality of terminal pads 14 are arranged in the peripheral region 2B. For example, each of the plurality of terminal pads 14 is arranged along four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of terminal pads 14 is an input / output terminal used when the semiconductor chip 2 is electrically connected to an external device.

[0020] <Logic Circuits> like Figure 2 As shown, the semiconductor chip 2 includes a logic circuit 13, which includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 outputs the output voltage (Vout) of each pixel 3 to the outside. The logic circuit 13 may, for example, include a complementary metal-oxide-semiconductor (CMOS) circuit, which includes a p-channel conductive (first conductivity type) metal-oxide-semiconductor field-effect transistor (MOSFET) and an n-channel conductive (second conductivity type) MOSFET as field-effect transistors.

[0021] For example, the vertical driving circuit 4 includes a shift register. The vertical driving circuit 4 sequentially selects the desired pixel driving lines 10 and provides pulses to the selected pixel driving lines 10 for driving pixels 3, thereby driving each pixel 3 row by row. That is, the vertical driving circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row along the vertical direction, and provides the pixel signal from each pixel 3, based on the signal charge generated by the photoelectric conversion element of the pixel 3 according to the amount of light received, to the column signal processing circuit 5 through the vertical signal line 11.

[0022] For example, the column signal processing circuit 5 is arranged for each column of pixels 3, and performs signal processing such as noise removal on the signal output from a row of pixels 3 for each column of pixels. For example, each column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) for removing pixel-specific fixed-pattern noise, as well as analog-to-digital (AD) conversion.

[0023] For example, the horizontal drive circuit 6 includes a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scan pulses to the column signal processing circuit 5 to sequentially select each column signal processing circuit 5, and causes each column signal processing circuit 5 to output the pixel signal obtained after signal processing to the horizontal signal line 12.

[0024] The output circuit 7 performs signal processing on the pixel signals provided sequentially from each column signal processing circuit 5 via the horizontal signal line 12, and outputs the processed signals. For example, the signal processing can use buffering, black level adjustment, column offset correction, and various types of digital signal processing.

[0025] The control circuit 8 generates clock and control signals based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, serving as a reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6. Then, the control circuit 8 outputs the generated clock and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6.

[0026] <pixel> Figure 3 This is an equivalent circuit diagram showing an example of the construction of pixel 3. Pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion region) FD for accumulating (holding) the signal charge photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR for transferring the signal charge photoelectrically converted by the photoelectric conversion element PD to the charge accumulation region FD. In addition, pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0027] The photoelectric conversion element PD generates a signal charge corresponding to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transmission transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, the photoelectric conversion element PD uses a photodiode.

[0028] The drain region of the transfer transistor TR is electrically connected to the charge accumulation region FD. The gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line in the pixel drive line 10 (see [link]). Figure 2 ). The charge holding region FD temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion element PD through the transfer transistor TR.

[0029] The readout circuit 15 reads the accumulated signal charge in the charge holding region FD and outputs a pixel signal based on the signal charge. For example, the readout circuit 15 includes, but is not limited to, an amplifying transistor AMP, a selecting transistor SEL, and a reset transistor RST as pixel transistors. For example, these transistors (AMP, SEL, RST) can be constructed as field-effect transistors using a MOSFET with a silicon oxide (SiO2) film as the gate insulating film. These transistors can also be metal-insulator-semiconductor field-effect transistors (MISFETs) using a silicon nitride (Si3N4) film or a stacked film (e.g., a silicon nitride film and a silicon oxide film) as the gate insulating film.

[0030] The source region of the amplifying transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd1. Then, the gate electrode of the amplifying transistor AMP is electrically connected to the charge accumulation region FD and the source region of the reset transistor RST.

[0031] The source region of the selector transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region is electrically connected to the source region of the amplifying transistor AMP. The gate electrode of the selector transistor SEL is... Figure 2 The select transistor drive line in the pixel drive line 10 shown is electrically connected.

[0032] The source region of the reset transistor RST is electrically connected to the charge accumulation region FD and the gate electrode of the amplification transistor AMP, and the drain region is electrically connected to the power supply line Vdd2.

[0033] When the transfer transistor TR is turned on, it transfers the signal charge generated by the photoelectric conversion element PD to the charge holding region FD. When the reset transistor RST is turned on, it resets the potential (signal charge) of the charge holding region FD to the potential of the power supply line Vdd2. The selection transistor SEL controls the timing of the output pixel signal from the readout circuit 15.

[0034] The amplifying transistor AMP generates a voltage signal corresponding to the level of the signal charge held in the charge holding region FD, which serves as the pixel signal. The amplifying transistor AMP constitutes a source follower type amplifier and outputs the pixel signal, the voltage of which corresponds to the level of the signal charge generated by the photoelectric conversion element PD. When the selector transistor SEL is turned on, the amplifying transistor AMP amplifies the potential of the charge holding region FD and outputs the pixel signal corresponding to this potential to the column signal processing circuit 5 through the vertical signal line 11 (VSL).

[0035] <Detailed Structure of Solid-State Imaging Devices> <Comparison Example> Figure 4A and4B This is a plan view illustrating a schematic structural example of a solid-state imaging device B1 according to a comparative example of the first embodiment of this disclosure. Furthermore, Figure 5A and 5B It is along Figure 4A and 4B The diagram shown is a partial cross-sectional view of a schematic structural example of the solid-state imaging device B1, taken by line A-A'.

[0036] like Figure 4A As shown, the solid-state imaging device B1 includes a semiconductor chip B2. The semiconductor chip B2 includes a single-crystal silicon substrate of a first conductivity type (e.g., p-type). The semiconductor chip B2 includes a well region B21 of a second conductivity type (e.g., n-type) and a well region B22 of the first conductivity type (e.g., p-type). Protection diodes B31 to B33 are arranged in the p-type well region B22. A power supply terminal B34 for applying a power supply VDD to the protection diodes B31 to B33 is provided in the n-type well region B21. Furthermore, the semiconductor chip B2 also includes a terminal B35 for providing a reference potential.

[0037] like Figure 4B As shown, terminal pad B14 is disposed in the region of semiconductor chip B2 adjacent to protection diodes B31 to B33. The upper surface of terminal pad B14 is exposed through opening B41.

[0038] like Figure 5A As shown, the semiconductor chip B2 includes a semiconductor layer B200 having a first surface S1 and a second surface S2 opposite to each other, a first wiring layer B300 stacked on the first surface S1 of the semiconductor layer B200, and a second wiring layer B400 stacked on the surface of the first wiring layer B300 opposite to the surface located on the side of the semiconductor layer B200 (third surface S3). For example, this stacked structure can be implemented by stacking the first wiring layer B300 on the first surface S1 of the semiconductor layer B200 and stacking and bonding the second wiring layer B400 on the third surface S3 of the first wiring layer B300. Furthermore, the second surface S2 side, which is one surface of the semiconductor layer B200, can be referred to as the light incident surface or the back surface, and the first surface S1, which is the other surface of the semiconductor layer B200, can be referred to as the device forming surface or the front surface.

[0039] In semiconductor chip B2, a component isolation section B210 is provided on the first surface S1 side. The component isolation section B210 is a region used to isolate each component, including protection diodes B31 to B33. In the first wiring layer B300, for example, a metal layer B310 connected to the anode of protection diode B32, a metal layer B320 connected to the cathode of protection diode B32, a metal layer B330 connected to the power supply terminal B34, and a metal layer B340 connected to the terminal B35 are formed.

[0040] like Figure 5B As shown, terminal pad B14 is disposed in the region of semiconductor chip B2 adjacent to protection diodes B31 to B33. Terminal pad B14 is exposed to the outside from the second surface S2 of semiconductor chip B2 through opening B41. Incidentally, in the solid-state imaging device B1 of the comparative example, the chip area is increased because a certain number of protection diodes B31 to B33 need to be arranged in the semiconductor chip B2.

[0041] <Implementation methods according to the first embodiment> Figure 6A and 6B This is a plan view illustrating a schematic structural example of the solid-state imaging apparatus 1A according to a first embodiment of the present disclosure. Furthermore, Figure 7A and 7B It is along Figure 6A and 6B The diagram shown is a partial cross-sectional view of a schematic structural example of the solid-state imaging device 1A, taken by line A-A'.

[0042] like Figure 6A As shown, the semiconductor chip 2 includes a single-crystal silicon substrate of a first conductivity type (e.g., p-type). The semiconductor chip 2 includes a well region 21 of a second conductivity type (e.g., n-type) and a well region 22 of the first conductivity type (e.g., p-type). Protection diodes 31 to 33 are arranged in the p-type well region 22. A power supply terminal 34 for applying a power supply voltage VDD to the protection diodes 31 to 33 is provided in the n-type well region 21. Furthermore, the semiconductor chip 2 also includes a terminal 35 for providing a reference potential. Note that, in addition to the protection diodes 31 to 33, components such as transistors can also be used to protect the transistors in the semiconductor chip 2 from ESD or PID. In the semiconductor chip 2, a component isolation portion 210 is provided on the first surface S1 side.

[0043] like Figure 6B As shown, terminal pad 14 is disposed in the area of ​​semiconductor chip 2 where protection diodes 31 to 33 are disposed. The upper surface of terminal pad 14 is exposed through opening 41 (example of pad opening).

[0044] like Figure 7AAs shown, the semiconductor chip 2 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 opposite to each other, a first wiring layer 300 stacked on the first surface S1 of the semiconductor layer 200, and a second wiring layer 400 stacked on a surface of the first wiring layer 300 opposite to the surface located on the side of the semiconductor layer 200 (third surface S3). For example, this stacked structure can be implemented by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200 and stacking and bonding the second wiring layer 400 on the third surface S3 of the first wiring layer 300. Furthermore, one surface of the semiconductor layer 200 (second surface S2) can be referred to as the light incident surface or the back surface, and the other surface of the semiconductor layer 200 (first surface S1) can be referred to as the element forming surface or the front surface. The solid-state imaging device 1A is a back-illuminated imaging device (an example of a light detection device), in which the first surface S1 is the front surface and the second surface S2 is the back surface.

[0045] In semiconductor chip 2, a component isolation section 210 is provided on the first surface S1 side. The component isolation section 210 is a region used to isolate each component, including protection diodes 31 to 33. In the first wiring layer 300, for example, a metal layer 310 connected to the anode of protection diode 32, a metal layer 320 connected to the cathode of protection diode 32, a metal layer 330 connected to power supply terminal 34, and a metal layer 340 connected to terminal 35 are formed.

[0046] (Terminal pads) like Figure 7B As shown, the terminal pad 14 is embedded in the semiconductor layer 200 (i.e., located on the side of the first surface S1 of the second surface S2 of the semiconductor layer 200), and includes an upper surface 14a, a lower surface 14b opposite to the upper surface 14a, and a via 14c. The upper surface 14a is exposed to the outside through the opening 41. The terminal pad 14 is an input / output terminal used when the solid-state imaging device 1A is electrically connected to an external device. Therefore, the terminal pad 14 is exposed to the outside. The lower surface 14b of the terminal pad 14 is connected to the via 14c. The terminal pad 14 is made of a conductive material such as aluminum.

[0047] Multiple vias 14c are provided. More specifically, two vias 14c are provided. The vias 14c are embedded in the semiconductor layer 200 and electrically connect the terminal pad 14 and the metal layer 352, which will be described later. One end of the via 14c penetrates the semiconductor layer 200 and is connected to the lower surface 14b of the terminal pad 14. The other end of the via 14c penetrates the n-well region 21 and p-well region 22 constituting the protection diodes 31 to 33 and the component isolation portion 210 in the thickness direction of the semiconductor layer 200 and extends into the first wiring layer 300. Then, the other end of the via 14c is connected to the metal layer 352 in the first wiring layer 300. Here, the metal layer 352 connected to the other end of the via 14c is referred to as metal layer 352a in order to distinguish it from other metal layers 352. Therefore, the protection diodes 31 to 33 are located between the lower surface 14b of the terminal pad 14 and the metal layer 352a.

[0048] (First wiring layer) like Figure 7B As shown, the first wiring layer 300 further includes an interlayer insulating film 351, a metal layer 352 (an example of metal wiring), a first connection pad 353, and a via 354. As shown, the metal layer 352 and the first connection pad 353 are stacked across the interlayer insulating film 351. The via 354 connects the metal layers 352 to each other and connects the metal layers 352 to the first connection pad 353.

[0049] (Second layer wiring) like Figure 7B As shown, the second wiring layer 400 includes an interlayer insulating film 411, a metal layer 412, a second connection pad 413, and a via 414. As shown, the metal layer 412 and the second connection pad 413 are stacked across the interlayer insulating film 411. The via 414 connects the metal layers 412 to each other and connects the metal layers 412 and the second connection pad 413. The second connection pad 413 is bonded to the first connection pad 353. Therefore, the terminal pad 14 is electrically connected to the metal layer 412 of the second wiring layer 400. Figure 7B As shown, terminal pad 14, first connection pad 353, and second connection pad 413 overlap each other in the thickness direction of semiconductor chip 2. The second wiring layer 400 may include a logic substrate forming logic circuitry 13. The logic substrate may include, for example, logic circuitry 13 such as control circuitry 8 for controlling the operation of each pixel 3.

[0050] <Methods for Manufacturing Solid-State Imaging Devices> The following will refer to Figures 8A to 8H A method for manufacturing a solid-state imaging apparatus 1A according to a first embodiment of the present disclosure is described. Figures 8A to 8HThis is a cross-sectional view illustrating the process flow of a method for manufacturing a solid-state imaging device 1A according to a first embodiment of the present disclosure. Note that various apparatuses such as film deposition apparatuses (including chemical vapor deposition (CVD) apparatuses and sputtering apparatuses), ion implantation apparatuses, thermal treatment apparatuses, etching apparatuses, chemical mechanical polishing (CMP) apparatuses, and bonding apparatuses are used to manufacture the solid-state imaging device 1A. These apparatuses will be collectively referred to as manufacturing apparatuses.

[0051] First, such as Figure 8A As shown, a substrate 51 is fabricated, in which a semiconductor layer 200, a first wiring layer 300, and a second wiring layer 400 are sequentially stacked. An n-type well region 21, a p-type well region 22, and a device isolation portion 210 are formed in the semiconductor layer 200. Then, a first connection pad 353 and a second connection pad 413 are bonded.

[0052] Next, as Figure 8B As shown, the manufacturing apparatus forms an opening 52 on the second surface S2 of the semiconductor layer 200 by etching. Next, as... Figure 8C As shown, the manufacturing apparatus forms openings 53 and 54 by etching from opening 52 toward the component isolation portion 210. Then, as... Figure 8D As shown, the manufacturing apparatus embeds the oxide film 55 into the openings 52, 53 and 54.

[0053] Subsequently, as Figure 8E As shown, the manufacturing apparatus etches the oxide film 55 to form an opening 56, which is used to form the terminal pad 14 and its through-hole 14c. At this time, the opening 56 penetrates the component isolation portion 210 and reaches the metal layer 320 of the first wiring layer 300. Next, as... Figure 8F As shown, the manufacturing apparatus, for example, patterns aluminum or the like within the opening 56 to form the terminal pad 14.

[0054] Next, as Figure 8G As shown, the manufacturing apparatus embeds the oxide film 57 into the portion where aluminum is not embedded. Next, as... Figure 8H As shown, the manufacturing apparatus etches oxide film 57 to form opening 41, which exposes the upper surface 14a of terminal pad 14 to the outside.

[0055] <Effects of the First Embodiment> As described above, according to the first embodiment, by arranging the protection diodes 31 to 33 between the lower surface 14b of the terminal pad 14 and the first wiring layer 300, it is not necessary to reserve area outside the terminal pad 14 separately within the semiconductor chip 2 for a certain number of protection diodes 31 to 33, thus reducing the chip area. Furthermore, by providing the terminal pad 14 on the semiconductor layer 200, wire bonding can be easily performed. Note that the terminal pad 14 may have a structure in which a portion is buried in the semiconductor layer 200, while another portion protrudes above the semiconductor layer 200.

[0056] <Second Embodiment> Figure 9A and 9B This is a plan view showing a schematic structural example as observed from the element forming surface of the solid-state imaging apparatus 1B according to a second embodiment of the present disclosure. Furthermore, Figure 10A and 10B It shows along Figure 9A and 9B The diagram shown is a partial cross-sectional view of a schematic structural example of the solid-state imaging device 1B, taken along line B-B'. Figure 9A and 9B In, with Figure 6A and 6B The same components are represented by the same reference numerals, and their detailed descriptions are omitted. Furthermore, in Figure 10A and 10B In, with Figure 7A and 7B The same parts are represented by the same reference numerals, and their detailed descriptions are omitted.

[0057] like Figure 9A As shown, the semiconductor chip 60 of the solid-state imaging device 1B includes a single-crystal silicon substrate of a second conductivity type (e.g., n-type). The semiconductor chip 60 has a well region 61 of a first conductivity type (e.g., p-type). The semiconductor chip 60 is provided with a power supply terminal 34 for applying a power supply voltage VDD to protection diodes 31 to 33. The cathodes of the protection diodes 31 to 33 are surrounded by a plurality of vias 354 of a first wiring layer 300, which will be described later.

[0058] like Figure 9B As shown, terminal pad 71 is disposed in the region of semiconductor chip 60 where protection diodes 31 to 33 are disposed. The upper surface 71a of terminal pad 71 is exposed through opening 72 (example of pad opening).

[0059] like Figure 10AAs shown, the semiconductor chip 60 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 opposite to each other, a first wiring layer 300 stacked on the first surface S1 of the semiconductor layer 200, and a second wiring layer 400 stacked on a surface (third surface S3) of the first wiring layer 300 opposite to the surface located on the side of the semiconductor layer 200. For example, this stacked structure can be implemented by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200 and stacking and bonding the second wiring layer 400 on the third surface S3 of the first wiring layer 300. Furthermore, one surface (second surface S2) of the semiconductor layer 200 can be referred to as the light incident surface or the back surface, and the other surface (first surface S1) of the semiconductor layer 200 can be referred to as the device forming surface or the front surface.

[0060] In the semiconductor chip 60, the component isolation portion 210 is provided on the first surface S1 side. In the first wiring layer 300, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, and a metal layer 330 connected to the power supply terminal 34 are formed.

[0061] The first wiring layer 300 also includes an interlayer insulating film 351, a metal layer 352 (an example of metal wiring), and a via 354. The metal layers 352 are stacked with the interlayer insulating film 351 as shown. The vias 354 connect the metal layers 352 to each other.

[0062] The second wiring layer 400 includes terminal pads 71, an interlayer insulating film 411, a metal layer 412, and vias 414. As shown, the terminal pads 71 ​​and the metal layer 412 are stacked with the interlayer insulating film 411 in between. The vias 414 connect the metal layers 412 to each other and connect the metal layers 412 to the terminal pads 71. Therefore, the terminal pads 71 ​​are electrically connected to the metal layer 412 of the second wiring layer 400. The second wiring layer 400 may include a logic substrate for forming logic circuits. The logic substrate may include, for example, pixel control circuitry for controlling the operation of each pixel 3 and front-end circuitry for quenching and charging each pixel 3.

[0063] like Figure 10B As shown, the terminal pad 71 is disposed as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b located on the side opposite to the upper surface 71a. The upper surface 71a is exposed to the outside through an opening 72. The terminal pad 71 is an input / output terminal used when the solid-state imaging device 1B is electrically connected to an external device. Therefore, the terminal pad 71 is exposed to the outside. The lower surface 71b of the terminal pad 71 is connected to a through hole 414. The through hole 414 electrically connects the terminal pad 71 and the metal layer 412.

[0064] like Figure 10B As shown, an opening 72 is formed from the second surface S2 (i.e., the light incident surface) of the semiconductor layer 200 to the terminal pad 71 of the second wiring layer 400. Protection diodes 31 to 33 are arranged at the location where the opening 72 is formed. After the opening 72 is formed, the protection diodes 31 to 33 disappear.

[0065] <Methods for Manufacturing Solid-State Imaging Devices> The following will refer to Figures 11A to 11E A method for manufacturing a solid-state imaging device 1B according to a second embodiment of the present disclosure is described. Figures 11A to 11E This is a cross-sectional view illustrating the process flow of a method for manufacturing a solid-state imaging device 1B according to a second embodiment of the present disclosure. Note that various apparatuses such as film deposition apparatuses (including chemical vapor deposition (CVD) equipment and sputtering equipment), ion implantation apparatuses, thermal treatment apparatuses, etching apparatuses, chemical mechanical polishing (CMP) apparatuses, and bonding apparatuses are used to manufacture the solid-state imaging device 1A. These apparatuses will be collectively referred to as manufacturing apparatuses.

[0066] First, such as Figure 11A As shown, a semiconductor chip 60 comprising only the semiconductor layer 200 is fabricated. Next, as... Figure 11B As shown, the manufacturing apparatus forms a p-type well region 61 and a component isolation portion 210 in the semiconductor layer 200 of the semiconductor chip 60.

[0067] Next, as Figure 11C As shown, the manufacturing apparatus stacks a first wiring layer 300 on the surface of the semiconductor layer 200 where the component isolation portion 210 is formed. At this time, an interlayer insulating film 351, a metal layer 352, and a via 354 are formed in the first wiring layer 300. During the formation of the metal layer 352 and the via 354, process-induced damage (PID) may occur, in which the generated plasma charge leads to gate defects in the transistor. To protect the solid-state imaging device 1B from PID, for example, a protection diode 32 is arranged in the arrangement area of ​​the terminal pad 71, and, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, and a metal layer 330 connected to the power supply terminal 34 are formed in the first wiring layer 300.

[0068] Next, as Figure 11D As shown, the manufacturing apparatus stacks the second wiring layer 400 onto the upper surface of the support substrate 73, and places the semiconductor chip 60 from... Figure 11C The state is reversed, and the first connection pad 353 of the first wiring layer 300 and the second connection pad 413 of the second wiring layer 400 are joined.

[0069] Next, as Figure 11EAs shown, the manufacturing apparatus forms an opening 72 from the second surface S2 (i.e., the light incident surface) of the semiconductor layer 200 to the terminal pad 71 of the second wiring layer 400, and exposes the upper surface 71a of the terminal pad 71 to the outside. With the formation of the opening 72, the protection diodes 31 to 33 arranged in the semiconductor layer 200 disappear.

[0070] <Effects of the Second Embodiment> As described above, according to the second embodiment, when the terminal pad 71 is located in the second wiring layer 400, by arranging protection diodes 31 to 33 at the formation location of the opening 72 until the opening 72 is formed to expose the terminal pad 71 from the second surface S2 (i.e., the light incident surface) of the semiconductor layer 200, other components in the semiconductor layer 200 can be protected from ESD, PID, etc. before the opening 72 is formed, and there is no need to reserve an area outside the terminal pad 71 separately for a certain number of protection diodes 31 to 33 in the semiconductor layer 200, thereby reducing the chip area.

[0071] <Third Embodiment> Figure 12 This is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging apparatus 1C according to a third embodiment of the present disclosure. Figure 12 In, with Figure 7B and Figure 10A The same parts are indicated by the same reference numerals, and their detailed descriptions are omitted.

[0072] The semiconductor chip 60 of the solid-state imaging device 1C includes a single-crystal silicon substrate of a second conductivity type (e.g., n-type). The semiconductor chip 60 has a well region 61 of a first conductivity type (e.g., p-type). The semiconductor chip 60 is provided with a power supply terminal 34 for applying a power supply voltage VDD to protection diodes 31 to 33.

[0073] Terminal pad 14 is embedded in semiconductor layer 200 (i.e., located on the side of the first surface S1 of the second surface S2 of semiconductor layer 200) and includes an upper surface 14a, a lower surface 14b located on the side opposite to the upper surface 14a, and a through-hole 14c. The upper surface 14a is exposed to the outside through opening 41. Terminal pad 14 is an input / output terminal used when the solid-state imaging device 1A is electrically connected to an external device. Therefore, terminal pad 14 is exposed to the outside. The lower surface 14b of terminal pad 14 is connected to through-hole 14c.

[0074] Multiple vias 14c are provided. More specifically, two vias 14c are provided. The vias 14c are embedded in the semiconductor layer 200 and electrically connect the terminal pad 14 and the metal layer 352. One end of the via 14c penetrates the semiconductor layer 200 and connects to the lower surface 14b of the terminal pad 14. The other end of the via 14c penetrates the n-well region 21 and p-well region 22 constituting the protection diodes 31 to 33 and the component isolation portion 210 in the thickness direction of the semiconductor layer 200, and extends into the first wiring layer 300. Then, the other end of the via 14c is connected to the metal layer 352 in the first wiring layer 300. Here, the metal layer 352 connected to the other end of the via 14c is referred to as metal layer 352a in order to distinguish it from other metal layers 352. Therefore, the protection diodes 31 to 33 are located between the lower surface 14b of the terminal pad 14 and the metal layer 352a.

[0075] <Effects of the Third Embodiment> As described above, similar effects to those of the first embodiment can be achieved even in the third embodiment.

[0076] <Fourth Embodiment> Figure 13A and 13B This is a partial cross-sectional view illustrating a schematic structural example of a solid-state imaging apparatus 1D according to a fourth embodiment of the present disclosure. Figure 13A and 13B In, with Figure 10A and 10B The same components are indicated by the same reference numerals, and their detailed descriptions are omitted.

[0077] like Figure 13A As shown, the semiconductor chip 2 of the solid-state imaging device 1D includes a single-crystal silicon substrate of a first conductivity type (e.g., p-type). The semiconductor chip 2 includes a well region 21 of a second conductivity type (e.g., n-type) and a well region 22 of the first conductivity type (e.g., p-type). Protection diodes 31 to 33 are arranged in the p-type well region 22. A power supply terminal 34 for applying a power supply voltage VDD to the protection diodes 31 to 33 is provided in the n-type well region 21. In addition, the semiconductor chip 2 also includes a terminal 35 for providing a reference potential.

[0078] In the first wiring layer 300, for example, a metal layer 310 connected to the anode of the protection diode 32, a metal layer 320 connected to the cathode of the protection diode 32, a metal layer 330 connected to the power supply terminal 34, and a metal layer 340 connected to the terminal 35 are formed.

[0079] like Figure 13BAs shown, the terminal pad 71 is provided as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b located on the side opposite to the upper surface 71a. The upper surface 71a is exposed to the outside through an opening 72. The terminal pad 71 is an input / output terminal used when the solid-state imaging device 1B is electrically connected to an external device. Therefore, the terminal pad 71 is exposed to the outside. The lower surface 71b of the terminal pad 71 is connected to a through-hole 414. The through-hole 414 electrically connects the terminal pad 71 and the metal layer 412.

[0080] like Figure 13B As shown, an opening 72 is formed from the second surface S2 (i.e., the light incident surface) of the semiconductor layer 200 to the terminal pad 71 of the second wiring layer 400. Protection diodes 31 to 33 are arranged at the location where the opening 72 is formed. After the opening 72 is formed, the protection diodes 31 to 33 disappear.

[0081] <Effects of the Fourth Embodiment> As described above, similar effects to those of the second embodiment can be achieved even in the fourth embodiment.

[0082] <Fifth Embodiment> Figure 14A and 14B This is a partial cross-sectional view illustrating a schematic structural example of the solid-state imaging apparatus 1E according to a fifth embodiment of the present disclosure. Figure 14A and 14B In, with Figure 7A and 7B The same parts are indicated by the same reference numerals, and their detailed descriptions are omitted.

[0083] like Figure 14A As shown, the semiconductor chip 2 of the solid-state imaging device 1E includes a semiconductor layer 200 having a first surface S1 and a second surface S2 located on opposite sides, and a first wiring layer 300 stacked on the first surface S1 of the semiconductor layer 200.

[0084] like Figure 14B As shown, the terminal pad 14 is embedded in the semiconductor layer 200 (i.e., located on the side of the first surface S1 of the second surface S2 of the semiconductor layer 200), and includes an upper surface 14a, a lower surface 14b located on the side opposite to the upper surface 14a, and a through hole 14c.

[0085] <Effects of the Fifth Embodiment> As described above, similar effects to those of the first embodiment can be achieved even in the fifth embodiment.

[0086] <Sixth Embodiment> Figure 15This is a partial cross-sectional view illustrating a schematic structural example of the solid-state imaging apparatus 1F according to a sixth embodiment of the present disclosure. Figure 15 In, with Figure 7B The same parts are indicated by the same reference numerals, and their detailed descriptions are omitted.

[0087] like Figure 15 As shown, the semiconductor chip 2 includes a semiconductor layer 200 having a first surface S1 and a second surface S2 opposite to each other, a first wiring layer 300 stacked on the first surface S1 of the semiconductor layer 200, a second wiring layer 400 stacked on a third surface S3 of the first wiring layer 300 opposite to the surface located on the semiconductor layer 200, and a third wiring layer 500 stacked on a fourth surface S4 of the second wiring layer 400 opposite to the third surface S3. This stacked structure can be implemented, for example, by stacking the first wiring layer 300 on the first surface S1 of the semiconductor layer 200, stacking and bonding the second wiring layer 400 on the third surface S3 of the first wiring layer 300, and stacking and bonding the third wiring layer 500 on the fourth surface S4 of the second wiring layer 400.

[0088] (Third wiring layer) like Figure 15 As shown, the third wiring layer 500 includes an interlayer insulating film 511, a metal layer 512, and a via 513. The metal layer 512 is stacked across the interlayer insulating film 511 as shown. The via 513 connects the metal layers 512 to each other. The metal layer 512 is bonded to the metal layer 412 of the second wiring layer 400 through a through-via 81 made of conductive material. Therefore, the terminal pad 14 is electrically connected to the metal layer 512 of the third wiring layer 500. The terminal pad 14, the first connection pad 353, and the second connection pad 413 overlap each other in the thickness direction of the semiconductor chip 2, but the terminal pad 14 and the through-via 81 do not overlap each other in the thickness direction of the semiconductor chip 2.

[0089] (First substrate) like Figure 15 As shown, the second wiring layer 400 includes a first substrate 415. The first substrate 415 may be, for example, a pixel substrate of the second layer, or a logic substrate forming logic circuits (e.g., control circuit 8). The first substrate 415 is located on the fourth surface S4 side and is formed of a semiconductor substrate of a first conductivity type (e.g., p-type). The first substrate 415 is provided with component isolation portions 416 for isolating multiple transistors and the like from other components. Furthermore, the first substrate 415 is electrically connected to the metal layer 412 through vias 414.

[0090] (Second substrate) like Figure 15As shown, the third wiring layer 500 includes, for example, a second substrate 514 for forming logic circuits (e.g., column signal processing circuit 5). The second substrate 514 is located on the side opposite to the fourth surface and is formed of a semiconductor substrate of a first conductivity type (e.g., p-type). The second substrate 514 is provided with component isolation portions 515 for isolating multiple transistors and the like from other components. Furthermore, the second substrate 514 is electrically connected to the metal layer 512 through vias 513.

[0091] <Effects of the Sixth Embodiment> As described above, similar effects to those of the first embodiment can be achieved even in the sixth embodiment. Furthermore, according to the sixth embodiment, since the various circuits constituting the logic circuit 13 (e.g., the column signal processing circuit 5 and the control circuit 8) can be arranged along the thickness direction of the semiconductor chip 2, the area of ​​the entire solid-state imaging device 1F can be reduced.

[0092] <Seventh Embodiment> Figure 16 This is a partial cross-sectional view illustrating a schematic structural example of the solid-state imaging apparatus 1G according to a seventh embodiment of the present invention. Figure 16 In, with Figure 15 The same parts are indicated by the same reference numerals, and their detailed descriptions are omitted.

[0093] like Figure 16 As shown, the third wiring layer 500 includes an interlayer insulating film 511, a metal layer 512, a via 513, and a third connection pad 516. As shown, the metal layer 512 and the third connection pad 516 are stacked with the interlayer insulating film 511 in between. The via 513 connects the metal layer 512 and the third connection pad 516. The third connection pad 516 is bonded to the second connection pad 413. Therefore, the terminal pad 14 is electrically connected to the metal layer 512 of the third wiring layer 500.

[0094] The first substrate 415 is located on the third surface S3 side. A through-hole 81 connects to the metal layer 352 of the first wiring layer 300 and the metal layer 412 of the second wiring layer 400. At this time, the through-hole 81 penetrates the first substrate 415.

[0095] <Effects of the Seventh Embodiment> As described above, similar effects to those in the sixth embodiment can be achieved even in the seventh embodiment.

[0096] <Eighth Embodiment> Figure 17 This is a partial cross-sectional view illustrating a schematic structural example of the solid-state imaging apparatus 1H according to the eighth embodiment of this disclosure. Figure 17 In, with Figure 13B and Figure 15The same parts are indicated by the same reference numerals, and their detailed descriptions are omitted.

[0097] like Figure 17 As shown, the terminal pad 71 is disposed as a metal layer 412 in the second wiring layer 400, and has an upper surface 71a and a lower surface 71b located on the side opposite to the upper surface 71a. The upper surface 71a is an exposed surface exposed to the outside through an opening 72. The metal layer 512 of the third wiring layer 500 is connected to the metal layer 412 of the second wiring layer 400 through a through-hole 81 made of conductive material. Therefore, the terminal pad 71 is electrically connected to the metal layer 512 of the third wiring layer 500.

[0098] <Effects of the Eighth Embodiment> As described above, similar effects to those of the second embodiment can be achieved even in the eighth embodiment. Furthermore, according to the eighth embodiment, since the various circuits constituting the logic circuit 13 (e.g., the column signal processing circuit 5 and the control circuit 8) can be arranged along the thickness direction of the semiconductor chip 2, the area of ​​the entire solid-state imaging device 1H can be reduced.

[0099] <Other Embodiments> The present technology has been described with reference to the first to eighth embodiments, but it should not be construed as limiting the present technology by the specification and drawings, which form part of this disclosure. Those skilled in the art should understand that, after understanding the spirit of the technical content disclosed in the first to eighth embodiments, various alternative embodiments, examples, and operational techniques can be included in the present technology. Furthermore, the constructions disclosed in the first to eighth embodiments can be appropriately combined without creating contradictions. For example, constructions disclosed in multiple different embodiments can be combined together, or constructions disclosed in multiple different modifications of the same embodiment can be combined together.

[0100] <Application Examples of Electronic Devices> The aforementioned solid-state imaging device can be applied to various electronic devices such as imaging devices like digital still cameras and digital video cameras, mobile phones with imaging capabilities, or other devices with imaging capabilities. Figure 18 This is a block diagram illustrating an example of the construction of an imaging system as an electronic device applying this technology.

[0101] Figure 18 The imaging system 2201 shown includes an optical system 2202, a shutter device 2203, a solid-state imaging element 2204 (as a solid-state imaging device), a control circuit 2205, a signal processing circuit 2206, a monitor 2207, and two memories 2208, and can capture still images and moving images.

[0102] The optical system 2202 includes one or more lenses and directs light (incident light) from the subject to the solid-state imaging element 2204 to form an image on the light-receiving surface of the solid-state imaging element 2204. According to the control circuit 2205, the shutter device 2203 arranged between the optical system 2202 and the solid-state imaging element 2204 controls the illumination period and the shading period of the solid-state imaging element 2204.

[0103] The solid-state imaging element 2204 includes a package containing the aforementioned solid-state imaging element. The solid-state imaging element 2204 accumulates signal charge over a certain period of time based on light forming an image on a light-receiving surface through the optical system 2202 and the shutter device 2203. The signal charge accumulated in the solid-state imaging element 2204 is transmitted according to a drive signal (timing signal) provided from the control circuit 2205.

[0104] The control circuit 2205 outputs drive signals to control the transmission operation of the solid-state imaging element 2204 and the shutter operation of the shutter device 2203, so as to drive the solid-state imaging element 2204 and the shutter device 2203.

[0105] The signal processing circuit 2206 performs various types of signal processing on the signal charge output from the solid-state imaging element 2204. The image (image data) obtained by the signal processing circuit 2206 through the signal processing is provided to the monitor 2207 for display, or provided to the memory 2208 for storage (recording). Furthermore, in the imaging system 2201 constructed as described above, solid-state imaging devices 1A to 1H can be used instead of the solid-state imaging element 2204.

[0106] <Application Examples of Moving Objects> The technology according to embodiments of this disclosure (the technology) can be applied to a variety of products. For example, the technology according to embodiments of this disclosure can be implemented as a device mounted on any type of mobile body. Non-limiting examples of mobile bodies may include automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, any personal mobility device, aircraft, unmanned aerial vehicles (UAVs), ships, and robots.

[0107] Figure 19 This is a block diagram illustrating a schematic construction example of a vehicle control system, which is an example of a mobile body control system to which the technology according to embodiments of this disclosure can be applied. The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 19In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional components of the integrated control unit 12050.

[0108] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 acts as a control device for devices such as: a drive force generating device (e.g., an internal combustion engine, drive motor, etc.) for generating vehicle driving force, a drive force transmission mechanism for transmitting driving force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating vehicle braking force.

[0109] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device for devices such as keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, or fog lights. In this case, radio waves or signals from various switches transmitted from a portable device that serves as a key alternative can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, or lights, etc.

[0110] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing for detecting objects such as people, vehicles, obstacles, signs, or characters on the road surface, or processing for detecting their distances.

[0111] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image or an electrical signal as distance measurement information. Furthermore, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0112] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. The driver state detection unit 12041 includes, for example, a camera for imaging the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or determine whether the driver is dozing off.

[0113] The microcomputer 12051 can calculate target control values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize functions of advanced driver assistance systems (ADAS), including collision avoidance or shock absorption, following distance-based driving, speed maintenance driving, collision warning, or lane departure warning.

[0114] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for autonomous driving by controlling the drive force generating device, steering mechanism or braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation.

[0115] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12030 based on information about the vehicle's exterior obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlights to switch from high beams to low beams, for example, based on the position of the vehicle ahead or oncoming vehicle detected by the exterior information detection unit 12030.

[0116] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle. Figure 19 In the example, audio speaker 12061, display unit 12062, and instrument panel 12063 are shown as output devices. Display unit 12062 may include, for example, at least one of a vehicle display and a head-up display.

[0117] Figure 20 This is a diagram showing an example of the mounting position of the imaging unit 12031. exist Figure 20In the vehicle 12100, imaging units 12101, 12102, 12103, 12104 and 12105 are imaging units 12031.

[0118] Imaging units 12101, 12102, 12103, 12104, and 12105 are installed in locations such as the front nose, rearview mirrors, rear bumper, rear door, and upper part of the interior windshield of vehicle 12100. Imaging unit 12101 at the front nose and imaging unit 12105 at the upper part of the interior windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 at the rearview mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 at the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 at the upper part of the interior windshield is primarily used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes ahead.

[0119] Notice, Figure 20 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located at the rearview mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located at the rear bumper or rear door. For example, a bird's-eye view image of vehicle 12100 is obtained by overlaying image data captured by imaging units 12101 to 12104.

[0120] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0121] For example, the microcomputer 12051 can determine the distance and time-varying distance (relative speed to the vehicle 12100) of each three-dimensional object within the imaging range 12111 to 12114 based on distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, specifically existing on the driving path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can pre-set a following distance to be maintained in front of the preceding vehicle and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, coordinated control for autonomous driving can be performed, enabling the vehicle to drive automatically without relying on driver operation, etc.

[0122] For example, microcomputer 12051 can classify three-dimensional object data of three-dimensional objects into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that can be visually recognized by the driver of vehicle 12100 and obstacles that are difficult to visually recognize by the driver of vehicle 12100. Then, microcomputer 12051 determines a collision risk to indicate the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, microcomputer 12051 outputs a warning to the driver through audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering through driving system control unit 12010. Microcomputer 12051 can thus assist driving to avoid collisions.

[0123] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras; and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to overlay a square outline for emphasis on the identified pedestrian. In addition, the sound / image output unit 12052 can control the display unit 12062 to display icons or the like for indicating pedestrians at a desired location.

[0124] Please note that this disclosure may also have the following constructions. (1) A light detection device, comprising: A semiconductor layer including a photoelectric conversion unit, wherein one surface of the semiconductor layer is a light incident surface and the other surface of the semiconductor layer is a device forming surface; A wiring layer, which is stacked on the element formation surface of the semiconductor layer; Terminal pads, which are at least partially located in the semiconductor layer and connected to the metal wiring of the wiring layer; The component is arranged between the terminal pads and the wiring layer. (2) The photodetector according to (1), wherein the element is a protection diode for protecting other elements arranged in the semiconductor layer. (3) The light detection device according to (1), wherein the semiconductor layer is used in a back-illuminated light detection device, the element forming surface of the back-illuminated light detection device is the front side, and the light incident surface of the back-illuminated light detection device is the back side. (4) The photodetector according to (1), wherein the terminal pad is located on the element forming surface side of the light incident surface of the semiconductor layer. (5) The optical detection device according to (1), wherein a plurality of the wiring layers are stacked together. (6) The optical detection device according to (5), wherein the plurality of wiring layers comprises: A first wiring layer is stacked on the device formation surface of the semiconductor layer; and A second wiring layer is stacked on the surface of the first wiring layer opposite to the surface located on the semiconductor layer side, and The second wiring layer includes a substrate on which logic circuits are formed. (7) The optical detection device according to (5), wherein the plurality of wiring layers comprises: A first wiring layer is stacked on the device formation surface of the semiconductor layer; A second wiring layer is stacked on the surface of the first wiring layer opposite to the surface located on the semiconductor layer side; and A third wiring layer is stacked on the surface of the second wiring layer opposite to the surface located on the side of the first wiring layer, and The second wiring layer includes a first substrate on which a first logic circuit is formed, and the third wiring layer includes a second substrate on which a second logic circuit is formed. (8) A light detection device, comprising: A semiconductor layer including a photoelectric conversion unit, wherein one surface of the semiconductor layer is a light incident surface and the other surface of the semiconductor layer is a device forming surface; A wiring layer, which is stacked on the element formation surface of the semiconductor layer; Terminal pads, located on the wiring layer side of the device formation surface of the semiconductor layer, and connected to the metal wiring of the wiring layer; and The pad opening extends from the light incident surface of the semiconductor layer to the terminal pad, exposing the terminal pad from the light incident surface, wherein... Before the pad opening is formed, a component is arranged at the location where the pad opening is formed. (9) The photodetector according to (8), wherein the element is a protection diode for protecting other elements disposed in the semiconductor layer. (10) The light detection device according to (8), wherein the semiconductor layer is used in a back-illuminated light detection device, the element forming surface of the back-illuminated light detection device is the front side, and the light incident surface of the back-illuminated light detection device is the back side. (11) The optical detection device according to (8), wherein a plurality of the wiring layers are stacked together. (12) The optical detection device according to (11), wherein the plurality of wiring layers comprises: A first wiring layer is stacked on the device formation surface of the semiconductor layer; and A second wiring layer is stacked on the surface of the first wiring layer opposite to the surface located on the semiconductor layer side, and The second wiring layer includes a substrate on which logic circuits are formed. (13) The optical detection device according to (12), wherein the terminal pad is located in the second wiring layer. (14) The optical detection device according to (11), wherein the plurality of wiring layers comprises: A first wiring layer is stacked on the device formation surface of the semiconductor layer; A second wiring layer is stacked on the surface of the first wiring layer opposite to the surface located on the semiconductor layer side; and A third wiring layer is stacked on the surface of the second wiring layer opposite to the surface located on the side of the first wiring layer, and The second wiring layer includes a first substrate on which a first logic circuit is formed, and the third wiring layer includes a second substrate on which a second logic circuit is formed. (15) The optical detection device according to (14), wherein the terminal pad is located in the second wiring layer. (16) An electronic device including a light detection device, the light detection device comprising: A semiconductor layer including a photoelectric conversion unit, wherein one surface of the semiconductor layer is a light incident surface and the other surface of the semiconductor layer is a device forming surface; A wiring layer, which is stacked on the element formation surface of the semiconductor layer; Terminal pads, which are at least partially located in the semiconductor layer and connected to the metal wiring of the wiring layer; The component is arranged between the terminal pads and the wiring layer. (17) An electronic device including a light detection device, the light detection device comprising: A semiconductor layer including a photoelectric conversion unit, wherein one surface of the semiconductor layer is a light incident surface and the other surface of the semiconductor layer is a device forming surface; A wiring layer, which is stacked on the element formation surface of the semiconductor layer; Terminal pads are located on the wiring layer side of the device forming surface of the semiconductor layer and are connected to the metal wiring of the wiring layer; The pad opening extends from the light incident surface of the semiconductor layer to the terminal pad, exposing the terminal pad from the light incident surface, wherein... Before the pad opening is formed, a component is arranged at the location where the pad opening is formed. (18) A method for manufacturing a light detection device, comprising: In fabricating a semiconductor chip, a wiring layer is stacked on the element formation surface of a semiconductor layer including a photoelectric conversion unit, one surface of the semiconductor layer is a light incident surface, and the other surface of the semiconductor layer is the element formation surface; Terminal pads are formed in the semiconductor layer, with the upper surface of the terminal pads exposed to the outside; and The lower surface of the terminal pad and the metal wiring of the wiring layer are connected by through-holes, such that the components arranged in the semiconductor layer are located between the lower surface of the terminal pad and the wiring layer. (19) A method for manufacturing an optical detection device, comprising: A semiconductor chip is fabricated, the semiconductor chip including a photoelectric conversion unit and a wiring layer stacked on the element formation surface of a semiconductor layer, one surface of the semiconductor layer being a light incident surface and the other surface of the semiconductor layer being the element formation surface; Terminal pads that are connected to the metal wiring of the wiring layer are formed on the wiring layer side of the element forming surface of the semiconductor layer; A pad opening is formed, the pad opening extending from the light incident surface of the semiconductor layer to the terminal pad, and exposing the terminal pad from the light incident surface; and Before forming the pad opening, the components are arranged at the location where the pad opening is formed. List of reference numerals

[0125] 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, B1 Solid-state imaging devices 2.60 Semiconductor Chips 2A pixel area 2B Peripheral Area 3 pixels 4 Vertical drive circuit 5-column signal processing circuits 6. Horizontal drive circuit 7 Output Circuit 8. Control Circuit 10-pixel drive line 11 Vertical signal line 12 Horizontal Signal Lines 13 Logic Circuits 14, 71 terminal pads 15 Readout Circuit 14a, 71a upper surface 14b, 71b lower surface 14c through hole Tunnel regions 21, 22, and 61 31, 32, 33 Protection Diodes 34 power terminals 35 terminals 41, 52, 53, 54, 56, 72 Opening 51 substrate 55, 57 Oxide film 73 Supporting substrate 81 Through-hole 200 semiconductor layers Component isolation section for 210, 416, and 515 300 First wiring layer Metal layers 310, 320, 330, 340, 352, 352a, 412, 512 351, 411, 511 interlayer insulating film 353 First connection pad 354, 414, 513 through holes 400 Second wiring layer 413 Second connection pad 415 First substrate 500 Third wiring layer 514 Second substrate 516 Third Connection Pad 2201 Imaging System 2202 Optical System 2203 Shutter mechanism 2204 Solid-State Imaging Element 2205 Control Circuit 2206 Signal Processing Circuit 2207 Monitor 2208 Memory 12000 Vehicle Control System 12001 Communication Network 12010 Drive System Control Unit 12020 Body System Control Unit 12030 External Information Detection Unit 12031 Imaging Unit 12040 In-vehicle Information Detection Unit 12041 Driver Status Monitoring Department 12050 Integrated Control Unit 12051 Microcomputer 12052 Audio / Image Output Unit 12061 Audio Speaker 12062 Display Unit 12063 Dashboard Vehicle 12100 Imaging section 12101 to 12105 Imaging range from 12111 to 12114

Claims

1. A light detection device, comprising: A semiconductor layer including a photoelectric conversion unit, wherein one surface of the semiconductor layer is a light incident surface and the other surface of the semiconductor layer is a device forming surface; A wiring layer, which is stacked on the element formation surface of the semiconductor layer; Terminal pads, which are at least partially located in the semiconductor layer and connected to the metal wiring of the wiring layer; The component is arranged between the terminal pads and the wiring layer.

2. The optical detection device according to claim 1, wherein, The element is a protective diode used to protect other elements arranged in the semiconductor layer.

3. The optical detection device according to claim 1, wherein, The semiconductor layer is used in a back-illuminated light detection device, wherein the element forming surface of the back-illuminated light detection device is the front side and the light incident surface of the back-illuminated light detection device is the back side.

4. The optical detection device according to claim 1, wherein, The terminal pad is located on the element formation side of the light incident surface of the semiconductor layer.

5. The optical detection device according to claim 1, wherein, Multiple wiring layers are stacked together.

6. The optical detection device according to claim 5, wherein, The plurality of wiring layers include: A first wiring layer is stacked on the device formation surface of the semiconductor layer; and A second wiring layer is stacked on the surface of the first wiring layer opposite to the surface located on the semiconductor layer side, and The second wiring layer includes a substrate on which logic circuits are formed.

7. The optical detection device according to claim 5, wherein, The plurality of wiring layers include: A first wiring layer is stacked on the device formation surface of the semiconductor layer; A second wiring layer is stacked on the surface of the first wiring layer opposite to the surface located on the semiconductor layer side; and A third wiring layer is stacked on the surface of the second wiring layer opposite to the surface located on the side of the first wiring layer, and The second wiring layer includes a first substrate on which a first logic circuit is formed, and the third wiring layer includes a second substrate on which a second logic circuit is formed.

8. A light detection device, comprising: A semiconductor layer including a photoelectric conversion unit, wherein one surface of the semiconductor layer is a light incident surface and the other surface of the semiconductor layer is a device forming surface; A wiring layer, which is stacked on the element formation surface of the semiconductor layer; Terminal pads are located on the wiring layer side of the device forming surface of the semiconductor layer and are connected to the metal wiring of the wiring layer; as well as The pad opening extends from the light incident surface of the semiconductor layer to the terminal pad, exposing the terminal pad from the light incident surface, wherein... Before the pad opening is formed, a component is arranged at the location where the pad opening is formed.

9. The optical detection device according to claim 8, wherein, The element is a protective diode used to protect other elements disposed in the semiconductor layer.

10. The optical detection device according to claim 8, wherein, The semiconductor layer is used in a back-illuminated light detection device, wherein the element forming surface of the back-illuminated light detection device is the front side and the light incident surface of the back-illuminated light detection device is the back side.

11. The optical detection device according to claim 8, wherein, Multiple wiring layers are stacked together.

12. The optical detection device according to claim 11, wherein, The plurality of wiring layers include: A first wiring layer is stacked on the device formation surface of the semiconductor layer; and A second wiring layer is stacked on the surface of the first wiring layer opposite to the surface located on the semiconductor layer side, and The second wiring layer includes a substrate on which logic circuits are formed.

13. The optical detection device according to claim 12, wherein, The terminal pads are located in the second wiring layer.

14. The optical detection device according to claim 11, wherein, The plurality of wiring layers include: A first wiring layer is stacked on the device formation surface of the semiconductor layer; A second wiring layer is stacked on the surface of the first wiring layer opposite to the surface located on the semiconductor layer side; and A third wiring layer is stacked on the surface of the second wiring layer opposite to the surface located on the side of the first wiring layer, and The second wiring layer includes a first substrate on which a first logic circuit is formed, and the third wiring layer includes a second substrate on which a second logic circuit is formed.

15. The optical detection device according to claim 14, wherein, The terminal pads are located in the second wiring layer.

16. An electronic device including a light detection device, the light detection device comprising: A semiconductor layer including a photoelectric conversion unit, wherein one surface of the semiconductor layer is a light incident surface and the other surface of the semiconductor layer is a device forming surface; A wiring layer, which is stacked on the element formation surface of the semiconductor layer; Terminal pads, which are at least partially located in the semiconductor layer and connected to the metal wiring of the wiring layer; The component is arranged between the terminal pads and the wiring layer.

17. An electronic device including a light detection device, the light detection device comprising: A semiconductor layer including a photoelectric conversion unit, wherein one surface of the semiconductor layer is a light incident surface and the other surface of the semiconductor layer is a device forming surface; A wiring layer, which is stacked on the element formation surface of the semiconductor layer; Terminal pads are located on the wiring layer side of the device forming surface of the semiconductor layer and are connected to the metal wiring of the wiring layer; The pad opening extends from the light incident surface of the semiconductor layer to the terminal pad, exposing the terminal pad from the light incident surface, wherein... Before the pad opening is formed, a component is arranged at the location where the pad opening is formed.

18. A method for manufacturing a light detection device, comprising: In fabricating a semiconductor chip, a wiring layer is stacked on the element formation surface of a semiconductor layer including a photoelectric conversion unit, one surface of the semiconductor layer is a light incident surface, and the other surface of the semiconductor layer is the element formation surface; Terminal pads are formed in the semiconductor layer, with the upper surface of the terminal pads exposed to the outside; and The lower surface of the terminal pad and the metal wiring of the wiring layer are connected by through-holes, such that the components arranged in the semiconductor layer are located between the lower surface of the terminal pad and the wiring layer.

19. A method for manufacturing a light detection device, comprising: A semiconductor chip is fabricated, the semiconductor chip including a photoelectric conversion unit and a wiring layer stacked on the element formation surface of a semiconductor layer, one surface of the semiconductor layer being a light incident surface and the other surface of the semiconductor layer being the element formation surface; Terminal pads that are connected to the metal wiring of the wiring layer are formed on the wiring layer side of the element forming surface of the semiconductor layer; A pad opening is formed, the pad opening extending from the light incident surface of the semiconductor layer to the terminal pad, and exposing the terminal pad from the light incident surface; and Before forming the pad opening, the components are arranged at the location where the pad opening is formed.

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