Pin multiplexing-based compression test system and method

Abstract

The invention discloses a compression test system and method based on pin multiplexing, and relates to the technical field of testability design. The corresponding system comprises a plurality of chip passivation holes, a segment insertion byte unit, a test data register and a compression and decompression unit, wherein the compression and decompression unit is provided with an initial chip passivation hole and at least one standby chip passivation hole; the segment insertion byte unit and the test data register are arranged between the chip passivation hole and the compression and decompression unit, and are used for connecting the compression and decompression unit to a standby chip passivation hole configured by the compression and decompression unit under the condition that the initial chip passivation hole corresponding to the compression and decompression unit fails; or the compression and decompression unit is configured to a preset standby chip passivation hole or an initial chip passivation hole of the compression and decompression unit. According to the invention, the influence of the chip passivation trepanning performance on the internal logic test can be weakened.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, particularly to the field of design for testability technology, and specifically to a compression test system and method based on pin multiplexing. Background Technology

[0002] As Moore's Law slows its implementation, the integrated circuit industry has entered the post-Moore era, with new processes, materials, and architectures constantly emerging, driving the development of integrated circuits. Against this backdrop, the technological development trends in the integrated circuit industry emphasize multi-path innovation in advanced processing, advanced packaging, and architectural innovation.

[0003] For Design for Testability (DPT), chip designs are becoming increasingly larger. Limited by the number of passivation openings (PADs), the large number of test registers for the logic under test (DUT) leads to increasingly longer scan chains, further impacting test time and increasing chip costs. To address this issue, the industry, while keeping the external test PADs unchanged, splits the internal scan chain and processes it in parallel using a Compress and Decompress (CODEC) unit to complete data test control and monitoring. The CODEC unit provides very high compression capabilities for DPT. Typically, the ratio of test ports to scan chains is 1:200, and each scan chain controls no more than 1000 scan registers within the constraints of test time cost. Therefore, for DPT, a pair of CODEC test ports typically handles the control and monitoring of 200,000 registers.

[0004] The data flow for testing a specific chip under test is as follows: test base - chip PAD - CODEC test port - scan short link - target register. The test base is a testing tool independent of the chip. For researchers in design for testability, there is still a two-order-of-magnitude gap between the chip PAD and the CEDEC test port in actual chip design processes. Therefore, how to compress the test channel between the chip PAD and the target scan register and further simplify the test cost is a technical problem that urgently needs to be solved by those skilled in the art.

[0005] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0006] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a compression testing system and method based on pin multiplexing.

[0007] First, this application provides a compression test system based on pin multiplexing, including: multiple chip passivation apertures, segment insertion byte units, test data registers, and compression / decompression units, wherein:

[0008] The compression / decompression unit is configured with an initial chip passivation aperture and at least one spare chip passivation aperture.

[0009] The segment insertion byte unit and the test data register are disposed between the chip passivation aperture and the compression / decompression unit, and are used to connect the compression / decompression unit to a configured backup chip passivation aperture in the event that the initial chip passivation aperture corresponding to the compression / decompression unit fails; or

[0010] Configure the compression / decompression unit to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation aperture.

[0011] In some embodiments, the chip passivation aperture includes: a chip passivation input aperture and a chip passivation output aperture;

[0012] The test data register includes: a test data input register and a test data output register; wherein:

[0013] The test data input register is used, in the event of a failure of the chip passivation input aperture, to cooperate with the segment insertion byte unit to configure the compression / decompression unit initially configured with the failed chip passivation input aperture to its corresponding backup chip passivation input aperture; or

[0014] Configure the compression / decompression unit of the faulty chip passivation input aperture to the backup chip passivation input aperture or the initial chip passivation input aperture of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation input aperture.

[0015] The test data output register is used, in the event of a failure of the passivation output aperture of the chip, in conjunction with the segment insertion byte unit, to configure the compression / decompression unit initially configured with the failed passivation output aperture of the chip to its corresponding backup passivation output aperture; or

[0016] Configure the compression / decompression unit of the faulty chip passivation output opening to the backup chip passivation output opening or the initial chip passivation output opening of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation output opening.

[0017] In some embodiments, the configuration relationship between the compression / decompression unit and the spare chip passivation aperture is determined by the number of logic under test and the number of compression / decompression units corresponding to the logic under test.

[0018] In some embodiments, the test data register further includes a logic register to be tested, used to switch and split multiple logics to be tested in conjunction with the segment insertion byte unit.

[0019] In some embodiments, the test data output register is further used to output the level value of the chip passivation output opening; wherein the level value is used to characterize whether the chip passivation output opening has failed.

[0020] In some embodiments, a compression test system based on pin multiplexing further includes:

[0021] Multiple AND-OR gate logic circuits are connected to the test data register and correspond one-to-one with the multiple compression / decompression units, used to switch the configuration relationship between the compression / decompression units and the chip passivation openings.

[0022] In some embodiments, a compression test system based on pin multiplexing further includes:

[0023] It also includes: a test access port controller, used to cooperate with the segment insertion byte unit and the test data register to multiplex the same type of compression and decompression unit in multiple modules for logical testing, and to call different types of compression and decompression units in multiple modules for logical testing.

[0024] Secondly, this application also provides a compression testing method based on pin multiplexing, applied to the aforementioned compression testing system based on pin multiplexing, the method comprising:

[0025] The segment insertion byte unit and the test data register are located between the chip passivation aperture and the compression / decompression unit. In the event of a failure in the initial chip passivation aperture corresponding to the compression / decompression unit, the compression / decompression unit is connected to its configured backup chip passivation aperture; or

[0026] The compression / decompression unit is configured to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and the pre-set compression / decompression unit is configured to its available chip passivation aperture; wherein the compression / decompression unit is pre-configured with an initial chip passivation aperture and at least one spare chip passivation aperture.

[0027] In some embodiments, the chip passivation aperture includes: a chip passivation input aperture and a chip passivation output aperture;

[0028] The test data register includes: a test data input register and a test data output register;

[0029] In the event of a failure of the chip passivation input aperture, the test data input register, in conjunction with the segment insertion byte unit, configures the compression / decompression unit initially configured with the failed chip passivation input aperture to its corresponding backup chip passivation input aperture; or

[0030] Configure the compression / decompression unit of the faulty chip passivation input aperture to the backup chip passivation input aperture or the initial chip passivation input aperture of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation input aperture.

[0031] In the event of a failure of the passivation output aperture on the chip, the test data output register, in conjunction with the segment insertion byte unit, configures the compression / decompression unit initially configured with the failed passivation output aperture to its corresponding backup passivation output aperture; or

[0032] Configure the compression / decompression unit of the faulty chip passivation output opening to the backup chip passivation output opening or the initial chip passivation output opening of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation output opening.

[0033] In some embodiments, the configuration relationship between the compression / decompression unit and the spare chip passivation aperture is determined by the number of logic under test and the number of compression / decompression units corresponding to the logic under test.

[0034] In some embodiments, the test data register further includes: a logic register under test; a compression test method based on pin multiplexing further includes:

[0035] The test logic register is switched and split into multiple test logics by cooperating with the segment insertion byte unit.

[0036] In some embodiments, a compression test method based on pin multiplexing further includes:

[0037] The voltage level of the passivation output aperture of the chip is output through the test data output register; wherein, the voltage level is used to characterize whether the passivation output aperture of the chip has failed.

[0038] In some embodiments, a compression test method based on pin multiplexing further includes:

[0039] Multiple AND-OR gate logic circuits are connected to the test data register, and each corresponds to one of the multiple compression / decompression units;

[0040] The configuration relationship between the compression / decompression unit and the chip passivation aperture is switched by the plurality of AND / OR gate logic circuits.

[0041] In some embodiments, a compression test method based on pin multiplexing further includes:

[0042] The logic test is performed by using the same type of compression / decompression unit from multiple modules in conjunction with the test access port controller, the segment insertion byte unit, and the test data register, as well as by calling different types of compression / decompression units from multiple modules.

[0043] This application also provides a board, which includes the compression test system based on pin multiplexing described in the above embodiments.

[0044] This application also provides an electronic device, which includes the board described in the above embodiments.

[0045] This application proposes a pin-multiplexed compression testing system and method. The corresponding pin-multiplexed compression testing system includes: multiple chip passivation apertures, segment insertion byte units, test data registers, and compression / decompression units. The compression / decompression units are configured with an initial chip passivation aperture and at least one spare chip passivation aperture. The segment insertion byte unit and the test data register are located between the chip passivation aperture and the compression / decompression unit. In the event of a failure of the initial chip passivation aperture corresponding to the compression / decompression unit, the compression / decompression unit is connected to its configured spare chip passivation aperture; or the compression / decompression unit is configured to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and the pre-set compression / decompression unit is configured to its available chip passivation aperture.

[0046] The compression test system based on pin multiplexing provided in this application can avoid the dependency between the CODEC test port and the chip passivation aperture PAD when there is an order of magnitude difference between them. This weakens the impact of the chip passivation aperture PAD performance on internal logic testing and provides a solution for the testability design test of the packaged chip. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0048] Figure 1 This is a schematic diagram of the structure of an integrated circuit with data interoperability and virtual pins for peripheral connection in the prior art;

[0049] Figure 2 This is a schematic diagram of another type of integrated circuit in the prior art that has data interoperability and is used for peripheral connection via virtual pins;

[0050] Figure 3 This is a schematic diagram of a compression testing system based on pin multiplexing provided in an embodiment of this application;

[0051] Figure 4 This is a schematic diagram of the data transmission between the compression / decompression unit configuration and the chip passivation aperture in a compression test system based on pin multiplexing provided in this application embodiment;

[0052] Figure 5 This is another schematic diagram of a compression test system based on pin multiplexing provided in an embodiment of this application;

[0053] Figure 6 This is a schematic diagram of the physical structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0054] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0055] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0056] See Figure 1 as well as Figure 2 This demonstrates two integrated circuits with data interoperability and virtual pins for peripheral connectivity, providing communication between any input / output (I / O) pins and onboard peripherals. The integrated circuit may include multiple onboard peripherals, multiple I / O pins, an input multiplexer for each input of a peripheral, and an output multiplexer for each I / O pin. Each peripheral may include one input and one output, and the I / O pins may include a set of physical I / O pins and a set of non-physical virtual I / O pins. Each physical I / O pin is configured to provide external connectivity to each peripheral, and each non-physical virtual I / O pin is configured to provide internal connectivity between each peripheral and at least one other peripheral. The input multiplexer may be connected to the input of a corresponding peripheral and configured to transmit signals from at least one I / O pin to the connected corresponding peripheral.

[0057] An output multiplexer can be connected to a corresponding I / O pin and configured to transmit signals from at least one output of a peripheral device to the connected corresponding I / O pin. Furthermore, the integrated circuit can be configured to include a first set of hardwired connections from each I / O pin to each input multiplexer, and a second set of hardwired connections from each output of the peripheral device to each output multiplexer. The first set of hardwired connections may include a first crossbar switch and a dedicated hardwired connection between each I / O pin and the first crossbar switch. The second set of hardwired connections may include a second crossbar switch and a dedicated hardwired connection between each output of the peripheral device and the second crossbar switch. Additionally, the first and second sets of hardwired connections together can provide hardwired connections between each peripheral device.

[0058] It is not difficult to see that, Figure 1 as well as Figure 2 In the example shown, there is a difference between the number of onboard device interfaces on the test base and the number of chip PADs. This structure is designed to flexibly handle the difference in the number of ports. However, there is no order of magnitude difference between the two. If directly mapped to the chip PADs and CODEC test ports, the difference of more than two orders of magnitude would cause the above data path multiplexing structure to lose its effect and further amplify the strong dependency between the two. That is, one PAD corresponds to dozens or even hundreds of test ports, which further increases the burden of compatibility requirements for subsequent integrated circuit design.

[0059] To address the aforementioned issues, this application provides a compression testing system and method based on pin multiplexing to achieve the aforementioned technical objectives.

[0060] Figure 3 This application provides a schematic diagram of a compression test system based on pin multiplexing, as shown below. Figure 3 As shown, this application provides a compression test system based on pin multiplexing, including:

[0061] Multiple chip passivation apertures (PAD1, PAD2…PAD12), segment insertion byte units (PINMUX SIB), test data registers (PINMUX TDR, which consists of three parts: the logic under test register (mode TDR), the test data input register (CRTL INPUT PAD TDR), and the test data output register (CRTL OUTPUT PAD TDR)), and compression / decompression units (CODEC A1, CODEC A2, etc. in the figure) are embedded in the chip module.

[0062] The compression / decompression unit is configured with an initial chip passivation aperture and at least one spare chip passivation aperture (see [link]). Figure 4 This refers to the compression and decompression unit being configured with compression test monitoring data, which includes an initial chip passivation aperture and at least one spare chip passivation aperture. Figure 4In the process, the compression / decompression unit configuration inputs the aforementioned compression test detection data to the chip passivation input aperture and the chip passivation output aperture. The chip passivation input aperture and the chip passivation output aperture feed back the compression test control data to the compression / decompression unit configuration (the same applies below). It should be noted that the initial chip passivation aperture and the spare chip passivation aperture belong to the aforementioned chip passivation apertures. Furthermore, the initial chip passivation aperture of the current compression / decompression unit may be a spare chip passivation aperture of another compression / decompression unit, and the spare chip passivation aperture of the current compression / decompression unit may also be an initial chip passivation aperture of another compression / decompression unit. This mapping relationship is preset, and its complexity depends on the number of logic to be tested and the number of compression / decompression units corresponding to the logic to be tested, i.e., it is determined by the number of compression / decompression units (CODEC) and the number of chip passivation apertures (PAD). (The port test control data source of the compression / decompression unit configuration is not unique; the chip passivation aperture can provide test control data for the ports of multiple compression / decompression units (not simultaneously)).

[0063] The segment insertion byte unit and the test data register are located between the chip passivation aperture and the compression / decompression unit. This is used to connect the compression / decompression unit to a configured backup chip passivation aperture in the event of a failure in the initial chip passivation aperture corresponding to the compression / decompression unit; or

[0064] Configure the compression / decompression unit to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation aperture.

[0065] Specifically, the port of the compression / decompression unit is configured to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and the port of the pre-set compression / decompression unit is configured to its available chip passivation aperture.

[0066] The aforementioned Segment Insertion Bit (SIB) is a core component of IJTAG technology. It allows for the implementation of arbitrary hierarchical structures in the IJTAG network by inserting a single bit of TDR, thereby enabling flexible configuration of the IJTAG network.

[0067] The Test Data Register (TDR) can be used to control and configure network access, and also to control and monitor the module through the embedded module interface. The control, configuration, and operation signals of the TDR are generated by the TAP controller. TDRs are available in three types: write-only, read-only, and writable / read-only.

[0068] The compression / decompression unit has the following functions: in a design for testability environment, the compression / decompression circuit enables more scan chains to be implemented with a limited number of pins, and further improves test efficiency by configuring the number of scan chains to increase and the length to decrease.

[0069] For the aforementioned chip passivation aperture PAD, the network inside the integrated circuit needs to be brought out to the outside of the chip for packaging. In order to avoid the line width being too thin and unable to withstand the pressure of soldering, it needs to be connected to a large metal block first. The large metal block that bears the pressure is the PAD.

[0070] As described above, this application, in order to configure the most spare chip passivation aperture PADs for test data, completes port selection and test channel configuration through the IJTAG structure. Therefore, a new set of PINMUX SIB and PINMUX TDR is introduced into the basic testability design architecture. The test data register TDR does not independently configure the initial chip passivation aperture and the spare chip passivation aperture for the CODEC test channel. Instead, a "shared" chip passivation aperture mechanism is used to achieve the above purpose (i.e., not a zero-or-one). Specifically, the initial chip passivation aperture PAD of the current compression / decompression unit CODEC may be a spare chip passivation aperture PAD of another compression / decompression unit CODEC, and the spare chip passivation aperture of the current compression / decompression unit CODEC may also be the initial chip passivation aperture PAD of another compression / decompression unit CODEC. This allows for maximum flexibility in matching the compression / decompression unit CODEC to perform complete logic test analysis of the chip in the event of a failure of a certain chip passivation aperture.

[0071] This application proposes a compression test system based on pin multiplexing, comprising: multiple chip passivation apertures, segment insertion byte units, test data registers, and compression / decompression units. The compression / decompression units are configured with an initial chip passivation aperture and at least one spare chip passivation aperture. The segment insertion byte unit and the test data register are located between the chip passivation aperture and the compression / decompression unit. In the event of a failure of the initial chip passivation aperture corresponding to the compression / decompression unit, the compression / decompression unit is connected to its configured spare chip passivation aperture; or the compression / decompression unit is configured to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and the pre-set compression / decompression unit is configured to its available chip passivation aperture.

[0072] This application can avoid the dependency between the CODEC test port and the chip passivation aperture PAD when there is an order of magnitude difference between them, thereby weakening the impact of chip PAD performance on internal logic testing, and providing a solution for the testability design and testing of packaged chips.

[0073] In some embodiments, see continue to see Figure 3 The chip passivation aperture PAD includes: chip passivation input aperture (PAD1, PAD2...PAD6) and chip passivation output aperture (PAD7, PAD8...PAD12); and the chip passivation input aperture and the chip passivation output aperture correspond one-to-one, for example, PAD1 corresponds to PAD7, PAD2 corresponds to PAD8, and so on.

[0074] The Test Data Register (TDR) includes: Test Data Input Register (CRTL INPUT PAD TDR) and Test Data Output Register (CRTL OUTPUT PAD TDR).

[0075] The Test Data Input Register (CRTL INPUT PAD TDR) is used, in conjunction with the Segment Insertion Byte Unit (PINMUX SIB), to configure the compression / decompression unit initially configured with the faulty chip passivation input opening (PAD1, PAD2…PAD6) to its corresponding spare chip passivation input opening in the event of a failure; or

[0076] Configure the compression / decompression unit of the faulty chip passivation input aperture to the backup chip passivation input aperture or the initial chip passivation input aperture of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation input aperture.

[0077] The test data output register is used, in conjunction with the segment insertion byte unit, to configure the compression / decompression unit initially configured for the faulty passivation output opening to its corresponding backup passivation output opening in the event of a failure; or

[0078] Configure the compression / decompression unit of the faulty chip passivation output opening to the backup chip passivation output opening or the initial chip passivation output opening of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation output opening.

[0079] The above content is illustrated in Table 1 below. Table 1 shows the pre-defined configuration relationships between compression / decompression units, chip passivation input openings, and chip passivation output openings. Input PAD (in): PAD1 data is configured to CODEC A1, PAD2 to CODEC C1, and so on, and they are mutually exclusive. However, if the above conditions are not met (i.e., if a PAD malfunctions), the pre-defined priority relationship between the ports of the PAD and the CODEC will be weakened, and the actual channel configuration will be affected, as shown in the table below. Output PAD (out): PAD7 data is configured to CODEC B11, and PAD9 data is configured to CODEC B11 and CODEC B21, which are not one-to-one correspondences.

[0080] Table 1

[0081] To further illustrate with CODEC B21, when a process defect exists in PAD9, the value of CTRL OUTPUT PAD TDR is 1101, corresponding to a select value of 0 for the secondary MUX before the PAD. This allows CODEC B21 to monitor data through PAD11. When a process defect exists in PAD7, the value of CTRL OUTPUT PAD TDR is 0111. In this case, the data from CODEC B11 will occupy PAD9, and CODEC B21's data monitoring will still be achieved through PAD11.

[0082] The reason why the above control logic and test channel selection are simplified is that the mapping relationship between the test port CODEC and the chip passivation aperture PAD in the above structure is one-to-two (PAD to CODEC test port is one-to-many). This leads to the decision to select the test channel as either one or the other. However, with the further improvement of reuse, the control logic has a step improvement. It should still be noted that since there are far more CODEC test ports than PADs in actual working conditions, the number of PADs corresponding to one port will not be too high, and it will also be subject to other design limitations (Example 2).

[0083] In some embodiments, the configuration relationship between the compression / decompression units and the spare chip passivation apertures is determined by the number of logic under test and the number of compression / decompression units corresponding to the logic under test.

[0084] See also Figure 3 And Table 1, the configuration relationship between the compression / decompression unit and the spare chip passivation opening (preset, as shown in Table 1) is determined by the number of logic modes to be tested and the number of test port CODECs within the logic modes to be tested.

[0085] In some embodiments, see continue to see Figure 3 The test data register also includes: the logic under test register modeTDR, which is used in conjunction with the segment insertion byte unit PINMUX SIB to switch and split multiple logic modes under test.

[0086] In some embodiments, the test data output register is also used to output the level value of the chip passivation output aperture; wherein, the level value is used to characterize whether the chip passivation output aperture has failed. For example, if the high-level instrument chip passivation output aperture is functioning correctly and performing well, referring to Table 1, taking the CODEC B21 test port as an example, when PAD7 has a process defect, the value of CTRL OUTPUT PAD TDR is 0111. At this time, the data of CODEC B11 will occupy PAD9, and the data monitoring of CODEC B21 is still achieved through PAD11.

[0087] In some embodiments, see Figure 3 A compression test system based on pin multiplexing also includes:

[0088] Multiple AND-OR gate logic circuits are connected to the test data register and correspond one-to-one with multiple compression / decompression units, used to switch the configuration relationship between the compression / decompression units and the chip passivation openings.

[0089] In some embodiments, see Figure 3 A compression test system based on pin multiplexing also includes:

[0090] The Test Access Port Controller (TAP) is used in conjunction with the segment insertion byte unit and the test data register to multiplex the same type of compression / decompression unit in multiple modules for logical testing, and to call different types of compression / decompression units in multiple modules for logical testing.

[0091] In addition, the test access port controller is a core component of the JTAG interface. It is a finite state machine responsible for controlling the sequence of JTAG test operations, including state transitions and data transfers.

[0092] As described above, the compression test system based on pin multiplexing proposed in this application includes: multiple chip passivation apertures, segment insertion byte units, test data registers, and compression / decompression units. The compression / decompression unit is configured with an initial chip passivation aperture and at least one spare chip passivation aperture. The segment insertion byte unit and the test data register are located between the chip passivation aperture and the compression / decompression unit, and are used to connect the compression / decompression unit to its configured spare chip passivation aperture when the initial chip passivation aperture corresponding to the compression / decompression unit fails; or to configure the compression / decompression unit to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and to configure the pre-set compression / decompression unit to its available chip passivation aperture. Compared with the prior art, this application has the following beneficial effects:

[0093] First, the strong dependence of the test port CODEC on the chip passivation aperture PAD is weakened: when there are far more test ports CODEC than chip passivation aperture PAD, by reusing the chip passivation aperture PAD, the complete chip logic test can be completed even when some chip passivation aperture PADs have process defects.

[0094] Secondly, the data transmission problem after the chip passivation aperture PAD and the test port CODEC are mapped to each other is solved: by adding control logic to complete the test channel configuration, the transmission path can be reconfigured for all test ports even if some chip passivation aperture PADs have process defects.

[0095] In some embodiments, based on the above-described pin-multiplexed compression test system, this application also provides a pin-multiplexed compression test method applied to the above-described pin-multiplexed compression test system, the method comprising the following steps:

[0096] The segment insertion byte unit and the test data register are located between the chip passivation aperture and the compression / decompression unit. In the event of a failure in the initial chip passivation aperture corresponding to the compression / decompression unit, the compression / decompression unit is connected to its configured backup chip passivation aperture; or

[0097] The compression / decompression unit is configured to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and the pre-set compression / decompression unit is configured to its available chip passivation aperture; wherein the compression / decompression unit is pre-configured with an initial chip passivation aperture and at least one spare chip passivation aperture.

[0098] In some embodiments, the chip passivation aperture includes: a chip passivation input aperture and a chip passivation output aperture;

[0099] The test data registers include: a test data input register and a test data output register;

[0100] In the event of a failure in the chip passivation input aperture, the test data input register, in conjunction with the segment insertion byte unit, configures the compression / decompression unit initially configured for the failed chip passivation input aperture to its corresponding spare chip passivation input aperture; or

[0101] Configure the compression / decompression unit of the faulty chip passivation input aperture to the backup chip passivation input aperture or the initial chip passivation input aperture of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation input aperture.

[0102] In the event of a failure in the chip passivation output aperture, the test data output register, in conjunction with the segment insertion byte unit, configures the compression / decompression unit initially configured for the failed chip passivation output aperture to its corresponding backup chip passivation output aperture; or

[0103] Configure the compression / decompression unit of the faulty chip passivation output opening to the backup chip passivation output opening or the initial chip passivation output opening of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation output opening.

[0104] In some embodiments, the configuration relationship between the compression / decompression units and the spare chip passivation apertures is determined by the number of logic under test and the number of compression / decompression units corresponding to the logic under test.

[0105] In some embodiments, the test data register further includes: a logic register under test; a compression test method based on pin multiplexing further includes:

[0106] The test logic register is switched and split into multiple test logics by coordinating with the segment insertion byte unit.

[0107] In some embodiments, a compression test method based on pin multiplexing further includes:

[0108] The voltage level of the passivation output aperture of the chip is output through the test data output register; the voltage level is used to characterize whether the passivation output aperture of the chip has failed.

[0109] In some embodiments, a compression test method based on pin multiplexing further includes:

[0110] Multiple AND-OR gate logic circuits are connected to the test data register, and each corresponds to one of the multiple compression / decompression units;

[0111] The configuration relationship between the compression / decompression unit and the chip passivation aperture is switched by multiple AND / OR gate logic circuits.

[0112] In some embodiments, a compression test method based on pin multiplexing further includes:

[0113] Logical testing is performed by using the test access port controller, segment insertion byte unit, and test data register in conjunction with multiple modules to reuse the same type of compression / decompression unit, and by calling different types of compression / decompression units from multiple modules.

[0114] Here, we will use two specific application examples to illustrate the above-mentioned compression test system based on pin multiplexing and the corresponding test method.

[0115] The present invention aims to solve two problems:

[0116] 1. Under the condition that the number of CODEC test ports and the number of chip passivation aperture PADs are very different, complete the configuration and test monitoring of the one-to-many data path PAD to CODEC;

[0117] 2. Weaken the one-to-one correspondence between the chip passivation aperture PAD and the CODEC test port to avoid losing the ability to control and monitor the relevant logic when a manufacturing defect exists in a certain PAD, i.e., the one-to-many configuration relationship between the data path CODEC test port and PAD.

[0118] The above two are the core components of the pin multiplexing structure provided in this application. The CODEC test ports are in a one-to-many relationship, but there is a significant difference in the number of the two. The core function of this application is to provide corresponding PADs and orderly test channels for all CODEC test ports under the premise that some PADs are defective due to manufacturing defects and the test conditions are poor.

[0119] As described above, in order to provide the chip passivation aperture PAD with the maximum surplus of test data, this application completes the port selection and test channel configuration through the I JTAG structure. Therefore, a new set of PINMUXSIB and PINMUXTDR is introduced into the basic design for testability architecture. The PINMUXTDR consists of three parts: the logic under test register mode TDR for controlling the chip's logic under test splitting; the test data input register (CRTL INPUT PADTDR) for avoiding manufacturing defects of the input PAD; and the test data output register (CRTL OUTPUT PAD TDR) for avoiding manufacturing defects of the output PAD.

[0120] Specific application example 1:

[0121] In the compression test system based on pin multiplexing provided in this application, there must be a priority and mutual exclusion relationship between the PAD and CODEC in the correspondence of channel selection. This design requirement is implemented through additional control logic (i.e., Table 3).

[0122] Next, see Figure 3 The PINMUX interconnect topology provided in this application mainly consists of four parts: the logic under test (DUT) within the dashed box, I JTAG modules (PINMUXSIB, TAP, PINMUXTDR), combinational logic controlling the selection of test channels, and six pairs of input / output pads. To simplify the correspondence of logical relationships and demonstrate the functional advantages of the PINMUX structure, the DUT is divided into three modes to control seven CODEC units to complete corresponding logic tests. Furthermore, to present the complex testing requirements of actual chip design for testability (DFT), the DUT includes module reuse (block A type 0 & block A type 1) and joint testing of cross-module CODEC units (CODEC A1 & CODECC). The first-level MUX and DEMUX of the input / output ports are used for switching test logic blocks in different modes.

[0123] The above structure enables 12 PADs to control and detect 60 CODEC test ports (one test port corresponds to two PADs, and one PAD corresponds to multiple test ports; the latter number is affected by two factors: the number of modes and the number of test ports within a certain mode).

[0124] It should be further explained that in actual chip integration, the number of CODEC test ports is much greater than the number of PADs. In this architecture, it is still possible to achieve the design requirement of multiple PADs corresponding to a specific test port. The specific correspondence is shown in Table 1. The check mark indicates that there is a connection relationship between the PAD and the CODEC test port. The test channel construction is completed by CODEC B21. The correspondence in the table is consistent with that in the topology. It can be seen that CODEC B21 completes the test control and monitoring by input PAD1 and PAD5 and output PAD9 and PAD11. The purpose is to ensure the test and analysis of the complete logic of the chip when a manufacturing process defect occurs in a certain PAD. However, the specific data input and output of the test port should be configured through which channels are controlled by IJTAG PINMUXTDR and combinational logic. PINMUXTDR corresponds to a specific chip PAD, and a high level indicates that the PAD is functionally correct and performs well.

[0125] When there are many PADs and the reuse requirement is not high, the actual design can have a one-to-one priority relationship between PADs and CODEC test ports. For example, in Table 1, input PAD (in): PAD1 data is sent to CODEC C1, PAD2 data is sent to CODEC C1, and so on, and they are mutually exclusive. However, if the above conditions are not met, the priority relationship between PADs and CODEC ports will be weakened, and the actual channel configuration will be affected. As shown in the table below, output PAD (out): PAD7 data is sent to CODEC B11, PAD9 data is sent to CODEC B11 and CODEC B21, which is not a one-to-one correspondence (specific application example one mainly shows two correspondence relationships, so the input and output are not symmetrical, and the improvement of reuse is reflected in specific application example two).

[0126] Further explanation using the CODEC B21 test port reveals that when PAD9 has a process defect, the value of CTRL OUTPUT PADTDR is 1101 (meaning PAD7, PAD8, and PAD10 function normally; PAD9 malfunctions), and the select terminal of the corresponding PAD's pre-amplifier secondary MUX is 0. This causes CODEC B21's data monitoring to be implemented through PAD11 (PAD9 is replaced by PAD11). When PAD7 has a process defect, the value of CTRL OUTPUT PAD TDR is 0111 (meaning PAD7 malfunctions, PAD8, PAD9, and PAD10 function normally). In this case, CODEC B11's data will occupy PAD9, and CODEC B21's data monitoring will still be implemented through PAD11 (the chip passivation output aperture of CODEC B11 is replaced by the spare PAD9 instead of the initial PAD7; since PAD7 is occupied by CODEC B11, CODEC B21 uses its spare PAD11 as the chip passivation output aperture).

[0127] The fundamental reason for simplifying the control logic and test channel selection is that the mapping relationship between ports and PADs in the above structure is one-to-two (the chip passivation aperture PAD to CODEC test port is one-to-many). This leads to an either-or decision for the test channel selection. However, as the chip passivation aperture reuse rate is further improved, the complexity of the control logic will inevitably increase exponentially. It should still be noted that there are far more CODEC test ports than PADs, so the number of PADs corresponding to one port will not be too high, and it will also be subject to other design limitations (see Specific Application Example 2).

[0128] Specific application example two:

[0129] See Figure 5The second specific application example uses a single-mode, output port channel configuration structure to illustrate the PAD multiplexing problem (input and output can be implemented symmetrically). To simplify signal transmission in the structure diagram, all lines only represent data interaction or data transmission and do not represent actual connection relationships.

[0130] The correspondence between PADs and CODEC test ports is shown in Table 2. In the actual testing process, the DFT design completes the testing work "as a whole" for the target logic. At least four PADs need to be in a state of correct function and good performance to complete the monitoring of test data of four CODEC ports. At this time, there is a surplus of two PADs. For any single port, there can be a limit of 3 PADs for reuse. If the reuse degree is further increased to 4 (i.e., it is acceptable for 3 PADs to have process defects at the same time), then while increasing the logic cost, no testing benefits or testing requirements will be met (a complete set of test PADs cannot be provided). Therefore, when using the extreme PAD reuse threshold, in order to ensure the rationality of PAD fan-in and fan-out, the one-to-one correspondence and mutual exclusion control logic structure between PADs and CODEC ports is no longer used.

[0131] Table 2

[0132] Compared to Specific Application Example 1, the priority of test channel selection in Specific Application Example 2 is not only subject to the priority relationship between PAD and test port, but also, when two PADs have performance defects at the same time, there will inevitably be a test port that cannot be selected and can only complete data transmission through the remaining PAD. This function is implemented in the above structure through TDR configuration and the combinational logic before the XOR tree (a hierarchical tree structure composed of XOR gates).

[0133] For example, when PAD3 and PAD5 have process defects, the value of CTRL OUTPUT PAD TDR is 110101, and the XOR tree outputs 0010 from left to right (this value is determined by the hierarchical tree structure and cannot be read in the diagram). In this case, CODEC 3 will skip the condition "CODEC2 data prioritizes PAD2" and force CODEC 2 data to PAD4, and CODEC 4 data to PAD6. The data in CODEC 1 remains unaffected and is still tested by PAD1. The configuration of the above test channels is all completed by the control logic, and when any one or two PADs have process defects, the control logic can provide a set of ordered PADs to complete the test.

[0134] Extending this reusability to Specific Application Instance 1 (the maximum number of test ports in a single mode in Specific Application Instance 1 is 4, consistent with Specific Application Instance 2, so this extension is practically feasible), the PINMUX interconnect structure can then complete the testing of 12 PADs corresponding to 90 CODEC ports.

[0135] As the number of test modes increases, the number of PADs will only be limited by the number of test ports in a single mode and the degree of multiplexing. In actual chip design, it is possible to control and monitor 1000+ CODEC test ports with 50+ PADs.

[0136] Figure 6 This is a block diagram illustrating an electronic device for implementing the above-described breakpoint resume method, according to an exemplary embodiment. For example, the electronic device may be an AI server, a training and promotion integrated machine, etc.

[0137] Reference Figure 6 The electronic device may include one or more of the following components: an AI-accelerated computing module, a CPU module, a power supply module, a hard drive module, and a fan module. Each module works in conjunction with the bus system through a standardized hardware interface, as detailed in the following architecture:

[0138] The AI-accelerated computing module comprises multiple AI accelerator cards deployed in parallel. Each AI accelerator card integrates at least one AI accelerator chip (such as an RPU chip, GPU chip, or CGRA chip). Data communication between the AI ​​accelerator cards is achieved through a high-speed card-to-card (C2C) interconnect structure, supporting low-latency, high-bandwidth horizontal scaling. The AI ​​accelerator chip is dedicated to performing AI computing tasks such as high-density matrix operations, neural network model training, and / or inference, providing the main computing power support.

[0139] The CPU module includes at least one CPU board, which houses a central processing unit (CPU) chip and associated CPU memory (such as DDR4 / DDR5, RAM). The CPU chip serves as the system control center, responsible for task scheduling, resource allocation, I / O management, and coordinating the parallel computing of the AI ​​acceleration computing module, while also handling non-accelerated general-purpose computing tasks.

[0140] The power module is equipped with redundant power supply units to provide stable power distribution and management for the AI ​​acceleration computing module, CPU module and other modules.

[0141] The hard drive module integrates a high-speed solid-state drive (SSD) and / or a large-capacity hard disk drive (HDD), connected to the system bus via a backplane. The hard drive stores the operating system, AI training datasets, model parameters, and computation results, providing high-throughput data read / write channels and supporting data preprocessing and persistence.

[0142] The fan module uses a multi-zone independent speed-controlled fan array, which is configured in key heat source areas (such as AI accelerator cards and CPU heat dissipation areas) to achieve system heat dissipation through forced air cooling and ensure the stable operation of high-efficiency computing components.

[0143] The CPU module is connected to the AI ​​acceleration computing module via the PCIe bus to enable task distribution, result collection, and memory coordination.

[0144] The CPU module manages the data access of the hard drive module through SATA / SAS / NVMe interfaces.

[0145] The power module provides tiered power to all functional modules through the power distribution backplane.

[0146] The fan module adjusts the fan speed based on temperature monitoring signals from the CPU board and AI accelerator card.

[0147] The electronic device provided in this application embodiment includes the above-described data transmission system, and therefore can achieve the same technical effects as the data transmission system, which will not be described in detail here.

[0148] This application is described with reference to flowchart illustrations and / or block diagrams of methods and apparatus (systems) according to embodiments of this application.

[0149] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0150] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A compression testing system based on pin multiplexing, characterized in that, include: Multiple chip passivation apertures, segment insertion byte units, test data registers, and compression / decompression units, among which: The compression / decompression unit is configured with an initial chip passivation aperture and at least one spare chip passivation aperture. The segment insertion byte unit and the test data register are disposed between the chip passivation aperture and the compression / decompression unit, and are used to connect the compression / decompression unit to a configured backup chip passivation aperture in the event that the initial chip passivation aperture corresponding to the compression / decompression unit fails; or Configure the compression / decompression unit to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation aperture.

2. The compression testing system according to claim 1, characterized in that, The chip passivation openings include: chip passivation input openings and chip passivation output openings; The test data register includes: a test data input register and a test data output register; The test data input register is used, in the event of a failure of the chip passivation input aperture, to cooperate with the segment insertion byte unit to configure the compression / decompression unit initially configured with the failed chip passivation input aperture to its corresponding backup chip passivation input aperture; or Configure the compression / decompression unit of the faulty chip passivation input aperture to the backup chip passivation input aperture or the initial chip passivation input aperture of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation input aperture. The test data output register is used, in the event of a failure of the passivation output aperture of the chip, in conjunction with the segment insertion byte unit, to configure the compression / decompression unit initially configured with the failed passivation output aperture of the chip to its corresponding backup passivation output aperture; or Configure the compression / decompression unit of the faulty chip passivation output opening to the backup chip passivation output opening or the initial chip passivation output opening of the pre-set compression / decompression unit, and configure the pre-set compression / decompression unit to its available chip passivation output opening.

3. The compression testing system according to claim 1, characterized in that, The configuration relationship between the compression / decompression unit and the spare chip passivation aperture is determined by the number of logic under test and the number of compression / decompression units corresponding to the logic under test.

4. The compression testing system according to claim 2, characterized in that, The test data register also includes a logic register under test, used to switch and split multiple logics under test in conjunction with the segment insertion byte unit.

5. The compression testing system according to any one of claims 2 or 4, characterized in that, The test data output register is also used to output the level value of the chip passivation output opening; wherein, the level value is used to characterize whether the chip passivation output opening has failed.

6. The compression testing system according to claim 5, characterized in that, Also includes: Multiple AND-OR gate logic circuits are connected to the test data register and correspond one-to-one with multiple compression / decompression units, used to switch the configuration relationship between the compression / decompression units and the chip passivation openings.

7. The compression testing system according to any one of claims 1 to 4 and 6, characterized in that, Also includes: The test access port controller is used to cooperate with the segment insertion byte unit and the test data register to multiplex the same type of compression and decompression units in multiple modules for logical testing, and to call different types of compression and decompression units in multiple modules for logical testing.

8. A compression test method based on pin multiplexing, characterized in that, The compression test system based on pin multiplexing as described in any one of claims 1 to 7 includes: The segment insertion byte unit and the test data register are located between the chip passivation aperture and the compression / decompression unit. In the event of a failure in the initial chip passivation aperture corresponding to the compression / decompression unit, the compression / decompression unit is connected to its configured backup chip passivation aperture; or The compression / decompression unit is configured to a pre-set spare chip passivation aperture or an initial chip passivation aperture of the compression / decompression unit, and the pre-set compression / decompression unit is configured to its available chip passivation aperture; wherein the compression / decompression unit is pre-configured with an initial chip passivation aperture and at least one spare chip passivation aperture.

9. A circuit board, characterized in that, The compression test system based on pin multiplexing as described in any one of claims 1 to 7.

10. An electronic device, characterized in that, Includes the board as described in claim 9.

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