Automatic power control circuit

Abstract

The invention provides an automatic power control circuit of an optical communication chip. The automatic power control circuit is coupled to a digital control unit and a DC-DC converter. The automatic power control circuit includes: a digital-to-analog converter coupled to a digital control unit, the digital-to-analog converter receiving a digital code generated by the digital control unit to generate a digital-to-analog converter output voltage; an output buffer circuit coupled to the digital analog converter and the DC-DC converter, the output buffer circuit providing an internal node voltage; and the analog-to-digital converter is coupled to the output buffer circuit and the digital control unit, and the analog-to-digital converter controls a supply voltage output by the DC-DC converter through the digital-to-analog converter, so that a voltage difference between the supply voltage and the internal node voltage is maintained within a normal working range interval.

Description

Technical Field

[0001] This application relates to an automatic power control circuit, and more particularly to an automatic power control circuit applied to optical communication chips. Background Technology

[0002] Optical communication chips play a vital role in modern communications. Here are some of their key, exemplary applications:

[0003] High-efficiency data transmission: Optical communication chips utilize optical signals for data transmission, offering higher bandwidth and speed compared to traditional electrical signals. This enables optical communication chips to transmit large amounts of data in a very short time, making them suitable for high-speed internet, data centers, and large-scale computing applications.

[0004] Low latency and high stability: Optical signal transmission has low latency and is unaffected by electromagnetic interference, providing stable and reliable data communication. This is especially important for applications requiring high precision and real-time performance, such as financial transactions and telemedicine.

[0005] Reduced power consumption: Optical communication chips consume relatively little energy because optical signals have high transmission efficiency and generate little heat. This helps save energy and reduce operating costs in large facilities such as data centers that need to operate for extended periods.

[0006] Long-distance communication: Fiber optic communication technology allows for data transmission over extremely long distances with minimal signal attenuation. Optical communication chips are widely used in transcontinental and transnational communication networks to achieve global connectivity.

[0007] Telecommunications infrastructure: Modern telecommunications networks rely heavily on fiber optic communication. Optical communication chips play a core role in base stations, switches, and routers, supporting high-speed internet, 5G networks, and other telecommunications services.

[0008] Data Center Interconnection: In large data centers, high-speed connections are required between various servers and storage devices. Optical communication chips provide high-bandwidth, low-latency connections, improving the operational efficiency of data centers.

[0009] Quantum communication: Optical communication chips are also one of the core components of quantum communication technology. Quantum communication utilizes the quantum states of photons for transmission, achieving ultra-high security communication.

[0010] Therefore, effectively reducing the energy consumption of optical communication chips is one of the industry's key areas of focus. Summary of the Invention

[0011] To address the aforementioned technical problems, the purpose of this application is to provide an automatic power control circuit for use in optical communication chip architecture.

[0012] The objective of this application and the technical problem it solves are achieved through the following technical solution. From one perspective, this application proposes an automatic power control circuit for an optical communication chip, coupled to a digital control unit and a DC-DC converter. The automatic power control circuit includes: a digital-to-analog converter coupled to the digital control unit, the digital-to-analog converter receiving a digital code generated by the digital control unit to generate a digital-to-analog converter output voltage; an output buffer circuit coupled to the digital-to-analog converter and the DC-DC converter, the output buffer circuit providing an internal node voltage; and an analog-to-digital converter coupled to the output buffer circuit and the digital control unit, the analog-to-digital converter controlling a supply voltage output by the DC-DC converter, such that a voltage difference between the supply voltage and the internal node voltage is maintained within a normal operating range.

[0013] To provide a better understanding of the above and other aspects of this application, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0014] Figure 1A and Figure 1B A circuit diagram of an automatic power control circuit according to an embodiment of this application is shown.

[0015] Figure 2 A circuit diagram of an automatic power control circuit according to another embodiment of this application is shown.

[0016] Figure 3A A circuit diagram of an automatic power control circuit according to another embodiment of this application is shown.

[0017] Figure 3B A circuit diagram of an automatic power control circuit according to another embodiment of this application is shown.

[0018] Figure 4 A circuit diagram of an automatic power control circuit according to another embodiment of this application is shown.

[0019] Figure 5 A circuit diagram of an automatic power control circuit according to another embodiment of this application is shown. Detailed Implementation

[0020] The foregoing descriptions and other technical contents, features, and effects of this application will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. The following descriptions of the embodiments are with reference to the accompanying drawings and are used to illustrate specific embodiments in which this application can be implemented. The foregoing descriptions and other technical contents, features, and effects of this application will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings.

[0021] The accompanying drawings and descriptions are intended to be illustrative in nature, not restrictive. In the drawings, structurally similar units are denoted by the same reference numerals. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrarily illustrated, but this application is not limited thereto. Where possible, those skilled in the art may selectively implement some or all of the technical features of any embodiment, or selectively combine some or all of the technical features of these embodiments.

[0022] To further illustrate the technical means and effects adopted by this application to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, describes the specific implementation, structure, features, and effects of an automatic power control circuit for an optical communication chip proposed in this application.

[0023] Please refer to Figure 1A and Figure 1B This diagram illustrates an automatic power control circuit 50A according to an embodiment of the present application. According to an embodiment of the present application, the automatic power control circuit 50A can be applied, for example, but not limited to, in an optical communication chip. A digital control unit 10, a DC-DC converter 20, and a load 40 are coupled to the automatic power control circuit 50A. The optical communication chip (not shown) includes: a digital control unit 10, a DC-DC converter 20, a load 40, and the automatic power control circuit 50A. The automatic power control circuit 50A includes: a voltage mode digital analog converter (VDAC) 100A and an analog digital converter (ADC) 120, wherein the analog digital converter 120 is a selective component. The voltage mode digital analog converter (VDAC) 100A includes: a digital analog converter (DAC) 30 and an output buffer circuit 105A.

[0024] In one embodiment, the digital control unit 10 is coupled to the DC-DC converter 20. The digital control unit 10 is configured according to the voltage-mode digital-to-analog converter 100A (e.g., Figure 1A (as shown) or 100B (as shown) Figure 1B The internal node voltage VOUT (as shown) generates a digital code D, which is sent to the digital-to-analog converter 30 to control the output voltage VD of the digital-to-analog converter 30. That is, at... Figure 1A and Figure 1B In this context, the internal node voltage VOUT of the voltage-mode digital-to-analog converter 100A or 100B is detected to control the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30.

[0025] In one embodiment, the DC-DC converter 20 generates a supply voltage VSUPPLY and a supply current i to a voltage-mode digital-to-analog converter 100A or 100B.

[0026] In one embodiment, the digital-to-analog converter 30 receives digital code D generated by the digital control unit 10 to generate the digital-to-analog converter output voltage VD.

[0027] In one embodiment, the load 40 includes, for example, but not limited to, a load resistor RLOAD. One end of the load resistor RLOAD is coupled to an internal node voltage VOUT. The load resistor RLOAD may be, for example, but not limited to, a silicon photonic circuit to control wavelength or phase.

[0028] In one embodiment, the output buffer circuit 105A includes: a transistor MP, an error amplifier EA, and a voltage divider circuit 110.

[0029] In one embodiment, the transistor MP includes: a first terminal (e.g., but not limited to, a source) receiving a supply voltage VSUPPLY generated by the DC-DC converter 20; a second terminal (e.g., but not limited to, a drain) coupled to the voltage divider circuit 110 and the load 40; and a control terminal (e.g., but not limited to, a gate) receiving the output signal of the error amplifier EA.

[0030] In one embodiment, the error amplifier EA includes: a first terminal (e.g., a positive input terminal) receiving a voltage divider voltage VDIV from the voltage divider circuit 110; a second terminal (e.g., a negative input terminal) receiving a digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30; and an output terminal coupled to the control terminal of the transistor MP.

[0031] In one embodiment, voltage divider circuit 110 divides the internal node voltage VOUT to generate a divided voltage VDIV, which is fed back to the first terminal of error amplifier EA. Voltage divider circuit 110 includes resistors R1 and R2. Resistor R1 includes: a first terminal coupled to a second terminal of resistor R2; and a second terminal coupled to ground. Resistor R2 includes: a first terminal coupled to a second terminal of transistor MP; and a second terminal coupled to the first terminal of resistor R1.

[0032] In one embodiment, the analog-to-digital converter 120 converts the internal node voltage VOUT of the output buffer circuit 105A into a digital signal and transmits the digital signal to the digital control unit 10, so that the digital control unit 10 generates a digital code D for the digital-to-analog converter 30 based on the digital signal.

[0033] In one embodiment, unlike the output buffer circuit 105A (e.g. Figure 1A As shown), the output buffer circuit 105B (as shown) Figure 1B The transistor shown is replaced with an N-type transistor MN. The N-type transistor MN includes: a first terminal (e.g., but not limited to, drain) receiving the supply voltage VSUPPLY generated by the DC-DC converter 20; a second terminal (e.g., but not limited to, source) coupled to the voltage divider circuit 110 and the load 40; and a control terminal (e.g., but not limited to, gate) receiving the output signal of the error amplifier EA.

[0034] like Figure 1B As shown, in the output buffer circuit 105B, the error amplifier EA includes: a first terminal (e.g., a positive input terminal) receiving the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30; a second terminal (e.g., a negative input terminal) receiving the divided voltage VDIV from the voltage divider circuit 110; and an output terminal coupled to the control terminal of the transistor MN. The transistor MN, the error amplifier EA, and the voltage divider circuit 110 form the output buffer circuit 105B.

[0035] In principle, the automatic power control circuit is 50A (e.g.) Figure 1A (as shown) and 50B (as shown) Figure 1A The operating details of the automatic power control circuit 50A are the same or similar to those shown below; therefore, the operating details of the automatic power control circuit 50A will be described below. Those skilled in the art will be able to understand the operating details of the automatic power control circuit 50B from this description.

[0036] In one embodiment, this application uses feedback control to reduce the power consumption of transistor MP (or MN). Details will now be described.

[0037] Please refer to section [number]. Figure 1A or Figure 1BThe power consumption P of transistor MP is as follows: P = (VSUPPLY - VOUT) * I = VDS * i, where i is the supply current flowing through transistor MP and load 40, and VDS represents the drain-source voltage difference of transistor MP.

[0038] Generally, the internal node voltage VOUT can be obtained from the output voltage VD of the digital-to-analog converter. When the voltages across the error amplifier EA are equal, it can be deduced that: VOUT = (1 + R1 / R2) * VD. Therefore, the value of VOUT can be obtained from the above formula. However, in one embodiment of this application, for more precise control, the internal node voltage VOUT can be detected by the ADC 120. That is, the internal node voltage VOUT can be converted into a digital signal by the ADC 120 and the digital signal can be transmitted to the digital control unit 10.

[0039] In one embodiment, the digital-to-analog converter output voltage VD is related to the digital code D generated by the digital control unit 10. For example, a 4-bit digital code D is used as an example, but this application is not limited to this. When the digital code D is 0000, the digital-to-analog converter output voltage VD is a first voltage value; when the digital code D is 0001, the digital-to-analog converter output voltage VD is a second voltage value, and so on. Furthermore, through the feedback control of the error amplifier EA, the digital-to-analog converter output voltage VD is very close to the voltage divider voltage VDIV. Moreover, when the resistance of resistor R2 is very small, the internal node voltage VOUT is also very close to the voltage divider voltage VDIV.

[0040] Therefore, through the digital signal from ADC 120, the digital control unit 10 can control the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30, such that VDS = (VSUPPLY - VOUT) ≥ VDS_MIN, where VDS_MIN represents the minimum value of the drain-source voltage difference of transistor MP. In other words, under the premise that VDS = (VSUPPLY - VOUT) ≥ VDS_MIN holds, this application can reduce the power consumption of transistor MP by reducing the value of (VSUPPLY - VOUT), thereby reducing the heat dissipation and temperature of transistor MP.

[0041] In other words, in one embodiment of this application, the analog-to-digital converter 120 controls the voltage difference between the supply voltage VSUPPLY and the internal node voltage VOUT to maintain or lower the voltage difference between the supply voltage and the internal node voltage so that the transistor MP is within a normal operating range.

[0042] Please refer to Figure 2 The diagram illustrates a circuit diagram of an automatic power control circuit according to another embodiment of this application. Figure 2As shown, another embodiment of the automatic power control circuit 200 of this application includes: a plurality of voltage-mode digital-to-analog converters 205, a multiplexer 220, and an ADC 230. Each voltage-mode digital-to-analog converter 205 includes a digital-to-analog converter 30 and an output buffer circuit 210.

[0043] In one embodiment, each output buffer circuit 210 includes: a transistor MP, an error amplifier EA, and a voltage divider circuit 110. That is, in Figure 2 In the middle, each output buffer circuit 210 is composed of Figure 1A The output buffer circuit 105A is implemented. However, in other embodiments of this application, each output buffer circuit 210 may also be implemented by... Figure 1B The output buffer circuit 105B is implemented, which is also within the spirit of this application.

[0044] In one embodiment, the multiplexer 220 is coupled to the output buffer circuit 210 of each voltage-mode digital-to-analog converter 205.

[0045] In one embodiment, the ADC 230 is coupled to the multiplexer 220. That is, these voltage-mode digital-to-analog converters 205 share the ADC 230.

[0046] The explanation is as follows Figure 2 Operational details. Figure 2 In this process, the multiplexer 220 uses time-division multiplexing technology to select one of the internal node voltages VOUT1-VOUTn of these output buffer circuits 210 and transmit it to the ADC 230 at different time points. The ADC 230 converts one of the internal node voltages VOUT1-VOUTn into a digital signal and transmits the digital signal to the digital control unit 10, so that the digital control unit 10 generates one of the digital codes D1-Dn according to the digital signal to control these digital-to-analog converters 30, and in turn controls the digital-to-analog converter output voltages VD1-VDn generated by these digital-to-analog converters 30.

[0047] That is, at Figure 2 In this process, the voltages VOUT1-VOUTn of each internal node of the automatic power control circuit 200 are detected to control the output voltages VD1-VDn of the digital-to-analog converter generated by the digital-to-analog converter 30.

[0048] In one embodiment, to reduce the power consumption of transistor MP and VDAC 30, the voltage VSUPPLY is controlled under the premise that VDS=(VSUPPLY-VOUT_MAX)≧VDS_MIN, where VOUT_MAX represents the maximum value of the internal node voltages VOUT1-VOUTn.

[0049] Please refer to Figure 3A The diagram illustrates a circuit diagram of an automatic power control circuit according to another embodiment of this application. Figure 3A As shown, another embodiment of the automatic power control circuit 50C of this application includes: VDAC 300A, current mirror 320, and ADC 340. VDAC 300A includes: DAC 30 and output buffer circuit 310.

[0050] At Figure 3A In the middle, the output buffer circuit 310 is composed of Figure 1A The output buffer circuit 310 is implemented by the output buffer circuit 105A. However, in other embodiments of this application, the output buffer circuit 310 may also be implemented by... Figure 1B The output buffer circuit 105B is implemented, which is also within the spirit of this application.

[0051] In one embodiment, a current mirror 320 is used to mirror the internal transistor current of the output buffer circuit 310. The current mirror 320 includes transistors M2 and M3, and a sensing resistor RDET. Transistor M2 includes a first terminal (e.g., source) coupled to the DC-DC converter 20 to receive the supply voltage VSUPPLY; a second terminal (e.g., drain) coupled to transistor M3; and a control terminal receiving the output signal of the error amplifier EA. Transistor M3 includes a first terminal (e.g., source) coupled to the second terminal of transistor M2; a second terminal (e.g., drain) coupled to the sensing resistor RDET and the ADC 340; and a control terminal coupled to transistor M1. The sensing resistor RDET includes a first terminal coupled to transistor M3 and the ADC 340, and a second terminal coupled to ground.

[0052] In one embodiment, the ADC 340 converts the detected voltage of the sensing resistor RDET into a digital signal, which is then sent to the digital control unit 10. The digital control unit 10 generates a digital code D based on the digital signal from the ADC 340 and sends it to the digital-to-analog converter 30 to control the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30. That is, in... Figure 3A In this process, the transistor current (current flowing through transistor M1, M2, or M3) of the automatic power control circuit 50C is detected to control the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30.

[0053] In one embodiment, it is assumed that the size ratio of transistor M1 to transistor M2 is k:1. Therefore, the current flowing through the current mirror 320 is i / k. Thus, the detection voltage V of the detection resistor RDET can be expressed as: V = RDET * i / k. Therefore, it can be deduced that the current i can be expressed as: i = V * k / RDET.

[0054] Similarly, the power consumption P of transistor M1 is P = (VSUPPLY - VOUT) * i. Therefore, when the digital control unit 10 determines that P is greater than the upper limit of the power allowance, the digital control unit 10 controls the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30 to decrease, thereby reducing the power P, until P is less than the upper limit of the power allowance. Of course, the above control is still subject to the premise that (VSUPPLY - VOUT) ≥ VDS_MIN.

[0055] Please refer to Figure 3B The diagram illustrates a circuit diagram of an automatic power control circuit according to another embodiment of this application. Figure 3B As shown, the automatic power control circuit 50D of another embodiment of this application includes: VDAC 300A, current mirror 320, ADC 340 and error amplifier 330.

[0056] In one embodiment, at Figure 3B In the middle, the output buffer circuit 310 is composed of Figure 1A The output buffer circuit 310 is implemented by the output buffer circuit 105A. However, in other embodiments of this invention, the output buffer circuit 310 may also be implemented by... Figure 1B The output buffer circuit 105B is implemented, which is also within the spirit of this application.

[0057] In one embodiment, a current mirror 320 is used to mirror the internal transistor current of the output buffer circuit 310. The current mirror 320 includes transistors M2 and M3, and a sensing resistor RDET. Transistor M2 includes a first terminal (e.g., source) coupled to the DC-DC converter 20 to receive a supply voltage VSUPPLY; a second terminal (e.g., drain) coupled to transistor M3; and a control terminal receiving the output signal of the error amplifier EA. Transistor M3 includes a first terminal (e.g., source) coupled to a second terminal of transistor M2; a second terminal (e.g., drain) coupled to the sensing resistor RDET and the ADC 340; and a control terminal receiving the output signal of the error amplifier 330. The sensing resistor RDET includes a first terminal coupled to transistor M3 and the ADC 340, and a second terminal coupled to ground.

[0058] In one embodiment, the error amplifier 330 includes: a first terminal (e.g., a positive input terminal) coupled to an internal node voltage VOUT; a second terminal (e.g., a negative input terminal) coupled to the coupling point of transistors M2 and M3 of the current mirror 330; and an output terminal coupled to a control terminal of transistor M3 of the current mirror 330. The error amplifier 330 is used to compare the internal node voltage VOUT with a voltage at the coupling point of transistors M2 and M3 of the current mirror 330.

[0059] In one embodiment, the ADC 340 converts the detected voltage of the sensing resistor RDET into a digital signal, which is then sent to the digital control unit 10. The digital control unit 10 generates a digital code D based on the digital signal from the ADC 340 and sends it to the digital-to-analog converter 30 to control the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30. That is, in... Figure 3B In this process, the transistor current (current flowing through transistor M1, M2, or M3) of the automatic power control circuit 50D is detected to control the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30.

[0060] In one embodiment, it is assumed that the size ratio of transistor M1 to transistor M2 is k:1. Therefore, the current flowing through the current mirror 320 is i / k. Thus, the detection voltage V of the detection resistor RDET can be expressed as: V = RDET * i / k. Therefore, it can be deduced that the current i can be expressed as: i = V * k / RDET.

[0061] Similarly, the power consumption P of transistor M1 is P = (VSUPPLY - VOUT) * i. Therefore, when the digital control unit 10 determines that P is greater than the upper limit of the power allowance, the digital control unit 10 controls the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30 to decrease, thereby reducing the power P, until P is less than the upper limit of the power allowance. Of course, the above control is still subject to the premise that (VSUPPLY - VOUT) ≥ VDS_MIN.

[0062] Please refer to Figure 4 The diagram illustrates a circuit diagram of an automatic power control circuit according to another embodiment of this application. Figure 4 As shown, another embodiment of the automatic power control circuit 50E of this application includes: VDAC 400 and ADC 420. VDAC 400 includes: DAC 30 and output buffer circuit 410. Output buffer circuit 410 includes: error amplifier EA, transistor MP, resistors R1 and R2 and detection resistor RDET.

[0063] In one embodiment, the sensing resistor RDET includes: a first terminal coupled to the transistor MP, and a second terminal coupled to the load 40. The sensing resistor RDET is selectively coupled to the ADC 420. Specifically, when controlling the power of VDAC and the transistor MP, the sensing resistor RDET is coupled to the ADC 420; and when not controlling the power of VDAC and the transistor MP, the sensing resistor RDET is disconnected from the ADC 420.

[0064] In one embodiment, the ADC 420 converts the detected current of the sensing resistor RDET into a digital signal, which is then sent to the digital control unit 10. The digital control unit 10 generates a digital code D based on the digital signal from the ADC 420 and sends it to the digital-to-analog converter 30 to control the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30. That is, in... Figure 4 In this process, the transistor current (current flowing through transistor MP) of the automatic power control circuit 50E is detected to control the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30.

[0065] In one embodiment, the detection current i of the detection resistor RDET can be expressed as: i = (V1 - V2) / RDET, where V1 and V2 are the voltages across the detection resistor RDET detected by the ADC 420. The detection current i of the detection resistor RDET is substantially very close to the current flowing through the transistor MP.

[0066] Similarly, the power consumption P of transistor M1 is P = (VSUPPLY - VOUT) * i. Therefore, when the digital control unit 10 determines that P is greater than the upper limit of the power allowance, the digital-to-analog converter output voltage VD generated by the digital-to-analog converter 30 of the digital control unit 10 is reduced to reduce the power P until P is less than the upper limit of the power allowance. Of course, the above control is still subject to the premise that (VSUPPLY - VOUT) ≥ VDS_MIN.

[0067] Although the above embodiments are illustrated using a VDAC as an example, it is understood that this application can also be used for other types of DACs, such as current-mode DACs (IDACs), all of which fall within the spirit and scope of this application. That is, the power consumption of an IDAC can be controlled using the methods described in the above embodiments of this application.

[0068] Please refer to Figure 5 The diagram illustrates a circuit diagram of an automatic power control circuit according to another embodiment of this application. Figure 5 As shown, the automatic power control circuit 50F of one embodiment of this application can be applied, for example, but not limited to, optical communication chips. The automatic power control circuit 50F includes a current-mode digital analog-to-analog converter (IDAC) 510 and an ADC 120 (selective component). The current-mode digital-to-analog converter 510 includes a digital-to-analog converter (DAC) 520 and an output buffer circuit 530.

[0069] In one embodiment, the output buffer circuit 530 includes: transistors M4-M5, error amplifier EA, and resistor R4.

[0070] In one embodiment, transistor M4 includes: a first terminal (e.g., but not limited to, a source) receiving a supply voltage VSUPPLY generated by DC-DC converter 20; a second terminal (e.g., but not limited to, a drain) coupled to resistor R4; and a control terminal (e.g., but not limited to, a gate) receiving an output signal from error amplifier EA.

[0071] In one embodiment, transistor M5 includes: a first terminal (e.g., but not limited to, a source) receiving a supply voltage VSUPPLY generated by DC-DC converter 20; a second terminal (e.g., but not limited to, a drain) coupled to ADC 120 and load 40; and a control terminal (e.g., but not limited to, a gate) receiving an output signal from error amplifier EA. That is, transistors M4 and M5 constitute a current mirror.

[0072] In one embodiment, the error amplifier EA includes: a first terminal (e.g., a positive input terminal) coupled to a resistor R4; a second terminal (e.g., a negative input terminal) receiving a voltage VD generated by a digital-to-analog converter 520; and an output terminal coupled to the control terminals of transistors M4 and M5.

[0073] In one embodiment, resistor R4 is coupled between transistor M4 and ground to convert a current (i1) of the fourth transistor M4 into an internal node voltage VOUT.

[0074] In one embodiment, the ratio of transistors M4 to M5 is, for example, m:n. Then, the current i1 flowing through transistor M4 and the current i2 flowing through transistor M5 are: i1:i2 = m:n, where i1 = VD / R4. The analog-to-digital converter 120 converts the current i2 flowing through transistor M5 into a digital signal and transmits the digital signal to the digital control unit 10, so that the digital control unit 10 generates a digital code D based on the digital signal and sends it to the digital-to-analog converter 520.

[0075] The operational details of the automatic power control circuit 50F are similar to those of the automatic power control circuit 50A, so the details are omitted here.

[0076] The above disclosure provides different features for implementing some embodiments or examples of this disclosure. Specific examples of components and configurations described above (e.g., mentioned values ​​or names) are used to simplify / illustrate some embodiments of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. Furthermore, reference numerals and / or letters may be repeated in various instances of some embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Terms such as "in one embodiment" are used repeatedly. This term does not usually refer to the same embodiment; however, it may refer to the same embodiment. Words such as "comprising," "having," and "including" are synonyms unless the context otherwise indicates otherwise.

[0077] The above description is merely a specific embodiment of this application, intended to facilitate understanding of the content of this application by those skilled in the art, and is not intended to limit this application in any way. Although this application has been disclosed above with specific embodiments, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An automatic power control circuit for an optical communication chip, coupled to a digital control unit and a DC-DC converter, characterized in that, The automatic power control circuit includes: A digital-to-analog converter is coupled to the digital control unit, the digital-to-analog converter receiving a digital code generated by the digital control unit to generate a digital-to-analog converter output voltage; An output buffer circuit, coupled to the digital-to-analog converter and the DC-DC converter, the output buffer circuit providing an internal node voltage; and; An analog-to-digital converter is coupled to the output buffer circuit and the digital control unit. The analog-to-digital converter controls a supply voltage output by the DC-DC converter through the digital-to-analog converter, so that a voltage difference between the supply voltage and the internal node voltage is maintained within a normal operating range.

2. The automatic power control circuit as claimed in claim 1, characterized in that the analog-to-digital converter adjusts the supply voltage so that the supply voltage decreases and approaches the internal node voltage, and the lower the voltage difference between the supply voltage and the internal node voltage, the lower the power consumption of the automatic power control circuit.

3. The automatic power control circuit as described in claim 1, wherein the analog-to-digital converter detects and converts the internal node voltage of the output buffer circuit into a digital signal, and the digital control unit generates the digital code based on the digital signal.

4. The automatic power control circuit as described in claim 1, wherein, The output buffer circuit includes: A first transistor includes: a first terminal receiving the supply voltage output by the DC-DC converter; a second terminal coupled to a load; and a control terminal; A first error amplifier includes: a first terminal; a second terminal receiving the output voltage of the digital-to-analog converter generated by the digital-to-analog converter; and an output terminal coupled to the control terminal of the first transistor; and A voltage divider circuit divides the internal node voltage to obtain a divided voltage, which is coupled to the first terminal of the first error amplifier.

5. The automatic power control circuit as described in claim 1, characterized in that, The output buffer circuit includes a plurality of output buffer circuits, and the automatic power control circuit further includes a multiplexer coupled between the analog-to-digital converter and the output buffer circuits. The multiplexer selects one of the plurality of internal node voltages of the output buffer circuits and transmits it to the analog-to-digital converter.

6. The automatic power control circuit as described in claim 1, further comprising: A current mirror, coupled to the output buffer circuit, is used to mirror an internal transistor current generated by the output buffer circuit.

7. The automatic power control circuit as described in claim 6, characterized in that, The current mirror includes: a second transistor and a third transistor, and a detection resistor. The second transistor includes: a first terminal coupled to the DC-DC converter to receive the supply voltage; a second terminal coupled to the third transistor; and a control terminal coupled to the output buffer circuit. The third transistor includes: a first terminal coupled to the second terminal of the second transistor; a second terminal coupled to the detection resistor and the analog-to-digital converter; and a control terminal coupled to the output buffer circuit. The detection resistor includes: a first terminal coupled to the third transistor and the analog-to-digital converter; and a second terminal coupled to ground. The analog-to-digital converter converts a detected voltage of the detection resistor into a digital signal, which is then sent to the digital control unit.

8. The automatic power control circuit as described in claim 1, further comprising: A current mirror, coupled to the output buffer circuit, is used to mirror an internal transistor current generated by the output buffer circuit. as well as A second error amplifier, coupled to the output buffer circuit and the current mirror, is used to compare the internal node voltage of the output buffer circuit with a coupling point voltage of the current mirror, wherein... The current mirror includes: a second transistor and a third transistor, and a detection resistor. The second transistor includes: a first terminal coupled to the DC-DC converter to receive the supply voltage; a second terminal coupled to the third transistor; and a control terminal coupled to the output buffer circuit. The third transistor includes: a first terminal coupled to the second terminal of the second transistor; a second terminal coupled to the sensing resistor and an analog-to-digital converter; and a control terminal for receiving an output signal from the second error amplifier. The detection resistor includes: a first terminal coupled to the third transistor and the analog-to-digital converter; and a second terminal coupled to ground; and The second error amplifier includes: a first terminal coupled to the internal node voltage; a second terminal coupled to a coupling point between the second transistor and the third transistor of the current mirror; and an output terminal coupled to the control terminal of the third transistor. The analog-to-digital converter converts a detected voltage of the detection resistor into a digital signal, which is then sent to the digital control unit.

9. The automatic power control circuit as described in claim 4, characterized in that, The output buffer circuit further includes: a detection resistor coupled between the first transistor and the voltage divider circuit. The detection resistor includes: a first terminal coupled to the first transistor, and a second terminal coupled to the load. The detection resistor can be selectively coupled to the analog-to-digital converter. When controlling the power consumption of the digital-to-analog converter and the first transistor, the detection resistor is coupled to the analog-to-digital converter. The analog-to-digital converter converts a detected current from the detection resistor into a digital signal, which is then sent to the digital control unit.

10. The automatic power control circuit as described in claim 9, characterized in that, The load is a silicon photonic circuit.

11. The automatic power control circuit as described in claim 1, characterized in that, The output buffer circuit includes: A fourth transistor includes: a first terminal receiving the supply voltage output by the DC-DC converter; a second terminal coupled to a fourth resistor; and a control terminal; A fifth transistor includes: a first terminal receiving the supply voltage output by the DC-DC converter; a second terminal coupled to the analog-to-digital converter; and a control terminal, wherein the fourth and fifth transistors form a current mirror; A first error amplifier includes: a first terminal; a second terminal receiving the output voltage of the digital-to-analog converter generated by the digital-to-analog converter; and an output terminal coupled to the control terminals of the fourth transistor and the fifth transistor; and A fourth resistor, coupled to the fourth transistor and the first error amplifier, converts a current in the fourth transistor into the internal node voltage.

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