Bandgap reference circuit

Abstract

The application discloses a band gap reference circuit, which comprises a starting module, a voltage sampling and feedback module, a band gap reference core module and a negative feedback loop thereof, and a UVLO module; the voltage sampling and feedback module and the UVLO module share part of the negative feedback loop; the starting module is used for providing a starting current and a bias voltage; the voltage sampling and feedback module is used for sampling an input voltage to obtain an input sampling voltage; and a feedback voltage is output to the band gap reference core module through the negative feedback loop; the band gap reference core module is used for establishing a normal working point under the triggering of the starting current, and generating a stable band gap reference voltage based on the control of the negative feedback loop; and the UVLO module is used for performing voltage detection on the input sampling voltage according to the band gap reference voltage, outputting a digital logic level signal according to a detection result, and realizing an under-voltage lockout function. The circuit has high integration and low power consumption.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more specifically to a bandgap reference circuit. Background Technology

[0002] A bandgap reference (BGR) is an indispensable and crucial module in integrated circuit design, generating a reference voltage that is virtually unaffected by temperature, supply voltage, and manufacturing process. With the advancement of integrated circuit technology, higher demands are being placed on the area, power consumption, and power supply rejection ratio (PSRR) characteristics of the bandgap reference.

[0003] Undervoltage lockout (UVLO) is a commonly incorporated feature in circuit design. It ensures that the system operates normally only when the power supply voltage is above the UVLO threshold, and is in a protected state when it falls below the minimum operating voltage. Designing a UVLO circuit with lower power consumption and smaller footprint is of significant engineering value. Traditional UVLOs often use a voltage divider of the input voltage as a comparison voltage. A comparator compares this voltage with a bandgap reference voltage to determine if the system is undervoltage. While this method effectively protects the circuit, the voltage divider branch and comparator increase area and power consumption. Even when the system is in a static state, the current in the voltage divider branch and comparator increases power consumption. Summary of the Invention

[0004] This invention provides a bandgap reference circuit to improve integration and PSRR performance while reducing power consumption.

[0005] This invention provides a bandgap reference circuit, the circuit comprising: a startup module, a voltage sampling and feedback module, a bandgap reference core module and its negative feedback loop, and a UVLO module; the voltage sampling and feedback module and the UVLO module reuse a portion of the negative feedback loop;

[0006] The startup module is used to provide a startup current for the bandgap reference core module, a first bias voltage for the UVLO module, and a second bias voltage for the voltage sampling and feedback module.

[0007] The voltage sampling and feedback module is used to sample the input voltage to obtain the input sample voltage; and outputs the feedback voltage to the bandgap reference core module through the negative feedback loop.

[0008] The bandgap reference core module is used to establish a normal operating point under the triggering of the starting current, and to generate a stable bandgap reference voltage based on the control of the negative feedback loop.

[0009] The UVLO module is used to perform voltage detection on the input sampling voltage based on the bandgap reference voltage, and output a digital logic level signal based on the detection result to realize the undervoltage lockout function.

[0010] Optionally, the bandgap reference core module includes: a first current mirror, a core unit, and a voltage transmission unit;

[0011] The first current mirror is used to mirror the starting current to obtain a first current and a second current;

[0012] The core unit includes a transistor pair consisting of a first transistor and a second transistor, and an emitter resistor network.

[0013] The first transistor and the second transistor generate negative temperature coefficient voltages in response to the first current and the second current, respectively, and form a voltage difference with a positive temperature coefficient based on different current densities;

[0014] The emitter resistor network is connected to the emitter paths of the first transistor and the second transistor, and is used to generate a positive temperature coefficient compensation voltage in the emitter path of the second transistor based on the positive temperature coefficient voltage difference.

[0015] The bases of the first transistor and the second transistor are connected and serve as the output terminal of the bandgap reference core module to output the bandgap reference voltage;

[0016] The voltage transmission unit is used to form the negative feedback loop with a portion of the circuitry of the voltage sampling and feedback module and the UVLO module.

[0017] Optionally, the first current mirror includes two identical MOS transistors with the same width-to-length ratio, forming a current mirror structure with a 1:1 ratio.

[0018] Optionally, the first transistor and the second transistor are bipolar transistors.

[0019] Optionally, the emitter resistor network includes: a first resistor and a second resistor; the first resistor is connected between the emitter of the first transistor and the first node; the second resistor is connected between the first node and ground; and the emitter of the second transistor is connected to the first node.

[0020] Optionally, the emitter resistor network includes a third resistor and a fourth resistor, wherein the third resistor is connected between the emitter of the first transistor and ground, and the fourth resistor is connected between the emitter of the second transistor and ground.

[0021] Optionally, the startup module includes:

[0022] A signal generation unit is used to generate the startup current, the first bias voltage, and the second bias voltage;

[0023] A current mirror unit is used to provide a current transmission path to transmit the startup current to the bandgap reference core module;

[0024] The control unit is used to disconnect the current transmission path when the bandgap reference voltage reaches a set value.

[0025] Optionally, the UVLO module includes a PMOS transistor and an NMOS transistor, wherein the source of the PMOS transistor is connected to the input sampling voltage, the gate of the PMOS transistor is connected to the source, the drain of the PMOS transistor is connected to the drain of the NMOS transistor, the source of the NMOS transistor is grounded, and the gate of the NMOS transistor is connected to the first bias voltage.

[0026] Optionally, the circuit further includes a UVLO hysteresis module for introducing positive feedback to provide an internal reference threshold for voltage detection of the UVLO module, the internal reference threshold including a rising turn-on threshold and a falling turn-off threshold.

[0027] Optionally, the UVLO hysteresis module includes: a bias current source and a hysteresis switch;

[0028] The bias current source is used to receive the first bias voltage and provide a constant current;

[0029] The hysteresis switch is used to switch the path of the constant current and output the internal reference threshold by turning it on or off according to the digital logic level signal.

[0030] Optionally, both the bias current source and the hysteresis switch are NMOS transistors.

[0031] Optionally, the voltage sampling and feedback module, the UVLO module, and the UVLO hysteresis module are integrated into the same module.

[0032] Optionally, the circuit further includes: a level shifting network and / or an inverter;

[0033] The level shifting network is used to perform level shifting and waveform shaping on the digital logic level signal output by the UVLO module;

[0034] The inverter is used to invert the digital logic level signal output by the UVLO module.

[0035] Optionally, the level shifting network includes an NMOS transistor and a grounding resistor. The gate and drain of the NMOS transistor are interconnected to form a diode connection structure. The drain of the NMOS transistor is connected to the digital logic level signal. The source of the NMOS transistor is grounded through the grounding resistor. The source of the NMOS transistor outputs a conversion voltage.

[0036] The input terminal of the inverter is connected to the source of the NMOS transistor to receive the conversion voltage and shape the conversion voltage to output an enable control signal.

[0037] Optionally, the circuit further includes a startup and pre-regulation module, used to connect to an external power supply and clamp the input voltage at a low level to achieve the pre-regulation function.

[0038] The bandgap reference circuit provided in this embodiment of the invention integrates the UVLO function into the negative feedback loop of the bandgap reference, which effectively improves the system integration, achieves high PSRR, and reduces power consumption.

[0039] Furthermore, the UVLO module saves area and reduces power consumption by reusing branches in the bandgap reference negative feedback loop.

[0040] Compared to conventional high PSRR and low power bandgap bands, it also has lower voltage margin requirements. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of an existing op-amp-less high PSRR bandgap reference circuit and an external UVLO circuit;

[0042] Figure 2 This is a schematic diagram of a bandgap reference circuit provided in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of a specific structure of the bandgap reference circuit provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of another specific structure of the bandgap reference circuit provided in an embodiment of the present invention. Detailed Implementation

[0045] The principles and spirit of the invention will now be described with reference to exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way.

[0046] Existing bandgap reference circuits generally employ an op-amp-less structure to achieve low-power bandgap reference ratio (BGR). However, op-amp-less structures typically have low loop gain, which is not conducive to achieving high power-to-voltage ratio (PSRR). Introducing a high-gain op-amp increases power consumption and area, and also introduces errors due to the op-amp's offset voltage. While using an op-amp-less, cascode structure improves PSRR to some extent, it consumes more voltage margin (i.e., the minimum difference between the supply voltage and the output voltage allowed for the circuit to maintain normal voltage regulation / constant voltage function), which is not conducive to low-voltage applications.

[0047] like Figure 1 The diagram shows the structure of an existing op-amp-less high PSRR bandgap reference circuit and an external UVLO circuit. Existing op-amp-less high PSRR bandgap references mostly employ pre-biasing technology. The bandgap base circuit 10 includes a pre-biasing circuit 11 and a bandgap reference voltage generation circuit 12. The pre-biasing circuit 11 generates a stable voltage to power the bandgap reference voltage generation circuit 12, which outputs the bandgap reference voltage. .

[0048] The core function of UVLO circuit 20 is to protect subsequent circuits or chips from malfunctioning under excessively low power supply voltage, preventing circuit logic corruption, burnout of driver transistors during half-conduction, or the generation of huge short-circuit currents. The output of bandgap reference voltage generation circuit 12... The comparator 21 in the UVLO circuit 20 is connected to the non-inverting input terminal. In the UVLO circuit 20, the voltage is divided by voltage divider resistors R1 and R2. Reference voltage obtained by voltage division Connect to the negative input terminal of comparator 21.

[0049] when Below reference voltage At startup (initial stage), the output of comparator 21 A low level indicates "power not ready". Higher than reference voltage At that time, the output of comparator 21 A high level indicates "normal power supply". This is the output of comparator 21. It can be directly connected to the enable or disable terminals of subsequent modules to control the opening or closing of subsequent modules (such as voltage regulators, power-on reset circuits, etc.).

[0050] Figure 1 While the circuit shown can reduce the interference of power supply fluctuations on the bandgap output and improve PSRR, the pre-bias structure often introduces more branches, increasing power consumption. Furthermore... Figure 1 The implementation of the UVLO function in the traditional method requires a resistor divider branch and a comparator module, which has low integration and high power consumption.

[0051] To address this, embodiments of the present invention provide a bandgap reference circuit that integrates the UVLO function into the bandgap feedback loop, effectively improving system integration, achieving high PSRR, and reducing power consumption.

[0052] like Figure 2 The diagram shown is a schematic diagram of the bandgap reference circuit provided in an embodiment of the present invention.

[0053] The bandgap reference circuit includes: a voltage sampling and feedback module 201, a bandgap reference core module 202 and its negative feedback loop, a startup module 203, and a UVLO module 204. The voltage sampling and feedback module 201 and the UVLO module 204 reuse a portion of the negative feedback loop. Wherein:

[0054] The startup module 203 is used to provide startup current for the bandgap reference core module 202, provide a first bias voltage for the UVLO module 204, and provide a second bias voltage for the voltage sampling and feedback module 201.

[0055] The voltage sampling and feedback module 201 is used to sample and feedback the input voltage. The input sampling voltage is obtained by sampling and output to node A; and the feedback voltage is output through the negative feedback loop. The voltage supplied to the bandgap reference core module 202 serves as the power supply voltage for the bandgap reference core module 202.

[0056] The bandgap reference core module 202 is used to establish a normal operating point under the triggering of the starting current, and to generate a stable bandgap reference voltage based on the control of the negative feedback loop;

[0057] UVLO module 204 is used to sample the input voltage (including the input voltage) based on the bandgap reference voltage. The system performs voltage detection and outputs a digital logic level signal based on the detection result to achieve undervoltage lockout function.

[0058] For example, in some practical applications, when the UVLO module 204 detects that the input voltage is lower than the set undervoltage threshold, it outputs a shutdown signal to put the subsequent circuits (such as the reference source, driver, and power transistor) into a shutdown state to prevent the subsequent circuits from malfunctioning when the power supply is insufficient; when the voltage recovers to the normal operating range, it outputs an enable signal to allow the subsequent circuits to start normally.

[0059] To prevent the UVLO module 204 from repeatedly triggering UVLO protection at critical points, some embodiments may further include a UVLO hysteresis module 205. The UVLO hysteresis module 205 is used to introduce positive feedback, providing an internal reference threshold for voltage detection by the UVLO module 204. The internal reference threshold includes a rising turn-on threshold and a falling turn-off threshold.

[0060] The bandgap reference is a closed-loop system, therefore a negative feedback loop is necessary. In this embodiment of the invention, the negative feedback loop of the bandgap reference can dynamically adjust the bandgap reference supply voltage while stabilizing the bandgap reference voltage. This enables voltage clamping and temperature compensation.

[0061] In this embodiment, the feedback voltage The dynamic adjustment loop is located in the bandgap reference negative feedback loop, and a stable feedback voltage is generated through negative feedback. This provides power to the bandgap reference core module 202, thereby improving its power supply rejection ratio. Simultaneously, by reusing part of the circuitry in the negative feedback loop to achieve input voltage sampling and UVLO functions, not only is the circuit integration significantly improved, but power consumption is also saved.

[0062] Reference Figure 2 The bandgap reference core module 202 generates the bandgap reference voltage. Output bandgap reference voltage Or the output includes a bandgap reference voltage. The information outputs sampled voltage to node B, and the voltage sampling and feedback module 201 samples the input voltage. Sampling, the sampled data includes the input voltage Information input sampling voltage Output to node A.

[0063] The UVLO module 204 includes a PMOS transistor PM1 and an NMOS transistor NM1. The drains of PM1 and NM1 are connected together as the output terminal, outputting digital logic level signals. PM1 is used to sense the input voltage. Whether the UVLO threshold (including the rising turn-on threshold and the falling turn-off threshold) is reached, and whether the UVLO threshold is higher than the bandgap reference voltage. Establish the required minimum input voltage Digital logic level signals Used in input voltage The chip shuts down other modules when undervoltage occurs. NM1 is a pull-down driver transistor.

[0064] The startup module 203 provides startup current to the bandgap reference core module 202 and provides a first bias voltage to NM1, causing NM1 to generate a relatively weak pull-down.

[0065] Reference Figure 2 Input voltage When the voltage decreases, the voltage at node A... As a result, the voltage at node B decreases, and the voltage at node B becomes... , ( When the input voltage is equal to the threshold voltage of PM1, the potential of node C (i.e., the drain of PM1) is pulled low, triggering UVLO protection; conversely, when the input voltage is higher than the threshold voltage of PM1, the potential of node C (i.e., the drain of PM1) is pulled low, triggering UVLO protection. As the voltage rises from 0, the voltage at node A... Rise, due to input voltage Rise to bandgap reference voltage After establishing the required minimum value The input voltage remains stable and unchanged. As the voltage continues to rise, the upward pull of PM1 gradually increases. When the voltage of node C reaches the threshold for activation, the voltage of node C is pulled up, and the UVLO protection ends.

[0066] The bandgap reference circuit provided in this embodiment of the invention integrates some circuits of voltage sampling and UVLO function into the negative feedback loop of the bandgap reference, which effectively improves the system integration, can achieve high PSRR, and reduces power consumption.

[0067] like Figure 3 The diagram shown is a specific structural schematic of a bandgap reference circuit provided in an embodiment of the present invention.

[0068] In this embodiment, the startup module 203 includes: a signal generation unit 231, a current mirror unit, and a control unit.

[0069] The signal generating unit 231 is used to generate a starting current. First bias voltage Second bias voltage The first bias voltage The NMOS transistors provided in the UVLO hysteresis module 205 The second bias voltage PMOS transistors provided in voltage sampling and feedback module 201 .

[0070] The current mirror unit is used to provide a current transmission path to transmit the starting current. Transmitted to the bandgap reference core module 202. (For example...) Figure 3 As shown, the current mirror unit includes a PMOS transistor. and The second current mirror, composed of a PMOS transistor, is formed. The third current mirror is formed. Starting current. Through the second current mirror, the third current mirror, and the UVLO hysteresis module 205, the PMOS transistor... The fourth current mirror is mirrored to the bandgap reference core module 202 to provide the start-up current for the bandgap reference core module 202.

[0071] The control unit is used to control the bandgap reference voltage generated by the bandgap reference core module 202. When the set value is reached, the current transmission path is disconnected. For example... Figure 3 As shown, in a non-limiting embodiment, the control unit may be an NMOS transistor. To achieve this.

[0072] During initial startup, less than threshold voltage , It is in a closed state. The current path between them is opened, and the starting current is activated. via the second current mirror and Third current mirror Fourth current mirror The image is mirrored to the bandgap reference core module 202 to provide startup current for it. After the bandgap reference core module 202 starts up... Increase, when Rise to hour, When the circuit is open, it is in the conductive state, making The current path between them is broken, and at this time, the operating current of the bandgap reference core module 202 is provided by an external power supply. Operating current via the fourth current mirror The image is mirrored to the bandgap reference core module 202, so that the bandgap reference core module 202 can maintain normal operation.

[0073] It should be noted that the two PMOS transistors in each of the above current mirrors can have the same width-to-length ratio, forming a current mirror structure with a 1:1 ratio. Of course, they can also have different width-to-length ratios, which is not limited in this embodiment of the invention.

[0074] Continue to refer to Figure 3 The bandgap reference core module 202 includes: a current mirror, a core unit, and a voltage transmission unit. Among them:

[0075] The first current mirror is used to mirror the startup current to obtain a first current and a second current. The first current mirror includes two identical MOSFETs, such as... Figure 3 As shown, two identical MOSFETs can be replaced with PMOS transistors. and . and The source is connected to the feedback voltage on the negative feedback loop. , gate and gate connection, The gate is also connected to its drain. The first current is The current in the branch, the second current is The current in the branch circuit.

[0076] In one non-limiting embodiment, and They can have the same width-to-length ratio to form a current mirror structure with a 1:1 ratio, clamping the current in two different branches.

[0077] In standard logic processes or conventional circuit designs, to achieve a larger drive current, the dimensions of MOSFETs are typically designed so that W > L, where W is the channel width and L is the channel length. Due to the inverted geometry, inverting MOSFETs exhibit different electrical characteristics from conventional MOSFETs, mainly in the following aspects: low current drive capability, high output impedance, small transconductance, and large gate capacitance.

[0078] In this embodiment of the invention, and By employing an inverting transistor, and leveraging its high output impedance, the change in drain voltage has a minimal impact on the current. This reduces the deviation in baseband voltage caused by channel length modulation, ensuring consistent output voltage (i.e., bandgap reference voltage). When the current changes, the mirror current remains accurate, making the current mirror output closer to the ideal constant current source.

[0079] The core unit includes a first transistor. Second transistor The network consists of a pair of transistors and an emitter resistor.

[0080] Among them, the first transistor collector and The drain connection, the second transistor collector and The drain connection. First transistor. The base and the second transistor The base connection allows the output of a bandgap reference voltage with zero temperature coefficient. The first transistor Second transistor The voltages generate negative temperature coefficients in response to the first current and the second current, respectively, and form a voltage difference with a positive temperature coefficient based on different current densities.

[0081] Bandgap reference voltage By the second transistor The voltage of the PN junction is superimposed with the compensation voltage.

[0082] In one non-limiting embodiment, the first transistor Second transistor Bipolar junction transistors (BJTs) can be used. and The size (i.e., emitter area) is different. The size is larger than The dimensions. For example, in a non-limiting embodiment, the dimensions of the two can be 8:1, and correspondingly, under the same conditions, Its conductivity (or preset current) is Eight times that.

[0083] The emitter resistor network is connected to the first transistor. Second transistor The emitter path is used for the voltage difference in the second transistor based on the positive temperature coefficient. A compensation voltage with a positive temperature coefficient is generated in the emitter path.

[0084] like Figure 3 As shown, in some embodiments, the emitter resistor network may include: a first resistor. Second resistor First resistor Connected to the first transistor Between the emitter and the first node; the second resistor Connected between the first node and ground; second transistor The emitter is connected to the first node.

[0085] In this emitter resistor network structure, the first resistor The first transistor Second transistor Base-emitter voltage difference under different current densities Converted to PTAT (Proportional To Absolute Temperature) current. For the first transistor The base-emitter voltage, For the second transistor Base-emitter voltage; second resistor The current is converted into a compensation voltage.

[0086] It should be noted that the emitter resistor network is not limited to Figure 3 The structure shown above can also have other structures. For example, in a non-limiting embodiment, the emitter resistor network may include a third resistor and a fourth resistor, wherein the third resistor is connected between the emitter of the first transistor and ground, and the fourth resistor is connected between the emitter of the second transistor and ground. In this emitter resistor network structure, the two branches each generate a PTAT current, which is then summed at the output node.

[0087] Of course, there can be other variations, which will not be listed here.

[0088] like Figure 3 As shown, the voltage transmission unit includes an NMOS transistor. Located on the bandgap negative feedback loop, it forms the negative feedback loop with a portion of the circuitry of the voltage sampling and feedback module 201 and the UVLO module 204.

[0089] exist Figure 3 In the illustrated embodiment, the voltage sampling and feedback module 201 consists of two MOSFETs, such as... Figure 3 PMOS and and NMOS transistor .in, The source is connected to the input voltage. , The gate is connected to a second bias voltage provided by the signal generation unit 231 in the startup module 203. , Drain and The drain connection, The drain is also connected to its gate. The source (i.e., node A) outputs the input sampling voltage, which, for ease of description, is denoted as . .

[0090] exist Figure 3 In the illustrated embodiment, the UVLO module 204 consists of two MOS transistors, such as... Figure 3 The PMOS transistor shown and NMOS transistor , and The structure consists of voltage detection and level conversion, which converts the input sampled voltage. The comparison result with the internal reference threshold is mapped to high and low levels.

[0091] in, As a pull-up detection switch in the input stage, it is responsible for sensing the establishment of the input voltage; As a logic pull-down switch in the output stage, it is responsible for locking the output state after the undervoltage is released. (By...) Pull up and The pull-down action produces a clear logical '0' or logical '1'.

[0092] UVLO hysteresis module 205 is used to introduce positive feedback and provide an internal reference threshold for voltage detection of UVLO module 204. The internal reference threshold includes a rising turn-on threshold and a falling turn-off threshold. By setting upper and lower thresholds, repeated state transitions caused by voltage fluctuations near a single threshold can be avoided, ensuring that the system has clean and stable state transitions during startup and shutdown.

[0093] In this embodiment of the invention, the UVLO hysteresis module 205 includes a bias current source and a hysteresis switch. The bias current source receives the first bias voltage and provides a constant current; the hysteresis switch is used to turn on or off according to the digital logic level signal output by the UVLO module 204 to control the conduction or disconnection of the constant current path and output the internal reference threshold.

[0094] It should be noted that, depending on the required control logic, the digital logic level signal output by the UVLO module 204 can be directly connected to the UVLO hysteresis module 205, or it can be inverted and then connected to the UVLO hysteresis module 205. This embodiment of the invention does not limit this.

[0095] In a non-limiting embodiment, the bias current source and the hysteresis switch can be implemented using NMOS transistors. Figure 3 In the example shown, the NMOS transistor As a bias current source, the NMOS transistor As a hysteresis switch. Among them, Drain and The drain connection, The gate is connected to the first bias voltage , The source pole and The drain connection, The source is grounded. The gate is connected to a digital logic level signal. . For node C (i.e. The digital logic level signal output from the drain of the device. The inverted signal.

[0096] Reference Figure 3 When the input voltage When the voltage decreases, the output sampling voltage is reduced. Accordingly, the UVLO threshold (including the rising turn-on threshold and the falling turn-off threshold) is reduced to a value greater than the minimum input voltage required for reference establishment. At that time, the potential of node B Remain unchanged, when ( for When the threshold voltage is reached, the potential of node C is... Pull down, at this time the potential of node A This is the UVLO descent shutdown threshold. Because when UVLO is triggered, High potential On, second bias voltage It persists after power-on. Conductive, The current of the branch is mirrored to The branch circuit generates operating current. Operating current injection The branch raises the potential of node B. Therefore, the input voltage During the process of increasing the potential from 0, a higher potential at node A is needed to raise the potential at node C. The potential at node A corresponding to the increase in the potential at node C is... This is the rising threshold for UVLO, obviously UVLO hysteresis .

[0097] exist Figure 3 In the example shown, , , , , This provides a negative feedback loop with a certain gain for the bandgap without an op-amp structure. The pF-level capacitor provides compensation for the negative feedback loop.

[0098] The following is combined with Figure 3 This section details the working principle of the bandgap reference circuit.

[0099] Assuming the first current mirror in the bandgap reference core module 202 A current mirror structure with a 1:1 ratio is constructed. and If the size ratio is 8:1, then the bandgap reference voltage generated by the bandgap reference core module 202... It can be represented as:

[0100] ;

[0101] in, for The base-emitter voltage provides the negative temperature compensation portion in the bandgap reference voltage; Thermoelectric voltage, k is Boltzmann's constant, T is the absolute temperature, and q is the electron charge; For the natural logarithm term.

[0102] exist Figure 3 In the example shown, the working process of the bandgap negative feedback loop is as follows: , , , , Construct a voltage modulation loop, , and It has a relatively large width and length, and operates in the subthreshold region. Gate-source voltage Approximately equal to threshold voltage MOS transistors operating in the subthreshold region have high transconductance efficiency, meaning they can provide higher transconductance for the same current, thereby improving loop gain and better suppressing power supply disturbances. Operating in the subthreshold region results in a lower characteristic frequency, meaning a smaller bandwidth and slower speed. However, bandgap references primarily require high PSRR in the low to mid-frequency range, and the bandwidth of the subthreshold region is usually sufficient to cover this range. Thus, , , All of them operate in the subthreshold region, and their gate-source voltage difference... The feedback voltage is approximately equal to its own threshold voltage, therefore... Stable at This effectively improves PSRR by increasing the voltage supplied to the bandgap reference. The input voltage is generated by a high-gain feedback loop. The disturbance will be suppressed by the loop, and the PSRR magnitude is positively correlated with the loop gain. By integrating the voltage modulation loop and the bandgap reference negative feedback loop, the suppression path is shortened, which is more conducive to improving PSRR.

[0103] If in and Apply a positive perturbation to the base, that is If the base potential rises, then The collector potential decreases, that is... If the gate potential decreases, then the potential of node A also decreases. gate potential ( for The threshold voltage decreases, and the feedback voltage decreases. reduce, The gate potential also decreases accordingly, eventually The base potential decreases.

[0104] The voltage modulation loop (which is the same loop as the bandgap negative feedback loop) is also included in the bandgap negative feedback loop. If the feedback voltage... If it rises, then The gate potential increases. The base potential increases, therefore As the collector potential decreases, the potential at node A increases. Gate potential decreases, feedback voltage Reduce, ultimately achieving feedback voltage The voltage is stabilized, thereby improving the reference PSRR.

[0105] The bandgap reference circuit provided in this embodiment of the invention generates a feedback voltage through negative feedback. Feedback voltage Compared to existing pre-biasing techniques, this pre-bias voltage does not introduce an additional current branch, while The voltage modulation loop is contained within the bandgap negative feedback loop, and one of its branches is reused (i.e. , , , The branch circuit (where it is located) implements UVLO functionality, achieving high integration while also consuming less power.

[0106] It should be noted that in some embodiments, the voltage sampling and feedback module 201, the UVLO module 204, and the UVLO hysteresis module 205 can be integrated into the same module as an integrated UVLO module. Compared to the existing solution in traditional designs that separate the UVLO function from the bandgap reference core module and require an additional comparator module, this not only improves the overall circuit integration but also reuses the current of the same branch, saving power consumption.

[0107] like Figure 4 The diagram shown is a schematic diagram of another specific structure of the bandgap reference circuit provided in an embodiment of the present invention.

[0108] and Figure 3 The difference between the embodiments shown is that, Figure 4 In the illustrated embodiment, the bandgap reference circuit further includes: a level shifting network 206 and / or an inverter 207. Wherein:

[0109] Level shifting network 206 is used to process the digital logic level signals output by UVLO module 204. Level shifting and waveform shaping are performed to output a noise-free, steep-edge digital enable signal to the subsequent controlled module.

[0110] Inverter, used to adjust the digital logic level signal output by UVLO module 204. Invert the signal and output the inverted digital logic level signal. .

[0111] like Figure 4 As shown, in some embodiments, the level shifting network 206 includes an NMOS transistor. and grounding resistance , The gate and drain are interconnected to form a diode connection structure. The drain of the UVLO module 204 is connected to the digital logic level signal output by the UVLO module. , The source through Grounding, The source output conversion voltage.

[0112] The input of inverter 207 is connected to The source of the signal is used to receive the converted voltage and shape the converted voltage to output an enable control signal. This enable control signal Access UVLO hysteresis module 205 The gate.

[0113] Figure 4 middle This is a small filter capacitor.

[0114] In some embodiments, the bandgap reference circuit may further include:

[0115] The startup and pre-regulation module is used to connect to an external power supply and to apply the input voltage to the bandgap reference circuit. Clamped at a low level, it achieves pre-regulation function. For example... Figure 4 As shown, the startup and pre-regulation module can be composed of an N-channel JFET (Junction FET). To achieve this.

[0116] If the pinch-off voltage is 5V, that is Its gate-source voltage At that time, the channel was just pre-pinched off, and the current decreased to near zero; At that time, the channel is not pinched off and the drain current is greater than zero.

[0117] External power supply voltage When the voltage is below 5V, The circuit descends and connects to the bandgap reference circuit. follow Decline, due to The function, It will enter the deep linear region, and at the second bias voltage Under the action, it will The on-resistance is very small, the source-drain voltage difference is very small, therefore the potential of node A is very small. The potential of node B , for The collector-base voltage difference. The decline made At that time, the potential of node C is Lower, For high, Turn on, generate current injection The potential of node B in the branch is... Elevated Therefore, the external power supply voltage When rising, it must meet the following conditions. Only then can node C output a high potential.

[0118] In summary, the UVLO threshold, i.e., the internal benchmark threshold, is as follows:

[0119] Decreasing the shutdown threshold ;

[0120] Rise threshold ;

[0121] Hysteresis range is Req is Equivalent impedance to ground at the collector node.

[0122] Figure 3 middle Operating current after conduction injection The branch will raise the bandgap reference voltage. , Indicates the bandgap reference voltage The value before the increase Indicates bandgap voltage The value after the increase.

[0123] In this invention, the current mirror does not use a cascode structure (cascode structures require a higher voltage margin), theoretically the input voltage... Substituting the typical values ​​of each parameter, then It will then work normally. express The drain-source voltage. Because Operating in the linear region, its source-drain voltage is low. If calculated at 200mV, the input voltage... It only requires 2.8V, meaning it only needs a voltage margin of about 2.8V, making it suitable for low-voltage applications.

[0124] The bandgap reference circuit provided in this invention has high integration and reduces power consumption by multiplexing branches in the feedback loop. Moreover, compared to conventional high PSRR low-power bandgap circuits, it has lower voltage margin requirements. This bandgap reference circuit can be used in LDOs (Low Dropout Regulators) to allow them to maintain high PSRR at lower voltage drops; or in DC-DC converters to reduce their quiescent power consumption and improve their adaptability to a wide input voltage range.

[0125] In the description of the embodiments of the present invention, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects. Furthermore, ordinal numbers do not represent the number of related objects.

[0126] In the description of the embodiments of this invention, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Other quantifiers are similar.

[0127] The terms "or" and "and / or" used in this invention are used to describe the relationship between associated objects, indicating a non-exclusive inclusion. For example, "A and / or B" can include: "A alone", "B alone", or "A and B". Additionally, the character " / " in this document indicates that the preceding and following associated objects have an "or" relationship.

[0128] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of modules is merely a logical functional division, and there may be other division methods in actual implementation, which this invention does not limit.

[0129] In the embodiments of the present invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0130] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or they can be separate physical units, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware or in the form of hardware and software functional units.

[0131] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Any person skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments without departing from the spirit and scope of the present invention.

Claims

1. A bandgap reference circuit, characterized in that, The circuit includes: a startup module, a voltage sampling and feedback module, a bandgap reference core module and its negative feedback loop, and a UVLO module; the voltage sampling and feedback module and the UVLO module reuse part of the negative feedback loop to integrate the UVLO function into the negative feedback loop; The startup module is used to provide a startup current for the bandgap reference core module, a first bias voltage for the UVLO module, and a second bias voltage for the voltage sampling and feedback module. The voltage sampling and feedback module is used to sample the input voltage to obtain the input sampling voltage; and through the negative feedback loop, outputs a feedback voltage to the bandgap reference core module, the feedback voltage serving as the power supply voltage for the bandgap reference core module; The bandgap reference core module is used to establish a normal operating point under the triggering of the starting current, and to generate a stable bandgap reference voltage based on the control of the negative feedback loop. The UVLO module is used to perform voltage detection on the input sampling voltage based on the bandgap reference voltage, and output a digital logic level signal based on the detection result to realize the undervoltage lockout function.

2. The bandgap reference circuit according to claim 1, characterized in that, The core module of the bandgap reference includes: a first current mirror, a core unit, and a voltage transmission unit; The first current mirror is used to mirror the starting current to obtain a first current and a second current; The core unit includes a transistor pair consisting of a first transistor and a second transistor, and an emitter resistor network. The first transistor and the second transistor generate negative temperature coefficient voltages in response to the first current and the second current, respectively, and form a voltage difference with a positive temperature coefficient based on different current densities; The emitter resistor network is connected to the emitter paths of the first transistor and the second transistor, and is used to generate a positive temperature coefficient compensation voltage in the emitter path of the second transistor based on the positive temperature coefficient voltage difference. The bases of the first transistor and the second transistor are connected and serve as the output terminal of the bandgap reference core module to output the bandgap reference voltage; The voltage transmission unit is used to form the negative feedback loop with a portion of the circuitry of the voltage sampling and feedback module and the UVLO module.

3. The bandgap reference circuit according to claim 2, characterized in that, The first current mirror includes two identical MOS transistors, which have the same width-to-length ratio, forming a current mirror structure with a ratio of 1:

1.

4. The bandgap reference circuit according to claim 2, characterized in that, The first transistor and the second transistor are bipolar transistors.

5. The bandgap reference circuit according to claim 2, characterized in that, The emitter resistor network includes: a first resistor and a second resistor; the first resistor is connected between the emitter of the first transistor and the first node; the second resistor is connected between the first node and ground; and the emitter of the second transistor is connected to the first node.

6. The bandgap reference circuit according to claim 2, characterized in that, The emitter resistor network includes a third resistor and a fourth resistor, wherein the third resistor is connected between the emitter of the first transistor and ground, and the fourth resistor is connected between the emitter of the second transistor and ground.

7. The bandgap reference circuit according to claim 1, characterized in that, The startup module includes: A signal generation unit is used to generate the startup current, the first bias voltage, and the second bias voltage; A current mirror unit is used to provide a current transmission path to transmit the startup current to the bandgap reference core module; The control unit is used to disconnect the current transmission path when the bandgap reference voltage reaches a set value.

8. The bandgap reference circuit according to claim 7, characterized in that, The UVLO module includes a PMOS transistor and an NMOS transistor. The source of the PMOS transistor is connected to the input sampling voltage, the gate of the PMOS transistor is connected to the source, the drain of the PMOS transistor is connected to the drain of the NMOS transistor, the source of the NMOS transistor is grounded, and the gate of the NMOS transistor is connected to the first bias voltage.

9. The bandgap reference circuit according to claim 8, characterized in that, The circuit also includes: The UVLO hysteresis module is used to introduce positive feedback and provide an internal reference threshold for the voltage detection of the UVLO module. The internal reference threshold includes a rising turn-on threshold and a falling turn-off threshold.

10. The bandgap reference circuit according to claim 9, characterized in that, The UVLO hysteresis module includes: a bias current source and a hysteresis switch; The bias current source is used to receive the first bias voltage and provide a constant current; The hysteresis switch is used to switch the path of the constant current and output the internal reference threshold by turning it on or off according to the digital logic level signal.

11. The bandgap reference circuit according to claim 10, characterized in that, Both the bias current source and the hysteresis switch are NMOS transistors.

12. The bandgap reference circuit according to claim 10, characterized in that, The voltage sampling and feedback module, the UVLO module, and the UVLO hysteresis module are integrated into the same module.

13. The bandgap reference circuit according to any one of claims 1 to 12, characterized in that, The circuit also includes: a level shifting network, and / or an inverter; The level shifting network is used to perform level shifting and waveform shaping on the digital logic level signal output by the UVLO module; The inverter is used to invert the digital logic level signal output by the UVLO module.

14. The bandgap reference circuit according to claim 13, characterized in that, The level shifting network includes an NMOS transistor and a grounding resistor. The gate and drain of the NMOS transistor are interconnected to form a diode connection structure. The drain of the NMOS transistor is connected to the digital logic level signal. The source of the NMOS transistor is grounded through the grounding resistor. The source of the NMOS transistor outputs a conversion voltage. The input terminal of the inverter is connected to the source of the NMOS transistor to receive the conversion voltage and shape the conversion voltage to output an enable control signal.

15. The bandgap reference circuit according to any one of claims 1 to 12, characterized in that, The circuit also includes: The startup and pre-regulation module is used to connect to an external power supply and clamp the input voltage to a low level to achieve the pre-regulation function.

Images