AWG waveform data storage method based on DDR architecture

Abstract

The invention relates to the technical field of data storage, and particularly discloses an AWG waveform data storage method based on a DDR architecture, which comprises the following steps: waveform data storage configuration: performing logic hierarchical division on a DDR storage space, and configuring header information descriptors containing data length information for each waveform sub-block, classified storage and identification of test excitation waveform data are realized; and dynamic waveform scheduling: after the upper computer issues the initial base address of the unified waveform data block, the FPGA calculates the initial address of the waveform data of each channel according to the initial base address, and transmits the waveform data of each channel to the corresponding DAC unit in parallel in combination with the length of the waveform data to generate a test excitation waveform. The DDR storage space is logically divided into multi-channel independent areas, multi-waveform sub-blocks are divided in each area, and a special header information descriptor is matched, so that pre-storage and quick positioning of multiple test excitation waveforms are realized, and the limitation that a traditional scheme only supports a single test mode is solved.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically to an AWG waveform data storage method based on DDR architecture. Background Technology

[0002] In FPGA applications, high-capacity DDR SDRAM can be used as the core of waveform storage. Test stimulus waveform data is preloaded into memory. During testing, the DMA controller and custom logic in the FPGA directly and stably read massive amounts of waveform data from DDR at high speed, and convert it into analog signals through a high-precision DAC to generate the required test stimulus waveform.

[0003] However, existing technologies have significant drawbacks: DDR-based AWG solutions typically treat the entire DDR memory space as a single unit, or allocate only a single waveform storage area for each channel. When test tasks require switching between different test stimuli, the system cannot achieve rapid output and dynamic switching of multiple test stimuli, resulting in low test efficiency and severely limiting the system's adaptability in multi-scenario, multi-parameter testing, making it difficult to meet the concurrency and flexibility requirements of high-end chip testing. Summary of the Invention

[0004] The purpose of this invention is to provide an AWG waveform data storage method based on DDR architecture to solve the above-mentioned technical problems.

[0005] The objective of this invention can be achieved through the following technical solutions: The AWG waveform data storage method based on DDR architecture includes the following steps: Waveform data storage configuration: By logically dividing the DDR storage space into layers and configuring header information descriptors containing data length information for each waveform sub-block, the classification, storage and identification of test stimulus waveform data can be realized. Dynamic waveform scheduling: After the host computer sends out the unified waveform data block start base address, the FPGA calculates the start address of each channel waveform data according to the start base address, and combines it with the waveform data length to transmit the waveform data of each channel in parallel to the corresponding DAC unit to generate the test excitation waveform.

[0006] As a further aspect of the present invention, the specific steps for configuring the waveform data storage are as follows: The DDR memory space is logically divided into multiple independent memory areas that correspond one-to-one with the physical output channels; Each of the independent storage areas is further divided into several waveform sub-blocks for storing different test excitation waveform data respectively; Configure a header information descriptor for each waveform sub-block.

[0007] As a further aspect of the present invention, the specific steps of the dynamic waveform scheduling are as follows: The host computer sends a unified waveform data block start base address to the FPGA; The FPGA calculates the header information descriptor address corresponding to all physical output channels by using a fixed address offset, based on the preset memory structure rules. The FPGA reads the header information descriptor of each channel through the DDR controller IP core, and then calculates the waveform data start address of the corresponding waveform sub-block of each channel according to the starting base address and storage layout rules. The FPGA combines the waveform data start address and waveform data length information, and through the DDR controller IP core and internal logic, transmits the waveform data of each channel in parallel to the corresponding DAC unit to generate test excitation waveforms.

[0008] As a further aspect of the present invention: the number of independent storage areas is consistent with the number of physical output channels, and the size of each independent storage area is a fixed value or a configurable value.

[0009] As a further aspect of the present invention: the waveform sub-blocks in each independent storage area are either contiguous or non-contiguous storage structures.

[0010] As a further aspect of the present invention: the header information descriptor occupies a fixed amount of storage space in DDR, and the header information descriptor address corresponding to each channel is obtained by accumulating a unified base address and a fixed offset.

[0011] As a further aspect of the present invention: the FPGA reads waveform data from each independent storage area through an independent data path, thereby achieving parallel output of multi-channel waveform data, and the test excitation waveforms output by each channel do not interfere with each other.

[0012] As a further aspect of the present invention: the output engine of a single physical output channel dynamically jumps to any waveform sub-block in its dedicated independent storage area according to the sequence instructions, thereby realizing the switching of different test excitation waveforms without reloading waveform data.

[0013] As a further aspect of the present invention: the number of physical output channels is 8, and the corresponding independent storage areas are CH1-CH8 respectively. The waveform sub-block in each independent storage area can store several different test excitation waveform data.

[0014] As a further aspect of the present invention: the header information descriptor contains waveform data length information of the corresponding waveform sub-block.

[0015] The beneficial effects of this invention are as follows: This invention divides the DDR storage space into multiple independent channels by logically partitioning it, and further divides each channel into multiple waveform sub-blocks. Combined with a dedicated header information descriptor, it achieves pre-storage and rapid positioning of multiple test stimulus waveforms, overcoming the limitation of traditional solutions that only support a single test mode. By adopting an address calculation method of "unified base address + fixed offset", the FPGA can autonomously complete the reading of multi-channel header information and waveform data without the need for configuration by the host computer, simplifying the scheduling process and realizing the parallel output of multi-channel waveforms. A single channel can dynamically jump to any waveform sub-block according to the sequence command, realizing seamless waveform switching without reloading data, which improves the flexibility and efficiency of testing; each channel transmits data through an independent data path, and the output waveforms do not interfere with each other, effectively balancing the concurrency and flexibility of testing, and significantly improving the throughput and scenario adaptability of high-end chip testing. Attached Figure Description

[0016] The invention will now be further described with reference to the accompanying drawings.

[0017] Figure 1 This is a schematic diagram of the main architecture of the AWG waveform data storage method based on DDR architecture of the present invention; Figure 2 This is an operation flowchart of the DDR memory structure of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] In FPGA applications, high-capacity DDR SDRAM can be used as the core of waveform storage. Test stimulus waveform data is preloaded into memory. During testing, the DMA controller and custom logic in the FPGA directly and stably read massive amounts of waveform data from DDR at high speed, and convert it into analog signals through a high-precision DAC to generate the required test stimulus waveform.

[0020] In existing technologies, DDR-based AWG solutions typically treat the entire storage space as a single unit, or allocate a fixed single waveform storage area for each channel. When test tasks need to be switched, the system cannot achieve the output and dynamic switching of multiple test stimuli, thus limiting test efficiency and the system's adaptability in multi-scenario, multi-parameter testing.

[0021] To address the limitation of existing pre-stored waveform methods that only support a single test mode, this invention constructs and stores multiple independent test stimulus waveform data blocks during the waveform data pre-storage stage, and configures a dedicated header information descriptor for each data block. This header information accurately records the starting storage address and data length of the corresponding waveform segment, thereby achieving rapid location, sequential scheduling, and dynamic seamless switching of multiple test stimulus waveforms at the hardware level, significantly improving the parallel processing capability and scenario adaptability of the test system.

[0022] like Figure 1 As shown, the physical storage space of DDR is logically divided into eight independent storage areas (CH1 to CH8) of fixed or configurable size, with each area dedicated to a physical output channel. The eight channels can simultaneously read data from their respective dedicated DDR storage areas, outputting independent and completely different test stimulus waveforms through independent data paths, without interfering with each other, thus realizing the concurrent execution of a single test scheme across multiple channels.

[0023] Furthermore, each channel's dedicated storage area is further divided into N consecutive or non-consecutive sub-blocks. Each sub-block stores a complete, specific test stimulus waveform (e.g., Wave1, Wave2, ..., WaveN). Through configuration with the upper-level controller, each channel's output engine can dynamically jump to any waveform sub-block within its dedicated area for reading and output based on sequential instructions. This allows a single channel to quickly switch between outputting multiple stimulus waveforms as needed, without reloading data, greatly enhancing testing flexibility and efficiency.

[0024] like Figure 2 As shown, during the initialization phase of each test task, the host computer needs to configure a unified waveform data block starting base address for the task. When the task starts, the host computer sends this base address to the FPGA through a communication interface (such as PCIe).

[0025] After receiving the base address, the FPGA uses the pre-defined storage structure rules—that is, the header information descriptor of each channel (CH) occupies a fixed amount of storage space in DDR—to calculate the precise physical address of the header information descriptor of each of the eight channels in turn using a fixed address offset.

[0026] Subsequently, the FPGA initiates a read request through the DDR controller IP core, batch reading the header information descriptors of all channels from the eight calculated addresses. Crucially, this header information contains the actual length of the corresponding channel's waveform data. After obtaining the header information, the FPGA also calculates the starting address of the waveform data for each channel from the base address, according to a fixed memory layout rule.

[0027] Ultimately, the FPGA combines the start address and length information of the waveform data for each channel, and through the DDR controller IP core and the internal logic of the FPGA, accurately and in parallel transmits the waveform data blocks of each channel to the corresponding DAC unit, thereby synchronously generating independent and flexibly configurable test stimulus waveforms on eight channels.

[0028] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A method for storing AWG waveform data based on DDR architecture, characterized in that, Includes the following steps: Waveform data storage configuration: By logically dividing the DDR storage space into layers and configuring header information descriptors containing data length information for each waveform sub-block, the classification, storage and identification of test stimulus waveform data can be realized. Dynamic waveform scheduling: After the host computer sends out the unified waveform data block start base address, the FPGA calculates the start address of each channel waveform data according to the start base address, and combines it with the waveform data length to transmit the waveform data of each channel in parallel to the corresponding DAC unit to generate the test excitation waveform.

2. The AWG waveform data storage method based on DDR architecture according to claim 1, characterized in that, The specific steps for configuring the waveform data storage are as follows: The DDR memory space is logically divided into multiple independent memory areas that correspond one-to-one with the physical output channels; Each of the independent storage areas is further divided into several waveform sub-blocks for storing different test excitation waveform data respectively; Configure a header information descriptor for each waveform sub-block.

3. The AWG waveform data storage method based on DDR architecture according to claim 2, characterized in that, The specific steps of the dynamic waveform scheduling are as follows: The host computer sends a unified waveform data block start base address to the FPGA; The FPGA calculates the header information descriptor address corresponding to all physical output channels by using a fixed address offset, based on the preset memory structure rules. The FPGA reads the header information descriptor of each channel through the DDR controller IP core, and then calculates the waveform data start address of the corresponding waveform sub-block of each channel according to the starting base address and storage layout rules. The FPGA combines the waveform data start address and waveform data length information, and through the DDR controller IP core and internal logic, transmits the waveform data of each channel in parallel to the corresponding DAC unit to generate test excitation waveforms.

4. The AWG waveform data storage method based on DDR architecture according to claim 3, characterized in that, The number of independent storage areas is the same as the number of physical output channels, and the size of each independent storage area is a fixed value or a configurable value.

5. The AWG waveform data storage method based on DDR architecture according to claim 3, characterized in that, The waveform sub-blocks within each independent storage area can be either contiguous or non-contiguous storage structures.

6. The AWG waveform data storage method based on DDR architecture according to claim 3, characterized in that, The header information descriptor occupies a fixed amount of storage space in DDR, and the address of the header information descriptor corresponding to each channel is calculated by accumulating a unified base address and a fixed offset.

7. The AWG waveform data storage method based on DDR architecture according to claim 3, characterized in that, The FPGA reads waveform data from each independent storage area through independent data paths, realizing parallel output of multi-channel waveform data, and the test excitation waveforms output by each channel do not interfere with each other.

8. The AWG waveform data storage method based on DDR architecture according to claim 3, characterized in that, The output engine of a single physical output channel can dynamically jump to any waveform sub-block in its dedicated independent storage area according to the sequence instructions, so as to switch between different test excitation waveforms without reloading waveform data.

9. The AWG waveform data storage method based on DDR architecture according to claim 3, characterized in that, The number of physical output channels is 8, and the corresponding independent storage areas are CH1-CH8. Each independent storage area can store several different test excitation waveform data.

10. The AWG waveform data storage method based on DDR architecture according to claim 2, characterized in that, The header information descriptor contains waveform data length information for the corresponding waveform sub-block.

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