Information transmission method and device, equipment and medium

Abstract

The invention provides an information transmission method and device, equipment and a medium, and the method comprises the steps: if it is determined that PCIE equipment needing to communicate with a PCIE controller has a fault, clearing a first request which is not processed completely on an internal bus connected with the PCIE controller; sending a reset command to the PCIE controller to enable the PCIE controller to complete resetting; and when the PCIE controller finishes resetting and the state of the data link layer of the PCIE controller is switched to the connection state, a second request transmitted on the slave interface of the internal bus is acquired, and a simulation response result of the second request is fed back to a sender of the second request. In the embodiment of the invention, after the PCIE controller is reset and the data link layer is not successfully established, the simulation response is performed on the second request generated in the chip, so that the phenomenon that the internal bus is stuck is avoided.

Description

Technical Field

[0001] This application relates to the field of electronics, and more particularly to an information transmission method, apparatus, device, and medium. Background Technology

[0002] Currently, the high-speed serial computer expansion bus standard (Public Component Interconnect Express, or PCIe for short) is a commonly used peripheral bus in computer systems. Furthermore, computer system chips typically have a built-in PCIe controller. The functional modules within the chip can connect to the PCIe controller via an internal bus, and the PCIe controller performs the conversion between the internal bus protocol and the PCIe protocol, enabling the functional modules within the chip to communicate with external (i.e., external to the chip) PCIe devices.

[0003] In related technologies, when a link to a PCIe controller (i.e., the link connected to a PCIe device) fails, the PCIe controller can be reset so that the link can be re-established after the PCIe controller is reset.

[0004] However, if the link cannot be successfully established after the PCIe controller is reset, and the PCIe controller receives another access request from the internal functional module to access the external PCIe device, the access request will not be sent successfully because the link has not been successfully established. The functional module will remain in a state of waiting for the access request response, causing the internal bus to freeze. Summary of the Invention

[0005] This application provides an information transmission method, apparatus, device, and medium to reduce the risk of internal bus jamming in a chip.

[0006] In a first aspect, this application provides an information transmission method, including:

[0007] If it is determined that a PCIe device that needs to communicate with a high-speed serial computer expansion bus standard PCIe controller is faulty, then clear the first unprocessed request on the internal bus to which the PCIe controller is connected.

[0008] Send a reset command to the PCIe controller to cause the PCIe controller to complete a reset;

[0009] During the period from when the PCIe controller completes a reset until the data link layer of the PCIe controller switches to the connected state, a second request transmitted on the slave interface of the internal bus is acquired, and a simulated response result of the second request is sent back to the sender of the second request; the slave interface is an interface used to receive requests from the internal bus to access the PCIe device.

[0010] In one example, determining that a PCIe device that needs to communicate with the PCIe controller is faulty includes:

[0011] If a specific situation is determined, then the PCIe device that needs to communicate with the PCIe controller is determined to be faulty;

[0012] The specific situation includes one or more of the following: situation 1, situation 2, situation 3, situation 4, and situation 5;

[0013] The first scenario is that the state of the data link layer of the PCIe controller switches from a connected state to a disconnected state;

[0014] The second scenario is that the physical layer link state of the PCIe controller switches from the normal operating state to the device detection state;

[0015] The third scenario is when the data link layer is in a connected state, there is a third request whose token waiting time is greater than the first preset value.

[0016] The fourth scenario is that the PCIe controller receives a reset command;

[0017] The fifth situation is when there is a fourth request whose response waiting time is greater than the second preset value;

[0018] The third request is a request received by the PCIe controller from the slave interface of the internal bus for requesting access to the PCIe device; the token wait time is the waiting time for the PCIe device to provide a token supporting the PCIe controller in sending the third request;

[0019] The fourth request is a non-reporting request sent from the slave interface of the internal bus and the PCIe controller to the PCIe device; the response waiting time is the duration for the PCIe device to return the response data or response requested by the fourth request.

[0020] In one example, clearing the first request transmitted on the internal bus connected to the PCIe controller includes:

[0021] If the first request is a write request on the main interface of the internal bus, then a fifth request is sent to the recipient of the first request to clear the first request; wherein the fifth request is used to indicate the writing of preset data.

[0022] In one example, clearing the first request transmitted on the internal bus connected to the PCIe controller includes:

[0023] If the first request is a read request or an atomic operation request on the main interface of the internal bus, then the first request is sent to the recipient of the first request, and the response data of the first request sent by the recipient of the first request is received to clear the first request.

[0024] In one example, clearing the first request transmitted on the internal bus connected to the PCIe controller includes:

[0025] If the first request is a write request on the slave interface of the internal bus, then the first request is acquired, and a write response is sent back to the sender of the first request to clear the first request.

[0026] In one example, clearing the first request transmitted on the internal bus connected to the PCIe controller includes:

[0027] If the first request is a read request or an atomic operation request on the slave interface of the internal bus, then the first request is acquired, and a simulated data response is sent back to the sender of the first request according to the target data requested by the first request, so as to clear the first request; the simulated data response carries invalid data, and the data length of the invalid data is the same as the data length of the target data. Optionally, the content of the invalid data can be all 0s, all 1s, or any other arbitrary value.

[0028] In one example, sending a reset command to the PCIe controller includes:

[0029] If it is determined that all write requests on the internal bus have been cleared and all data requests on the internal bus have been cleared, a reset command is sent to the PCIe controller; the data request is a read request or an atomic operation request.

[0030] In one example, determining that all write requests on the internal bus have been cleared includes:

[0031] Obtain first record information corresponding to the first target interface in the internal bus; wherein, the first target interface is the master interface of the internal bus used for transmitting write requests or the slave interface of the internal bus used for transmitting write requests; the first record information is used to record whether each write request transmitted under the first target interface has received a write acknowledgment; or, the first record information is used to record a count value; the count value is incremented by 1 after a write request is successfully transmitted at the first target interface, and decremented by 1 after a write acknowledgment is successfully received;

[0032] If the first record information indicates that all write requests transmitted by the first target interface are answered, then it is determined that all write requests on the internal bus have been cleared.

[0033] In one example, determining that all data requests on the internal bus have been cleared includes:

[0034] Obtain the second record information corresponding to the second target interface in the internal bus; wherein, the second target interface is the master interface or slave interface of the internal bus used to transmit data requests; the second record information is used to indicate whether all the data requested by each data request transmitted under the second target interface has been obtained; the data request is a read request or an atomic operation request;

[0035] If the second record information indicates that all data requests transmitted by the second target interface have obtained the requested data, then it is determined that all data requests on the internal bus have been cleared.

[0036] Secondly, this application provides an information transmission device, comprising:

[0037] The clearing unit is used to clear any unprocessed first requests on the internal bus to which the PCIe controller is connected if it is determined that a PCIe device that needs to communicate with the high-speed serial computer expansion bus standard PCIe controller is faulty.

[0038] The first sending unit is used to send a reset command to the PCIe controller so that the PCIe controller can complete the reset.

[0039] The acquisition unit is used to acquire a second request transmitted on the slave interface of the internal bus during the period from when the PCIe controller completes a reset until the state of the data link layer of the PCIe controller switches to the connected state.

[0040] The second sending unit is used to send back a simulated response result of the second request to the sender of the second request; the slave interface of the internal bus is an interface used to receive requests from the internal bus to access the PCIe device.

[0041] In one example, the clearing unit is specifically used for:

[0042] If a specific situation is determined, then the PCIe device that needs to communicate with the PCIe controller is determined to be faulty;

[0043] The specific situation includes one or more of the following: situation 1, situation 2, situation 3, situation 4, and situation 5;

[0044] The first scenario is that the state of the data link layer of the PCIe controller switches from a connected state to a disconnected state;

[0045] The second scenario involves determining that the physical layer link state of the PCIe controller has switched from the normal operating state to the device detection state.

[0046] The third scenario is when the data link layer is in a connected state, there is a third request whose token waiting time is greater than the first preset value.

[0047] The fourth scenario is that the PCIe controller receives a reset command;

[0048] The fifth situation is when there is a fourth request whose response waiting time is greater than the second preset value;

[0049] The third request is a request received by the PCIe controller from the slave interface of the internal bus for requesting access to the PCIe device; the token wait time is the waiting time for the PCIe device to provide a token supporting the PCIe controller in sending the third request;

[0050] The fourth request is a non-reporting request sent from the slave interface of the internal bus and the PCIe controller to the PCIe device; the response waiting time is the duration for the PCIe device to return the response data or response requested by the fourth request.

[0051] In one example, the clearing unit is specifically used for:

[0052] If the first request is a write request on the main interface of the internal bus, then a fifth request is sent to the recipient of the first request to clear the first request; wherein the fifth request is used to indicate the writing of preset data.

[0053] Optionally, the preset data can be empty data.

[0054] In one example, the clearing unit is specifically used for:

[0055] If the first request is a read request or an atomic operation request on the main interface of the internal bus, then the first request is sent to the recipient of the first request, and the response data of the first request sent by the recipient of the first request is received to clear the first request.

[0056] In one example, the clearing unit is specifically used for:

[0057] If the first request is a write request on the slave interface of the internal bus, then the first request is acquired, and a write response is sent back to the sender of the first request to clear the first request.

[0058] In one example, the clearing unit is specifically used for:

[0059] If the first request is a read request or an atomic operation request on the slave interface of the internal bus, then the first request is acquired, and a simulated data response is sent back to the sender of the first request according to the target data requested by the first request, so as to clear the first request; the simulated data response carries invalid data, and the data length of the invalid data is the same as the data length of the target data. Optionally, the invalid data can be all 0 values, all 1 values, or any other arbitrary value.

[0060] In one example, the first sending unit is specifically used for:

[0061] If it is determined that all write requests on the internal bus have been cleared and all data requests on the internal bus have been cleared, a reset command is sent to the PCIe controller; the data request is a read request or an atomic operation request.

[0062] In one example, the first sending unit is specifically used for:

[0063] Obtain first record information corresponding to the first target interface in the internal bus; wherein, the first target interface is the master interface of the internal bus used for transmitting write requests or the slave interface of the internal bus used for transmitting write requests; the first record information is used to record whether each write request transmitted under the first target interface has received a write acknowledgment; or, the count value in the first record information is incremented by 1 after a write request is successfully transmitted at the first target interface, and decremented by 1 after a write acknowledgment is successfully received.

[0064] If the first record information indicates that all write requests transmitted by the first target interface are answered, then it is determined that all write requests on the internal bus have been cleared.

[0065] In one example, the first sending unit is specifically used for:

[0066] Obtain the second record information corresponding to the second target interface in the internal bus; wherein, the second target interface is the master interface or slave interface of the internal bus used to transmit data requests; the second record information is used to indicate whether all the data requested by each data request transmitted under the second target interface has been obtained; the data request is a read request or an atomic operation request;

[0067] If the second record information indicates that all data requests transmitted by the second target interface have obtained the requested data, then it is determined that all data requests on the internal bus have been cleared.

[0068] Thirdly, this application provides a chip, comprising: a PCIe controller, an information transmission device as described in any of the second aspects, and at least one functional module; the PCIe controller is connected to the functional module inside the chip through the information transmission device.

[0069] Fourthly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0070] The memory stores computer-executed instructions;

[0071] The processor executes computer execution instructions stored in the memory to implement the method as described in any one of the first aspects.

[0072] Fifthly, this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method as described in any one of the first aspects.

[0073] Sixthly, this application provides a computer program product comprising a computer program that, when executed by a processor, implements the method described in any one of the first aspects.

[0074] This application provides an information transmission method, apparatus, device, and medium. The method includes: if it is determined that a PCIe device that needs to communicate with a PCIe controller is faulty, clearing any unprocessed first requests on the internal bus connected to the PCIe controller; sending a reset command to the PCIe controller to reset it; and during the period from the PCIe controller's reset to the data link layer switching to a connected state, acquiring a second request transmitted on the slave interface of the internal bus and sending a simulated response result of the second request back to the sender of the second request; the slave interface is an interface used to transmit requests to access the PCIe device. In this embodiment, by simulating a response to the second request generated internally by the chip during the period after the PCIe controller is reset and before the data link layer is successfully established, the risk of internal bus jamming caused by the PCIe controller directly sending the corresponding second request during the aforementioned period, as in related technologies, is avoided. Attached Figure Description

[0075] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0076] Figure 1 A flowchart illustrating an information transmission method provided for the implementation of this application;

[0077] Figure 2 A flowchart illustrating another information transmission method provided in an embodiment of this application;

[0078] Figure 3 This is a schematic diagram of the structure of an information transmission device provided in an embodiment of this application;

[0079] Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0080] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0081] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0082] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0083] The AXI (Advanced eXtensible Interface) bus is an on-chip bus designed for high performance, high bandwidth, and low latency. The AXI bus separates request and data transmission; when transmitting read and write requests on the bus, a request operation is considered complete only when the corresponding response is received on the appropriate response channel.

[0084] The PCIe bus is commonly used in computer systems to enable communication between processor chips or I / O bridge chips (or bridge chips) and external PCIe devices.

[0085] The following explanation uses a chip with a built-in PCIe controller as an example. The PCIe controller connects to other functional modules within the chip via an internal bus and provides conversion between the internal bus and the PCIe bus. The interaction between the PCIe controller and the internal bus has two directions: functional modules within the chip use the internal bus to access external PCIe devices through the PCIe controller; and external PCIe devices access functional modules on the chip's internal bus through the PCIe controller. It should be noted that the chip described above can be a processor in a computer system; no other restrictions are imposed in this embodiment.

[0086] Furthermore, when the chip and the PCIe device communicate and access each other, they need to receive each other's tokens before they can send the corresponding access requests.

[0087] When an external PCIe device malfunctions or experiences an abnormal event (such as being unplugged), ongoing internal bus operations performed by the PCIe controller (e.g., read, write, and atomic operations transmitted via the internal bus) may fail to complete or terminate. In such cases, functional modules within the chip accessing the PCIe controller via the internal bus, functional modules within the chip accessed by the PCIe controller via the internal bus, and the internal bus network itself may become stuck due to the inability to complete / terminate internal bus operations. For example, when a PCIe device malfunctions, it cannot provide a token to the chip, causing the chip to become stuck at its own PCIe controller because it cannot obtain the necessary token.

[0088] In one example, when the link state of the physical layer corresponding to the PCIe controller switches from the normal state (referred to as L0 state in the PCIe protocol) to the device detection state (referred to as detect state in the PCIe protocol), it can be considered that the PCIe device has failed. To avoid the risk of the internal bus freezing, a simulated response corresponding to the request already sent through the internal bus is generated, and the internal module is informed that no new requests can be submitted. Afterwards, the PCIe controller is reset so that it can re-establish the link.

[0089] However, in the above method, if the physical layer corresponding to the PCIe controller can be used normally, but a fault occurs inside the PCIe device that prevents it from releasing a new token to the PCIe controller, the PCIe controller will be unable to obtain the token, thus preventing the request from being sent and the corresponding response from being received. Furthermore, the internal bus will also be unable to receive and transmit new requests, leading to the risk of the internal bus freezing.

[0090] Furthermore, if the PCIe controller link still cannot be restored to normal after the PCIe controller is reset, the phenomenon that the access requests received by the PCIe controller from the internal bus will still be stuck at the PCIe controller and cannot be sent out will still occur.

[0091] The information transmission method, apparatus, equipment and medium provided in this application are intended to solve at least one of the above-mentioned technical problems.

[0092] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0093] Figure 1 This is a flowchart illustrating an information transmission method provided in an embodiment of this application, such as... Figure 1 As shown, the method includes the following steps:

[0094] S101. If it is determined that the PCIe device that needs to communicate with the PCIe controller is faulty, then clear the first unprocessed request on the internal bus connected to the PCIe controller.

[0095] For example, the functional modules inside the chip mentioned in this embodiment can communicate with external PCIe devices through a PCIe controller. Furthermore, in this embodiment, the bus connecting the PCIe controller and the functional modules inside the chip is referred to as the internal bus. The execution entity in this embodiment can be an information transmission device; specifically, this information transmission device can be located on the chip's internal bus.

[0096] During chip operation, to avoid the risk of the internal bus freezing, the system continuously monitors for faults in external PCIe devices communicating with the chip. Upon detection of a fault, the system clears the requests transmitted on the internal bus connected to the PCIe controller (i.e., the aforementioned first request). Clearing the first request can be understood as clearing the first request in the protocol layer corresponding to the PCIe controller (which may include the transaction layer, data layer, and physical layer).

[0097] It should be noted that this embodiment does not impose specific limitations on the method for detecting whether a PCIe device is faulty. Specifically, the fault can be detected by a circuit external to the chip used for PCIe device fault detection, or it can be determined by a fault detection circuit internal to the chip. For example, the faultiness of a PCIe device connected to the PCIe controller can be determined by detecting the connection status of the physical layer corresponding to the PCIe controller.

[0098] Furthermore, in this embodiment, an unprocessed first request can be understood as a first request currently being processed on the internal bus, i.e., a request that is being processed but has not yet finished. When the first request is a write request, the write request is considered complete only when a write response is received. When the first request is a read request or an atomic operation request, the read request or atomic operation request is considered complete only when the requested data or request result is returned. The number of first requests can be one or more. When there are multiple first requests, each first request can be cleared. In this embodiment, there is no specific limit to the number of first requests to be cleared. In addition, clearing the first request can be understood as a process to ensure the end of the sending and responding process of the first request. Specifically, the response corresponding to the first request can be simulated to clear the situation of the first request. The simulated response here is not a real response result, but a false response generated to end the first request.

[0099] It should be noted that the internal bus in this embodiment has a master interface and a slave interface. The master interface of the internal bus can be understood as the interface on the internal bus used to transmit access requests issued by PCIe devices to access the functional modules inside the chip. The access requests can be read requests, write requests, atomic operation requests, etc., and no specific restrictions are imposed in this embodiment. The slave interface of the internal bus can be understood as the interface on the internal bus used to transmit requests issued by the functional modules inside the chip to access the PCIe devices. The requests can be read requests, write requests, atomic operation requests, etc., and no specific restrictions are imposed in this embodiment.

[0100] S102. Send a reset command to the PCIe controller to make the PCIe controller complete the reset.

[0101] For example, after the first request is cleared, a reset command can be sent to the PCIe controller so that the PCIe controller can perform clearing, resetting, or other processing.

[0102] In one possible implementation, during a PCIe controller reset, access to the PCIe device via the internal bus can be prevented; for example, this can be achieved by setting an interrupt within the chip. The process here is similar to that in the prior art and will not be described in detail here.

[0103] S103. During the period from when the PCIe controller completes its reset to when the data link layer of the PCIe controller switches to the connected state, the second request transmitted from the slave interface of the internal bus is acquired, and a simulated response result of the second request is fed back to the sender of the second request; the slave interface is an interface used to receive requests from the internal bus to access the PCIe device.

[0104] For example, in this embodiment, after the PCIe controller completes a reset, because the PCIe controller's data link layer needs to re-establish the data link or there is a risk that the data link cannot be successfully established after the reset, the PCIe controller will not immediately process the second request (i.e., the request to access the PCIe device) generated by the chip's internal module before the data link layer can be used normally (i.e., before the data link layer's state switches from the disconnected state to the connected state). Instead, the information transmission device will first obtain the second request transmitted from the interface and generate a simulated response result corresponding to the second request based on the received second request. It should be noted that the simulated response result here is not the real result fed back by the PCIe device after the second request is sent to the PCIe device, but a simulated false response result. That is, in this embodiment, the second request is not sent to the PCIe device after being processed by the PCIe controller, but is intercepted and obtained by the information transmission device in the path of the second request being transmitted to the PCIe controller, and the information transmission device feeds back the corresponding simulated response result to the requester of the second request. By adopting this technical solution, the communication interaction between the second request and its corresponding response can be completed on the internal bus. Subsequent second requests will not be blocked on the internal bus, thus avoiding the chip getting stuck during the period when the data link layer cannot be successfully connected after the PCIe controller is reset, which would affect the use of the chip.

[0105] It should be noted that the connection state of the data link layer in this application can be represented as DL_Up in the protocol, and the disconnection state of the data link layer can be represented as DL_Down in the protocol.

[0106] In one possible implementation, after the PCIe controller resets and the data link layer returns to the connected state, the information transmission device no longer executes the above information transmission process. Instead, the PCIe controller continues to process the request for communication between the internal functional modules of the chip and the external PCIe device.

[0107] Understandably, compared to related technologies where the PCIe controller is immediately granted permission to send access requests to PCIe devices after a PCIe controller reset, in this embodiment, when the PCIe controller resets but the data link layer has not successfully established a connection, the access request is not processed by the PCIe controller. Instead, the access request is intercepted by the information transmission device. This is to avoid the risk of the internal bus freezing due to the inability to obtain the corresponding response result for access requests generated inside the chip before the data link layer of the PCIe controller has been successfully established.

[0108] Figure 2A flowchart illustrating another information transmission method provided in this application embodiment is shown below. Figure 2 As shown, the method includes the following steps:

[0109] S201. It has been determined that the PCIe device that needs to communicate with the PCIe controller is faulty.

[0110] This embodiment uses an information transmission device as an example to illustrate the execution subject.

[0111] In one example, step S201 includes the following steps:

[0112] If a specific condition is identified, then the PCIe device that needs to communicate with the PCIe controller is determined to be faulty.

[0113] Among them, the specific situations include one or more of the following: situation one, situation two, situation three, situation four, and situation five;

[0114] The first scenario is when the PCIe controller's data link layer state switches from connected to disconnected; the second scenario is when the PCIe controller's physical layer link state switches from normal operation to device detection; the third scenario is when, while the data link layer is in a connected state, a token wait time for a third request exceeds a first preset value; the fourth scenario is when the PCIe controller receives a reset command; the fifth scenario is when a response wait time for a fourth request exceeds a second preset value; the third request is a request received by the PCIe controller from the slave interface of the internal bus to request access to the PCIe device; the token wait time is the waiting time for the PCIe device to provide a token supporting the PCIe controller in sending the third request;

[0115] The fourth request is a non-posted request sent by the PCIe controller to the PCIe device via the internal bus slave interface; the response wait time is the duration for the PCIe device to return the response data or response requested by the fourth request.

[0116] It should be noted that a Non-Posted request is considered complete only after all corresponding responses are received after it is sent on the PCIe link. Here, the PCIe link can be understood as the transmission medium required for information exchange between PCIe devices and the functional modules inside the chip.

[0117] For example, this embodiment provides five scenarios that indicate a PCIe device is faulty. In practical applications, a PCIe device can be determined to be faulty when any of the above scenarios are met.

[0118] First scenario: The data link layer state of the PCIe controller switches from connected to disconnected; Second scenario: The physical layer link state of the PCIe controller switches from normal operation to device detection.

[0119] For example, both of the above scenarios involve the PCIe link corresponding to the PCIe controller failing to connect normally. In this scenario, the failure of the PCIe link prevents communication with the PCIe device. Therefore, in this scenario, the PCIe device can be considered to be faulty, and the internal bus of the chip is protected to avoid the phenomenon of internal bus jamming.

[0120] The third scenario: When the data link layer is in a connected state, after the PCIe controller receives a third request to access the PCIe device, the waiting time for the PCIe device's authorization token information exceeds a first preset value. That is, the PCIe controller waits for a considerable time without obtaining the token required by the PCIe device to allow the PCIe controller to send the third request. In this scenario, to avoid internal bus congestion caused by the long token waiting time, it can be assumed that the PCIe device is faulty, and the corresponding information transmission process is initiated (i.e., the protection method provided in this application embodiment is executed). It should be noted that when accessing a PCIe device, the accessed party typically needs to send a token packet to the accessing party. The token packet includes the number of tokens for various types of requests provided by the accessed party. If, when the accessing party sends an access request, there are still unused tokens for the corresponding request type, and the number of tokens meets the requirement for sending the access request, then the access request can be sent to the accessed party.

[0121] Fourth scenario: It is determined that the PCIe controller has received a reset command.

[0122] It should be noted that in this scenario, after the PCIe controller performs a reset operation, it needs to re-establish communication with the PCIe device. During this re-establishment process, the internal functional modules of the chip (i.e., the chip that needs to access the PCIe device through the PCIe controller) cannot communicate with the PCIe device. Therefore, the aforementioned information transmission process can still be initiated in this scenario. Furthermore, in this embodiment, the command instructing the PCIe controller to perform a reset operation can be a reset command sent from within the chip to the PCIe controller, or a reset command transmitted on the PCIe link connected externally to the chip; no specific limitations are imposed in this embodiment.

[0123] Fifth scenario: If a Non-Posted request initiated by a functional module within the chip (i.e., the fourth request mentioned above) is sent to the PCIe device, and the waiting time for the corresponding response data or response feedback result (referred to as the response waiting time in this embodiment) exceeds the second preset value, then the PCIe device is considered to be faulty. That is, when a Non-Posted request fails to obtain the requested data or response for a long time, it can easily lead to other access requests within the chip being unable to be sent, and the already sent Non-Posted requests failing to receive results, resulting in bus congestion within the chip. It should be noted that the aforementioned Non-Posted request can be a read request issued by the chip, an atomic operation request, an IO write request, or a configuration write request in practical applications; no specific restrictions are made in this embodiment. An atomic operation request refers to an uninterruptible operation or series of operations, meaning that the operation will not be interrupted by any other transaction or event before completion. When the PCIe controller performs an atomic operation, sending a single request is sufficient to complete the three steps of reading the original value of the destination address, modifying the original value, and returning the original value.

[0124] The response waiting time can be timed as follows: Timing begins after a Non-Posted request is sent to the PCIe device, or after an internal functional module sends a Non-Posted request to the internal bus. The timer resets to zero when the requested response data or response is returned. This timing method can be used to record whether there are any Non-Posted requests that have not received a complete response (e.g., all data or all responses), allowing for the estimation of PCIe device malfunctions based on the timing results. Optionally, if the current response data or response does not represent all the data or responses requested, the timer continues counting from 0 until the next corresponding response data is received, and the process repeats. Compared to accumulating time on the existing timer data when not all response data is returned, the method of starting timing from 0 effectively reduces the required timer bit width. Once all the data or response corresponding to the request has been returned, the Non-Posted request is no longer timed.

[0125] Understandably, in this embodiment, the PCIe device is determined to be faulty by considering scenarios such as the PCIe data layer link status, physical layer link status, whether a reset command has been received, whether there is a long response waiting time for a Non-Posted request, or whether a token has not been received for a long time. This is to further reduce the possibility of internal bus jamming within the chip and to ensure the normal operation of the chip.

[0126] S202. If there is an unprocessed first request on the internal bus, and the first request is a write request on the main interface of the internal bus, then a fifth request is sent to the recipient of the write request to clear the first request; wherein, the fifth request is used to indicate that preset data is written.

[0127] For example, in this embodiment, after determining that the PCIe device is faulty, if an unprocessed write request is detected on the main interface of the internal bus, i.e., the first request is a write request on the main interface, the data in the ongoing write request may be abnormal or inaccurate due to the PCIe device failure. Therefore, in order to ensure the normal transmission of the write request, a fifth request carrying preset data is sent to the recipient of the first request. For example, the preset data can be a string of all zeros, and the length of the string is the same as the length of the data to be written that is expected to be carried in the original write request.

[0128] Understandably, in this embodiment, when a PCIe device malfunctions, write requests transmitted via the main interface of the internal bus can continue to be processed. That is, the fifth request in this embodiment can replace the continued transmission of the aforementioned write requests, thus completing the processing of write requests on the internal bus and ensuring that write requests on the internal bus are cleared before the PCIe device is reset. This avoids the internal bus freezing caused by directly interrupting incomplete write requests.

[0129] S203. If there is an unprocessed first request on the internal bus, and the first request is a read request or an atomic operation request on the main interface of the internal bus, then send the first request to the recipient of the first request; and receive the response data of the first request sent by the recipient of the first request to clear the first request.

[0130] For example, after step S201, if it is determined that there is a read request or atomic operation request initiated by a PCIe device on the internal bus (i.e., the first request is a read request or atomic operation request on the main interface of the internal bus), the received read request or atomic operation request will continue to be sent to the receiver of the first request inside the chip. Furthermore, the request result fed back by the receiver of the first request based on the first request will also be received. Therefore, by continuing to execute the read request or atomic operation request on the main interface of the internal bus and completing the reception of the request result corresponding to the above request, it is ensured that both the read request and the atomic operation request on the main interface of the internal bus can be completed on the internal bus, avoiding a scenario where the request gets stuck on the internal bus and cannot continue execution.

[0131] It should be noted that for write requests, atomic operation requests, and read requests initiated by PCIe devices, if the above requests have not yet been processed and transmitted through the internal bus, the unprocessed requests in the data link layer corresponding to the PCIe controller can be cleared through the subsequent reset operation of the PCIe controller.

[0132] S204. If there is an unprocessed first request on the internal bus, and the first request is a write request on the slave interface of the internal bus, then the first request is obtained, and a write response is sent back to the sender of the first request to clear the first request.

[0133] For example, the scenario mentioned in this step is a situation where a PCIe device malfunctions, but the internal bus is still transmitting and processing write requests for writing data from the chip to the PCIe device. In this scenario, the information transmission device intercepts the write request; that is, the write request will not be sent to the PCIe controller, and the information transmission device generates a write response based on the intercepted write request. It should be noted that this write response is used to inform the sender of the write request (i.e., the sender of the first request) that the processing of the write request has been completed. However, this write response is not actually generated by the PCIe device after the write request is sent to it; rather, it is a spurious response. This is to end all processing of the write request on the internal bus and avoid bus freezing caused by the inability to obtain the corresponding request response due to a PCIe device malfunction.

[0134] S205. If there is an unprocessed first request on the internal bus, and the first request is a read request or an atomic operation request on the slave interface of the internal bus, then the first request is obtained, and a simulated data response is sent back to the sender of the first request according to the target data requested by the first request, so as to clear the first request; the simulated data response carries invalid data, and the data length of the invalid data is the same as the data length of the target data.

[0135] For example, in this embodiment, when a PCIe device malfunction is determined, if there is an unprocessed first request on the chip's internal bus, and this first request is a read request or atomic operation request from within the chip to access the PCIe device, in order to terminate the processing flow of the first request on the internal bus, the information transmission device in this embodiment will intercept the first request, that is, it will not transmit the first request to the PCIe controller, and based on the acquired first request, it will send back invalid data with the same data length as the target data requested by the first request to the sender of the first request, so as to terminate the processing of the first request. The invalid data sent back is not the actual data expected by the first request, but only simulated pseudo-data. In this embodiment, there is no specific restriction on the value of the invalid data; for example, it can be a sequence of all 0s or all 1s, or a sequence of any values. It is understood that through the above processing, it can be ensured that read requests and atomic operation requests appearing on the slave interface of the internal bus are cleared, so as to avoid the internal bus from freezing.

[0136] S206. If it is determined that all write requests on the internal bus have been cleared and all data requests on the internal bus have been cleared, a reset command is sent to the PCIe controller to cause the PCIe controller to complete the reset; the data request is a read request or an atomic operation request.

[0137] For example, in this embodiment, after ensuring that all write requests, all read requests, and all atomic operation requests on the internal bus (i.e., all requests that have started processing but have not yet been completed) are cleared, the information transmission device can send a reset command to the PCIe controller so that the PCIe controller can perform a reset process. In addition, during the reset process, the PCIe controller will also delete any requests that have not yet been processed in the data link layer.

[0138] Understandably, clearing all unprocessed requests on the internal bus before sending a reset command can reduce the likelihood of the internal bus freezing.

[0139] In one example, determining whether a request on the internal bus has been cleared can be done by the information transmission device receiving the request monitoring results from other detection devices, or by the information transmission device itself detecting the request processing results on the internal bus. That is, there is no specific restriction on whether the information transmission device itself has the above-mentioned function (i.e., the function of detecting whether a request on the internal bus has been cleared).

[0140] In one example, it is determined that all write requests on the internal bus have been cleared, including:

[0141] Obtain the first record information corresponding to the first target interface in the internal bus; wherein, the first target interface is the master interface of the internal bus used to transmit write requests or the slave interface of the internal bus used to transmit write requests; the first record information is used to record whether each write request transmitted by the first target interface has received a write acknowledgment; or, the first record information is used to record a count value; the count value is incremented by 1 after the first target interface successfully transmits a write request, and decremented by 1 after successfully receiving a write acknowledgment; if the first record information indicates that all write requests transmitted by the first target interface have been acknowledged, then it is determined that all write requests on the internal bus have been cleared.

[0142] For example, in this embodiment, both the master interface and the slave interface on the internal bus used for transmitting write requests have their own first record information. The first record information is used to record the monitoring results of the write requests in the corresponding first target interface, wherein the monitoring results are used to indicate whether the write request processing has ended.

[0143] In one possible implementation, the first record information can record the unique identifier assigned to each write request transmitted in the first target interface, and each identifier corresponds to a vector. When the write response corresponding to the write request is returned on the internal bus, the vector corresponding to the unique identifier of the write request is cleared to indicate that the write request has been processed. If the write response corresponding to the write request has not yet been returned on the internal bus, the vector corresponding to the unique identifier of the write request can be set to 1. Furthermore, the first record information can also include a write status identifier. If the vectors corresponding to all successfully transmitted write requests are 0, and no other unprocessed write requests continue to appear on the first target interface (i.e., all write requests transmitted through the internal bus (including those successfully transmitted or those in progress when a fault is detected) have been responded to), the write status identifier can be set to 1 to indicate that the channel corresponding to the first target interface is currently cleared; otherwise, the write status identifier can be set to 0 to indicate that the channel corresponding to the first target interface is not currently cleared.

[0144] In one possible implementation, the first record information stores a counter value. When a write request is detected on the first target interface, this counter value is incremented by 1; when a write acknowledgment is received, the counter value is decremented by 1; when the counter value returns to its initial value and no further write requests appear on the first target interface, it indicates that the channel corresponding to the first target interface is cleared, i.e., the channel in the internal bus is cleared. Similarly, the first record information can also be set with the write status flag described above, which will not be elaborated here. Optionally, the initial value can be 0. Optionally, in one scenario, if a write request is transmitted simultaneously and a write acknowledgment is successfully received within the same clock cycle, the counter value can remain unchanged within that clock cycle.

[0145] In one possible implementation, the write request can be determined directly by obtaining the write status flag from the first record information to determine whether it has been cleared. The method for determining the write status flag can refer to the two implementation methods mentioned above, and will not be elaborated further here.

[0146] It is understood that in this embodiment, the processing status of write requests on the first target interface of the internal bus can be recorded so that subsequent information transmission devices can quickly determine whether the transmission channel of write requests on the internal bus has been cleared.

[0147] In one example, it is determined that all data requests on the internal bus have been cleared, including:

[0148] Obtain the second record information corresponding to the second target interface in the internal bus; wherein, the second target interface is the master interface or slave interface of the internal bus used to transmit data requests; the second record information is used to indicate whether all data requested by each data request transmitted under the second target interface has been obtained; the data request is a read request or an atomic operation request; if the second record information indicates that all data requests transmitted by the second target interface have obtained the requested data, then it is determined that all data requests on the internal bus have been cleared.

[0149] For example, in this embodiment, the second target interface is either a master interface for transmitting read requests or atomic operation requests on the internal bus, or a slave interface on the internal bus for transmitting read requests or atomic operation requests. Both the master and slave interfaces for transmitting read requests and atomic operation requests have their own corresponding second record information. This second record information can be used to indicate whether the read requests or atomic operation requests transmitted on the second target interface have received all the requested data. If the second record information determines that all successfully transmitted data requests have successfully obtained all the corresponding data, and there are no incomplete data requests at the second target interface—that is, after all data requests transmitted through the second target interface have obtained the requested data—then it indicates that all data requests have been cleared.

[0150] For example, the second record information may record the unique identifier assigned to each data request and the indication information corresponding to each data request, wherein the indication information is used to indicate whether all the data expected by the data request has been successfully received.

[0151] Optionally, the second record information may also record the amount of unreturned data corresponding to the data request. For example, when a data request is successfully sent, the amount of unreturned data is equal to the total amount of data expected. When a response to the data request is received, the amount of unreturned data can be updated in real time based on the data carried in the response. If the amount of unreturned data is cleared, it is determined that all data of the data request has been successfully returned, and the corresponding indication information can be adjusted from 1 to 0 to indicate that the data request has been processed.

[0152] Optionally, the second record information may also record the number of timers in which no data was returned for the data request. The number of timers is the quotient of the data volume and the internal bus width, and may also indicate the amount of data that was not returned.

[0153] Optionally, the second record information may also include a request status identifier, which indicates whether the channel corresponding to the second target interface has been cleared. This request status identifier can be determined based on the indication information in the second record information. If, based on the indication information in the second record information, it is determined that all data requests transmitted at the second target interface have been processed, then the channel corresponding to the current second target interface is cleared.

[0154] It is understood that in this embodiment, the processing status of read requests and atomic operations on the second target interface of the internal bus can be recorded to determine whether the channel corresponding to the second target interface of the internal bus has been cleared. This facilitates the subsequent information transmission device to quickly determine whether the transmission channel on the internal bus has been cleared.

[0155] S207. During the period from when the PCIe controller completes its reset to when the state of the PCIe controller's data link layer switches to the connected state, the second request transmitted from the slave interface of the internal bus is acquired, and a simulated response result of the second request is sent back to the sender of the second request.

[0156] For example, the technical principle of step S207 can be found in step S103, and will not be repeated here.

[0157] Understandably, in this embodiment, by real-time monitoring of requests transmitted on the internal bus, it is possible to quickly determine whether the internal bus has been cleared when a PCIe device malfunctions. Furthermore, when a PCIe device malfunctions, different requests from different interfaces are processed differently to clear the requests on the internal bus and prevent it from becoming stuck.

[0158] Figure 3 This is a schematic diagram of the structure of an information transmission device provided in an embodiment of this application, as shown below. Figure 3 As shown, the device includes:

[0159] Clear unit 301 is used to clear the first unprocessed request on the internal bus to which the PCIe controller is connected if it is determined that a PCIe device that needs to communicate with the high-speed serial computer expansion bus standard PCIe controller is faulty.

[0160] The first sending unit 302 is used to send a reset command to the PCIe controller so that the PCIe controller can complete the reset.

[0161] The acquisition unit 303 is used to acquire the second request transmitted from the slave interface of the internal bus during the period from when the PCIe controller completes a reset to when the state of the data link layer of the PCIe controller switches to the connected state.

[0162] The second sending unit 304 is used to send back the simulated response result of the second request to the sender of the second request; the slave interface of the internal bus is an interface used to receive requests from the internal bus to access the PCIe device.

[0163] In one example, clearing cell 301 is specifically used for:

[0164] If a specific condition is identified, then the PCIe device that needs to communicate with the PCIe controller is determined to be faulty.

[0165] Among them, the specific situations include one or more of the following: situation one, situation two, situation three, situation four, and situation five;

[0166] The first scenario is that the data link layer state of the PCIe controller switches from the connected state to the disconnected state;

[0167] The second scenario is that the physical layer link state of the PCIe controller switches from the normal working state to the device detection state;

[0168] The third scenario is when the data link layer is in a connected state, there is a third request whose token waiting time is greater than the first preset value;

[0169] The fourth scenario is that the PCIe controller receives a reset command;

[0170] The fifth scenario is when there is a fourth request whose response waiting time is greater than the second preset value;

[0171] The third request is a request received by the PCIe controller from the slave interface of the internal bus to request access to the PCIe device; the token wait time is the waiting time for the PCIe device to send the token that supports the PCIe controller in sending the third request;

[0172] The fourth request is a Non-Posted request sent from the internal bus slave interface and PCIe controller to the PCIe device; the response wait time is the duration for the PCIe device to return the response data or response requested in the fourth request.

[0173] In one example, clearing a cell is specifically used for:

[0174] If the first request is a write request on the main interface of the internal bus, then a fifth request is sent to the recipient of the first request to clear the first request; wherein the fifth request is used to indicate that preset data is written.

[0175] Optionally, the preset data can be empty.

[0176] In one example, clearing a cell is specifically used for:

[0177] If the first request is a read request or an atomic operation request on the main interface of the internal bus, then the first request is sent to the recipient of the first request, and the response data of the first request sent by the recipient of the first request is received to clear the first request.

[0178] In one example, clearing a cell is specifically used for:

[0179] If the first request is a write request on the slave interface of the internal bus, then the first request is acquired and a write response is sent back to the sender of the first request to clear the first request.

[0180] In one example, clearing a cell is specifically used for:

[0181] If the first request is a read request or an atomic operation request on the slave interface of the internal bus, then the first request is acquired, and a simulated data response is sent back to the sender of the first request according to the target data requested in the first request, so as to clear the first request; the simulated data response carries invalid data, and the data length of the invalid data is the same as the data length of the target data. Optionally, the invalid data can be all 0 values, all 1 values, or any other arbitrary value.

[0182] In one example, the first transmitting unit is specifically used for:

[0183] If it is determined that all write requests on the internal bus have been cleared and all data requests on the internal bus have been cleared, a reset command is sent to the PCIe controller; the data request is a read request or an atomic operation request.

[0184] In one example, the first transmitting unit is specifically used for:

[0185] Obtain the first record information corresponding to the first target interface in the internal bus; wherein, the first target interface is the master interface of the internal bus used to transmit write requests or the slave interface of the internal bus used to transmit write requests; the first record information is used to record whether each write request transmitted under the first target interface has received a write acknowledgment; or, the count value in the first record information is incremented by 1 after a write request is successfully transmitted at the first target interface, and decremented by 1 after a write acknowledgment is successfully received.

[0186] If the first record information indicates that all write requests transmitted by the first target interface have been acknowledged, then it is determined that all write requests on the internal bus have been cleared.

[0187] In one example, the first transmitting unit is specifically used for:

[0188] Obtain the second record information corresponding to the second target interface in the internal bus; wherein, the second target interface is the master interface or slave interface of the internal bus used to transmit data requests; the second record information is used to indicate whether all the data requested by each data request transmitted under the second target interface has been obtained; the data request is a read request or an atomic operation request;

[0189] If the second record information indicates that all data requests transmitted by the second target interface have obtained the requested data, then it is determined that all data requests on the internal bus have been cleared.

[0190] The apparatus provided in this embodiment is used to implement the technical solution provided by the above method. Its implementation principle and technical effect are similar, and will not be described again.

[0191] Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of this application, such as... Figure 4As shown, the chip includes: a PCIe controller, an information transmission device, and at least one functional module (three are used as an example in the figure); the PCIe controller is connected to the functional modules inside the chip through the information transmission device.

[0192] For example, the functional modules in this embodiment can communicate with external PCIe devices via an information transmission device and a PCIe controller. When the PCIe device is functioning normally, the information transmission device transmits data transparently on the internal bus. However, when a PCIe device malfunction is detected, the information transmission device intercepts requests that the functional modules need to send out, simulates and generates corresponding responses, and sends them back to prevent the internal bus from becoming stuck. Specifically, the bus protection method corresponding to the information transmission device when the PCIe device malfunctions can be found in the description of the above embodiments, and will not be repeated here.

[0193] This application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0194] The memory stores the instructions that the computer executes;

[0195] The processor executes computer execution instructions stored in memory to implement the information transmission method as described in the above embodiments.

[0196] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 5 As shown, the electronic device includes:

[0197] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can invoke logical instructions stored in the memory 292 to execute the methods of the above embodiments.

[0198] Furthermore, the logic instructions in the aforementioned memory 292 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0199] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, thereby implementing the methods in the above-described method embodiments.

[0200] The memory 292 may include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 292 may include high-speed random access memory and may also include non-volatile memory. The electronic device in this embodiment can be used to implement the source server or target server described in the above embodiments.

[0201] This application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement any of the methods.

[0202] This application provides a computer program product, which includes a computer program that, when executed by a processor, implements any one of the methods.

[0203] A non-transitory computer-readable storage medium, wherein when the instructions in the storage medium are executed by the processor of a terminal device, the terminal device is able to execute the aforementioned screen splitting method.

[0204] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0205] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An information transmission method, characterized in that, include: If it is determined that a PCIe device that needs to communicate with a high-speed serial computer expansion bus standard PCIe controller is faulty, then clear the first unprocessed request on the internal bus to which the PCIe controller is connected. Send a reset command to the PCIe controller to cause the PCIe controller to complete a reset; During the period from when the PCIe controller completes a reset until the state of the PCIe controller's data link layer switches to the connected state, the second request transmitted from the slave interface of the internal bus is acquired, and a simulated response result of the second request is sent back to the sender of the second request. The slave interface is an interface used to receive requests from the internal bus to access the PCIe device.

2. The method according to claim 1, characterized in that, The determination that a PCIe device that needs to communicate with the PCIe controller is faulty includes: If a specific situation is determined, then the PCIe device that needs to communicate with the PCIe controller is determined to be faulty; The specific situation includes one or more of the following: situation 1, situation 2, situation 3, situation 4, and situation 5; The first scenario is that the state of the data link layer of the PCIe controller switches from a connected state to a disconnected state; The second scenario is that the physical layer link state of the PCIe controller switches from the normal operating state to the device detection state; The third scenario is when the data link layer is in a connected state, there is a third request whose token waiting time is greater than the first preset value. The fourth scenario is that the PCIe controller receives a reset command; The fifth situation is when there is a fourth request whose response waiting time is greater than the second preset value; The third request is a request received by the PCIe controller from the slave interface of the internal bus for requesting access to the PCIe device; the token wait time is the waiting time for the PCIe device to provide a token supporting the PCIe controller in sending the third request; The fourth request is a non-reporting request sent from the slave interface of the internal bus and the PCIe controller to the PCIe device; the response waiting time is the duration for the PCIe device to return the response data or response requested by the fourth request.

3. The method according to claim 1, characterized in that, The first request to clear the transmission on the internal bus connected to the PCIe controller includes: If the first request is a write request on the main interface of the internal bus, a fifth request is sent to the recipient of the first request to clear the first request; wherein the fifth request is used to indicate writing preset data; the main interface is the interface on the internal bus used to transmit access requests sent by the PCIe controller.

4. The method according to claim 1, characterized in that, The first request to clear the transmission on the internal bus connected to the PCIe controller includes: If the first request is a read request or an atomic operation request on the main interface of the internal bus, then the first request is sent to the recipient of the first request, and the response data of the first request sent by the recipient of the first request is received to clear the first request.

5. The method according to claim 1, characterized in that, The first request to clear the transmission on the internal bus connected to the PCIe controller includes: If the first request is a write request on the slave interface of the internal bus, then the first request is acquired, and a write response is sent back to the sender of the first request to clear the first request.

6. The method according to claim 1, characterized in that, The first request to clear the transmission on the internal bus connected to the PCIe controller includes: If the first request is a read request or an atomic operation request on the slave interface of the internal bus, then the first request is obtained, and a simulated data response is sent back to the sender of the first request according to the target data requested by the first request, so as to clear the first request; the simulated data response carries invalid data, and the data length of the invalid data is the same as the data length of the target data.

7. The method according to any one of claims 1-6, characterized in that, Sending a reset command to the PCIe controller includes: If it is determined that all write requests on the internal bus have been cleared and all data requests on the internal bus have been cleared, a reset command is sent to the PCIe controller; the data request is a read request or an atomic operation request.

8. The method according to claim 7, characterized in that, Determining that all write requests on the internal bus have been cleared includes: Obtain first record information corresponding to the first target interface in the internal bus; wherein, the first target interface is the master interface of the internal bus used for transmitting write requests or the slave interface of the internal bus used for transmitting write requests; the first record information is used to record whether each write request transmitted under the first target interface has received a write acknowledgment; or, the first record information is used to record a count value; the count value is incremented by 1 after a write request is successfully transmitted at the first target interface, and decremented by 1 after a write acknowledgment is successfully received; If the first record information indicates that all write requests transmitted by the first target interface are answered, then it is determined that all write requests on the internal bus have been cleared.

9. The method according to claim 7, characterized in that, The step of determining that all data requests on the internal bus have been cleared includes: Obtain the second record information corresponding to the second target interface in the internal bus; wherein, the second target interface is the master interface or slave interface of the internal bus used to transmit data requests; the second record information is used to indicate whether all the data requested by each data request transmitted under the second target interface has been obtained; the data request is a read request or an atomic operation request; If the second record information indicates that all data requests transmitted by the second target interface have obtained the requested data, then it is determined that all data requests on the internal bus have been cleared.

10. An information transmission device, characterized in that, The device includes: The clearing unit is used to clear any unprocessed first requests on the internal bus to which the PCIe controller is connected if it is determined that a PCIe device that needs to communicate with the high-speed serial computer expansion bus standard PCIe controller is faulty. The first sending unit is used to send a reset command to the PCIe controller so that the PCIe controller can complete the reset. The acquisition unit is used to acquire a second request transmitted on the slave interface of the internal bus during the period from when the PCIe controller completes a reset until the state of the data link layer of the PCIe controller switches to the connected state. The second sending unit is used to send back a simulated response result of the second request to the sender of the second request; the slave interface is an interface used to receive requests from the internal bus to access the PCIe device.

11. A chip, characterized in that, include: The PCIe controller, the information transmission device as described in claim 10, and at least one functional module; The PCIe controller is connected to the functional modules inside the chip through the information transmission device.

12. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 9.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 9.

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