Master and slave verification method based on bus communication, chip, computer readable storage medium and printing system

Abstract

The invention discloses a master and slave verification method based on bus communication, comprising: receiving a first instruction from a master, the first instruction being used for instructing the slave to perform verification calculation; receiving a first request from the host; judging whether a preset first event occurs or not; if the preset first event occurs, sending a first mark to the host; receiving a second request from the host; judging whether a preset second event occurs or not; and sending an algorithm result to the host in response to judging that the preset second event occurs, wherein the slave is configured to not send the algorithm result before judging that the preset second event does not occur. And the slave is configured to not send the algorithm result before judging that the preset second event does not occur, so that the situation that the slave is exposed to security information or enters an unexpected state due to program conflicts is avoided, and the security of the system is improved.

Description

Technical Field

[0001] This invention relates to the field of master-slave communication interaction technology based on bus communication, and specifically to a master-slave verification method, chip, computer-readable storage medium, and printing system based on bus communication. Background Technology

[0002] Many systems have replaceable parts essential for their operation. These replaceable parts often contain consumable materials that are depleted with each use of the system. Such systems typically include, for example, drinking water systems with replaceable filters, medical systems that dispense medications with replaceable dispensers, and printing systems that dispense fluids or solids with replaceable dispensers. Verifying that the replaceable dispenser is a reliable device from a legitimate manufacturer can help system users avoid using defective or counterfeit equipment. As mentioned above, verifying the reliability of the replaceable dispenser for use in certain systems can help system users avoid problems associated with the unintentional use of defective or counterfeit equipment. For example, in printing systems that use consumable toners or ink cartridges, accidentally replacing the cartridge with a counterfeit one can lead to a range of problems, from poor print quality to leaky cartridges that can damage the printing system.

[0003] Methods for authenticating replaceable devices typically involve strong authentication methods using a secret key known to a secure microcontroller on both the replaceable supply device (capable of dispensing fluids or solids, etc.) and the host device (e.g., an image forming device). If the replaceable device can prove its legitimacy by issuing a correct response to the host (typically an authentication response to the key), the host will infer that the device is from the original manufacturer and authenticate it. However, a weakness of this authentication method is its reliance on the system's ability to store the secret key. If an attacker can recover all the keys from the host or the replaceable device, they can store the keys in the microcontroller of an illegitimate replaceable supply device, causing it to produce the same correct response as a trusted device from the original manufacturer. Summary of the Invention

[0004] To address the problems in existing technologies where slave devices expose security information or enter unexpected states due to program conflicts, and where malicious hosts occupy bus resources through high-frequency requests, this application provides a master-slave verification method based on bus communication, applied to a slave device. The slave device includes a second control unit and a second memory. The method includes: receiving a first instruction from a master device, the first instruction instructing the slave device to perform verification calculations; receiving a first request from the master device; determining whether a preset first event has occurred; if the preset first event has occurred, sending a first flag to the master device, the first flag indicating that the slave device is in a first waiting state while processing the first instruction; receiving a second request from the master device; determining whether a preset second event has occurred; and in response to determining that the preset second event has occurred, sending an algorithm result to the master device; wherein the slave device is configured not to send the algorithm result until it is determined that the preset second event has not occurred. In particular, the slave device is configured not to send the algorithm result until a preset second event (such as the dynamically calculated target response time) occurs. Instead, it maintains the communication connection through an intermediate flag or protects the bus through a negative character. This ensures the integrity of the communication protocol while preventing the slave device from exposing security information or entering an unexpected state due to program conflicts, thus improving the security of the system.

[0005] Secondly, this application provides a chip, including: a communication interface configured to communicate with a host via a bus; a second memory for storing instructions and data; and a second control unit connected to the communication interface and the second memory. The second control unit is configured to perform the following operations: receive a first instruction from the host via the communication interface; receive a first request from the host via the communication interface; determine whether a preset first event has occurred; if the preset first event has occurred, send a first flag to the host via the communication interface, the first flag indicating that the slave device is in a first waiting state while processing the first instruction; receive a second request from the host via the communication interface; determine whether a preset second event has occurred; and in response to determining that the preset second event has occurred, send an algorithm result to the host via the communication interface; wherein the second control unit is configured not to send the algorithm result before determining that the preset second event has not occurred.

[0006] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the master-slave verification method based on bus communication as described above.

[0007] Fourthly, this application provides a printing system, including a host and a chip as described above; the host includes a first control unit and a first memory, the first control unit being configured to send the first instruction, the first request and the second request to the chip, and to receive the algorithm result to verify the legitimacy of the chip. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A block diagram illustrating the host and slave device connection provided in an embodiment of this application is shown;

[0010] Figure 2 The illustration shows a flowchart of a master-slave verification method based on bus communication provided in an embodiment of this application;

[0011] Figure 3 This illustration shows a block diagram of the master and slave communication in a master-slave verification method based on bus communication provided in an embodiment of this application.

[0012] Figure 4 A block diagram illustrating the connection between the host and the chip provided in an embodiment of this application is shown;

[0013] Figure 5 A block diagram of a printing system provided in an embodiment of this application is shown. Detailed Implementation

[0014] To address the issues of fixed slave response times in existing technologies, which are vulnerable to side-channel attacks, and malicious hosts occupying bus resources through high-frequency requests, a master-slave verification method based on bus communication is proposed.

[0015] like Figure 1As shown, the host 10 includes a first control unit 11 and a first memory 12. The first control unit 11 communicates with slave devices 20 via a bus, which utilizes a communication transmission protocol such as an Inter-Integrated Circuit (I2C) bus or a Serial Peripheral Interface (SCI). In some instances, the host 10 is connected to one or more slave devices 20 via an I2C bus (containing two bidirectional serial data lines (SDA) and a serial clock line (SCL)). Each slave device 20 includes a second control unit 21 and a second memory 22. The first control unit 11 is configured as the master node of the bus, and the second control unit 21 in each slave device 20 is configured as a slave node. In some embodiments, the first control unit 11 and the second control unit 21 can be any of a central processing unit (CPU), a semiconductor-based microprocessor, a graphics processing unit (GPU), an FPGA, an ASIC, and / or other hardware devices suitable for retrieving and executing instructions stored in memory. The processor can fetch, decode, and / or execute instructions stored in memory (e.g., contact connectivity determination instructions). Additionally or alternatively, the processor may include one or more electronic circuits, which include electronic components for performing one or more functions of instructions.

[0016] In some embodiments, the first memory 12 and the second memory 22 can be any electronic, magnetic, optical, or other physical storage device that contains or stores electronic information (e.g., instructions and / or data). The memory can be, for example, random access memory (RAM), electrically erasable programmable read-only memory (EEPROM), storage devices, optical discs, etc. In some examples, the memory can be volatile and / or non-volatile memory, such as dynamic random access memory (DRAM), EEPROM, magnetoresistive random access memory (MRAM), phase-change RAM (PCRAM), flash memory, etc. In some implementations, the memory can be a non-transitory tangible machine-readable storage medium, where the term "non-transitory" does not cover transient propagation signals. In some examples, the memory can include multiple devices (e.g., RAM cards and solid-state drives (SSDs)).

[0017] like Figure 2As shown, from the start to step 101, in step 101, the second control unit 21 of the slave device 20 receives a first instruction from the master device 10. Specifically, the first control unit 11 of the master device 10 sends the first instruction to the second control unit 21 of the slave device 20 via the SDA line of the bus. After receiving the first instruction, all second control units 21 connected to the bus compare the address code of the slave device 20 included in the first instruction with their own address code. If the address codes match, it means that the current first instruction instructs the current slave device 20 to respond. In some embodiments, in addition to including the address code of the slave device 20, the first instruction also includes a write operation code with a write bit set to represent a write request value, which represents an operation to write data. The data to be written here can refer to rewritable or immutable data that is useful for operation, such as the firmware version number, manufacturing date, serial number, and electronic signature of the master device 10 in the first memory 12. In some embodiments, the address code and write opcode of the first instruction are composed of binary codes. The address code indicates the address where data is to be written in the array of the second memory 22, and the last code following the address code is the write opcode, which indicates that the current first instruction is a data write operation. Specifically, the address code in the first instruction can be 7 bits, and the write opcode can be 1 bit. In general, the address code comes first, and the write opcode comes last. For example, 0x20 (0010 0000) represents a write operation (0) to address (0010 000). Conversely, in some embodiments, the first instruction can also be a data read operation. Specifically, the address code can be 7 bits, and the read opcode can be 1 bit. The positions of the address code and read opcode are the same as those of the address code and write opcode described above. For example, 0x21 (0010 0001) represents a read operation (1) to address (0010 000). In some embodiments, the content represented by the first instruction consisting of the address code and the write opcode is not limited to the above examples. For example, the first instruction may have the write opcode first and the address second, or it may include a first instruction for verification requests and / or continuous read requests. This application does not impose any restrictions here.

[0018] In some embodiments, the first instruction also corresponds to the start condition (S), whereby all slave devices 20, including the second control unit 21, enter a ready-to-work state from an idle state to prepare to receive the first instruction sent by the first control unit 11 of the master 10 via the SDA line of the bus. The first instruction here also includes algorithm parameters N, which can be used to authenticate the legitimacy of the slave device 20, detect the remaining capacity of the slave device 20, or test whether normal communication exists between the master and slave devices 20. In some embodiments, the first instruction also includes algorithm execution data, which can instruct the slave device 20 to calculate the algorithm parameters N.

[0019] In step 102, a first message is sent to the host 10 in response to the first instruction. Specifically, the first message here represents an acknowledgment character (ACK), indicating that the second control unit 21 for address matching has acknowledged receiving the first instruction sent from the first control unit 11 and is ready to receive the next request or instruction sent from the first control unit 11. In some embodiments, after the host 10 sends the first instruction, the first control unit 11 of the host 10 actively releases the SDA line and controls the SCL line to generate a pulse. At this time, the second control unit 21 of the matched slave 20, after identification, will pull the SDA line low during the pulse generation period of the SCL line and send an acknowledgment character (ACK) through the SDA line. When the host 10 detects that the SDA line is pulled low, it means that the addressing is successful. If a negative acknowledgment character (NACK) is sent, it is considered that the addressing has failed, and the host 10 can terminate the transmission or resend the instruction or request to the slave 20 so that the appropriate slave 20 can be successfully addressed.

[0020] In step 103, at least one first request is received from the host 10. The first control unit 11 sends the first request to the second control unit 21 via the SDA line on the bus, and the second control unit 21 receives the first request from the host 10. In some embodiments, the first request can be a write request or a read request. A write request can be a request to write rewritable or immutable data useful for operation, such as the firmware version number, manufacturing date, serial number, and electronic signature of the host 10, to the second memory 22. A read request can be a request to read rewritable or immutable data, such as the firmware version number, manufacturing date, serial number, electronic signature, consumable type, consumable color, and consumption data of the slave 20, stored in the second memory 22. In some embodiments, the first request is only an address, without any write or read operations. In some embodiments, the first request can be a request with only an address code, requiring the second control unit 21 of the slave 20 to respond to the current state.

[0021] In step 104, it is determined whether a preset first event has occurred. Here, the first preset event can be a time attribute representing a preset time, such as 1ms, 2ms, or 5ms. In some embodiments, when the first preset event is a time attribute, the start point of the preset time can be the time when the first information is sent to the host 10, that is, the timestamp when the host 10 receives the first information; or it can be the time when the first instruction sent by the host 10 is received, that is, the timestamp when the slave 20 receives the first instruction; and the end point of the preset time can be a timestamp 1ms, 2ms, 5ms... after the time the first information is sent to the host 10, or a timestamp 1ms, 2ms, 5ms... after the time the first instruction is received by the host 10.

[0022] If the preset first event does not occur in step 104, proceed to step 105. In step 105, each time the second control unit 21 receives a first request from the host 10, it sends a second message to the first control unit 11 of the host 10. This second message represents the negative character NACK, indicating that the communication bus is in a locked state, also known as a bus protection state. This prevents the host 10 from maliciously repeating read and write requests and excessively consuming the computing resources of the second control unit 21 of the slave 20, ensuring that the first instruction in the second control unit 21 can be processed correctly. After completing step 105, return to step 103 to receive the first request from the host 10 again. Proceed to step 104 again to continue determining whether the preset first event has occurred. This cycle repeats.

[0023] If a preset first event is detected, in step 106, the second control unit 21 will send a first flag to the first control unit 11 of the host 10 in response to the read request. Specifically, here, the second control unit 21 of the slave 20 sends the first flag containing the first information to the first control unit 11 of the host 10 via the SDA line. The first flag indicates that the slave 20 is in an initial waiting state (first non-idle state, busy state, and first waiting state), that is, it indicates that the slave 20 is processing the first instruction sent by the first control unit 11 of the host 10. Figure 3 As shown, in some embodiments, during step 106, the second control unit 21 sends first information before sending the first flag to the first control unit 11 of the host 10 or during sending the first flag to the first control unit 11 of the host 10. The first information here is the same as the first information representing the ACK character mentioned above.

[0024] In step 107, the second control unit 21 of the slave device 20 receives a second instruction from the master device 10. The first control unit 11 sends the second instruction to the second control unit 21 via the SDA line on the bus. In some embodiments, the second instruction may have the same format as the first instruction described above. In other embodiments, the second instruction may have a shorter format than the first instruction. For example, it may only have an address code without any data or read / write opcodes. In some embodiments, the address code of the second instruction in step 107 is the same as the address code of the first instruction in step 101, enabling the slave device 20 to respond quickly to the second instruction.

[0025] In step 108, the second control unit 21 of the slave device 20 sends first information to the first control unit 11 of the master device 10 in response to the second instruction, indicating that the second control unit 21, whose address code matches the address code in the second instruction, has confirmed receipt of the first instruction sent by the first control unit 11, and is ready to receive the next request or instruction sent from the first control unit 11. In some embodiments, after the master device 10 sends the second instruction, the first control unit 11 of the master device 10 actively releases the SDA line and controls the SCL line to generate a pulse.

[0026] In step 109, a second request is received from the first control unit 11 of the host 10. In some embodiments, the second request may be a write request or a read request. A write request may be a request to write rewritable or immutable data useful for operation, such as the firmware version number, manufacturing date, serial number, and electronic signature of the host 10, to the second memory 22. A read request may be a request to read rewritable or immutable data, such as the firmware version number, manufacturing date, serial number, electronic signature, consumable type, consumable color, and consumption data of the slave 20, stored in the second memory 22. In some embodiments, the first request is only an address and does not involve any write or read operations.

[0027] In step 110, it is determined whether a preset second event has occurred. In some embodiments, the second preset event is a preset event that can be dynamically adjusted according to the read request of the second control unit 21, relative to the first preset event. Here, the second preset event can be a time attribute that represents a preset time that can be dynamically adjusted, such as 5ms, 10ms, or 20ms, just like the first preset event described above; it can also be a threshold attribute that can be dynamically adjusted to experience one or more events (e.g., an event of receiving one or more first requests consecutively before the first instruction is processed); it can also be a flag attribute that can be dynamically adjusted to indicate that the second control unit 21 of the slave 20 has finished processing the first instruction; or it can be an adjustment attribute that can be dynamically adjusted based on the algorithm parameter N of the first instruction as a dynamic adjustment factor. Taking the adjustment attribute as an example, if the first instruction issued by the host 10 includes the algorithm parameter N, and the preset time of the previous read request is 5ms, the second preset event is adjusted according to the algorithm parameter N of the first instruction as a dynamic adjustment factor. Specifically, the second control unit 21 of the slave device 20 parses the algorithm parameter N. If N ≥ 3, T1 = 5ms, and T2 = T1 + K*N (K is a preset coefficient, such as 10ms / time), then T2 = 5ms + 10ms*3 = 35ms. Within 35ms, the second control unit 21 of the slave device 20 completes the execution of the first instruction in step 101, but waits 35ms before responding to the algorithm result. The second control unit 21 can control the timing of responding to the algorithm result, preventing attackers from performing side-channel analysis through response time.

[0028] If it is determined in step 110 that no preset second event has occurred, proceed to step 111. In step 111, the second control unit 21 of the slave device 20 sends a second flag to the first control unit 11 of the host device 10. In some embodiments, the second flag represents that the slave device 20 is in a second waiting state (second non-idle, busy state), or it can represent that the slave device 20 is processing the first instruction, or it can represent that the slave device 20 is waiting for the second preset event to occur. This indicates that the second control unit 21 is responding to the fact that the first instruction in step 101 has not yet been processed, thereby preventing the host device 10 from maliciously making repeated read and write requests and excessively occupying the computing resources of the second control unit 21 of the slave device 20, so as to ensure that the first instruction in the second control unit 21 can be processed correctly. Then return to step 107, re-receive the second instruction sent from the first control unit 11 of the host device 10, and continuously execute steps 108 to 110. Until it is determined in step 110 that a preset second event has occurred, then jump to step 112. Figure 3 As shown, in some embodiments, during step 111, the second control unit 21 sends first information before or during sending the second flag to the first control unit 11 of the host 10. This first information is the same as the first information representing the ACK character mentioned above.

[0029] In step 112, the second control unit 21 of the slave device 20 sends the algorithm result to the first control unit 11 of the host device 10 in response to the second request. In some embodiments, the algorithm result is the result of processing the algorithm parameters of the second control unit 21 of the slave device 20 according to the first instruction sent by the first control unit 11 of the host device 10 in step 101. Figure 3 As shown, in some embodiments, the second control unit 21 sends first information before sending the algorithm result to the first control unit 11 of the host 10 or during the sending of the algorithm result to the first control unit 11 of the host 10. This first information is the same as the first information representing the ACK character mentioned above. In some embodiments, even after the second control unit 21 has processed the first instruction in step 101, it still needs to wait for the occurrence of a second preset event before sending the algorithm result to the first control unit 11 of the host 10.

[0030] In step 103, when the second control unit 21 of the slave device 20 receives the first request from the first control unit 11 of the master device 10, it records the timestamp and source address of the received first request. If the first control unit 11 of the master device 10 sends more than M read requests (e.g., M≥2) within the timestamp specified in step 103, and using the same source address, the slave device 20 temporarily locks that address, rejects subsequent read and write requests, and records a security event. After step 103, the second control unit 21 of the slave device 20 will only respond once, automatically clearing the relevant state of the first instruction to prevent the reuse of historical instructions.

[0031] To perform the corresponding steps in the above embodiments and various possible methods, a chip 40 is provided below. Further, as... Figure 4 As shown, the chip 40 provided in this embodiment has the same basic principle and technical effect as the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. Chip 40 includes: a communication interface configured to communicate with host 10 via a bus; a second memory 22 for storing instructions and data; and a second control unit 21 connected to the communication interface and the second memory 22. Understandably, the second control unit 21 is capable of performing the above steps 101-112: receiving a first instruction from host 10 via the communication interface; receiving a first request from host 10 via the communication interface; determining whether a preset first event has occurred; if the preset first event has occurred, sending a first flag to host 10 via the communication interface, the first flag indicating that slave 20 is in a first waiting state while processing the first instruction; receiving a second request from host 10 via the communication interface; determining whether a preset second event has occurred; and in response to determining that the preset second event has occurred, sending an algorithm result to host 10 via the communication interface; wherein the second control unit 21 is configured not to send the algorithm result before determining that the preset second event has not occurred.

[0032] The second control unit 21 is further configured to: if it is determined that the preset first event has not occurred, send a second message to the host 10; wherein the second message is a negative character, indicating that the communication bus is in a locked state, which can also be called a bus protection state, thereby preventing the host 10 from maliciously making repeated read and write requests and excessively occupying the computing resources of the second control unit 21 of the slave 20, so as to ensure that the first instruction in the second control unit 21 can be correctly processed. After sending the second message, the slave 20 returns to the operation of receiving the first request from the host 10.

[0033] The second control unit 21 is further configured to: if it is determined that the preset second event has not occurred, send a second flag to the host 10; wherein the second flag is used to indicate that the slave 20 is in a second waiting state of processing the first instruction or waiting for the preset second event to occur; after sending the second flag, the slave 20 returns to the operation of receiving the second instruction from the host 10.

[0034] The first instruction includes an algorithm parameter N, and the algorithm result is calculated by the slave device 20 based on the algorithm parameter N. The preset second event is a time-attribute event. When the second control unit 21 determines whether the preset second event has occurred, the second control unit 21 is configured to: parse the first instruction to obtain the algorithm parameter N; determine the target response time corresponding to the preset second event based on the algorithm parameter N as a dynamic adjustment factor; and determine whether the current time has reached the target response time.

[0035] The second control unit 21 determines whether a preset first event has occurred by: determining whether the time elapsed since sending the response information for the first instruction or since receiving the first instruction has reached a first preset time threshold.

[0036] The second control unit 21 is further configured to: when receiving the first request from the host 10, record the received timestamp and source address; determine whether the number of times the first request is received within a limited timestamp and from the same source address exceeds a preset threshold M; if it exceeds the preset threshold M, lock the source address and reject subsequent read or write requests.

[0037] The second control unit 21 is further configured to: after sending the algorithm result to the host 10 through the communication interface in response to determining that the preset second event has occurred, it further includes: automatically clearing the relevant status of the first instruction and the algorithm result.

[0038] The chip 40 provided in this application embodiment introduces a dual verification mechanism of a first preset event and a second preset event through the control of the second control unit 21. In particular, the slave device 20 is configured not to send the algorithm result before determining that the preset second event has not occurred, but instead to indicate the current state to the master device 10 through the first flag and the second flag to maintain the communication connection or protect the bus. This ensures the integrity of the communication protocol while hiding the actual algorithm calculation time, thereby improving the security of the system.

[0039] Optionally, the above modules can be stored in the form of software or firmware. Figure 1The second memory 22 shown may be stored in or embedded in the operating system (OS) of the chip 40, and may be generated by... Figure 1 The second control unit 21 in the system executes the commands. Simultaneously, the data and program code required to execute the aforementioned modules can be stored in memory.

[0040] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0041] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0042] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0043] like Figure 5As shown, a printing system is provided, including a host 10 and the aforementioned chip 40; the host 10 includes a first control unit 11 and a first memory 12, the first control unit 11 is configured to send the first instruction, the first request and the second request to the chip 40, and receive the algorithm result to verify the legitimacy of the chip 40.

[0044] Preferably, after receiving the first flag or the second flag, the host 10 maintains its occupation of the bus or resends the first request or the second request after a predetermined time until it receives the algorithm result.

[0045] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A master-slave verification method based on bus communication, characterized in that, Applied to a slave device, the slave device including a second control unit and a second memory, the method includes: Receive a first instruction from the host, the first instruction being used to instruct the slave to perform a verification calculation; Receive a first request from the host; Determine if the preset first event has occurred; If the preset first event occurs, a first flag is sent to the host, the first flag being used to indicate that the slave is in a first waiting state while processing the first instruction; Receive a second request from the host; Determine whether a pre-set second event has occurred; and In response to the determination that the preset second event has occurred, the algorithm result is sent to the host; The slave device is configured not to send the algorithm result until it determines that the preset second event has not occurred.

2. The method of claim 1, wherein, Prior to the step of receiving the second request from the host, the method further includes: Receive a second instruction from the host, and send first information to the host in response to the second instruction; The second instruction is used to trigger the slave device to prepare to respond to the second request.

3. The method according to claim 1, characterized in that, After the step of determining whether a preset first event has occurred, the method further includes: If it is determined that the preset first event has not occurred, send the second information to the host; The second information is a negative character, indicating that the communication bus is in a locked state. After sending the second information, the slave device returns to the step of receiving the first request from the host.

4. The method according to claim 2, characterized in that, After the step of determining whether a preset second event has occurred, the method further includes: If it is determined that the preset second event has not occurred, a second flag is sent to the host; The second flag is used to indicate that the slave device is in a second waiting state, either processing the first instruction or waiting for the preset second event to occur. After sending the second flag, the slave device returns to the step of receiving the second instruction from the host.

5. The method according to claim 1, characterized in that, The first instruction includes algorithm parameters N, and the algorithm result is calculated by the slave device based on the algorithm parameters N; The preset second event is a time-attributed event, and determining whether the preset second event has occurred includes: Parse the first instruction to obtain the algorithm parameter N; The target response time corresponding to the preset second event is determined based on the algorithm parameter N as a dynamic adjustment factor; Determine whether the current time has reached the target response time.

6. The method according to claim 5, characterized in that, Determining the target response time corresponding to the preset second event includes: The target response time T2 is calculated using the formula T2 = T1 + K * N; Where T1 is the basic preset time, K is the preset coefficient, and N is the algorithm parameter; The slave device hides the actual algorithm calculation completion time before the target response time T2 arrives.

7. The method according to claim 1, characterized in that, The first instruction includes an address code and a write opcode, and the first request and the second request include an address code and a read opcode; The first information and the first flag include an acknowledgment character; The algorithm results include verification data generated based on the first instruction.

8. The method according to claim 1, characterized in that, The determination of whether a preset first event has occurred includes: Determine whether the time elapsed since sending the response information to the first instruction or since receiving the first instruction has reached a first preset time threshold.

9. The method according to claim 1, characterized in that, The method further includes: Upon receiving the first request from the host, record the timestamp of receipt and the source address; Determine whether the number of times the first request is received within a limited timestamp and from the same source address exceeds a preset threshold M; If the preset threshold M is exceeded, the source address is locked, and subsequent read or write requests are rejected.

10. The method according to claim 1, characterized in that, After the step of sending the algorithm result to the host in response to determining that the preset second event has occurred, the method further includes: Automatically clear the relevant status of the first instruction and the algorithm result.

11. A chip, characterized in that, include: The communication interface is configured to communicate with the host via a bus; The second memory is used to store instructions and data; as well as A second control unit, connected to the communication interface and the second memory, is configured to perform the following operations: Receive a first instruction from the host through the communication interface; Receive a first request from the host through the communication interface; Determine if the preset first event has occurred; If the preset first event occurs, a first flag is sent to the host through the communication interface. The first flag is used to indicate that the slave is in a first waiting state while processing the first instruction. Receive a second request from the host through the communication interface; Determine if a pre-set second event has occurred; as well as In response to the determination that the preset second event has occurred, the algorithm result is sent to the host through the communication interface; The second control unit is configured not to send the algorithm result before determining that the preset second event has not occurred.

12. The chip according to claim 11, characterized in that, The second control unit is also configured to: If it is determined that the preset first event has not occurred, send the second information to the host; The second information is a negative character, indicating that the communication bus is in a locked state. After sending the second information, the slave device returns to the operation of receiving the first request from the host.

13. The chip according to claim 11, characterized in that, The second control unit is also configured to: If it is determined that the preset second event has not occurred, a second flag is sent to the host; The second flag is used to indicate that the slave device is in a second waiting state, either processing the first instruction or waiting for the preset second event to occur. After sending the second flag, the slave device returns to the operation of receiving the second instruction from the host.

14. The chip according to claim 11, characterized in that, The first instruction includes an algorithm parameter N, and the algorithm result is calculated by the slave device based on the algorithm parameter N; The preset second event is a time-attribute event. When determining whether the preset second event has occurred, the second control unit is configured as follows: Parse the first instruction to obtain the algorithm parameter N; The target response time corresponding to the preset second event is determined based on the algorithm parameter N as a dynamic adjustment factor; Determine whether the current time has reached the target response time.

15. The chip according to claim 11, characterized in that, The second control unit determines whether a preset first event has occurred, including: Determine whether the time elapsed since sending the response information to the first instruction or since receiving the first instruction has reached a first preset time threshold.

16. The chip according to claim 11, characterized in that, The second control unit is also configured to: Upon receiving the first request from the host, record the timestamp of receipt and the source address; Determine whether the number of times the first request is received within a limited timestamp and from the same source address exceeds a preset threshold M; If the preset threshold M is exceeded, the source address is locked, and subsequent read or write requests are rejected.

17. The chip according to claim 11, characterized in that, The second control unit is also configured to: After responding to the determination that the preset second event has occurred and sending the algorithm result to the host through the communication interface, the method further includes: Automatically clear the relevant status of the first instruction and the algorithm result.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 10.

19. A printing system, characterized in that, Includes the host and the chip as described in any one of claims 11 to 17; The host includes a first control unit and a first memory. The first control unit is configured to send the first instruction, the first request, and the second request to the chip, and to receive the algorithm result to verify the legitimacy of the chip.

20. The printing system according to claim 19, characterized in that, After receiving the first flag or the second flag, the host maintains its access to the bus or resends the first request or the second request after a predetermined time until it receives the algorithm result.

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