SoC reset circuit generation method based on node negotiation

Abstract

The invention provides a SoC reset circuit generation method based on node negotiation. The SoC reset circuit generation method comprises the following steps: step 1, defining reset node connection information and a reset negotiation rule; step 2, acquiring original code information containing reset node connection information; step 3, generating a connection structure of a reset tree according to a reset negotiation rule; and step 4, generating a final SoC reset circuit according to the reset node connection structure, and completing generation of the SoC reset circuit based on node negotiation. The design efficiency of the reset circuit generation method is improved, the design flexibility of the reset circuit generation method is enhanced, the code quality of the reset circuit generation method is improved, and the complexity is reduced while the intuition is kept.

Description

Technical Field

[0001] This invention relates to a method for generating a SoC reset circuit, and more particularly to a method for generating a SoC reset circuit based on node negotiation. Background Technology

[0002] This section provides only background information relevant to this disclosure and is not necessarily prior art.

[0003] In modern System-on-Chip (SoC) design flows, the variability of IP modules and application scenarios frequently leads to changes in reset requirements and their architecture. This presents a challenge: chip design engineers need to update the reset architecture diagram and corresponding code synchronously with each change. Frequent changes and synchronous updates not only increase the complexity of the design phase but also the likelihood of errors, consequently extending the development cycle. Although methods for generating reset code based on tables or schematics exist, these methods typically require engineers to meticulously draw every component and its relationships. This process is not only tedious but also increases the probability of errors, especially with increasing architectural complexity.

[0004] To address the aforementioned technical problems, the prior art, specifically the invention patent application CN116301775A entitled "Code Generation Method, Apparatus, and Device Based on Chip Reset Tree Prototype Diagram," proposes a method based on a reset tree prototype diagram. While this method is visually intuitive, constructing a detailed prototype diagram is extremely time-consuming and error-prone. For complex and large-scale reset networks, even minor modifications may require extensive manual adjustments and verification.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] Purpose of the invention: The technical problem to be solved by the present invention is to provide a method for generating SoC reset circuit based on node negotiation, which addresses the shortcomings of the prior art.

[0007] To address the aforementioned technical problems, this invention discloses a method for generating a SoC reset circuit based on node negotiation, comprising the following steps:

[0008] Step 1: Define the reset node connection information and reset negotiation rules;

[0009] Step 2: Obtain the raw code information containing the reset node connection information;

[0010] Step 3: Generate the connection structure of the reset tree according to the reset negotiation rules;

[0011] Step 4: Based on the reset node connection structure, generate the final SoC reset circuit to complete the generation of the SoC reset circuit based on node negotiation.

[0012] Furthermore, the definition of the reset node connection information includes:

[0013] Define the reset node and connector.

[0014] Furthermore, the definition of the reset node includes:

[0015] Define the reset node parameters and reset node type.

[0016] Furthermore, the reset node parameters include incoming edge parameters and outgoing edge parameters.

[0017] Furthermore, the incoming edge parameter represents the negotiation result with the upstream reset node, providing the current reset node with information from the upstream reset node.

[0018] Furthermore, the outgoing edge parameter represents the negotiation result with the downstream reset node, providing the downstream reset node with information about the current reset node.

[0019] Furthermore, the reset node types include: reset source node, reset routing node, and reset destination node; wherein,

[0020] The reset source node is the starting point in the reset tree and is used to provide the initial reset signal;

[0021] The reset source node includes: a power-on reset node, a watchdog reset node, and an external reset node;

[0022] The reset source node needs to be configured with an effective voltage level;

[0023] The reset source node only has outgoing edge parameters, and the outgoing edge parameters of the reset source node contain the reset information in the reset source node;

[0024] The reset routing node, acting as an intermediary in the reset tree, is used for reset signal distribution and management, including: reset extension, reset merging, and reset synchronization;

[0025] The reset routing node includes: a reset delay node and a reset synchronization node; the reset routing node also includes a custom type of reset routing node.

[0026] The reset routing node has incoming edge parameters and outgoing edge parameters. The incoming edge parameters of the reset routing node are the negotiation results between the reset routing node and the upstream reset node, and the outgoing edge parameters of the reset routing node are the negotiation results between the node and the downstream reset node.

[0027] The reset destination node is the termination point in the reset tree, used to receive and consume reset signals;

[0028] The reset target node includes: IP node, CPU node, JTAG node, UART node, and DSP node;

[0029] The reset destination node receives a reset signal from the upstream reset node;

[0030] The reset destination node only has incoming edge parameters, which are the result of negotiation with the upstream node.

[0031] Furthermore, the definition of the connector includes:

[0032] The connection symbol <- is used as the connector to indicate the connection direction of nodes according to the connection rules, and to generate incoming edge parameters and outgoing edge parameters for each connection.

[0033] Furthermore, the connection rules include:

[0034] The reset nodes on the left and right sides of the connector are the slave node and the master node, respectively;

[0035] Reset routing nodes to allow direct connections;

[0036] Each time a reset node is connected, it creates either an incoming edge parameter or an outgoing edge parameter for the reset nodes on both sides.

[0037] The reset source node is the master node relative to the reset routing node and the reset destination node; the reset routing node is the slave node relative to the reset source node and the master node relative to the reset destination node; the reset destination node is the slave node relative to the reset source node and the reset routing node.

[0038] Furthermore, the reset negotiation rules described in step 3 include:

[0039] Rule 1: For each reset source node, determine whether it participates in reset extension, reset merging, and reset synchronization;

[0040] Rule 2: For each reset destination node, determine all reset source nodes that affect the reset destination node;

[0041] Rule 3: Set the reset valid level for the reset source node and the reset destination node;

[0042] Rule 4: Determine whether the reset trigger of the reset target node is independent;

[0043] Rule 5: Determine whether each reset destination node requires reset extension and reset synchronization.

[0044] Beneficial effects:

[0045] 1. This invention improves the design efficiency of the reset circuit generation method: it reduces the amount of manual work in the design, verification and code generation process, and reduces the possibility of errors.

[0046] 2. This invention enhances the design flexibility of the reset circuit generation method: it can easily cope with changes during the design phase and adapt to different design requirements through simple parameter adjustments or node negotiation, rather than performing tedious manual adjustments.

[0047] 3. This invention improves the code quality of the reset circuit generation method: the automatically generated Verilog code reduces errors and inconsistencies introduced by manual coding.

[0048] 4. This invention reduces complexity while retaining intuitiveness: Although it does not rely on complex prototype diagrams, it still provides sufficient intuitiveness and ease of understanding through the logical expression of nodes and the description of relationships, assisting designers in making decisions and verifications. Attached Figure Description

[0049] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0050] Figure 1 This is a schematic diagram of the overall process of the present invention.

[0051] Figure 2 This is a schematic diagram of the original code information in one embodiment.

[0052] Figure 3 This is a schematic diagram of the structure corresponding to the node connections in one embodiment.

[0053] Figure 4 This is a schematic diagram of the final circuit generated in one embodiment. Detailed Implementation

[0054] This invention proposes a node negotiation-based method for generating SoC reset circuits. This method utilizes a negotiation mechanism between nodes to achieve dynamic, flexible construction and adjustment of the reset structure. Compared to methods based on schematics or tables, the node negotiation-based method provides a more streamlined, intuitive, and robust solution for handling varied and complex design requirements, reducing the burden on engineers in detailed design and modification, while maintaining the system's robustness and flexibility. The overall approach is as follows:

[0055] By introducing three different types of reset node definitions (reset source node, reset routing node, and reset destination node) and a negotiation-based parameter and circuit generation mechanism, a more flexible and efficient reset network management scheme is provided.

[0056] First, through clear node definitions, this invention makes the construction of reset networks more structured and modular. The classification of reset source nodes, reset routing nodes, and reset destination nodes provides a clear hierarchy for the entire system, allowing designers to better understand and manage complex reset networks. Compared with traditional reset circuit design methods, this greatly simplifies the design process and improves design efficiency. It not only maintains a certain degree of intuitiveness but also significantly reduces the complexity of the design process.

[0057] Secondly, the negotiation-based parameter and reset circuit generation mechanism provides significant flexibility for specific applications. By setting different reset negotiation rules, designers can automatically determine the actual configuration of the reset source and reset level transition according to specific needs and constraints. This adaptive design method not only reduces the workload of manual configuration and optimization but also ensures optimal performance of the reset network. Compared to traditional methods, this rule-based automatic configuration is more intelligent and efficient, helping to solve reset circuit design problems in complex systems.

[0058] In summary, the innovative concepts and techniques introduced in this invention for reset network design provide an effective solution to the technical challenges in reset circuit design, making the design process more efficient and concise.

[0059] The specific technical solution of the present invention is as follows:

[0060] A method for generating a SoC reset circuit based on node negotiation, the overall process is as follows: Figure 1 As shown, it depends on the definition of three different types of nodes, two parameter types, and a connector.

[0061] Two parameter types:

[0062] Reset node incoming edge parameters: It represents the negotiation result with the upstream node and provides the current node with information from the upstream node.

[0063] Reset node outgoing edge parameters: It represents the negotiation result with downstream nodes and provides downstream nodes with information about the current node.

[0064] Three types of nodes:

[0065] Reset source nodes: These are the starting points for resets, such as power-on reset, watchdog reset, or external reset. For a reset source node, its valid voltage level and other information must be input. A reset source node only has reset output parameters, which contain information about each reset operation within that reset source node. The number of reset source nodes can be arbitrary.

[0066] Reset routing nodes: These act as intermediaries in the reset tree, responsible for distributing and managing resets. Reset routing nodes can be further subdivided into reset delay nodes, reset synchronization nodes, etc. Each reset routing node contains both reset incoming edge parameters and reset outgoing edge parameters. The reset incoming edge parameters are the result of negotiation with the upstream node, while the reset outgoing edge parameters are the result of negotiation with the downstream node. Based on the parameter negotiation results, this node may generate multiple circuit instances. The subdivisions of routing nodes can be customized and extended.

[0067] Reset Destination Nodes: These are the termination points for the reset, such as IP addresses, CPUs, and DSPs. They receive reset signals from the reset routing node or directly from the reset source node. The reset destination node only has reset incoming edge parameters, which are the result of negotiation with upstream nodes. The number of reset destination nodes can be arbitrary.

[0068] Connector:

[0069] The connector is represented by "<-". When connecting nodes using the connector, the slave node must be on the left of the connector symbol, and the master node must be on the right. Furthermore, routing nodes can be directly connected. Each time a node is connected, the incoming edge parameters or outgoing edge parameters of both adjacent nodes are reset.

[0070] Of the three types of nodes, the reset source node is the master node relative to both the reset route node and the reset destination node; the reset route node is a slave node relative to the reset source node and a master node relative to the reset destination node; and the reset destination node is a slave node relative to both the reset source node and the reset route node. When describing node connections, slave nodes should be placed to the left of the connection symbol, and master nodes should be placed to the right of the connection symbol. Furthermore, reset route nodes can be directly connected; the route node to the left of the connection symbol is a slave node relative to the reset route node to the right of the connection symbol.

[0071] like Figure 2The diagram shows the original code information used to connect the nodes according to the above definitions. The original code shows that three types of reset source nodes are used: power-on reset node (active low), watchdog reset node (active high), and external reset node (active low); three types of reset routing nodes are used: reset extension node and reset synchronization node; and three types of reset destination nodes are used: CPU node, JTAG node, and DMA node. The power-on reset node, watchdog reset node, and external reset node are all connected as master nodes to the reset extension node. The reset extension node, as a master node, is connected to the reset synchronization node. The reset synchronization node is connected to the reset merging node. Finally, the reset merging node is connected to the three reset destination nodes: the CPU node, JTAG node, and DMA node.

[0072] After defining the node connection information, node negotiation rules are used to negotiate the parameters between nodes. One possible negotiation rule is as follows:

[0073] 1. Each reset source can participate in reset extension, reset merging, and reset synchronization.

[0074] 2. JTAG is only affected by power-on reset.

[0075] 3. The CPU and UART accept a low-level active reset, while the JTAG accepts a high-level active reset.

[0076] 4. The reset triggering of each reset destination node needs to be independent.

[0077] 5. Each reset node needs to be released synchronously.

[0078] Through the above negotiation rules, each node will negotiate specific parameters and circuits, forming a structure as follows: Figure 3 The nodes shown are connected to the corresponding structures.

[0079] Power-on reset node, external reset node, and watchdog reset node: Since each reset source can participate in reset extension, each reset source is connected to the downstream reset extension module.

[0080] Reset extension node: Since the reset triggering of the three reset destination nodes needs to be independent, the reset extension node will establish three independent reset extension modules;

[0081] Reset merging node: Since the reset triggering of the three reset destination nodes needs to be independent, the reset merging node will establish three independent reset merging modules. Because each reset source can participate in reset merging, the source of each reset merging module is a collection of all reset sources; since the CPU node and UART node have no restrictions on reset sources, their corresponding reset merging modules will merge resets from the three reset source nodes (power-on reset, external reset, and watchdog reset); since JTAG can only accept power-on resets, its corresponding reset merging module only merges power-on reset sources.

[0082] Reset Synchronization Node: Since the reset of the three reset destination nodes needs to be released synchronously, the reset synchronization node will establish three independent reset synchronization modules.

[0083] CPU, JTAG, and UART nodes: Directly accept resets from the reset synchronization node.

[0084] Based on the above parameters and connections, the final structure is as follows: Figure 4 The circuit shown.

[0085] In one embodiment, the present invention proposes to apply the above method to the implementation of an actual reset circuit generation method, which can be achieved by the following technical solution:

[0086] 1. Graphical Interface-Based Design Methodology: This method provides designers with an intuitive graphical interface, allowing them to create and connect different types of nodes through simple operations such as drag and drop, thereby constructing reset networks. This approach visualizes the entire design process, making it more intuitive and user-friendly.

[0087] 2. Preset Template Method: This method provides a series of preset reset net templates, allowing designers to select the appropriate template and make necessary modifications. This simplifies the design process but may sacrifice some flexibility.

[0088] 3. Hybrid approach: Combining the advantages of the above methods, for example, a graphical interface can be used for initial design first, and then scripts or programming languages ​​can be used for refinement and optimization.

[0089] In its specific implementation, this application provides a computer storage medium and a corresponding data processing unit. The computer storage medium is capable of storing a computer program, which, when executed by the data processing unit, can run the invention's content regarding a node negotiation-based SoC reset circuit generation method, as well as some or all of the steps in various embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0090] Those skilled in the art will clearly understand that the technical solutions in the embodiments of the present invention can be implemented using computer programs and their corresponding general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of computer programs, i.e., software products. These computer program software products can be stored in a storage medium and include several instructions to cause a device containing a data processing unit (which may be a personal computer, server, microcontroller, MCU, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0091] This invention provides a concept and method for generating a SoC reset circuit based on node negotiation. Many methods and approaches exist for implementing this technical solution; the above description is merely a preferred embodiment of the invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A method for generating a SoC reset circuit based on node negotiation, characterized in that, Includes the following steps: Step 1: Define the reset node connection information and reset negotiation rules; Step 2: Obtain the raw code information containing the reset node connection information; Step 3: Generate the connection structure of the reset tree according to the reset negotiation rules; Step 4: Based on the reset node connection structure, generate the final SoC reset circuit to complete the generation of the SoC reset circuit based on node negotiation.

2. The method for generating a SoC reset circuit based on node negotiation according to claim 1, characterized in that, The defined reset node connection information includes: Define the reset node and connector.

3. The method for generating a SoC reset circuit based on node negotiation according to claim 2, characterized in that, The definition of the reset node includes: Define the reset node parameters and reset node type.

4. The SoC reset circuit generation method based on node negotiation according to claim 3, characterized in that, The reset node parameters include incoming edge parameters and outgoing edge parameters.

5. The method for generating a SoC reset circuit based on node negotiation according to claim 4, characterized in that, The incoming edge parameter represents the negotiation result with the upstream reset node, providing the current reset node with information from the upstream reset node.

6. The method for generating a SoC reset circuit based on node negotiation according to claim 4, characterized in that, The outgoing edge parameter represents the negotiation result with the downstream reset node, providing the downstream reset node with information about the current reset node.

7. The method for generating a SoC reset circuit based on node negotiation according to claim 4, characterized in that, The reset node types include: reset source node, reset routing node, and reset destination node; wherein... The reset source node is the starting point in the reset tree and is used to provide the initial reset signal; The reset source node includes: a power-on reset node, a watchdog reset node, and an external reset node; The reset source node needs to be configured with an effective voltage level; The reset source node only has outgoing edge parameters, and the outgoing edge parameters of the reset source node contain the reset information in the reset source node; The reset routing node, acting as an intermediary in the reset tree, is used for reset signal distribution and management, including: reset extension, reset merging, and reset synchronization; The reset routing node includes: a reset delay node and a reset synchronization node; the reset routing node also includes a custom type of reset routing node. The reset routing node has incoming edge parameters and outgoing edge parameters. The incoming edge parameters of the reset routing node are the negotiation results between the reset routing node and the upstream reset node, and the outgoing edge parameters of the reset routing node are the negotiation results between the node and the downstream reset node. The reset destination node is the termination point in the reset tree, used to receive and consume reset signals; The reset target node includes: IP node, CPU node, JTAG node, UART node, and DSP node; The reset destination node receives a reset signal from the upstream reset node; The reset destination node only has incoming edge parameters, which are the result of negotiation with the upstream node.

8. The method for generating a SoC reset circuit based on node negotiation according to claim 7, characterized in that, The defined connectors include: The connection symbol <- is used as the connector to indicate the connection direction of nodes according to the connection rules, and to generate incoming edge parameters and outgoing edge parameters for each connection.

9. The method for generating a SoC reset circuit based on node negotiation according to claim 8, characterized in that, The connection rules include: The reset nodes on the left and right sides of the connector are the slave node and the master node, respectively; Reset routing nodes to allow direct connections; Each time a reset node is connected, it creates either an incoming edge parameter or an outgoing edge parameter for the reset nodes on both sides. The reset source node is the master node relative to the reset routing node and the reset destination node; the reset routing node is the slave node relative to the reset source node and the master node relative to the reset destination node; the reset destination node is the slave node relative to the reset source node and the reset routing node.

10. The method for generating a SoC reset circuit based on node negotiation according to claim 9, characterized in that, The reset negotiation rules mentioned in step 3 include: Rule 1: For each reset source node, determine whether it participates in reset extension, reset merging, and reset synchronization; Rule 2: For each reset destination node, determine all reset source nodes that affect the reset destination node; Rule 3: Set the reset valid level for the reset source node and the reset destination node; Rule 4: Determine whether the reset trigger of the reset target node is independent; Rule 5: Determine whether each reset destination node requires reset extension and reset synchronization.

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