Visualization method of chip parasitic resistance network, electronic equipment and storage medium

Abstract

The invention discloses a chip parasitic resistance network visualization method, electronic equipment and a storage medium, and relates to the technical field of chips, and the method comprises the steps: obtaining two-dimensional netlist data of parasitic resistance networks generated by all conductor stacking structures in a chip according to a parasitic parameter file of the chip, obtaining a stack structure data table of the chip according to the process parameter file of the chip, and obtaining three-dimensional netlist data of the parasitic resistance network according to the stack structure data table and the two-dimensional netlist data, establishing a first three-dimensional model of the parasitic resistance network according to the three-dimensional netlist data, establishing a second three-dimensional model for generating each stacked structure of the parasitic resistance network according to the process parameter file, and displaying at least part of the first three-dimensional model and a target second three-dimensional model, a user can conveniently and quickly search calculation problems existing in the back-end simulation calculation process based on the three-dimensional information storage table, and the problem search efficiency and accuracy are improved.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method for visualizing chip parasitic resistance networks, an electronic device, and a storage medium. Background Technology

[0002] The post-layout simulation stage of integrated circuit (IC) design requires calculating and simulating the physical characteristics of the chip at the layout level. For example, it verifies whether the chip's power consumption, timing frequency, etc., meet expectations. The simulation calculations for power consumption and / or timing frequency rely heavily on extracting parasitic parameter information (parasitic resistance, parasitic capacitance, etc.) between the chip's transistors and various interconnects. Based on this extracted parameter information, a netlist is generated, aiming to identify computational problems in the post-layout simulation.

[0003] The parasitic resistance netlist in related technologies is an abstract description of the physical characteristics of all layer conductors of a chip. Each section of layer conductor is abstractly described as a parasitic resistor in a two-dimensional unfolding manner. Then, all layer conductors are abstracted into n parasitic resistors of different lengths and resistance values. The n parasitic resistors form a huge parasitic resistance network, so each parasitic resistor is displayed in a preset two-dimensional view in the form of two points and a line.

[0004] However, with the increasing integration of chips, when the contents of the parasitic resistance netlists corresponding to the wires in different layers are displayed together, different parasitic resistances may have complex intersections and overlaps in the preset two-dimensional view. As a result, the search efficiency and accuracy of users in finding simulation calculation problems based on parasitic resistance netlists using relevant technologies are low. Summary of the Invention

[0005] This application provides a visualization method, electronic device, and storage medium for chip parasitic resistance networks, aiming to solve the problems of low efficiency and accuracy in simulation calculation of parasitic resistance netlist files in related technologies.

[0006] To achieve the above objectives: In a first aspect, embodiments of this application provide a method for visualizing a chip parasitic resistance network, the method comprising: The two-dimensional netlist data of the parasitic resistance network generated by all the stacked structures of conductors in the chip is obtained according to the parasitic parameter file of the chip. The two-dimensional netlist data includes the planar structure information of each parasitic resistor in the parasitic resistance network. The stacking structure data table of the chip is obtained according to the chip's process parameter file, wherein the stacking structure data table includes the chip's stacking structure information; The three-dimensional netlist data of the parasitic resistance network is obtained based on the stacked structure data table and the two-dimensional netlist data, wherein the three-dimensional netlist data includes at least the three-dimensional structure information of each parasitic resistance; A first three-dimensional model of the parasitic resistance network is established based on the three-dimensional netlist data. A second three-dimensional model of each stack structure that generates the parasitic resistance network is established based on the process parameter file. At least a portion of the first three-dimensional model and a target second three-dimensional model are displayed. The target second three-dimensional model is established based on the stack structure that generates the target parasitic resistance. The target parasitic resistance is the parasitic resistance corresponding to the displayed first three-dimensional model.

[0007] In one embodiment, obtaining the three-dimensional netlist data of the parasitic resistance network based on the stacked structure data table and the two-dimensional netlist data includes: Obtain a first identifier from the two-dimensional netlist data, wherein the first identifier refers to the stacked structure that is a conductor; Determine the stack thickness information mapped to each of the first identifiers from the stack structure data table; The stacking thickness information is determined as the third-dimensional structural information of the parasitic resistance in the two-dimensional netlist data that maps to the first identifier; The three-dimensional netlist data is obtained based on all the third-dimensional structural information and the two-dimensional netlist data.

[0008] In one embodiment, determining the stack thickness information mapped to each of the first identifiers from the stack structure data table includes: Obtain the stack thickness information mapped to the second identifier from the stack structure data table, wherein the second identifier refers to the conductor stack structure of the non-via type; Obtain the start position and end position mapped to the third identifier from the stacked structure data table, wherein the third identifier refers to the conductor-type stacked structure of the via type; The stacking thickness information mapped to the third identifier is calculated based on the start and end positions of the mapping.

[0009] In one embodiment, displaying at least a portion of the first three-dimensional model and the target second three-dimensional model includes: First selection information for the parasitic resistance network is obtained; based on the first selection information, the parasitic resistances that need to be displayed in the parasitic resistance network are determined; and a first three-dimensional model of the parasitic resistances to be displayed and a second three-dimensional model of the target are displayed on the display interface.

[0010] In one embodiment, displaying the first three-dimensional model of the parasitic resistance and the second three-dimensional model of the target in the display interface includes: In response to a display mode selection operation, a display mode instruction is generated, and a matching preset display mode is obtained according to the display mode instruction; According to the preset display mode which is the first display mode, the first three-dimensional model and the target second three-dimensional model corresponding to the same parasitic resistance that needs to be displayed are superimposed and displayed on the display interface; According to the preset display mode for the second display mode, the first three-dimensional model and the target second three-dimensional model corresponding to the parasitic resistance to be displayed are displayed in the display interface in sections.

[0011] In one embodiment, the three-dimensional netlist data further includes parameter information corresponding to each of the parasitic resistances, and the method further includes: obtaining second selection information for the parasitic resistance network, obtaining and displaying the matching parameter information corresponding to the parasitic resistance from the three-dimensional netlist data according to the second selection information.

[0012] In one embodiment, the step of establishing a first three-dimensional model of the parasitic resistance network based on the three-dimensional netlist data includes: determining the three-dimensional coordinates of the parasitic resistance corresponding to each first identifier in a preset three-dimensional view based on the three-dimensional netlist node information corresponding to each first identifier in the three-dimensional netlist data, and constructing a graphic of the corresponding parasitic resistance in the preset three-dimensional view based on each three-dimensional coordinate to obtain the first three-dimensional model.

[0013] In one embodiment, the method further includes: obtaining an operation instruction input by a user to adjust the parasitic parameter file; generating a new parasitic parameter file based on the operation instruction and the adjusted simulation model; and re-executing the step of obtaining two-dimensional netlist data of the parasitic resistance network generated by the stacked structure of all conductors in the chip based on the chip's parasitic parameter file according to the new parasitic parameter file.

[0014] Secondly, embodiments of this application provide a visualization device for a chip parasitic resistance network, comprising: The first acquisition module is configured to acquire two-dimensional netlist data of the parasitic resistance network generated by all the stacked structures of conductors in the chip according to the parasitic parameter file of the chip, wherein the two-dimensional netlist data includes the planar structure information of each parasitic resistor in the parasitic resistance network. The second acquisition module is configured to acquire a stacking structure data table of the chip according to the chip's process parameter file, wherein the stacking structure data table includes the chip's stacking structure information. The three-dimensional netlist data generation module is configured to obtain three-dimensional netlist data of the parasitic resistance network based on the stacked structure data table and the two-dimensional netlist data, wherein the three-dimensional netlist data includes at least the three-dimensional structure information of each parasitic resistance. The display module is configured to establish a first three-dimensional model of the parasitic resistance network based on the three-dimensional netlist data, establish a second three-dimensional model of each stack structure that generates the parasitic resistance network based on the process parameter file, and display at least a portion of the first three-dimensional model and a target second three-dimensional model, wherein the target second three-dimensional model is established based on the stack structure that generates the target parasitic resistance, and the target parasitic resistance is the parasitic resistance corresponding to the displayed first three-dimensional model.

[0015] Thirdly, embodiments of this application provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the above-described method.

[0016] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0017] Compared with related technologies, the visualization method, apparatus, device, and storage medium for chip parasitic resistance networks provided in this application obtains three-dimensional netlist data of the parasitic resistance network by acquiring two-dimensional netlist data of the parasitic resistance network generated by all stacked structures that are conductors in the chip and a stacked structure data table of the chip. Based on the three-dimensional netlist data, a first three-dimensional model of the parasitic resistance network and a second three-dimensional model of each stacked structure that generates the parasitic resistance network are established and displayed. This facilitates users to quickly find computational problems in the back-end simulation calculation process based on the first three-dimensional model and the second three-dimensional model, improving the efficiency and accuracy of problem finding. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a method for visualizing a chip parasitic resistance network according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of a parasitic resistance in a preset two-dimensional view for related technologies.

[0020] Figure 3 This is a partial cross-sectional view of a chip in the related technology along its thickness direction.

[0021] Figure 4 This is a schematic diagram of the display interface for the partition display method provided in this application.

[0022] Figure 5A block diagram of a visualization device for a chip parasitic resistance network provided in an embodiment of this application.

[0023] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0025] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0026] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0027] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0028] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0029] The following is a brief explanation of the terms that may be used in this application: The back-end simulation stage (or post-simulation stage) occurs after the chip's physical design is completed. Generally, post-simulation occurs after the chip's placement and routing designs are finished. The purpose of post-simulation is to verify whether the chip's timing and functionality still meet the design requirements after the actual physical placement and routing are completed.

[0030] The process parameter file is a parameter file provided by the chip manufacturer. The process parameter file records the data such as the identification of each conductor layer, the thickness data of each conductor layer, the resistance and capacitance values ​​of each conductor layer under different width and length conditions, the identification of each dielectric layer, the thickness data of each dielectric layer, and the dielectric constant of each dielectric layer during the chip manufacturing process.

[0031] The parasitic parameter file is a parameter file calculated by the chip during the post-simulation process. The parasitic parameter file records the node information of the parasitic resistance netlist (such as node identifier, node position information of the node represented by the node identifier in the preset two-dimensional view, etc.) and parasitic resistance information (such as parasitic resistance identifier, resistance value of parasitic resistance, length of parasitic resistance in the preset two-dimensional view, width of parasitic resistance in the preset two-dimensional view, etc.).

[0032] Stacked structures are represented in the layout by patterns (e.g., rectangles, circles, etc.), including several layers formed in the chip and via structures. Each layer includes structures such as dielectrics, metal conductors, and electrodes. Vias are used to achieve electrical connection between the metal conductors in two layers.

[0033] The visualization method for chip parasitic resistance networks provided in this application can be executed by the visualization device for chip parasitic resistance networks provided in this application. The device can be implemented in software and / or hardware. In any embodiment of this application, the terminal device is taken as the execution subject of the method.

[0034] Specifically, such as Figure 1 As shown, the visualization method 100 for the chip parasitic resistance network in this embodiment includes steps S104, S105, S106, S107, and S108: Step S104: Obtain the two-dimensional netlist data of the parasitic resistance network generated by all the stacked structures that are conductors in the chip according to the chip's parasitic parameter file.

[0035] The two-dimensional netlist data includes planar structure information for each parasitic resistor in the parasitic resistance network.

[0036] The planar structure information of the parasitic resistance may include the parasitic resistance identifier, the first stacking structure identifier of the stacked structure that generates the parasitic resistance and is a conductor, and the node information of the parasitic resistance network corresponding to the parasitic resistance identifier.

[0037] The first stacking structure identifier is a unique identifiable information of the stacking structure recorded in the parasitic parameter file. It indicates the stacking structure that generates the corresponding parasitic resistance and can generally be the name of the stacking structure that generates the parasitic resistance when the parasitic parameter extraction tool extracts the parasitic resistance. The parasitic resistance identifier is a unique identifiable information of the parasitic resistance recorded in the parasitic parameter file and can generally be the name of the parasitic resistance when the parasitic parameter extraction tool extracts the parasitic resistance. For the same chip, any two stacking structure identifiers are different, and any two parasitic resistance identifiers are different.

[0038] It is worth mentioning that the parasitic parameter file obtained in the post-simulation stage records information such as all the stacked structures in the chip that can generate parasitic resistance and the magnitude of the generated parasitic resistance. Each parasitic resistance obtained in the post-simulation stage is assigned a corresponding parasitic resistance identifier for distinction, and the relationship between the parasitic resistance and the stacked structure that generates the parasitic resistance is stored in the parasitic parameter file.

[0039] Among them, the node information of the parasitic resistance network corresponding to the parasitic resistance identifier refers to the position information of the parasitic resistance represented by the parasitic resistance identifier in the two-dimensional planar view of the chip.

[0040] Step S105: Obtain the stacking structure data table of the chip according to the chip's process parameter file.

[0041] The stacking structure data table includes the chip's stacking structure information. This information includes a second stacking structure identifier for each stacking structure within the chip, as well as the height information of each stacking structure within the chip.

[0042] The second stacking structure identifier is a unique identifiable information of the stacking structure recorded in the process parameter file, and it can generally be the name of the stacking structure. For the same chip, the second stacking structure identifiers of any two stacking structures are different.

[0043] The height information of each stacked structure in the chip refers to the size information of the stacked structure in the thickness direction of the chip.

[0044] Furthermore, the height information specifically includes starting height data and ending height data. Specifically, for the stacked structures referred to by the same second stacked structure identifier, the starting height data is the distance between the side of the stacked structure closest to the chip and the substrate, and the ending height data is the distance between the side of the stacked structure furthest from the chip and the substrate.

[0045] It is worth mentioning that, in this embodiment, step S105 may be executed by the terminal device before step S104, step S105 may be executed by the terminal device after step S104, or step S105 may be executed synchronously with step S104. This application does not impose any restrictions on this.

[0046] Step S106: Obtain the three-dimensional netlist data of the parasitic resistance network based on the stacked structure data table and the two-dimensional netlist data.

[0047] The 3D netlist data includes at least the three-dimensional structural information of each parasitic resistor. That is, the 3D netlist data records the structural information of each parasitic resistor in the chip plane and the structural information of each parasitic resistor in the chip thickness direction.

[0048] In this way, the three-dimensional netlist data obtained in step S106 makes it easier for users to quickly discover and solve abnormal problems in the back-end simulation calculation process by combining the actual physical layout and wiring of the chip, thereby improving the efficiency of problem finding and the accuracy of problem solving, and reducing the time and manpower costs required in the post-simulation stage.

[0049] For example, Table 1-1 below shows a three-dimensional netlist data obtained based on step S106. The three-dimensional netlist data includes at least parasitic resistance identifier, first node identifier, second node identifier, resistance value, stacking structure index, first spatial location information, and second spatial location information.

[0050] Among them, the parasitic resistance identifier is the unique identifiable information of the parasitic resistance.

[0051] Wherein, the first node identifier and the second node represent the unique identifiable information of two physical nodes within the stacked structure that generate the parasitic resistance indicated by the corresponding parasitic resistance identifier. Accordingly, the first spatial location information includes the position information of the physical node indicated by the first node identifier in a two-dimensional planar view of the chip and the height information of the physical node indicated by the first node identifier within the chip; the second spatial location information includes the position information of the physical node indicated by the second node identifier in a two-dimensional planar view of the chip and the height information of the physical node indicated by the second node identifier within the chip.

[0052] Furthermore, either the first node information or the second node information also includes the node position, which is the position information of the physical node in the two-dimensional planar view of the chip.

[0053] The resistance value is the magnitude of the parasitic resistance indicated by the corresponding parasitic resistance identifier.

[0054] Among them, the stacking structure index is the index information of the stacking structure that generates the parasitic resistance indicated by the corresponding parasitic resistance identifier. Based on the correlation between the index information and the stacking structure information, the stacking structure that generates the parasitic resistance indicated by the corresponding parasitic resistance identifier can be determined through the index information.

[0055]

[0056] Table 1-1 Step S107: Establish a first three-dimensional model of the parasitic resistance network based on the three-dimensional netlist data, establish a second three-dimensional model of each stack structure that generates the parasitic resistance network based on the process parameter file, and display at least a portion of the first three-dimensional model and the target second three-dimensional model.

[0057] The parasitic parameter file describes the nodes and resistance values ​​that generate parasitic resistance in each conductor layer. Based on the 3D netlist data obtained from the parasitic parameter file, a first 3D model of the parasitic resistance network can be generated and displayed in 3D space. That is, the first 3D model of the parasitic resistance network is represented by the lines connecting the nodes in the corresponding layer structure. The target second 3D model is established based on the stacking structure that generates the target parasitic resistance, and the target parasitic resistance is the parasitic resistance corresponding to the displayed first 3D model.

[0058] This allows users to quickly find computational problems in the backend simulation process by generating a 3D information storage table of parasitic resistance based on the first and second 3D models, thus improving the efficiency and accuracy of problem finding.

[0059] In some embodiments, step S106 specifically includes: Step S1061: Obtain the first identifier from the two-dimensional netlist data. The first identifier refers to the stacked structure of the conductors.

[0060] Step S1062: Determine the third-dimensional structural information of the parasitic resistance mapped to each first identifier from the stacked structure data table. The third-dimensional structural information refers to the structural information of the parasitic resistance in the chip thickness direction.

[0061] The height information of the stacking structure identifier corresponding to the first identifier can be directly obtained from the stacking structure data table based on the mapping relationship between the first identifier and the stacking structure identifier in the stacking structure data table. Based on the association relationship described in step S1062, the terminal device can obtain the structural information of the corresponding stacking structure along the chip thickness direction from the stacking structure data table based on the data recorded in the process parameter file. Therefore, based on the structural information along the chip thickness direction, the starting position information, ending position information, and size information of the stacking structure represented by the stacking structure identifier corresponding to the first identifier along the chip thickness direction can be determined, thereby determining the structural information of the parasitic resistance along the thickness direction.

[0062] For example, for the same stacking structure, the field of the stacking structure identifier stored in the stacking structure data table is "M4", and the field of the stacking structure identifier stored in the two-dimensional netlist data is also "M4", so that the terminal device obtains the height information corresponding to "M4" from the stacking structure data table according to the determined "M4".

[0063] Step S1063: Based on all the third-dimensional structural information and the two-dimensional netlist data, obtain the three-dimensional netlist data.

[0064] Based on the three-dimensional structural information of all parasitic resistors and the planar structural information of all parasitic resistors in the two-dimensional plane, the three-dimensional structural information of the parasitic resistor network is obtained.

[0065] In this embodiment, based on steps S1061 to S1063, the three-dimensional structural information of each parasitic resistor in the parasitic resistance netlist that makes up the chip can be determined.

[0066] Further, in some embodiments, step S1062 includes: obtaining stack thickness information mapped to the second identifier from the stack structure data table, obtaining the start position and end position mapped to the third identifier from the stack structure data table, and calculating the stack thickness information mapped to the third identifier based on the start position and end position mapped to the third identifier.

[0067] The second identifier refers to a non-through-hole type stacked structure that is a conductor, and the third identifier refers to a through-hole type stacked structure that is a conductor.

[0068] In this embodiment, the stacking thickness information of the non-via type stacked structure that is a conductor is first determined in the chip, and then the stacking thickness information of the via type stacked structure that is a conductor is determined based on the relative positional relationship between the via type stacked structure that is a conductor and the non-via type stacked structure that is a conductor in the chip.

[0069] Furthermore, the "calculation of stacking thickness information mapped to the third identifier based on the starting position and ending position of the third identifier" specifically includes: calculating the spatial position information of the parasitic resistance corresponding to the third identifier based on the starting position, the ending position and the node information corresponding to the third identifier.

[0070] Since the starting and ending positions are positional information of the stacked structure along the chip thickness direction, and the stacked structure generates parasitic resistance, the positional information of the parasitic resistance along the chip thickness direction can be described based on the height information corresponding to the stacked structure.

[0071] It is worth mentioning that during the chip fabrication process, multiple layered stacked structures are sequentially formed on the substrate along the thickness direction of the chip. The starting height of the first layered stacked structure formed on the substrate is 0, and its ending height is the sum of the starting height 0 and the layer thickness h1 of the first stacked structure (i.e., 0 + h1). The starting height of the second layered stacked structure formed on the first stacked structure is h1, and its ending height is the sum of the starting height h1 and the layer thickness h2 of the second stacked structure (i.e., h2 + h1), and so on, thus the height information of each layered stacked structure can be calculated.

[0072] The following detailed example is illustrated in Table 1-2. Table 1-2 shows an example of a stacked structure data table. In Table 1-2, From is the start layer connectivity identifier, To is the end layer connectivity identifier, "layer" for the stacked structure type refers to a non-via structure, i.e., a layer structure, and "via" for the stacked structure type refers to a via structure. It is worth noting that for stacked structures with a non-via stacked structure type, both the start and end layer connectivity identifiers are invalid values. For stacked structures with a via stacked structure type, the layer thickness data is invalid.

[0073]

[0074] Table 1-2 Specifically, taking the first target stack identifier as M2 as an example, its target stack structure type in Table 1-2 is a layer structure. Then the terminal device performs the following steps to calculate the height information (i.e., the start height data and the end height data) of the stack structure represented by M2.

[0075] Step a: Obtain the calculated first reference termination height data.

[0076] Specifically, such as Figure 3As shown, the stacking identifier of the stacking structure represented by M2, which is close to the substrate SUB and whose stacking type is layer, is ILD3. That is, for M2, ILD3 is the first reference stacking identifier.

[0077] The termination height data of ILD3 is the distance between the side of ILD3 away from the substrate SUB and the substrate SUB, that is... Figure 3 The thickness data corresponding to M1, ILD2, and ILD3 shown are summed. By referring to Table 1-2, we can obtain that the thickness data corresponding to M1 is h1, the thickness data corresponding to ILD2 is h2, and the thickness data corresponding to ILD3 is h3. Therefore, the termination height data of ILD3 can be calculated and is specifically h1+h2+h3.

[0078] Step b: Assign the first reference termination height data to the starting height data of the stacking structure referred to by the first target stacking structure identifier.

[0079] When the first reference termination height data is h1+h2+h3, the starting height data of the stacking structure referred to by the first target stacking structure identifier is h1+h2+h3.

[0080] Step c: Obtain the target layer thickness data from the stack structure data table, and calculate the termination height data of the stack structure represented by the first target stack identifier based on the first reference termination height data and the target layer thickness data.

[0081] Specifically, the layer thickness data h4 corresponding to M2 is obtained from Table 1-2, which is the target layer thickness data. Based on the first reference termination height data h1+h2+h3 and the target layer thickness data h4, the termination height data of the stacking structure represented by M2 is calculated as h1+h2+h3+h4.

[0082] Please refer to Table 1-2. Taking the first target stack identifier as V23 as an example, its target stack structure type in Table 1-2 is a through-hole structure. Then the terminal device performs the following steps to calculate the height information (i.e., the starting height data and the ending height data) of the stack structure represented by V23.

[0083] Step e: Obtain the target starting layer connectivity identifier and the target ending layer connectivity identifier from the third information storage table.

[0084] Specifically, from Table 1-2, the From corresponding to V23 is used as the target starting layer connectivity identifier and the To corresponding to V23 is used as the target ending layer connectivity identifier. The target starting connectivity identifier is M2 and the target ending layer connectivity identifier is M3.

[0085] Step f: Obtain the calculated second reference termination height data based on the target start connectivity identifier.

[0086] Specifically, the second reference termination height data refers to the termination height data of the stacked structure represented by M2. The termination height data of M2 is the distance between the side of M2 furthest from the substrate SUB and the substrate SUB, that is... Figure 3 The sum of the thickness data h1 of M1, the thickness data h2 of ILD2, the thickness data h3 of ILD3, and the thickness data h4 of M2 shown is, i.e., the second reference termination height data is h1+h2+h3+h4.

[0087] Step g: Assign the second reference termination height data to the starting height data of the stack structure referred to by the first target stack identifier.

[0088] Specifically, the second reference termination height data h1+h2+h3+h4 is assigned the starting height data of V23.

[0089] Step h: Obtain the calculated third reference starting height data based on the target termination layer connectivity identifier.

[0090] Specifically, the third reference starting height data refers to the starting height data of the stacked structure represented by M3. The starting height data of the stacked structure represented by M3 is the distance between the side of M3 closest to the substrate SUB and the substrate SUB, that is... Figure 3 The sum of the thickness data h1 of M1, h2 of ILD2, h3 of ILD3, h4 of M2, h5 of ILD5, h6 of ILD6, and h7 of ILD7 shown is, that is, the third reference starting height data is h1+h2+h3+h4+h5+h6+h7.

[0091] Step i: Assign the third reference starting height data to the ending height data of the stack structure referred to by the first target stack identifier.

[0092] Specifically, the third reference starting height data h1+h2+h3+h4+h5+h6+h7 is assigned the ending height data of V23.

[0093] For the same parasitic resistor, since the third-dimensional structural information describes the position of the parasitic resistor in the chip thickness direction, and the node information corresponding to the parasitic resistor's identifier describes the position of the parasitic resistor in a two-dimensional planar view of the chip, and the chip thickness direction and the plane containing the two-dimensional planar view are intersecting rather than parallel in space, the spatial position information of the parasitic resistor can be jointly described by the third-dimensional structural information and the node information. Therefore, for all parasitic resistors in the chip, based on steps S1061 to S1063, the spatial position information of each parasitic resistor can be obtained.

[0094] Furthermore, in one embodiment provided in this application, the node information includes first node location information and second node location information, and for the same parasitic resistance identifier, the value of the second node location information corresponding to the parasitic resistance identifier is greater than or equal to the value of the first node location information.

[0095] The first node location information describes the location information of the first node among the "two points" in the preset two-dimensional view where the parasitic resistance indicated by the parasitic resistance identifier is displayed as "two points in a line". The second node location information describes the location information of the second node among the "two points" in the preset two-dimensional view where the parasitic resistance indicated by the parasitic resistance identifier is displayed as "two points in a line".

[0096] For example, the first node position information includes the position information of the first node in a first direction and the position information of the first node in a second direction. The first direction intersects the second direction, and the plane shared by the first and second directions is the plane containing the preset two-dimensional view.

[0097] Furthermore, based on the reference point determined in the preset two-dimensional view, the first node position information specifically includes the distance value between the first node and the reference point along the first direction and the distance value between the first node and the reference point along the width direction, and the second node position information specifically includes the distance value between the second node and the reference point along the first direction and the distance value between the second node and the reference point along the width direction.

[0098] In this way, for the same parasitic resistance identifier, if the value of the second node position information corresponding to the parasitic resistance identifier is greater than or equal to the value of the first node position information, one of the following three scenarios applies: In the first scenario, the distance between the second node and the reference point along the first direction is greater than or equal to the distance between the first node and the reference point along the first direction, and the distance between the second node and the reference point along the second direction is less than the distance between the first node and the reference point along the second direction.

[0099] In the second scenario, the distance between the second node and the reference point along the second direction is greater than or equal to the distance between the first node and the reference point along the second direction, and the distance between the second node and the reference point along the first direction is less than the distance between the first node and the reference point along the first direction.

[0100] In the third scenario, the distance between the second node and the reference point along the first direction is greater than or equal to the distance between the first node and the reference point along the first direction, and the distance between the second node and the reference point along the second direction is greater than or equal to the distance between the first node and the reference point along the second direction.

[0101] It is worth mentioning that, in order to facilitate subsequent simulation and comparison based on the method provided in this application, preferably, the first direction is the length direction of the chip substrate and the second direction is the width direction of the chip substrate.

[0102] The following is combined Figure 4 An illustrative example is provided. Assume an X-axis reference system is established along a first direction, a Y-axis reference system is established along a second direction, and a Z-axis coordinate system is established along the chip's thickness direction. The first spatial position information is labeled P1, the second spatial position information is labeled P2, the starting height data of the third-dimensional structural information is Z0, the ending height data of the third-dimensional structural information is Z1, the distance between the first node and the reference point along the first direction is X1, the distance between the first node and the reference point along the second direction is Y1, the distance between the second node and the reference point along the first direction is X2, and the distance between the second node and the reference point O1 along the second direction is Y2, where X1 is less than X2 and Y1 is less than Y2.

[0103] For example, step S1071 is as follows: Calculate the first spatial position information corresponding to the first spatial position information identifier P1 based on the initial height data Z0 and the first node position information (X1, Y1). Wherein, the X-axis coordinate value of P1 = X1, the Y-axis coordinate value of P1 = Y1 - dr / 2, and the Z-axis coordinate value of P1 = Z0, thus the first spatial position information can be described as (X1, Y1 - dr / 2, Z0).

[0104] For example, step S1072 is as follows: The second spatial position information corresponding to the second spatial position information identifier P2 is calculated based on the termination height data Z1 and the second node position information (X2, Y2). Here, the X-axis coordinate value of P2 = X2, the Y-axis coordinate value of P2 = Y2 + dr / 2, and the Z-axis coordinate of P = Z1. Therefore, the second spatial position information can be described as (X2, Y2 + dr / 2, Z1). It is worth noting that in the above example, dr represents the width information of the parasitic resistance corresponding to the first target height in the second direction.

[0105] Please see Figure 4 , Figure 4The closed quadrilateral pattern shown, enclosed by thick dotted lines, is a projection pattern of the stacked structure, represented by the second stack identifier corresponding to the parasitic resistance, in this preset two-dimensional view. When describing the first and second node position information for each parasitic resistance, the stacked structure is generally taken in the second direction (…). Figure 4 The Y-axis coordinate value corresponding to the median value of the width in the Y-axis direction is the distance between the first node and the reference point along the second direction. Generally, the Y-axis coordinate value corresponding to the median value of the width of this stacked structure in the second direction is taken as the distance between the second node and the reference point along the second direction.

[0106] Each parasitic resistance can be represented by a cuboid structure in three-dimensional space. To represent the position of a cuboid structure in three-dimensional space, it is necessary to determine its diagonal coordinates, such as the coordinates of its bottom-left corner and top-right corner. Correspondingly, the coordinates of the bottom-left corner of the cuboid are... Figure 4 The coordinates in the preset 2D view are (X1, Y1-dr / 2), and the coordinates of the upper right corner of the cuboid are... Figure 4 The coordinates in the preset 2D view are (X2, Y2+dr / 2).

[0107] Further, step S107, "displaying at least part of the first three-dimensional model and the target second three-dimensional model", includes: obtaining first selection information for the parasitic resistance network, determining the parasitic resistance to be displayed in the parasitic resistance network based on the first selection information, and displaying the first three-dimensional model of the parasitic resistance to be displayed and the target second three-dimensional model in the display interface.

[0108] The three-dimensional netlist data includes multiple parasitic resistance graphic information, which correspond one-to-one with multiple parasitic resistance identifiers. The parasitic resistance graphic includes two three-dimensional coordinate points corresponding to the spatial location information and a cuboid graphic determined based on the two three-dimensional coordinate points.

[0109] For the spatial location information corresponding to the same parasitic resistance, the Z-axis coordinate values ​​of the two corresponding three-dimensional coordinate points P3(X3,Y3,Z3) and P4(X4,Y4,Z4) are completely different, and at least one of the X-axis coordinate values ​​and Y-axis coordinate values ​​of the two corresponding three-dimensional coordinate points P3(X3,Y3,Z3) and P4(X4,Y4,Z4) is different, so that a cuboid shape can be constructed in the three-dimensional view based on the three-dimensional coordinate points P3(X3,Y3,Z3) and P4(X4,Y4,Z4).

[0110] Based on the chip's device characteristics, the larger the volume of the stacked structure, the smaller its parasitic resistance; conversely, the smaller the volume of the stacked structure, the larger its parasitic resistance. The cuboid shape shown in this step represents the volume of the stacked structure corresponding to this parasitic resistance. In this way, those performing simulation verification can intuitively determine the relative magnitudes of the parasitic resistance values ​​corresponding to multiple cuboid shapes by observing them. However, in related technologies, each parasitic resistance is displayed as a line between two points in its preset two-dimensional view, making it impossible for simulation verification personnel to determine the relative magnitudes of the resistance values ​​among multiple parasitic resistances.

[0111] Furthermore, if the stacked structures corresponding to multiple cuboid patterns are distributed in different layers of the parasitic circuit, the parasitic resistance three-dimensional netlist generated in this step will not present a chaotic overlapping situation in the three-dimensional view when displaying multiple cuboid patterns. Instead, it will be displayed in an orderly manner according to the deposition order in the chip manufacturing process, thus conforming to the actual stacking situation of each stacked structure in the chip.

[0112] Furthermore, in one embodiment provided in this application, "displaying the first three-dimensional model of the parasitic resistance and the second three-dimensional model of the target in the display interface" further includes: In response to the display mode selection operation, a display mode instruction is generated, and a matching preset display mode is obtained according to the display mode instruction; when the preset display mode is the first display mode, the first three-dimensional model corresponding to the parasitic resistance to be displayed and the target second three-dimensional model are superimposed and displayed on the display interface according to the first display mode; when the preset display mode is the second display mode, the first three-dimensional model corresponding to the parasitic resistance to be displayed and the target second three-dimensional model are displayed in sections on the display interface according to the second display mode.

[0113] For example, such as Figure 4 As shown, Figure 4 The diagram illustrates the display interface showing the overlay of the first and second 3D models. This overlay display allows users to intuitively understand parasitic resistance and the corresponding stacking structure through the interface. Users can then compare the displayed parasitic resistance graph with the corresponding stacking structure graph, based on their understanding of the chip, to determine if the 3D netlist data meets the preset benchmark. In another example, the display interface can also show the target second 3D model and the first 3D model from the same viewpoint, saving users the trouble of adjusting the viewpoint of each section during simulation comparison.

[0114] By using an overlay display method, users can easily determine whether the data in the 3D netlist matches based on the stacked structure. If the direction or displayed structure of the target second 3D model is inconsistent with the corresponding first 3D model, there may be data anomalies. This can be easily detected by comparing the first and second 3D models. For example, if the target second 3D model extends along one direction, while the corresponding first 3D model extends along a different direction, then the corresponding data in the 3D netlist may be anomaly. This suggests a potential problem with the chip's circuit design, requiring the user to combine their understanding of the chip to determine whether further adjustments to the circuit design are needed, such as inspection or secondary simulation.

[0115] Furthermore, in yet another embodiment provided in this application, the method 100 further includes: Step S108: Obtain second selection information for the parasitic resistance network, and obtain and display the parameter information corresponding to the matching parasitic resistance from the three-dimensional netlist data according to the second selection information.

[0116] The second selection information is the associated information of the parasitic resistance identifier corresponding to the cuboid graphic or the three-dimensional coordinate point selected by the user.

[0117] In this way, after the user selects one or more cuboid shapes on the display interface, the display interface can display at least one of the following information associated with the parasitic resistance identifier: the parasitic resistance identifier of the parasitic resistance corresponding to the selected cuboid shape, the resistance value of the corresponding parasitic resistance, the height information of the corresponding parasitic resistance, and the width information of the corresponding parasitic resistance.

[0118] Furthermore, in yet another embodiment provided in this application, the method 100 further includes: Step S109: Obtain the user-inputted operation instruction to adjust the parasitic parameter file, generate a new parasitic parameter file according to the operation instruction and the adjusted simulation model, and then execute the step of obtaining the two-dimensional netlist data of the parasitic resistance network generated by the stacked structure of all conductors in the chip according to the chip's parasitic parameter file again based on the new parasitic parameter file.

[0119] Specifically, when a user deems it necessary to adjust the data in the 3D netlist, the simulation model called in the post-simulation stage is first adjusted on the terminal device. Then, an operation command to adjust the parasitic parameter file is sent to the terminal device. Based on the adjusted simulation model, the terminal device performs simulation calculations on the chip again according to the operation command and generates a new parasitic parameter file. Subsequently, the updated 2D netlist data is obtained based on the new parasitic parameter file, and subsequent steps such as generating the 3D netlist data are performed again.

[0120] In a second aspect, this application also provides a visualization device for a chip parasitic resistance network, which is used to implement the above embodiments and preferred embodiments, and will not be repeated hereafter. The terms "module," "unit," "subunit," etc., used below can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0121] Specifically, such as Figure 5 As shown, the visualization device 200 includes a first acquisition module 201, a second acquisition module 202, a three-dimensional netlist data generation module 203, and a display module 204.

[0122] The first acquisition module 201 is configured to acquire two-dimensional netlist data of the parasitic resistance network generated by the stacked structure of all conductors in the chip according to the parasitic parameter file of the chip. The two-dimensional netlist data includes the planar structure information of each parasitic resistor in the parasitic resistance network.

[0123] The second acquisition module 202 is configured to acquire the chip's stacking structure data table based on the chip's process parameter file, wherein the stacking structure data table includes the chip's stacking structure information.

[0124] The three-dimensional netlist data generation module 203 is configured to obtain three-dimensional netlist data of the parasitic resistance network based on the stacked structure data table and the two-dimensional netlist data. The three-dimensional netlist data includes at least the three-dimensional structure information of each parasitic resistance.

[0125] The display module 204 is configured to establish a first three-dimensional model of the parasitic resistance network based on the three-dimensional netlist data, establish a second three-dimensional model of each stack structure that generates the parasitic resistance network based on the process parameter file, and display at least a portion of the first three-dimensional model and the target second three-dimensional model. The target second three-dimensional model is established based on the stack structure that generates the target parasitic resistance, and the target parasitic resistance is the parasitic resistance corresponding to the displayed first three-dimensional model.

[0126] Specific limitations regarding the visualization device for chip parasitic resistance networks can be found in the limitations of the visualization method for chip parasitic resistance networks described above, and will not be repeated here. Each module in the aforementioned parasitic resistance information processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the corresponding operations of each module.

[0127] Based on the same inventive concept as the foregoing embodiments, this application provides an electronic device in a third aspect. For example... Figure 6 As shown, the device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 6 The processor 310 shown in the diagram does not indicate that there is only one processor 310, but only indicates the positional relationship of the processor 310 relative to other devices. In practical applications, there can be one or more processors 310; similarly, Figure 6 The memory 311 illustrated herein has the same meaning, that is, it is only used to indicate the positional relationship of memory 311 relative to other devices. In practical applications, there can be one or more memories 311. When the processor 310 runs the computer program, the method applied to the above-mentioned device is implemented.

[0128] The device may also include at least one network interface 312. The various components of the device are coupled together via a bus system 313. It is understood that the bus system 313 is used to implement communication between these components. In addition to a data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 6 The general designated all buses as Bus System 313.

[0129] The memory 311 can be volatile memory or non-volatile memory, or both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); the magnetic surface memory can be disk storage or magnetic tape storage. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 311 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0130] The memory 311 in this embodiment of the invention is used to store various types of data to support the operation of the device. Examples of this data include: any computer programs used to operate on the device, such as operating systems and applications; contact data; phonebook data; messages; pictures; videos, etc. The operating system includes various system programs, such as the framework layer, core library layer, driver layer, etc., used to implement various basic services and handle hardware-based tasks. Applications can include various applications, such as media players, browsers, etc., used to implement various application services. Here, the program implementing the method of this embodiment of the invention can be included in the application.

[0131] Based on the same inventive concept as the foregoing embodiments, this embodiment also provides a computer-readable storage medium storing a computer program. The computer-readable storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it can also be various devices including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc. When the computer program stored in the computer-readable storage medium is executed by a processor, it implements the above method. For the specific steps implemented when the computer program is executed by the processor, please refer to the description of any method embodiment of this application, which will not be repeated here.

[0132] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for visualizing a chip parasitic resistance network, characterized in that, The method includes: The two-dimensional netlist data of the parasitic resistance network generated by all the stacked structures of conductors in the chip is obtained according to the parasitic parameter file of the chip. The two-dimensional netlist data includes the planar structure information of each parasitic resistor in the parasitic resistance network. The stacking structure data table of the chip is obtained according to the chip's process parameter file, wherein the stacking structure data table includes the chip's stacking structure information; The three-dimensional netlist data of the parasitic resistance network is obtained based on the stacked structure data table and the two-dimensional netlist data, wherein the three-dimensional netlist data includes at least the three-dimensional structure information of each parasitic resistance; A first three-dimensional model of the parasitic resistance network is established based on the three-dimensional netlist data. A second three-dimensional model of each stack structure that generates the parasitic resistance network is established based on the process parameter file. At least a portion of the first three-dimensional model and a target second three-dimensional model are displayed. The target second three-dimensional model is established based on the stack structure that generates the target parasitic resistance. The target parasitic resistance is the parasitic resistance corresponding to the displayed first three-dimensional model.

2. The method according to claim 1, characterized in that, The step of obtaining the three-dimensional netlist data of the parasitic resistance network based on the stacked structure data table and the two-dimensional netlist data includes: Obtain a first identifier from the two-dimensional netlist data, wherein the first identifier refers to the stacked structure that is a conductor; Determine the stack thickness information mapped to each of the first identifiers from the stack structure data table; The stacking thickness information is determined as the third-dimensional structural information of the parasitic resistance in the two-dimensional netlist data that maps to the first identifier; The three-dimensional netlist data is obtained based on all the third-dimensional structural information and the two-dimensional netlist data.

3. The method according to claim 2, characterized in that, Determining the stack thickness information mapped to each of the first identifiers from the stack structure data table includes: Obtain the stack thickness information mapped to the second identifier from the stack structure data table, wherein the second identifier refers to the conductor stack structure of the non-via type; Obtain the start position and end position mapped to the third identifier from the stacked structure data table, wherein the third identifier refers to the conductor-type stacked structure of the via type; The stacking thickness information mapped to the third identifier is calculated based on the start and end positions of the mapping.

4. The method according to claim 1, characterized in that, The display of at least a portion of the first three-dimensional model and the target second three-dimensional model includes: Obtain first selection information for the parasitic resistance network, determine the parasitic resistance to be displayed in the parasitic resistance network based on the first selection information, and display a first three-dimensional model of the parasitic resistance to be displayed and a second three-dimensional model of the target in the display interface.

5. The method according to claim 4, characterized in that, The step of displaying the first three-dimensional model of the parasitic resistance and the second three-dimensional model of the target in the display interface includes: In response to a display mode selection operation, a display mode instruction is generated, and a matching preset display mode is obtained according to the display mode instruction; According to the preset display mode which is the first display mode, the first three-dimensional model and the target second three-dimensional model corresponding to the same parasitic resistance that needs to be displayed are superimposed and displayed on the display interface; According to the preset display mode for the second display mode, the first three-dimensional model and the target second three-dimensional model corresponding to the parasitic resistance to be displayed are displayed in the display interface in sections.

6. The method according to claim 4, characterized in that, The three-dimensional netlist data also includes parameter information corresponding to each parasitic resistance, and the method further includes: Obtain second selection information for the parasitic resistance network, and retrieve and display the parameter information corresponding to the matching parasitic resistance from the three-dimensional netlist data based on the second selection information.

7. The method according to claim 1, characterized in that, The step of establishing the first three-dimensional model of the parasitic resistance network based on the three-dimensional netlist data includes: Based on the information of the three-dimensional netlist node corresponding to each first identifier in the three-dimensional netlist data, determine the three-dimensional coordinates of the parasitic resistance corresponding to each first identifier in the preset three-dimensional view, and construct the corresponding graph of the parasitic resistance in the preset three-dimensional view based on each three-dimensional coordinate to obtain the first three-dimensional model.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: The system obtains user input instructions to adjust the parasitic parameter file, generates a new parasitic parameter file based on the instructions and the adjusted simulation model, and then re-executes the step of obtaining the two-dimensional netlist data of the parasitic resistance network generated by the stacked structure of all conductors in the chip based on the chip's parasitic parameter file.

9. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method of any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.

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