Public path pessimistic margin removal method, product, method and storage medium

Abstract

The invention relates to the technical field of pessimism elimination algorithms, in particular to a public path pessimism margin removal method, product and method and a storage medium, and the method comprises the steps: providing a clock tree, traversing the clock tree, and generating an index table, a sequence table and a hierarchical table based on information obtained through traversing; generating a line segment tree based on the sequence table and the hierarchical table; for a starting point and an ending point of any given time sequence path, obtaining a nearest common node through line segment tree query; and determining a sub-tree modified in the optimization process based on the nearest common node, correspondingly modifying an index table, a sequence table and / or a hierarchical table, and then carrying out common path pessimistic margin removal analysis to remove pessimistic margin. The method provided by the invention can solve the technical problem that the current public path pessimistic margin removal method consumes much time.

Description

[Technical Field]

[0001] This invention relates to the field of pessimism elimination algorithm technology, and in particular to a method, product, method and storage medium for removing pessimism margin in common paths. [Background Technology]

[0002] In timing analysis, to prevent non-convergence issues during the signoff phase, calculations tend to be pessimistic. For example, during setup checks, signal path analysis might be performed based on maximum delay. However, excessive pessimism can lead to the discarding of many usable resources during layout design, necessitating the removal of unreasonable pessimistic margins. CPPR (common clock path pessimism removal) is a common method for removing pessimistic margins and is frequently used in timing analysis. Common overlapping paths easily occur between the launch and capture edges of a timing path. While timing analysis might analyze the launch and capture paths using minimum and maximum constraints respectively, this is unnecessary for common paths. At any given moment, the common path will not simultaneously exhibit both minimum and maximum constraints. Therefore, when determining whether a timing path converges, it's necessary to remove the pessimistic margins introduced by common paths.

[0003] The key step in pessimistic margin removal analysis for common paths is determining the longest common point originating from the clock. After identifying the nearest common point, it's only necessary to calculate the difference in arrival times between the emit and capture paths to this common point, i.e., the pessimistic margin. A common method for finding common points is forward tracing, which involves searching forward after determining the path start and path end until the longest common point is found. This exhaustive search mechanism often consumes significant time on complex layouts, and its time and memory consumption increase noticeably with the number of timing paths.

[0004] Besides forward tracing, there's a lookup method similar to building a discrete table first. First, an exhaustive traversal of the netlist is performed to record the connections between devices. Then, a discrete table is built to record the minimum element within the interval corresponding to the traversal order of any two devices. When calculating the pessimistic margin, a search is performed in the discrete table according to the device's corresponding index; the minimum element within the given interval is the nearest common node. Compared to forward tracing, this method reduces both time and space consumption. However, when the netlist is modified, the original lookup table becomes unusable, requiring a complete traversal of the clock tree and rebuilding of the hash table, which is very time-consuming. [Summary of the Invention]

[0005] To address the technical problem that current methods for removing pessimistic margins in common paths consume a significant amount of time, this invention provides a method, product, approach, and storage medium for removing pessimistic margins in common paths.

[0006] To address the aforementioned technical problems, this invention provides the following technical solution: a method for removing pessimistic residuals in common paths, comprising: providing a clock tree; traversing the clock tree and generating an index table, a sequence table, and a hierarchy table based on the information obtained from the traversal; generating a segment tree based on the sequence table and the hierarchy table; for any given start and end point of a time-series path, obtaining the nearest common node through a segment tree query; based on the nearest common node, determining the subtrees modified during the optimization process, modifying the index table, sequence table, and / or hierarchy table accordingly, and then performing a pessimistic residual removal analysis to remove the pessimistic residuals.

[0007] Preferably, providing a clock tree and generating an index table, a sequence table, and a hierarchy table based on the information obtained after traversing the clock tree includes: providing a clock tree, traversing the clock tree, obtaining each device in the integrated circuit; recording the corresponding index of each device in the index table; obtaining the order of device access according to the index table, and recording the order in the sequence table; when encountering a device not recorded in the index table, adding the corresponding device name to the index table; obtaining the level of the device accessed on the clock tree, and recording the corresponding level of the device in the hierarchy table.

[0008] Preferably, generating a segment tree based on a sequential table and a hierarchical table includes: providing the start and end points of the temporal path, and determining the size of the start and end points; if the start point is greater than the end point, then dividing the current interval into two sub-intervals, recording the maximum and minimum values ​​in the current interval, and recursively constructing segment trees in the two sub-intervals respectively; if the start point is equal to the end point, then constructing the leaf nodes of the segment tree based on the current value; if the start point is greater than the end point, then returning the start and end points of the temporal path.

[0009] Preferably, for any given start and end point of a timing path, the nearest common node is obtained by querying the segment tree, which includes: for any given start and end point of a timing path, determining the device and its index based on the index table; obtaining the minimum value index by querying the segment tree; and obtaining the corresponding device in the hierarchical table based on the minimum value index, which is the nearest common node.

[0010] Preferably, the optimization process includes adjustment operations and insertion operations.

[0011] Preferably, the adjustment operation includes: the integrated circuit includes several library modules, and when replacing one of the library modules in the integrated circuit, the index of the replaced library module is updated in the index table.

[0012] Preferably, the insertion operation includes: determining the sub-interval where the device needs to be inserted based on the nearest common node; incrementing the corresponding subtree level by 1; and modifying the corresponding level table based on the subtree.

[0013] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer program product, including a computer program, which, when executed by a processor, implements the above-mentioned common path pessimistic margin removal method.

[0014] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer device, including a storage device, a processor, and a computer program stored in the storage device, wherein the processor executes the computer program to implement steps such as the common path pessimistic margin removal method.

[0015] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements steps such as the common path pessimistic margin removal method.

[0016] Compared with existing technologies, the pessimistic margin removal method, product, method, and storage medium provided by this invention have the following advantages:

[0017] 1. This invention provides a method for removing pessimistic residuals in common paths. Addressing the problem of removing pessimistic residuals in time series analysis, this invention increases the friendliness of netlist modifications and reduces time series analysis time by pre-traversing and building a segment tree. Specifically, in the optimized process, each modification involves modifying the netlist. The segment tree only needs to update some subtrees and correspondingly modify some tables, without needing to rebuild the tables from scratch. This reduces the time loss of re-analyzing the removal of pessimistic residuals in common paths after each operation. Therefore, the segment tree performs better when modifying tables, shortens the time required to remove pessimistic residuals, and significantly reduces the time cost of time series analysis.

[0018] 2. The present invention provides a common path pessimistic margin removal method, which traverses the clock tree to establish a table of indexes, access sequences, and access levels of recording devices. This enables quick access and modification of relevant data in the index table, sequence table, and / or level table during path pessimistic margin removal analysis, significantly improving the efficiency of time series analysis.

[0019] 3. This invention provides a method for removing pessimistic margins in common paths. In the analysis of clock trees, segment trees can be used to quickly query and update the common path information of the clock tree. After completing the traversal process of the clock tree, a segment tree is generated based on the obtained table. The segment tree is an efficient data structure. As a balanced binary tree, it divides the interval into multiple search sub-intervals, thereby realizing efficient sub-interval search and modification operations.

[0020] 4. The pessimistic margin removal method for common paths provided by this invention is a suitable data structure for application scenarios that require searching for the minimum element within an interval. Furthermore, obtaining the nearest common node through segment tree queries not only improves the accuracy and efficiency of time series analysis, but also provides strong support for the optimization and dynamic maintenance of clock trees.

[0021] 5. The present invention provides a common path pessimistic margin removal method, in which adjustment and insertion operations optimize the propagation characteristics of clock signals, including delay, skew and stability, by adjusting the structure of the clock tree in the common path pessimistic margin removal analysis, thereby improving the timing performance and reliability of the entire design.

[0022] 6. The pessimistic margin removal method for common paths provided by this invention allows for the modification of library units into functionally equivalent library units with different driving capabilities during adjustment operations. Only the index table needs to be updated, while other tables and segment trees do not need to be modified, thereby improving the efficiency of adjustment operations and reducing time consumption.

[0023] 7. The present invention provides a common path pessimistic margin removal method. In the optimization process, in order to repair some excessively long connections, devices are often inserted in the middle of the connections to interrupt them. For some existing algorithms, this situation will completely fail and need to be rebuilt. However, the segment tree can handle this situation well by modifying the subtree and the corresponding table.

[0024] 8. The computer program product provided by this invention has similar beneficial effects to the above-mentioned method for removing pessimistic margins in common paths, and will not be described in detail here.

[0025] 9. The computer device provided by the present invention has similar beneficial effects to the above-mentioned common path pessimistic margin removal method, and will not be described in detail here.

[0026] 10. The computer-readable storage medium provided by the present invention has similar beneficial effects to the above-mentioned common path pessimistic margin removal method, and will not be described in detail here. [Attached Image Description]

[0027] Figure 1 This is a flowchart of the steps of the common path pessimistic margin removal method provided in the first embodiment of the present invention.

[0028] Figure 2 This is a flowchart of step S1 in the common path pessimistic margin removal method provided in the first embodiment of the present invention.

[0029] Figure 3 This is a flowchart of step S2 in the common path pessimistic margin removal method provided in the first embodiment of the present invention.

[0030] Figure 4 This is a flowchart of step S3 in the common path pessimistic margin removal method provided in the first embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram of a computer program product provided in the second embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram of a computer device provided in the third embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram of a computer-readable storage medium provided in the fourth embodiment of the present invention.

[0034] Explanation of reference numerals in the attached diagram:

[0035] 1. Computer program products; 2. Computer devices; 3. Computer-readable storage media;

[0036] 11. Computer program; 21. Storage device; 22. Processor; 23. Computer program; 31. Computer program.

Detailed Implementation Methods

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] It's important to note that in timing analysis, the common path pessimistic margin removal method is a technique used to optimize clock path analysis. The main purpose of this method is to eliminate unnecessary pessimism in clock path analysis to more accurately predict circuit performance. Since common portions may exist on different clock paths (such as transmit and capture clock paths), applying different derating factors to these common paths can lead to overly pessimistic analysis results. Common path pessimistic margin removal adjusts the timing analysis results by considering the difference between the maximum and minimum delay values ​​of the common clock path. This eliminates unnecessary pessimism caused by common paths, thus providing more accurate timing analysis calculations.

[0039] It's important to note that a segment tree is an advanced data structure used to store interval data and allows for efficient query and update operations on these intervals. It is widely used to handle interval query and update problems on arrays, such as finding the maximum or minimum value of an interval and interval sum queries. The main characteristic of segment trees is their good time complexity, allowing interval query and update operations to be completed in logarithmic time.

[0040] Please see Figure 1 The first embodiment of the present invention provides a common path pessimistic margin removal method, applied to timing analysis on integrated circuits, including the following steps:

[0041] S1: Provides a clock tree, and generates an index table, sequential table, and hierarchical table based on the information obtained after traversing the clock tree;

[0042] S2: Generate a segment tree based on sequential and hierarchical tables;

[0043] S3: For any given start and end point of a time sequence path, find the nearest common node by querying a segment tree;

[0044] S4: Based on the nearest common node, determine the subtrees modified during the optimization process, modify the index table, sequence table and / or hierarchy table accordingly, and then perform a common path pessimistic margin removal analysis to remove pessimistic margins.

[0045] Specifically, this invention addresses the problem of removing pessimistic margins in common paths during time series analysis by pre-traversing and building a segment tree, thereby increasing the friendliness of netlist modifications and reducing the time of time series analysis. In the optimized process, each modification involves modifying the netlist, but the segment tree only needs to update some subtrees and modify some tables accordingly, without having to rebuild the tables from scratch. This reduces the time loss of re-analyzing the removal of pessimistic margins in common paths after each operation. Therefore, the segment tree performs better when modifying tables, greatly reducing the time cost of time series analysis.

[0046] It should be noted that a clock tree is a network structure in an integrated circuit used to distribute clock signals, ensuring that clock signals can reach each register or flip-flop synchronously.

[0047] It should be noted that you should refer to [link / reference]. Figure 2 Step S1 specifically includes the following steps:

[0048] S11: Provides a clock tree; traverse the clock tree to obtain each device in the integrated circuit.

[0049] S12: Record the corresponding index of each device in the index table;

[0050] S13: Based on the index table, obtain the order in which the devices are accessed and record the order in the sequence table;

[0051] S14: When a device is not recorded in the index table, add the corresponding device name to the index table;

[0052] S15: Obtain the level of the device accessed on the clock tree and record the corresponding level of the device in the level table.

[0053] It should be noted that after the index table, sequential table, and hierarchical table are established, the relevant data in the index table, sequential table, and / or hierarchical table can be quickly accessed and modified when performing path pessimistic margin removal analysis, which significantly improves the efficiency of time series analysis.

[0054] Specifically, in step S13, the device index in the index table is used as the key value. The index is usually a numeric type. These numeric indexes are used to identify each node in the clock tree so as to quickly locate and reference it when traversing and operating the clock tree.

[0055] It should be noted that you should refer to [link / reference]. Figure 3 Step S2 specifically includes the following steps:

[0056] S21: Provide the start and end points of the timing path, and determine the size of the start and end points;

[0057] S22a: If the starting point is greater than the ending point, then divide the current time-series path interval into two sub-intervals, record the maximum and minimum values ​​in the current entire interval, and recursively construct segment trees in the two sub-intervals respectively;

[0058] S22b: If the starting point equals the ending point, then construct the leaf nodes of the segment tree based on the current value;

[0059] S22c: If the starting point is greater than the ending point, then return to S21.

[0060] It should be noted that S22a, S22b, and S22c are three different execution methods. That is, after step S21, based on the judgment result, any one of S22a, S22b, and S22c is selected for execution.

[0061] Specifically, the purpose of constructing a segment tree is to conveniently and quickly determine the nearest common node corresponding to the start and end points of any given temporal path.

[0062] It's important to note that a segment tree is a binary tree where each node represents an interval, and leaf nodes represent a single element, which is also the smallest element in the segment tree. When constructing a segment tree, given an array, build a segment tree where each leaf node stores an element from the array, and non-leaf nodes store the merged result of their child nodes.

[0063] Furthermore, in the segment tree established in step S2, each sub-interval has one or more leaf nodes on the segment tree constructed.

[0064] Furthermore, when performing an update operation on the segment tree, update a certain element in the array, and then update all the affected nodes in the segment tree.

[0065] It should be noted that you should refer to [link / reference]. Figure 4 Step S3 specifically includes the following steps:

[0066] S31: For any given timing path start and end point, determine the device and its index based on the index table;

[0067] S32: Obtain the minimum value index by querying a segment tree;

[0068] S33: Based on the minimum value index, the corresponding device is retrieved from the hierarchical table, and the corresponding device is the nearest common node.

[0069] Specifically, when performing time-series path interval queries, the minimum value index is used to determine the position of the queried minimum value in the segment tree. For application scenarios that require searching for the minimum value within an interval, the segment tree is a very suitable data structure. Furthermore, obtaining the nearest common node through segment tree queries not only improves the accuracy and efficiency of time-series analysis, but also provides strong support for the optimization and dynamic maintenance of the clock tree.

[0070] Furthermore, after retrieving the nearest common node, the pessimism of the common path can be calculated based on the nearest common node.

[0071] It should be noted that after the segment tree is built, if some changes occur during the optimization process, it is not necessary to modify the entire segment tree; only partial modifications are required. Therefore, the segment tree has good support for netlist updates and saves modification time.

[0072] Specifically, the optimization process includes adjustment and insertion operations. In the common path pessimistic margin removal analysis, adjustment and insertion operations optimize the propagation characteristics of the clock signal, including delay, skew, and stability, by adjusting the structure of the clock tree, thereby improving the timing performance and reliability of the entire design.

[0073] Further adjustments include:

[0074] An integrated circuit includes several library modules. When a library module in an integrated circuit is replaced, the index of the replaced library module is updated in the index table.

[0075] It should be noted that library modules are pre-designed logic gates or circuit modules that can be reused when designing integrated circuits.

[0076] It should be noted that, for timing or power optimization purposes, if a library unit is modified to another functionally equivalent library unit with different driving capabilities, only the index table needs to be updated; other tables and segment trees do not need to be modified. This design improves the efficiency of adjustment operations and reduces time consumption.

[0077] Furthermore, the insertion operation includes:

[0078] Based on the nearest common node, determine the sub-interval where the device needs to be inserted;

[0079] Increment the corresponding subtree level by 1, and modify the corresponding level table based on the subtree.

[0080] In this embodiment, the insertion device is a buffer. In the optimization process, in order to repair some excessively long connections, the buffer is inserted in the middle of the connection to break these connections.

[0081] Specifically, the insertion operation affects the interval from the insertion point to the leaf node, thus requiring modification of the subtree corresponding to the insertion unit. Some existing algorithms become completely ineffective in this scenario, necessitating a complete overhaul; however, segment trees can be modified by altering only a portion of the subtrees and corresponding tables, resulting in a shorter computation time.

[0082] It should be noted that since the optimization process only requires modification of some segment trees and tables, the time consumption for common path pessimistic margin removal analysis after each optimization operation is relatively short, which greatly reduces the time for removing pessimistic margins in timing analysis and improves the efficiency of optimizing integrated circuits.

[0083] Please see Figure 5 The second embodiment of the present invention provides a computer program product 1, including a computer program 11, which, when executed by a processor, implements the common path pessimistic margin removal method provided in the first embodiment above.

[0084] Please see Figure 6 The third embodiment of the present invention provides a computer device 2, including a storage 21, a processor 22 and a computer program 23 stored on the storage 21. The processor 22 executes the computer program 23 to implement the common path pessimistic margin removal method provided in the first embodiment above.

[0085] Please see Figure 7 The fourth embodiment of the present invention provides a computer-readable storage medium 3 on which a computer program 31 is stored. When the computer program 31 is executed by a processor, it implements the common path pessimistic margin removal method provided in the first embodiment above.

[0086] It is understood that, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined in the methods of this application. It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. Computer-readable storage media include, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0087] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0088] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0089] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0090] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0091] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0092] Compared with the prior art, the common path pessimistic margin removal method, product, method, and storage medium provided by the present invention have the following beneficial effects:

[0093] 1. This invention provides a method for removing pessimistic residuals in common paths. Addressing the problem of removing pessimistic residuals in common paths during time series analysis, this invention increases the friendliness of netlist modifications and reduces time series analysis time by pre-traversing and building a segment tree. Specifically, in the optimized process, each modification involves modifying the netlist. The segment tree only needs to update some subtrees and correspondingly modify some tables, without needing to rebuild the tables from scratch. This reduces the time loss of re-analyzing pessimistic residual removal after each operation. Therefore, the segment tree performs better when modifying tables, significantly reducing the time cost of time series analysis.

[0094] 2. The present invention provides a common path pessimistic margin removal method, which traverses the clock tree to establish a table of indexes, access sequences, and access levels of recording devices. This enables quick access and modification of relevant data in the index table, sequence table, and / or level table during path pessimistic margin removal analysis, significantly improving the efficiency of time series analysis.

[0095] 3. This invention provides a method for removing pessimistic margins in common paths. In the analysis of clock trees, segment trees can be used to quickly query and update the common path information of the clock tree. After completing the traversal process of the clock tree, a segment tree is generated based on the obtained table. The segment tree is an efficient data structure. As a balanced binary tree, it divides the interval into multiple search sub-intervals, thereby realizing efficient sub-interval search and modification operations.

[0096] 4. The pessimistic margin removal method for common paths provided by this invention is a suitable data structure for application scenarios that require searching for the smallest element within an interval, i.e., the nearest common node. Furthermore, obtaining the nearest common node through segment tree queries not only improves the accuracy and efficiency of time series analysis, but also provides strong support for the optimization and dynamic maintenance of clock trees.

[0097] 5. The present invention provides a common path pessimistic margin removal method, in which adjustment and insertion operations optimize the propagation characteristics of clock signals, including delay, skew and stability, by adjusting the structure of the clock tree in the common path pessimistic margin removal analysis, thereby improving the timing performance and reliability of the entire design.

[0098] 6. The pessimistic margin removal method for common paths provided by this invention allows for the modification of library units into functionally equivalent library units with different driving capabilities during adjustment operations. Only the index table needs to be updated, while other tables and segment trees do not need to be modified, thereby improving the efficiency of adjustment operations and reducing time consumption.

[0099] 7. The present invention provides a common path pessimistic margin removal method. In the optimization process, in order to repair some excessively long connections, devices are often inserted in the middle of the connections to interrupt them. For some existing algorithms, this situation will completely fail and need to be rebuilt. However, the segment tree can handle this situation well by modifying the subtree and the corresponding table.

[0100] 8. The computer program product provided by this invention has similar beneficial effects to the above-mentioned method for removing pessimistic margins in common paths, and will not be described in detail here.

[0101] 9. The computer device provided by the present invention has similar beneficial effects to the above-mentioned common path pessimistic margin removal method, and will not be described in detail here.

[0102] 10. The computer-readable storage medium provided by the present invention has similar beneficial effects to the above-mentioned common path pessimistic margin removal method, and will not be described in detail here.

[0103] The foregoing has provided a detailed description of a common path pessimistic margin removal method, product, method, and storage medium disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A common path pessimistic margin removal method, applied to timing analysis on integrated circuits, characterized in that, include: Provide a clock tree, and generate an index table, sequential table, and hierarchical table based on the information obtained after traversing the clock tree; Generate a segment tree based on sequential and hierarchical tables; For any given start and end point of a time-series path, the nearest common node can be obtained by querying a segment tree; Based on the nearest common node, identify the subtrees modified during the optimization process, and modify the index table, sequence table, and / or hierarchy table accordingly. Then, perform a common path pessimistic margin removal analysis to remove pessimistic margins.

2. The method for removing pessimistic margins in common paths as described in claim 1, characterized in that, A clock tree is provided. After traversing the clock tree, an index table, a sequential table, and a hierarchical table are generated based on the information obtained from the traversal, including: Provide a clock tree, traverse the clock tree to obtain each device in the integrated circuit; Record the corresponding index of each device in an index table; Based on the index table, obtain the order in which the devices are accessed and record the order in the sequence table; When a device is not recorded in the index table, the corresponding device name is added to the index table. Obtain the level of the device accessed in the clock tree and record the corresponding level of the device in the level table.

3. The method for removing pessimistic margins in common paths as described in claim 1, characterized in that, Generating a segment tree based on sequential and hierarchical tables includes: Provide the start and end points of the time sequence path, and determine the magnitude of the start and end points; If the starting point is greater than the ending point, then divide the current time sequence path interval into two sub-intervals, record the maximum and minimum values ​​in the current whole interval, and recursively construct segment trees in the two sub-intervals respectively; If the starting point equals the ending point, then construct the leaf node of the segment tree based on the current value; If the starting point is greater than the ending point, then the starting and ending points of the provided time sequence path are returned.

4. The method for removing pessimistic margins in common paths as described in claim 1, characterized in that, For any given start and end point of a time-series path, the nearest common node obtained by segment tree query includes: For any given timing path, the device and its index are determined based on the index table; The minimum value index is obtained by querying using a segment tree; Based on the minimum value index, the corresponding device is retrieved from the hierarchical table, and the corresponding device is the nearest common node.

5. The method for removing pessimistic margins in common paths as described in claim 1, characterized in that: The optimization process includes adjustment operations and insertion operations.

6. The method for removing pessimistic margins in common paths as described in claim 5, characterized in that, The adjustment operations include: An integrated circuit includes several library modules. When a library module in an integrated circuit is replaced, the index of the replaced library module is updated in the index table.

7. The method for removing pessimistic margins in common paths as described in claim 5, characterized in that, Insertion operations include: Based on the nearest common node, determine the sub-interval where the device needs to be inserted; Increment the corresponding subtree level by 1, and modify the corresponding level table based on the subtree.

8. A computer program product, characterized in that: Includes a computer program that, when executed by a processor, implements the common path pessimistic margin removal method as described in any one of claims 1-7.

9. A computer device, characterized in that: It includes a storage device, a processor, and a computer program stored on the storage device, wherein the processor executes the computer program to implement the steps of the common path pessimistic margin removal method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When a computer program is executed by a processor, it implements the steps of the common path pessimistic margin removal method as described in any one of claims 1 to 7.

Images