Gate driving circuit, brush control method and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a local brush control method and a display panel. The nth stage gate driving module comprises: a stage transmission generation unit configured to output an nth stage transmission signal through a stage transmission output end of a current stage in response to an (n-1)th stage transmission signal and a stage transmission clock signal of the current stage; a driving control unit configured to establish a driving control voltage on the driving control node according to the nth stage transmission signal; and a driving output unit configured to generate a gate driving signal of the current stage in response to the driving control voltage and a driving clock signal of the current stage. The application decouples the generation of the stage transmission signal and the output of the gate driving signal, eliminates the false output problem generated at the edge of the local refresh area due to the time sequence overlap of adjacent stage transmission signals, and guarantees the accuracy of picture display and the boundary definition.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit, a partial brush control method, and a display panel. Background Technology

[0002] With the increasing demand for large screen sizes, high resolutions, and low power consumption in display devices, progressive scanning using GOA (Gate Driver on Array) technology has become the mainstream driving method. Currently, to reduce display device power consumption, a partial refresh display mode has been proposed, which scans only the area where the image is being updated, rather than refreshing the entire screen, thus significantly reducing the power consumption of the GOA and the driver IC.

[0003] However, in the current partial refresh GOA circuit, under the multi-CK architecture, due to the long timing overlap between adjacent stage transmission signals, erroneous outputs are usually generated at the edge of the refresh area, resulting in display abnormalities and reducing the reliability of partial refresh.

[0004] Therefore, how to improve the erroneous output at the edge of local refresh is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a gate driving circuit, a local refresh control method, and a display panel. By decoupling the generation of the stage transmission signal from the output of the gate driving signal, the erroneous output problem caused by the timing overlap of adjacent stage transmission signals at the edge of the local refresh area is eliminated, ensuring the accuracy of the screen display and the clarity of the boundary.

[0006] In a first aspect, this application provides a gate driving circuit, including N cascaded gate driving modules. The nth-stage gate driving module includes: a stage transmission generation unit connected to the stage transmission clock signal line of the current stage and the stage transmission output terminal of the (n-1)th-stage gate driving module, configured to: output the nth-stage stage transmission signal through the stage transmission output terminal of the current stage in response to the (n-1)th-stage stage transmission signal and the stage transmission clock signal of the current stage; and a drive control unit connected to the stage transmission output terminal of the current stage and a drive control node, configured to: establish a drive control on the drive control node according to the nth-stage stage transmission signal. The driving control voltage has an amplitude greater than the amplitude of the nth stage transmission signal. A driving output unit, connected to the driving control node and the driving clock signal line of the current stage, is configured to: generate a gate driving signal for the current stage in response to the driving control voltage and the driving clock signal of the current stage; wherein, in the refresh row of the partial refresh mode, the driving clock signal line outputs an active level; in the non-refresh row of the partial refresh mode, the driving clock signal line outputs an inactive level; the transmission clock signal line and the driving clock signal line are independent signal lines.

[0007] Optionally, the stage transmission generation unit includes: a first transistor, wherein the control terminal and the first terminal of the first transistor are respectively connected to the stage transmission output terminal of the (n-1)th stage gate driving module, and the second terminal of the first transistor serves as a stage transmission control node; a second transistor, wherein the control terminal of the second transistor is connected to the stage transmission control node, the first terminal of the second transistor is connected to the stage transmission clock signal line, and the second terminal of the second transistor serves as a stage transmission output terminal; and a first capacitor, wherein the first terminal of the first capacitor is connected to the stage transmission control node, and the second terminal of the first capacitor is connected to the stage transmission output terminal.

[0008] Optionally, the stage transmission generation unit further includes: a third transistor, the control terminal of the third transistor being connected to the stage transmission output terminal of the (n+1)th stage gate drive module, the first terminal of the third transistor being connected to the stage transmission control node, and the second terminal of the third transistor being connected to a low-level terminal.

[0009] Optionally, the drive control unit includes: a fourth transistor, the control terminal and the first terminal of the fourth transistor being connected to the stage output terminal, and the second terminal of the fourth transistor serving as an intermediate control node; a fifth transistor, the control terminal of the fifth transistor being connected to the intermediate control node, the first terminal of the fifth transistor being connected to a power supply voltage terminal, and the second terminal of the fifth transistor serving as a drive control node; and a second capacitor, the first terminal of the second capacitor being connected to the intermediate control node, and the second terminal of the second capacitor being connected to the power supply voltage terminal.

[0010] Optionally, the drive control unit includes: a fourth transistor, the control terminal and the first terminal of the fourth transistor being connected to the stage output terminal, and the second terminal of the fourth transistor serving as an intermediate control node; a fifth transistor, the control terminal of the fifth transistor being connected to the intermediate control node, the first terminal of the fifth transistor being connected to a power supply voltage terminal, and the second terminal of the fifth transistor serving as a drive control node; and a second capacitor, the first terminal of the second capacitor being connected to the intermediate control node, and the second terminal of the second capacitor being connected to the drive control node.

[0011] Optionally, the drive output unit includes: a sixth transistor, the control terminal of which is connected to the drive control node, the first terminal of which is connected to the drive clock signal line, and the second terminal of which serves as the drive output terminal; and a third capacitor, the first terminal of which is connected to the drive control node, and the second terminal of which is connected to the drive output terminal.

[0012] Optionally, the gate driving module further includes: a pull-down unit; the pull-down unit includes: a seventh transistor, the control terminal of which is connected to the stage output terminal of the (n+i)th stage gate driving module, the first terminal of which is connected to the drive output terminal, and the second terminal of which is connected to a low-level terminal; an eighth transistor, the control terminal of which is connected to the control terminal of the seventh transistor, the first terminal of which is connected to the drive control node, and the second terminal of which is connected to the low-level terminal; and a ninth transistor, the control terminal of which is connected to the control terminal of the seventh transistor, the first terminal of which is connected to the intermediate control node, and the second terminal of which is connected to the low-level terminal.

[0013] Secondly, this application provides a partial refresh control method applied to a gate drive circuit. The partial refresh control method includes: in global refresh mode and partial refresh mode, generating a current stage transmission signal in response to the stage transmission signal of the previous stage and the stage transmission clock signal of the current stage; establishing a drive control voltage on the drive control node according to the stage transmission signal; and in partial refresh mode, controlling the drive clock signal line of the current stage to output an effective level during the corresponding time period of the refresh row, so that the refresh row outputs the gate drive signal of the current stage under the combined action of the drive control voltage and the drive clock signal.

[0014] Optionally, the partial refresh control method further includes: in partial refresh mode, controlling the current stage's drive clock signal line to output an invalid level during the corresponding time period of the non-refresh line, so that no gate drive signal is output for the non-refresh line.

[0015] Thirdly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; the non-display area includes the gate driving circuit, and the drive output terminal of the gate driving circuit is electrically connected to at least one scan line.

[0016] The technical solutions provided in this application have at least the following beneficial effects:

[0017] This application decouples the generation of cascade signals from the output of gate drive signals. It uses independent cascade clock signal lines and drive clock signal lines to control the cascade generation unit and drive output unit respectively, and sets up a drive control unit to convert the weak cascade signals into a higher-amplitude drive control voltage, thus achieving separation and enhancement of cascade and output. In partial refresh mode, the cascade generation unit remains operational, generating stable cascade signals step by step to ensure the integrity of the cascade chain. The drive clock signal line is selectively controlled, outputting a valid level only on refresh lines and an invalid level on non-refresh lines. Therefore, refresh lines output gate drive signals normally under the combined action of drive control voltage and drive clock, while non-refresh lines, although having drive control voltage, remain silent due to the lack of a drive clock. This eliminates the erroneous output problem at the edge of the partial refresh area caused by the timing overlap of adjacent cascade signals in multi-CK architectures, ensuring the accuracy and clarity of the display. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 The diagram shown is a schematic diagram of a display partition provided in an embodiment of this application.

[0020] Figure 2 The diagram shown is a schematic diagram of the gate drive module in the related technology.

[0021] Figure 3 The diagram shown is a circuit schematic of a gate drive module in the related art.

[0022] Figure 4 The diagram shown is a schematic of the driving timing in the related technology.

[0023] Figure 5 The diagram shown is a structural schematic of a gate driving module provided in an embodiment of this application.

[0024] Figure 6 The diagram shown is a circuit diagram of the first type of gate driving module provided in an embodiment of this application.

[0025] Figure 7 The diagram shown is a driving timing diagram provided in an embodiment of this application.

[0026] Figure 8 The diagram shown is a circuit diagram of a second type of gate driving module provided in an embodiment of this application.

[0027] Figure 9 The diagram shown is a flowchart of a local brush control method provided in an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures:

[0029] 100. Gate drive module; 110. Stage generation unit; 120. Drive control unit; 130. Drive output unit; 140. Pull-down unit;

[0030] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor;

[0031] Qn, stage transmission control node; Q1n, drive control node; An, intermediate control node; Fn, stage transmission output terminal; Gn, drive output terminal; VSS, low level terminal; VGH, power supply voltage terminal; FCK, stage transmission clock signal line; GCK, drive clock signal line. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0033] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0034] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0035] Most current display devices are active display devices, typically driven by a line-by-line scanning method for pixel setting. Each row of pixels has one scan line, and the scan lines are activated line by line, working in conjunction with data lines to write the target grayscale. The activation of the scan lines is generally achieved using the gate-of-aperture (GOA) method, where the GOA provides the gate drive signal and performs the line-by-line activation function. To save power consumption in display devices, a partial refresh display mode has been proposed, such as... Figure 1 As shown, during normal display, regions A, B, and C all need to be scanned and written line by line. When partial refresh display is used (for example, if only region B has a screen update, region B is partially refreshed), regions A and C are not scanned and written every frame, thereby reducing the output power consumption of GOA and IC. The partial refresh function can be applied to various display devices, such as electronic paper, OLDE, and LCD.

[0036] The inventors of this application have discovered that existing partial refresh GOA technology is generally applied to 2CK circuits in small-sized display devices, and there are no multi-CK GOA circuits. Figure 2 The diagram shows a commonly used basic GOA circuit unit, including a precharge unit, a pull-down unit, an output unit, a noise reduction unit, and a reset unit. The precharge unit and the pull-down unit are responsible for precharging and pulling down the Q point in the circuit, respectively. The precharge and pull-down are controlled by receiving stage transmission signals from the preceding and following stages, respectively. The output unit is turned on with the Q point as the gate and outputs using the clock signal as the gate drive signal. The noise reduction unit performs noise reduction processing on important signals in the circuit. The reset unit pulls down and resets the Q point in each frame. Figure 3 The diagram shows the basic components of a pre-charge unit, a pull-down unit, and an output unit. The diagram uses the first j-stage for pre-charging and the last i-stage for pull-down. Figure 4 As shown Figure 3 The waveform of the GOA circuit shown is that point Q is pulled high by the upper three-stage signals and pulled low by the lower four-stage signals, and the gate drive signal is output using point Q.

[0037] The inventors of this application have also discovered that when a multi-CK GOA circuit needs to employ a partial refresh function, the common practice is to trigger the partial refresh start stage using a pre-stored signal, causing the refresh to propagate from the local refresh position. However, in a multi-CK GOA circuit, the Q points and Gouts of adjacent stages overlap, making it difficult to conveniently pre-store and activate the local refresh start stage using signals. This results in erroneous pre-stored signals in adjacent stages above the target position, leading to incorrect output. Therefore, the current design can only be used in a 2CK GOA circuit and cannot be directly ported to a multi-CK GOA circuit to implement local refresh.

[0038] To improve the problem of erroneous output at local refresh edge positions, this application provides a new gate drive circuit, specifically including the following embodiments:

[0039] Figure 5 The diagram shown is a structural schematic of a gate driving module 100 provided in an embodiment of this application. The gate driving circuit of this embodiment includes N cascaded gate driving modules 100 (N is an integer greater than 1). Taking the nth stage (1≤n≤N) gate driving module as an example, two independent clock systems are used to decouple the generation of the cascaded signal from the output of the gate driving signal. Specifically:

[0040] like Figure 5 As shown, the nth stage gate drive module 100 includes a stage transmission generation unit 110, which is connected to the stage transmission clock signal line FCK of the current stage and the stage transmission output terminal of the (n-1)th stage gate drive module. It is configured to output the nth stage transmission signal through the stage transmission output terminal Fn of the current stage in response to the (n-1)th stage transmission signal and the stage transmission clock signal of the current stage.

[0041] It should be noted that the stage transmission generation unit 110 is the core of the 2CK GOA circuit, responsible for generating the stage transmission signal F(n) for this stage. Its operation is based on two inputs: the stage transmission signal F(n-1) of the (n-1)th stage and the corresponding stage transmission clock signal; wherein, the stage transmission clock adopts a two-phase clock of the 2CK architecture, used to generate narrow pulse stage transmission signals, such as the first stage transmission clock signal and the second stage transmission clock signal being used alternately; for example, if the nth stage gate drive module is connected to the first stage clock signal line, then the (n-1)th stage gate drive module and the (n+1)th stage gate drive module are connected to the second stage clock signal line.

[0042] Specifically, when the cascade signal F(n-1) of the (n-1)th stage is high, the pre-charge path inside the cascade generation unit 110 is activated to pre-charge the internal nodes. Subsequently, when the effective pulse of the cascade clock signal of this stage arrives, a narrow pulse with a width of approximately one clock cycle (1H) is generated at the output terminal of this stage through a boost coupling mechanism. This pulse is used to drive subsequent cascaded modules and serves as the input to the drive control unit 120 of this stage.

[0043] Therefore, the cascade signal generated by the cascade generation unit 110 in this embodiment is a narrow pulse, which has a light load and low noise, ensuring the stability of cascade transmission. In addition, the cascade signal in this embodiment adopts a 2CK architecture, which not only has a simple circuit structure and low power consumption, but also makes the cascade signal unaffected by the drive output load, realizing the decoupling of cascade transmission and output.

[0044] In this embodiment, as Figure 5As shown, the nth stage gate drive module 100 also includes a drive control unit 120, which is connected to the stage transmission output terminal Fn of the current stage and the drive control node Q1n, and is configured to: establish a drive control voltage on the drive control node Q1n according to the nth stage transmission signal; wherein the amplitude of the drive control voltage is greater than the amplitude of the nth stage transmission signal.

[0045] It should be noted that the drive control unit 120 is a crucial bridge connecting the stage transmission section and the output section. Its input is the stage transmission signal F(n) of this stage, and its output is the drive control voltage on the drive control node Q1n. Since the stage transmission signal is a narrow pulse under the 2CK architecture, its driving capability is weak and cannot directly drive large-size output transistors. The drive control unit 120 converts the stage transmission signal into a drive control voltage with a higher amplitude and stronger driving capability. Specifically, when the stage transmission signal is high, the drive control unit 120 charges the drive control node Q1n, causing the voltage of the drive control node Q1n to rise to a high level (close to Vgh); when the stage transmission signal disappears, the capacitor element inside the drive control unit 120 maintains the high level of the drive control node Q1n, ensuring the stability of the voltage of the drive control node Q1n during output.

[0046] In this embodiment, the amplitude of the drive control voltage is greater than the amplitude of the nth stage transmission signal. In other words, the drive control unit 120 not only realizes the transmission of the signal, but also realizes the increase of the voltage amplitude and the enhancement of the drive capability, thereby solving the problem of insufficient drive force of the transmission signal and ensuring that the drive output unit 130 can be fully turned on.

[0047] like Figure 5 As shown, the nth stage gate drive module 100 also includes a drive output unit 130, which is connected to the drive control node Q1n and the drive clock signal line GCK of the current stage, and is configured to generate the gate drive signal of the current stage in response to the drive control voltage and the drive clock signal of the current stage.

[0048] It should be noted that the drive output unit 130 is the final signal output stage. Its control terminal is connected to the drive control node Q1n, and its signal input terminal is connected to the corresponding drive clock signal line GCK. The drive clock adopts a multi-CK architecture (multi-phase clock), such as 6CK, 8CK, etc. The drive clock signal line GCK of the current stage is one of multiple drive clock signal lines GCK. In this embodiment, the multi-phase drive clock signal line GCK and the two-phase stage transmission clock signal line FCK are two completely independent sets of signal lines. When the drive control node Q1n is high, the drive output unit 130 is turned on, outputting the high level of the drive clock signal as a gate drive signal to the corresponding scan line, thus driving the pixel TFT. The output signal has sufficient driving capability and a steep rise edge.

[0049] In summary, this embodiment achieves precise control of the gate drive signal in partial refresh mode through the coordinated operation of the stage generation unit 110, the drive control unit 120, and the drive output unit 130. The specific working principle is as follows:

[0050] 1. Global refresh mode (normal scan)

[0051] When the display panel needs to be updated to full screen, enter global refresh mode:

[0052] (1) The transmission generation unit 110 operates step by step: the first stage is triggered by the start signal to generate the first stage transmission signal F(1); the first stage transmission signal F(1) drives the second stage transmission generation unit 110 to generate the second stage transmission signal F(2); and so on, the nth stage transmission signal F(n) pulse is transmitted step by step to form a complete transmission chain. The pulse width of each transmission signal is about 1H, which is stable and reliable.

[0053] (2) The drive control unit 120 synchronously establishes the drive voltage: For each stage, when the stage transmission signal F(n) of the nth stage arrives, the drive control unit 120 immediately charges the drive control node Q1n, causing the voltage of the drive control node Q1n to rise to the high level of Vgh. Due to the maintenance effect of the capacitor inside the drive control unit 120, the high level of Qn can still be maintained after F(n) disappears.

[0054] (3) Normal output of drive output unit 130: In global refresh mode, all drive clock signal lines GCK output valid pulses normally. When the drive control node Q1n of the nth stage is high and its corresponding drive clock pulse arrives, drive output unit 130 is turned on and outputs the gate drive signal of the nth stage to complete the row scan.

[0055] (4) Reset: At an appropriate time (such as when the stage transmission signal of stage n+i arrives), the drive control node Q1n and drive output terminal Gn of each stage are pulled down and reset to prepare for the next frame.

[0056] 2. Partial refresh mode

[0057] When the system needs to perform a partial refresh on a specific area (e.g., multiple consecutive rows starting from row n), it enters partial refresh mode:

[0058] (1) The cascade generation unit 110 always works: Regardless of whether a local refresh is performed, the cascade generation unit 110 always works normally, and the F(1), F(2)...F(N) pulses are transmitted step by step without interruption. This ensures the integrity of the cascade chain and provides the necessary control signals for subsequent rows.

[0059] (2) The drive control unit 120 still works normally: The drive control unit 120 of each stage still responds to the F(n) pulse and establishes the drive control voltage on the drive control node Q1n. This means that even for non-refresh lines, its drive control node Q1n is in a high-level state.

[0060] (3) The driving clock signal is selectively controlled: This is the key to achieving partial refresh. The system controls the driving clock signal line GCK so that it outputs a valid pulse only during the time period corresponding to the row that needs to be refreshed, and outputs an invalid level (keeps it low) during the time period corresponding to the non-refreshed row. Specifically:

[0061] ① For refresh rows (such as rows n, n+1, and n+2): The drive clock signal outputs normal pulses. When the drive control node Q1n for that row is high and the drive clock pulse arrives, the drive output unit 130 is turned on, outputting the gate drive signal to refresh that row.

[0062] ② For non-refreshed rows (such as rows n-1, n+3 and beyond): there is no pulse output of the drive clock signal. Although the drive control node Q1n of this row is high, the drive output unit 130 cannot be turned on because the drive clock is low, and there is no gate drive signal output. The pixels in this row retain the original data.

[0063] (4) The advantage of complete decoupling between transmission and output is reflected: Since the transmission signal F(n) and the driving clock are independent of each other, the F(n) of the non-refresh line is still transmitted normally, driving the transmission generation unit 110 of the subsequent level, but it will not cause the erroneous output of the line, thus avoiding the edge erroneous output problem caused by the overlap of transmission signals under the multi-CK architecture.

[0064] 3. Start and end control of partial refresh

[0065] (1) Start control: For the nth row that needs to be refreshed, simply ensure that the drive clock signal line GCK of that row outputs a valid level.

[0066] (2) End control: After the mth row that needs to be refreshed, stop the output of the driving clock pulse of the subsequent row; although the driving control node Q1n of the subsequent row is at a high level, it remains silent because there is no driving clock, thus achieving precise termination.

[0067] (3) Arbitrary position and length: By controlling the starting position and duration of the driving clock pulse, a local refresh area with any starting line and any number of lines can be realized, and the control is extremely simple.

[0068] 4. Reset and noise reduction mechanism

[0069] Regardless of whether it is a global refresh or a partial refresh, after each line scan is completed, when the subsequent transmission signal (such as the n+7th level) arrives, the pull-down unit 140 resets the current level's drive control node Q1n and drive output terminal Gn to a low level to prepare for the next frame; at the same time, the noise reduction unit performs noise reduction processing on each node during idle periods to prevent malfunctions caused by charge accumulation.

[0070] Therefore, this application decouples the generation of the cascade signal from the output of the gate drive signal. It uses independent cascade clock signal lines FCK and GCK to control the cascade generation unit 110 and the drive output unit 130 respectively, and sets up a drive control unit 120 to convert the weak cascade signal into a higher-amplitude drive control voltage, thus achieving separation and enhancement of cascade and output. In partial refresh mode, the cascade generation unit 110 remains operational, generating stable cascade signals step by step to ensure the integrity of the cascade chain. The drive clock signal line GCK is selectively controlled, outputting a valid level only on refresh lines and an invalid level on non-refresh lines. Thus, refresh lines output the gate drive signal normally under the combined action of the drive control voltage and the drive clock, while non-refresh lines, although having a drive control voltage, remain silent due to the lack of a drive clock. This eliminates the erroneous output problem caused by the timing overlap of adjacent cascade signals at the edge of the partial refresh area in the multi-CK architecture, ensuring the accuracy and clarity of the image display.

[0071] Meanwhile, the drive control unit 120 increases the voltage amplitude of the stage transmission signal, solving the problem of insufficient driving capability of the 2CK stage transmission signal, ensuring that the output transistor is fully turned on, and guaranteeing the output quality and stability of the gate drive signal. This application realizes on-demand start-up and precise control of the gate drive signal, effectively reducing the scanning power consumption of the non-refreshing area while ensuring display quality, supporting local refresh areas with arbitrary start positions and lengths, and significantly improving the energy efficiency ratio and overall reliability of the local refresh function of the display device. Therefore, this application provides a simple, convenient, and high-performance technical solution for large-size, multi-CK display devices to achieve low-power, high-performance local refresh functions.

[0072] Figure 6 The diagram shown is a circuit schematic of the first type of gate driving module 100 provided in an embodiment of this application; as shown Figure 6As shown, the stage transmission generation unit 110 includes a first transistor T1, a second transistor T2, and a first capacitor C1; the control terminal and the first terminal of the first transistor T1 are respectively connected to the stage transmission output terminal of the (n-1)th stage gate drive module, and the second terminal of the first transistor T1 serves as the stage transmission control node Qn; the control terminal of the second transistor T2 is connected to the stage transmission control node Qn, the first terminal of the second transistor T2 is connected to the stage transmission clock signal line FCK, and the second terminal of the second transistor T2 serves as the stage transmission output terminal Fn; the first terminal of the first capacitor C1 is connected to the stage transmission control node Qn, and the second terminal of the first capacitor C1 is connected to the stage transmission output terminal Fn.

[0073] Optionally, the stage generation unit 110 further includes: a third transistor T3, the control terminal of the third transistor T3 is connected to the stage output terminal of the (n+1)th stage gate drive module, the first terminal of the third transistor T3 is connected to the stage control node Qn, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0074] It should be noted that the working principle of the cascading generation unit 110 provided in this embodiment is as follows:

[0075] (1) Pre-charge stage: such as Figure 7 At time t1, when the output terminal of the (n-1)th stage outputs a high level, the first transistor T1 turns on, charging the stage transmission control node Qn through the stage transmission signal of the (n-1)th stage, and storing the charge through the first capacitor C1. At this time, the stage transmission clock signal line FCK of this stage outputs a low level. Although the second transistor T2 gradually turns on due to the rising potential of the stage transmission control node Qn, the stage transmission clock signal of the current stage is low, so the output terminal of this stage remains low.

[0076] The purpose of this stage is to pre-charge the stage control node Qn using the stage transmission signal from the previous stage, thus establishing the base voltage for the subsequent boost output.

[0077] (2) Boost output stage: such as Figure 7 At time t2, when the stage transmission clock signal line FCK of this stage outputs a high level, the stage transmission control node Qn is already in a pre-charged high-level state, the second transistor T2 is fully turned on, and the high level of the stage transmission clock signal is transmitted to the stage transmission output terminal of this stage through the turned-on second transistor T2, outputting the current stage transmission signal.

[0078] At the same time, the voltage rise at the stage transmission output terminal is coupled to the stage transmission control node Qn through the first capacitor C1, which further raises the potential of the stage transmission control node Qn, forming a bootstrap voltage boost effect, ensuring that the second transistor T2 remains in a deeply conducting state, and improving the output quality of the stage transmission signal.

[0079] The function of this stage is to generate a complete high-level pulse at the stage output terminal through the bootstrap coupling of the first capacitor C1, driven by the current stage transmission clock signal. At the same time, the potential of the stage transmission control node Qn is raised to a higher level, thereby improving the output quality of the stage transmission signal.

[0080] (3) Reset phase: such as Figure 7 After time t3, when the stage transmission output terminal of the (n+1)th stage outputs a high-level stage transmission signal: the third transistor T3 is turned on, the potential of the stage transmission control node Qn is pulled down to a low level, so that the stage transmission output terminal of this stage returns to a low level.

[0081] The purpose of this stage is to reset the circuit of this stage using the subsequent stage transmission signal, clear the residual charge on the transmission control node Qn, and prepare for the operation of the next frame.

[0082] Therefore, this embodiment completes the full cycle of pre-charge, boost, and reset through the cascade generation unit 110, ensuring reliable transmission of the cascade signal. The output of each stage depends on the cooperation of the preceding and following stages, forming a stable cascade chain. At the same time, the stable output of the cascade signal is a prerequisite for the normal operation of the subsequent drive control unit 120 and drive output unit 130, and is also the key to achieving decoupling between cascade transmission and output.

[0083] like Figure 6 As shown, the drive control unit 120 includes a fourth transistor T4, a fifth transistor T5, and a second capacitor C2. Specifically, the control terminal and the first terminal of the fourth transistor T4 are connected to the stage output terminal Fn, and the second terminal of the fourth transistor T4 serves as an intermediate control node An. The control terminal of the fifth transistor T5 is connected to the intermediate control node An, the first terminal of the fifth transistor T5 is connected to the power supply voltage terminal VGH, and the second terminal of the fifth transistor T5 serves as a drive control node Q1n. The first terminal of the second capacitor C2 is connected to the intermediate control node An, and the second terminal of the second capacitor C2 is connected to the power supply voltage terminal VGH.

[0084] Here, combined with Figure 7 The working principle of the drive control unit 120 in this embodiment is explained as follows:

[0085] (1) Intermediate node charging stage: such as Figure 7 At time t2, when the stage transmission output terminal of this stage outputs a high level: the fourth transistor T4 is turned on, the high-level stage transmission signal charges the intermediate control node An through the fourth transistor T4, and is stored through the second capacitor C2.

[0086] The purpose of this stage is to charge the intermediate control node An using the stage transmission signal, and to establish a voltage signal related to the stage transmission signal at the intermediate control node An. In addition, due to the diode connection of the fourth transistor T4, the current can only flow from the stage transmission output terminal to the intermediate control node An, ensuring that the voltage of the intermediate control node An will not flow back to the stage transmission output terminal.

[0087] (2) Pre-charge stage of drive control node Q1n: such as Figure 7 During the t2-t4 period: As the potential of the intermediate control node An rises, when the potential of the intermediate control node An reaches the turn-on threshold of the fifth transistor T5, the fifth transistor T5 begins to conduct. After the fifth transistor T5 is turned on, the power supply voltage Vgh (high level) output from the power supply voltage terminal VGH charges the drive control node Q1n through the fifth transistor T5, causing the potential of the drive control node Q1n to rise rapidly. Since the source of the fifth transistor T5 is connected to Vgh and the drain is connected to the drive control node Q1n, when the voltage of the drive control node Q1n rises to close to Vgh, the gate-source voltage (Vgs) of the fifth transistor T5 decreases, but the fifth transistor T5 can still maintain the high level of the drive control node Q1n.

[0088] The purpose of this stage is to convert the voltage signal of the intermediate control node An into a high-level drive voltage on the drive control node Q1n. Since Vgh is a stable high-level power supply, the drive control node Q1n can obtain the complete Vgh voltage, which is much higher than the voltage amplitude of F(n), thus achieving an increase in voltage amplitude.

[0089] (3) Maintenance phase: such as Figure 7 The t3-t5 time period: after the F(n) pulse ends ( Figure 7 After time t3): F(n) returns to low level, the fourth transistor T4 turns off, and the intermediate control node An loses its charging path. However, the second capacitor C2 has stored charge, and its voltage is (Vgh - VA). Since one end of the second capacitor C2 is connected to a fixed Vgh, the potential of the intermediate control node An is maintained by the charge of the second capacitor C2; as long as the leakage current of the second capacitor C2 is small enough, the potential of the intermediate control node An can remain at a high level after F(n) disappears, keeping the fifth transistor T5 on. Therefore, the high level of the drive control node Q1n can be maintained, providing a stable drive control voltage for the subsequent drive output unit 130.

[0090] The function of this stage is to utilize the charge storage capacity of the second capacitor C2 to maintain the potential of the intermediate control node An after F(n) disappears, thereby maintaining the high level of the drive control node Q1n and ensuring that the drive output unit 130 has enough time to wait for the arrival of the drive clock pulse.

[0091] (4) Reset preparation stage: such as Figure 7 At time t6, when the transmission signal of the (n+7)th level arrives, the pull-down unit 140 will reset the drive control node Q1n, the intermediate control node An and the drive output node to a low level, in preparation for the next frame.

[0092] like Figure 6 As shown, the drive output unit 130 includes a sixth transistor T6 and a third capacitor C3; the control terminal of the sixth transistor T6 is connected to the drive control node Q1n, the first terminal of the sixth transistor T6 is connected to the drive clock signal line GCK, and the second terminal of the sixth transistor T6 serves as the drive output terminal Gn; the first terminal of the third capacitor C3 is connected to the drive control node Q1n, and the second terminal of the third capacitor C3 is connected to the drive output terminal Gn.

[0093] Here, combined with Figure 7 The working principle of the drive output unit 130 in this embodiment is explained as follows:

[0094] (1) Waiting stage ( Figure 7 Before time t4: Before the arrival of the drive clock pulse, the drive control node Q1n has been pre-charged to a high level by the drive control unit 120, making the sixth transistor T6 in a ready-to-conduct state. At this time, the drive clock signal line GCK is at a low level, so the drive output terminal Gn remains at a low level. The voltage difference between the high level of the drive control node Q1n and the low level of the drive output terminal Gn is stored across the third capacitor C3.

[0095] (2) Output rising phase ( Figure 7 During the t4-t5 period: When the corresponding drive clock signal line GCK outputs a valid pulse, the signal changes from low to high. Since the sixth transistor T6 is turned on, the high level of the drive clock is transmitted to the drive output terminal Gn through the transistor, causing the voltage at the drive output terminal Gn to start rising.

[0096] At this point, the third capacitor C3 plays a crucial role: the rise of the drive output terminal Gn is coupled to the drive control node Q1n through the capacitor, further raising the potential of the drive control node Q1n. This coupling effect forms positive feedback, that is: the rise in the potential of the drive control node Q1n makes the sixth transistor T6 conduct more fully, the on-resistance decreases, the high level of the drive clock is transmitted to the output terminal more completely, the rise speed of the output terminal is accelerated, and finally reaches a high level close to that of the drive clock.

[0097] (3) Output maintenance phase ( Figure 7(At time t5): When the drive output terminal Gn reaches its highest level, the drive control node Q1n also reaches its peak potential due to coupling, and the sixth transistor T6 is in a deeply turned-on state. As long as the drive clock remains high, the drive output terminal Gn will maintain a high level output, providing the gate drive signal for the pixel transistors in the corresponding row.

[0098] (4) Output descent phase ( Figure 7 During the t5-t6 period: When the pulse of the drive clock signal line GCK ends, the signal jumps from high to low. Since the sixth transistor T6 is still conducting, the low level of the drive clock is transmitted to the drive output terminal Gn, causing Gn to begin to drop. The drop in the drive output terminal Gn is coupled back to the drive control node Q1n through the third capacitor C3, causing its potential to decrease accordingly. When the drive control node Q1n drops below the threshold voltage of the sixth transistor T6, the sixth transistor T6 is turned off, and the drive output terminal Gn is reset to low by the subsequent pull-down unit 140.

[0099] (5) Reset phase ( Figure 7 (At time t6 and after): When the subsequent cascade signal arrives, the drive output terminal Gn and the drive control node Q1n are reset to low level through the pull-down unit 140 to prepare for the next frame.

[0100] Therefore, the drive output unit 130 in this embodiment implements a ready-to-output responsive mechanism: the high level of the drive control node Q1n indicates that the current stage is ready, and the presence or absence of the drive clock pulse determines whether to execute the output; furthermore, the bootstrap coupling effect of the third capacitor C3 significantly improves the drive capability, ensures the steepness of the rising edge and the integrity of the amplitude of the gate drive signal, and completely decouples the stage transmission signal from the drive output. In the local refresh mode, the output area can be precisely controlled by controlling the position of the drive clock pulse, while the stage transmission signal always remains continuous, avoiding the problem of edge error output.

[0101] In one embodiment, such as Figure 6As shown, the gate drive module 100 further includes a pull-down unit 140; further, the pull-down unit 140 includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9; the control terminal of the seventh transistor T7 is connected to the stage output terminal of the (n+i)th stage gate drive module, the first terminal of the seventh transistor T7 is connected to the drive output terminal Gn, and the second terminal of the seventh transistor T7 is connected to the low-level terminal VSS; the control terminal of the eighth transistor T8 is connected to the control terminal of the seventh transistor T7, the first terminal of the eighth transistor T8 is connected to the drive control node Q1n, and the second terminal of the eighth transistor T8 is connected to the low-level terminal VSS; the control terminal of the ninth transistor T9 is connected to the control terminal of the seventh transistor T7, the first terminal of the ninth transistor T9 is connected to the intermediate control node An, and the second terminal of the ninth transistor T9 is connected to the low-level terminal VSS.

[0102] It should be noted that the pull-down unit 140 is composed of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9. The control terminals of all three are connected to the stage transmission output terminal of the (n+i)th stage gate drive module. When the stage transmission signal of the (n+i)th stage arrives (i.e., after the scanning of this stage ends), the high level simultaneously turns on the three transistors. Specifically: (1) The seventh transistor T7 turns on, pulling down the drive output terminal Gn to the low level to ensure that the pixel transistor is turned off in time; (2) The eighth transistor T8 turns on, pulling down the drive control node Q1n to the low level to clear the charge on it and prepare for the next frame; (3) The ninth transistor T9 turns on, pulling down the intermediate control node An to the low level to prevent charge accumulation from causing malfunctions.

[0103] The function of the pull-down unit 140 in this embodiment is to synchronously reset the three key nodes—the drive output terminal Gn, the drive control node Q1n, and the intermediate control node An—after each line scan is completed, ensuring that the circuit state is cleared, providing a definite initial condition for the scan of the next frame, and avoiding display abnormalities caused by residual charge.

[0104] Figure 8 The diagram shown is a circuit diagram of the second type of gate driving module 100 provided in an embodiment of this application; Figure 8 The gate drive module 100 shown is Figure 6 The difference between the gate drive module 100 shown is that the connection method of the second capacitor C2 is different; specifically as follows: Figure 8 As shown, in this embodiment, the first end of the second capacitor C2 is connected to the intermediate control node An, and the second end of the second capacitor C2 is connected to the drive control node Q1n.

[0105] It should be noted that in this embodiment, one end of the second capacitor C2 is connected to the intermediate control node An, and the other end is connected to the drive control node Q1n. When the intermediate control node An is charged, the second capacitor C2 stores the voltage difference between the intermediate control node An and the drive control node Q1n. When the drive control node Q1n is charged by the fifth transistor T5 and rises, the rise of the drive control node Q1n is coupled to the intermediate control node An through the second capacitor C2, further raising the potential of the intermediate control node An. The raised intermediate control node An makes the fifth transistor T5 conduct more fully, and the drive control node Q1n rises faster, forming positive feedback.

[0106] Therefore, it can be seen that the second capacitor C2 in this embodiment enables dynamic coupling between the intermediate control node An and the drive control node Q1n, which promote each other and have a positive feedback enhancement effect.

[0107] Figure 9 The diagram shown is a schematic flowchart of a local swiping control method provided in an embodiment of this application; as follows: Figure 9 As shown, the partial brush control method provided in this embodiment is applied to the gate drive circuit shown in the above embodiment, and specifically includes the following steps:

[0108] Step S100: In global refresh mode and local refresh mode, in response to the previous level's transmission signal and the current level's transmission clock signal, generate the current level's transmission signal.

[0109] Step S200: Establish a drive control voltage on the drive control node according to the transmission signal.

[0110] Step S300: In partial refresh mode, control the current stage's drive clock signal line to output an effective level during the corresponding time period of the refresh row, so that the refresh row outputs the current stage's gate drive signal under the combined action of the drive control voltage and the drive clock signal.

[0111] In one embodiment, the local refresh control method further includes: in local refresh mode, controlling the current stage's drive clock signal line to output an invalid level during the corresponding time period of the non-refresh line, so that no gate drive signal is output for the non-refresh line.

[0112] It should be noted that the working principle of the partial brush control method provided in this embodiment is essentially the same as that of the gate drive circuit described above. Both are based on the decoupling of cascade transmission and output. The generation of the cascade transmission signal and the output of the gate drive signal are controlled by independent cascade transmission clock signal lines and drive clock signal lines, respectively, to achieve a combination of stable cascade transmission and controllable output. Therefore, the specific workflow, signal timing, and potential changes of each node of this method can be found in the detailed description of the working principle of the gate drive circuit above, and will not be repeated here.

[0113] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The drive output terminal of the gate driving circuit is electrically connected to at least one scan line.

[0114] The gate drive circuit, partial brush control method, and display panel provided in this application decouple the generation of the stage transmission signal from the output of the gate drive signal. They use independent stage transmission clock signal lines and drive clock signal lines to control the stage transmission generation unit and the drive output unit respectively. The drive control unit is set to convert the weak stage transmission signal into a drive control voltage with higher amplitude and stronger drive capability, thereby realizing the separation and enhancement of stage transmission and output.

[0115] Specifically, the gate drive circuit of this application, through the coordinated operation of the cascade generation unit, drive control unit, and drive output unit, is compatible with traditional GOA functions in global refresh mode, and achieves precise local refresh in partial refresh mode through a mechanism of independent cascade and controllable output. The cascade generation unit always responds to the cascade signal of the previous stage and the cascade clock signal of the current stage, generating stable cascade signals stage by stage to ensure the integrity of the cascade chain. The drive control unit establishes an enhanced drive control voltage on the drive control node based on the cascade signals. The drive output unit outputs the gate drive signal under the combined action of the drive control voltage and the drive clock signal. In partial refresh mode, the drive clock signal line is selectively controlled, outputting an effective level only in refreshed rows and an ineffective level in non-refreshed rows. This ensures that only refreshed rows output the gate drive signal, while non-refreshed rows, although having a drive control voltage, remain silent due to the lack of a drive clock.

[0116] Therefore, this application eliminates the erroneous output problem caused by the timing overlap of adjacent stage transmission signals at the edge of the local refresh area under the multi-CK architecture by completely decoupling the stage transmission and output, and realizes precise control of the refresh boundary; the drive control unit increases the voltage amplitude of the stage transmission signal, solves the problem of insufficient driving capability of 2CK stage transmission signal, and ensures full conduction of the output tube and output waveform quality; the local refresh control is extremely simple, only requiring control of the occurrence position of the drive clock pulse to realize a local refresh area of ​​arbitrary starting position and arbitrary length, without the need for complex pre-stored trigger circuits; the stage transmission part has light load, low power consumption, and low noise, while the output part has strong drive, good waveform, and high uniformity; it is seamlessly compatible with the global refresh mode without changing the workflow of the existing display system; through modular circuit design, it is easy to integrate and implement in large-size, high-resolution display devices.

[0117] Therefore, this application provides a simple, easy-to-control, and high-performance technical solution for large-size, multi-CK display devices to achieve low-power, high-reliability local refresh functionality, which has significant industrial practical value and broad application prospects.

[0118] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0119] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0120] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, comprising N cascaded gate driving modules, characterized in that, The nth-stage gate drive module includes: The stage transmission generation unit is connected to the stage transmission clock signal line of the current stage and the stage transmission output terminal of the (n-1)th stage gate drive module, and is configured to: in response to the (n-1)th stage transmission signal and the stage transmission clock signal of the current stage, output the nth stage transmission signal through the stage transmission output terminal of the current stage. A drive control unit, connected to the current level's transmission output terminal and drive control node, is configured to: establish a drive control voltage on the drive control node according to the nth level transmission signal; wherein the amplitude of the drive control voltage is greater than the amplitude of the nth level transmission signal. The drive output unit, connected to the drive control node and the drive clock signal line of the current stage, is configured to generate the gate drive signal of the current stage in response to the drive control voltage and the drive clock signal of the current stage. In the partial refresh mode, the driving clock signal line outputs an active level for refreshed rows; in the partial refresh mode, the driving clock signal line outputs an inactive level for non-refreshed rows; the cascading clock signal line and the driving clock signal line are independent signal lines.

2. The gate driving circuit according to claim 1, characterized in that, The cascade generation unit includes: The first transistor has its control terminal and first terminal connected to the stage transmission output terminal of the (n-1)th stage gate drive module, and its second terminal serves as the stage transmission control node. The second transistor has its control terminal connected to the stage transmission control node, its first terminal connected to the stage transmission clock signal line, and its second terminal serving as the stage transmission output terminal of the current stage. A first capacitor, the first end of which is connected to the stage transmission control node, and the second end of which is connected to the stage transmission output terminal of the current stage.

3. The gate driving circuit according to claim 2, characterized in that, The cascade generation unit further includes: The third transistor has its control terminal connected to the stage transmission output terminal of the (n+1)th stage gate drive module, its first terminal connected to the stage transmission control node, and its second terminal connected to the low-level terminal.

4. The gate driving circuit according to claim 1, characterized in that, The drive control unit includes: The fourth transistor has its control terminal and first terminal connected to the stage output terminal of the current stage, and its second terminal serves as an intermediate control node. The fifth transistor has its control terminal connected to the intermediate control node, its first terminal connected to the power supply voltage terminal, and its second terminal serving as the drive control node. The second capacitor has its first terminal connected to the intermediate control node and its second terminal connected to the power supply voltage terminal.

5. The gate driving circuit according to claim 1, characterized in that, The drive control unit includes: The fourth transistor has its control terminal and first terminal connected to the stage output terminal of the current stage, and its second terminal serves as an intermediate control node. The fifth transistor has its control terminal connected to the intermediate control node, its first terminal connected to the power supply voltage terminal, and its second terminal serving as the drive control node. The second capacitor has its first end connected to the intermediate control node and its second end connected to the drive control node.

6. The gate driving circuit according to claim 1, characterized in that, The drive output unit includes: The sixth transistor has its control terminal connected to the drive control node, its first terminal connected to the drive clock signal line, and its second terminal serving as the drive output terminal. The third capacitor has its first end connected to the drive control node and its second end connected to the drive output terminal.

7. The gate driving circuit according to claim 4 or 5, characterized in that, The gate driving module further includes: a pull-down unit; the pull-down unit includes: The seventh transistor has its control terminal connected to the stage output terminal of the (n+i)th stage gate drive module, its first terminal connected to the drive output terminal, and its second terminal connected to the low-level terminal. The eighth transistor has its control terminal connected to the control terminal of the seventh transistor, its first terminal connected to the drive control node, and its second terminal connected to the low-level terminal. The ninth transistor has its control terminal connected to the control terminal of the seventh transistor, its first terminal connected to the intermediate control node, and its second terminal connected to the low-level terminal.

8. A local brush control method, characterized in that, The partial brush control method, applied to the gate drive circuit according to any one of claims 1-7, comprises: In global refresh mode and local refresh mode, the current level's transmission signal is generated in response to the transmission signal of the previous level and the transmission clock signal of the current level. Based on the current stage's transmission signal, establish a drive control voltage on the drive control node; In partial refresh mode, the drive clock signal line of the current stage is controlled to output an effective level during the corresponding time period of the refresh line, so that the refresh line outputs the gate drive signal of the current stage under the combined action of the drive control voltage and the drive clock signal.

9. The local brush control method according to claim 8, characterized in that, The local refresh control method also includes: In partial refresh mode, the drive clock signal line of the current stage is controlled to output an invalid level during the corresponding period of the non-refresh line, so that no gate drive signal is output for the non-refresh line.

10. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-7, wherein the driving output terminal of the gate driving circuit is electrically connected to at least one scan line.

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