Multi-valued storage oriented 2T0C DRAM (Dynamic Random Access Memory) read-write method and system

Abstract

The invention discloses a multi-valued storage oriented 2T0C DRAM (Dynamic Random Access Memory) read-write method and system, and relates to the technical field of multi-valued storage, and the method comprises the following steps: adopting a multi-valued current source, and transmitting preset write-in current matched with to-be-written-in data to all target storage units needing to write in the same to-be-written-in data in a 2T0C DRAM storage array; the write-in transistor and the read transistor in the target storage unit share the same bit line; all the target storage units generate respective storage node voltages in a self-adaptive manner by combining the threshold voltages of respective reading transistors on the basis of the preset write-in current, so that the overdrive voltages of the target storage units are the same; the overdrive voltage uniquely corresponds to the to-be-written data; when the data are read, the read current on the bit line is detected to obtain the storage data; the read current is uniquely determined by the overdrive voltage. The method is used for solving the influence of threshold voltage fluctuation on multi-value storage accuracy in the prior art.

Description

Technical Field

[0001] This invention relates to the field of multi-value storage technology, and in particular to a 2T0C DRAM read / write method and system for multi-value storage. Background Technology

[0002] In the field of semiconductor storage technology, Dynamic Random Access Memory (DRAM) has become an indispensable core storage component in various electronic devices due to its high read / write speed and good compatibility. Among them, DRAM with a 2T0C structure is gradually attracting attention in multi-value storage scenarios due to its potential advantages in area utilization and integration density. Multi-value storage technology allows a single storage cell to carry more than 1 bit of data. Compared with traditional binary storage, it can significantly increase storage density with the same number of storage cells, meeting the urgent need for large-capacity storage in current electronic devices.

[0003] However, traditional 2TOC DRAM, which uses voltage-based writing, faces significant challenges in practical applications. Due to non-ideal factors during device fabrication, such as uneven thin-film growth of channels or gate dielectrics and limited etching precision, the threshold voltage of different DRAM memory cells inevitably fluctuates. In traditional voltage-based writing mechanisms, the memory node voltage is boosted to the same level as the bit line voltage during writing, while the read operation relies on the current magnitude of the read bit line to determine the voltage state of the memory node and thus the stored data. However, fluctuations in the threshold voltage significantly affect the read current value, causing interference between multiple voltage levels of different memory cells. This makes it impossible to accurately distinguish the specific memory state, severely limiting the feasibility of 2TOC DRAM in multi-value storage applications. Summary of the Invention

[0004] The purpose of this invention is to provide a 2T0C DRAM read / write method and system for multi-value storage, which addresses the impact of threshold voltage fluctuations on the accuracy of multi-value storage in traditional technologies.

[0005] To achieve the above objectives, the present invention provides the following technical solution: In a first aspect, the present invention provides a 2TOC DRAM read / write method for multi-value storage, characterized in that it includes: A multi-value current source is used to deliver a preset write current that matches the data to be written to all target memory cells in the 2T0C DRAM memory array that need to be written with the same data; the write transistors and read transistors in the target memory cells share the same bit line; All target memory cells adaptively generate their own memory node voltages based on a preset write current and the threshold voltage of their respective read transistors, so that the overdrive voltage of each target memory cell is the same; the overdrive voltage corresponds uniquely to the data to be written. When reading data, the read current on the bit line is detected to obtain the stored data; the read current is uniquely determined by the overdrive voltage.

[0006] Optionally, a constraint relationship is established between the preset write current and the overdrive voltage; the overdrive voltage is the difference between the storage node voltage and the threshold voltage. All target memory cells adaptively generate their respective memory node voltages based on a preset write current and the threshold voltage of their respective read transistors, ensuring that the overdrive voltage of each target memory cell is the same, including: Based on the constraint relationship, target memory cells with different threshold voltages among all target memory cells adaptively adjust their own memory node voltages through the memory node to make the overdrive voltage of all target memory cells the same.

[0007] Optionally, the constraint relationship is the transistor current formula: ; in, ; This refers to the storage node voltage; This is the gate-source voltage written to the transistor; Preset write current; Carrier mobility; The capacitance of the gate oxide layer per unit area; The width-to-length ratio of the channel; The width of the channel; This refers to the length of the channel; This is to read the threshold voltage of the transistor.

[0008] Optionally, the drain of the write transistor and the drain of the read transistor are connected to the same bit line, and the bit line is directly connected to a multi-value current source; the gate of the write transistor is connected to the write word line. The source of the write transistor is connected to the memory node; the gate of the read transistor is connected to the memory node; the source of the read transistor is connected to the read word line and the read word line is always grounded. A multi-value current source is used to deliver a preset write current, matching the data to be written, to all target memory cells in the 2T0C DRAM memory array that require the same data to be written. This includes: Apply a preset high level to the write word line to turn on the write transistor; A preset write current is transmitted via a bit line using a multi-value current source. The preset write current flows into the drain of the write transistor and out of the source of the write transistor, and then flows to the storage node of the target storage cell. When the storage node is fully charged, the current path of the write transistor is turned off, so that the drain current of the read transistor is equal to the preset write current.

[0009] Optionally, before detecting the read current on the bit line to obtain the stored data, the method further includes: After the data is written, the write word line is set to a preset low level, which turns off the write transistor and converts the current signal of the connected bit line into a voltage signal.

[0010] Optionally, the multi-value current source includes Each branch has an independent current branch, and each branch outputs a discrete current value within a preset range. Each discrete current value corresponds to a multi-value storage state. The corresponding current branch is selected to input a matching current to the corresponding target storage unit. The number of bits for storing multiple values. Greater than or equal to 1.

[0011] Optionally, the preset range of discrete current values ​​output by the multi-value current source is 100pA-3μA.

[0012] Optionally, the multi-value current source is simulated by a semiconductor parameter tester and a probe station. After being generated by a semiconductor parameter tester, the write current signal is applied to the corresponding bit line via a probe station; The read current signal on the bit line is transmitted to the semiconductor parameter tester via the probe station. The tester detects the read current signal and obtains the stored data of the target memory cell by combining it with the preset current data mapping relationship.

[0013] Compared with existing technologies, the 2TOC DRAM read / write method for multi-value storage provided by this invention delivers a preset write current matching the data to be written to the target memory cell using a multi-value current source. Combined with the target memory cell adaptively generating a memory node voltage based on the preset write current and the threshold voltage of its respective read transistor, the overdrive voltage of each target memory cell is the same and uniquely corresponds to the data to be written. During reading, the bit line read current uniquely determined by the overdrive voltage is detected to obtain the stored data, thereby eliminating the impact of threshold voltage fluctuations on the accuracy of multi-value storage in traditional technologies and improving the accuracy and reliability of multi-value storage.

[0014] Secondly, the present invention also provides a 2T0C DRAM read / write system for multi-value storage, comprising: a multi-value current source, a 2T0C DRAM storage array, and a read detection module; The 2T0C DRAM memory array comprises multiple memory cells arranged in an array. Each memory cell includes a write transistor and a read transistor, which share the same bit line; Each bit line is connected to a multi-value current source and a readout detection module, respectively; The multi-value current source is used to deliver a preset write current that matches the data to be written to all target memory cells in the 2T0C DRAM memory array that need to be written with the same data. Each target memory cell is used to adaptively generate a memory node voltage based on a preset write current and the threshold voltage of its own read transistor, so that the overdrive voltage of each target memory cell is consistent and the overdrive voltage uniquely corresponds to the data to be written. The read detection module is used to detect the read current on the bit line to obtain the stored data when reading data; the read current is uniquely determined by the overdrive voltage. Attached Figure Description

[0015] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, are illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention.

[0016] In the attached diagram: Figure 1 A flowchart illustrating a 2TOC DRAM read / write method for multi-value storage provided in an embodiment of the present invention; Figure 2 A schematic diagram of the circuit structure of a 2T0C DRAM memory cell provided for one embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of a traditional 2T0C DRAM memory cell in the prior art; Figure 4 A schematic diagram of the state of the 2T0C DRAM memory cell write and read processes provided for a specific embodiment 1 of the present invention; Figure 5 A write / read timing diagram of a 2T0C DRAM memory array provided for specific embodiment 2 of the present invention; Figure 6 The bit line current distribution diagram of the read current of the 2T0C DRAM memory array provided in specific embodiment 2 of the present invention; Figure 7 To and Figure 6 The probability distribution diagram of the corresponding reading current; Figure 8 This is a schematic diagram of a 2T0C DRAM read / write system for multi-value storage provided in an embodiment of the present invention.

[0017] Reference numerals: 810 - Multi-value current source; 820 - 2T0C DRAM memory array; 830 - Read detection module. Detailed Implementation

[0018] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0019] It should be noted that in this invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions.

[0020] Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0021] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0022] like Figure 1 As shown, this embodiment of the invention provides a 2TOC DRAM read / write method for multi-value storage, which may include: Step 100: Using a multi-value current source, a preset write current matching the data to be written is delivered to all target memory cells in the 2T0C DRAM memory array that need to be written with the same data; the write transistor and read transistor in the target memory cell share the same bit line; the target memory cell groups corresponding to different data to be written together cover all memory cells in the array that need to be written with data.

[0023] Specifically, multi-value storage is a technology that allows a single storage unit to store more information. Unlike traditional binary storage, which can only store 0s or 1s, it enables a single unit to carry more than one bit of data. Using this technology, the same number of storage units can hold far more data than traditional storage, thus significantly increasing storage density. This storage technology relies on a special writing method, typically employing a multi-value current source that can output multiple different fixed current values, each corresponding to a different data state.

[0024] It's important to note that although multi-value current sources can output various different currents, the memory array cannot write all the current to all cells at once. This is because each cell in the memory array needs to be precisely located before operation; this location process is called "selection." "Selection" doesn't mean that some cells need to store data while others don't; rather, all cells will eventually store data, but a single write operation targets only one cell. To store the corresponding data, a fixed current corresponding to that data must be input to the target memory cell to ensure that the data stored in each cell is accurate. Without this "selection" operation, all current would flow into all cells simultaneously, resulting in all cells storing the same data, and the advantages of multi-value storage would not be realized.

[0025] A multi-value current source can be simulated by a semiconductor parameter tester (such as the HPB1500 tester) and a probe station. The specific workflow is as follows: the write current signal is generated by the semiconductor parameter tester and applied to the corresponding bit line via the probe station; during subsequent reading, the read current signal on the bit line is transmitted to the semiconductor parameter tester via the probe station. The tester detects this read current signal and, combined with a preset current-data mapping relationship (i.e., a preset "current-data" mapping relationship), obtains the stored data of the target memory cell, achieving precise transmission and detection of data writing and reading.

[0026] Multi-value current sources include Each independent current branch ( The number of bits for storing multiple values. (Greater than or equal to 1), each branch outputs discrete current values ​​within a preset range, and each discrete current value uniquely corresponds to a multi-value storage state. In practical applications, the corresponding current branch can be selected according to the number of bits to be stored, and the matching current can be input to the corresponding target storage unit. The preset range of the discrete current values ​​output by the multi-value current source is 100 picoamperes (pA) - 3 microamperes (μA). For example, when... At this time, the current source can output 16 different fixed current levels: 100pA corresponds to 0000, 200pA corresponds to 0001, 300pA corresponds to 0010, and so on. 3μA corresponds to 1111. These 16 levels just cover all possible states of 4-bit data, perfectly adapting to the needs of multi-value storage.

[0027] The 2T0C DRAM in this embodiment of the invention is a "two-transistor zero-capacitor DRAM". A 2T0C DRAM memory cell consists of a write transistor and a read transistor. Compared to traditional memory structures such as 2T1C, it has significant advantages in area utilization and integration density. For the specific connection relationship of the 2T0C DRAM memory cell, please refer to [link / reference]. Figure 2The drains of the write transistor and the read transistor are connected to the same bit line, which is directly connected to the aforementioned multi-value current source. The gate of the write transistor is connected to the write word line; the source of the write transistor is connected to the memory node SN; the gate of the read transistor is connected to the memory node SN; the source of the read transistor is connected to the read word line, which is always grounded. The write word line is used to control the on / off state of the write transistor, enabling the selection of the target memory cell, and does not handle data transmission. The read word line is a fixed ground terminal and does not participate in cell selection control. The bit line is used to transmit write current signals and read current signals, handling data transmission but not cell selection.

[0028] Figure 2 This common-line connection design not only simplifies the structure but also provides a stable physical path for the transmission of write current.

[0029] Step 200: All target memory cells adaptively generate their own memory node voltages based on the preset write current and the threshold voltage of their respective read transistors, so that the overdrive voltage of each target memory cell is the same; the overdrive voltage corresponds uniquely to the data to be written. It should be noted that the preset write current and overdrive voltage form a constraint relationship, and the overdrive voltage is the difference between the storage node voltage and the threshold voltage. Step 200 may specifically include: based on the constraint relationship, the target memory cells with different threshold voltages among all target memory cells adaptively adjust their own memory node voltages through the memory node, so that the overdrive voltage of all target memory cells is the same.

[0030] For example, the constraint relationship is the transistor current formula: ; in, This is an overdrive voltage; ; This refers to the storage node voltage; This is the gate-source voltage written to the transistor; Preset write current; Carrier mobility; The capacitance of the gate oxide layer per unit area; The width-to-length ratio of the channel; The width of the channel; This refers to the length of the channel; This is to read the threshold voltage of the transistor. The reason is... This is because the source of the write transistor is connected to the storage node SN; therefore, the gate-source voltage of the write transistor... Equivalent to storage node voltage . Indicates bit line.

[0031] Understandably, due to non-ideal factors such as uneven thickness of the channel or gate dielectric film during device fabrication and limited etching precision, the threshold voltage of the read transistor in different memory cells varies. There will inevitably be differences. And according to the above formula (1), we know that... With overdrive voltage A fixed constraint relationship is formed when the preset write current is reached. When the current is fixed, in order to meet the constraint of fixed current, each target memory cell will adaptively adjust its own current through the memory node. : Higher target storage units will automatically increase in height. , Lower units will automatically decrease This ensures that the overdrive voltage of all target storage cells writing the same data remains consistent, and that the overdrive voltage uniquely corresponds to the data to be written, thus fundamentally solving the problem of threshold voltage fluctuations interfering with multi-value storage in traditional voltage writing methods.

[0032] Step 300: When reading data, detect the read current on the bit line to obtain the stored data; the read current is uniquely determined by the overdrive voltage.

[0033] In a specific embodiment, before detecting the read current on the bit line to obtain the stored data, the method further includes: after the data is written, setting the write word line to a preset low level (e.g., -1V) to turn off the write transistor and convert the current signal connected to the bit line into a voltage signal.

[0034] Combination Figure 4 It should be emphasized that Formula (1) is not only the basis for the constraint of "preset write current and overdrive voltage" in the write stage, but also the basis for the corresponding "read current and overdrive voltage" in the read stage. The reason is that in the write and read stages, the read transistor always works in the same "saturation region", and the core control variable overdrive voltage has been locked in the write stage.

[0035] During the write phase, the read transistor is a current-constrained device. The preset write current is output by the multi-value current source. This will force the drain-source current of the transistor to be drawn. equal According to formula (1), in order to satisfy... Due to constraints, the read crystal will adaptively adjust its storage node voltage via the storage node SN. , Higher units automatically rise , Lower units automatically decrease Finally, a match was identified. The only corresponding fixed overdrive voltage And the overdrive voltage and Fluctuations are irrelevant.

[0036] During the read phase, the read transistor is a device that outputs current. After data writing is complete, the write transistor is turned off (cutting off the write path), but the read transistor continues to operate. Fixed during the write phase ( + Fixed overdrive voltage); At this time, a preset constant voltage (e.g., 2V) is applied to the bit line. Its function is to ensure that the read transistor is still in the saturation region. It can be understood that the read current is the same as the preset write current during data writing. Not entirely identical, because the drain voltage of the read transistor differs between the write and read phases. During the write phase, the bit line operates in current-source mode, while the drain voltage of the read transistor varies with... The transmission dynamics (determined by the characteristics of the current source); during the read phase, the bit line switches to a constant voltage mode, and the drain voltage is fixed at a preset constant voltage value (e.g., 2V). Although the drain voltage differs, the drain-source current remains constant because the read transistor always operates in the saturation region. It still follows formula (1) and is determined only by a fixed overdrive voltage, therefore the read current will exhibit the same characteristics as... The associated fixed distribution characteristic is confined to a fixed range that uniquely corresponds to the overdrive voltage, with extremely small dispersion. This not only does not affect the distinction between multiple storage states, but also completely avoids the threshold voltage. Disturbances caused by fluctuations.

[0037] In specific implementation method 1, see Figure 4 The current flow direction and bit line mode switching of the write and read processes of the 2T0C DRAM memory cell of the present invention are as follows.

[0038] 1. The bit line is in current source mode, such as Figure 4 In the left figure, a 2V high level is applied to the write word line, the write word line is in the open state, the write transistor is turned on, and the preset write current output by the multi-value current source flows along the path of "bit line → write transistor drain → write transistor source → memory node → read transistor gate → read transistor drain → read transistor source → read word line", which eventually makes the drain-source current of the read transistor equal to the preset write current, thus completing the adaptive generation of the memory node voltage.

[0039] 2. Bit line switching to voltage source mode. Applying a -1V low level to the write word line switches the write word line to the off state, the write transistor is turned off, and after applying a constant voltage to the bit line, the bit line switches from current source mode to voltage source mode: the gate voltage of the read transistor, that is, the storage node voltage, has been fixed in the write stage. At this time, the current flows along the path of "bit line → read transistor drain → read transistor source → read word line", and this current is the read current. Its magnitude is uniquely determined by the overdrive voltage locked in the write stage.

[0040] The bit line is a current source during the write phase to accurately input the preset write current to the memory cell and lock the overdrive voltage. During the read phase, it is switched to a voltage source to provide a stable operating bias for the read transistor, ensuring that it is in the saturation region, while avoiding interference from the current source mode on the read current detection and ensuring the stability of the read signal.

[0041] The beneficial effects of this embodiment: The 2TOC DRAM read / write method for multi-value storage provided by this embodiment solves the problem of threshold voltage fluctuations affecting the accuracy of multi-value storage in traditional technologies by using a scheme design of current writing, adaptive voltage adjustment, and overdrive voltage locking. It also considers storage density, structural simplification, and process compatibility. Specifically, 1) it breaks through the core constraint of threshold voltage fluctuations, significantly improving the accuracy of multi-value storage. Traditional 2TOC DRAM uses a voltage writing method, where the storage node voltage is forced to be consistent with the bit line voltage, and the read current is directly affected by the threshold voltage. Due to non-ideal factors such as uneven growth of the channel and gate dielectric films and limited etching precision during device fabrication, the threshold voltage of different cells inevitably fluctuates, resulting in large discreteness of the read current, mutual interference between multi-value levels, and an inability to accurately distinguish the storage state. This embodiment overcomes this challenge through three key design features: First, it replaces the traditional voltage source with a multi-value current source for writing, using a preset write current as the data carrier and establishing a fixed constraint relationship between the preset write current and the overdrive voltage through a transistor current formula. Second, it utilizes the adaptive voltage adjustment mechanism of the storage nodes. When different target storage cells differ, cells with higher threshold voltages automatically increase their storage node voltage, while cells with lower threshold voltages automatically decrease their storage node voltage, ensuring that the overdrive voltage of all target cells writing the same data is completely consistent. Finally, the read current during the read phase is uniquely determined by the overdrive voltage and is independent of fluctuations in the threshold voltage, completely eliminating the read current dispersion problem caused by non-ideal factors. Test results show that 16 different write current levels achieve stable 4-bit storage across 25 storage cells, verifying the significant advantage of this method in multi-value storage accuracy.

[0042] 2) Enhance the stability and reliability of multi-value storage and expand the upper limit of the number of storage bits. In this embodiment, the multi-value current source is through... Each independent current branch outputs a discrete current ranging from 100pA to 3μA, with each current value corresponding one-to-one with a multi-value storage state (e.g., 16 current levels covering all 4-bit states), achieving precise mapping of storage states. Simultaneously, an adaptive voltage adjustment mechanism ensures that the overdrive voltage corresponding to the same data remains constant regardless of fluctuations in the threshold voltage of the storage cell, significantly improving the consistency of read current and avoiding storage state confusion caused by threshold voltage differences in traditional technologies. This design not only guarantees the stable implementation of existing multi-value storage (e.g., 4-bit) but also provides a feasible path for higher bit-count multi-value storage (e.g., 8-bit), significantly expanding the application boundaries of 2T0C DRAM in the field of multi-value storage.

[0043] 3) Simplify structural design while balancing area optimization and process compatibility. (Through comparison...) Figure 2 The structure of this invention and Figure 3 In traditional 2TOC structures, both types of 2TOC memory cells contain three core components: a write transistor, a read transistor, and a memory node. However, there is a key difference in the connection method of the signal lines: In the traditional 2TOC structure, the drains of the write transistor and the read transistor are each connected to independent lines, meaning the write transistor corresponds to one line and the read transistor to another, requiring two separate control lines to transmit signals to the write and read transistors respectively. In the structure of this invention, the drains of the write transistor and the read transistor are connected to the same bit line, allowing signal transmission to both transistors simultaneously through a single bit line. In the traditional 2TOC structure, the drains of the write transistor and the read transistor need to be connected to separate bit line-type control lines, namely the write bit line and the read bit line, which need to be laid out and transmit signals independently. This invention, by connecting the drains of both transistors to the same bit line, effectively reduces one "independent bit line-type control line." In principle, in traditional structures, write operations require transmitting signals to the write transistor via the write bit line, and read operations require obtaining signals from the read transistor via the read bit line. Both bit lines must exist simultaneously to distinguish the write / read paths, thus requiring additional chip wiring area. Furthermore, when the two lines are placed adjacently, crosstalk can easily occur due to signal coupling. This invention, through a "common bit line" design, concentrates both the input of the write current and the output of the read current on the same bit line: during the write phase, a multi-value current source delivers current to the write transistor through this bit line; during the read phase, this bit line also serves as the transmission channel for the read current. The write / read paths can be distinguished simply by switching the level of the write word line (high level during write to turn on the write transistor, low level during read to turn off the write transistor), eliminating the need for additional independent bit lines.

[0044] This design eliminates the wiring space of a bit-line control line, reducing chip area occupancy, and avoids the risk of crosstalk between two bit lines. At the same time, it does not change the core manufacturing process of transistors and is fully compatible with the process of traditional 2T0C DRAM, achieving triple optimization of structural simplification, performance improvement and cost control.

[0045] 4) Improved accuracy and scalability of data reading and writing. The multi-value current source is simulated using a semiconductor parameter tester and probe station. The generation, transmission, and detection of the write current signal and read current are all highly accurate. Combined with a preset fixed mapping relationship between "current and data," precise matching between data writing and reading is ensured. Furthermore, the current range and number of current branches of the multi-value current source can be flexibly adjusted according to the storage bit count requirements (n can be set as needed), adapting to multi-value storage needs in different scenarios and possessing excellent scalability.

[0046] In summary, this embodiment, through its innovative read / write mechanism design, completely solves the core problem of threshold voltage fluctuations affecting the accuracy of multi-value storage in traditional technologies. While improving storage accuracy and stability, it achieves multiple optimizations in storage density, structural simplification, and process compatibility, providing key technical support for the large-scale application of 2T0C DRAM in the field of multi-value storage.

[0047] Specifically, a multi-value current source is used to deliver a preset write current matching the data to be written to all target memory cells in the 2T0C DRAM memory array that need to be written with the same data, including: Apply a preset high level (e.g., 2V) to the write word line to turn on the write transistor; A preset write current is transmitted via a bit line using a multi-value current source. The preset write current flows into the drain of the write transistor and out of the source of the write transistor, and then flows to the storage node of the target storage cell. When the storage node is fully charged, the current path of the write transistor is turned off, so that the drain current of the read transistor is equal to the preset write current.

[0048] In specific implementation 2, the 2TOC DRAM read / write method of the present invention for multi-value storage aims at 4-bit multi-value storage, combined with Figure 4 The write and read states of the 2T0C DRAM memory cell are accurately stored and retrieved using a multi-value current source to achieve 16 data states. The multi-value current source is simulated using an HPB1500 semiconductor parameter tester and probe station, capable of outputting discrete current values ​​ranging from 10pA to 3μA. Each current value uniquely maps to a 4-bit data state. See [link / reference]. Figure 5The preset "current-data" mapping relationship, in ascending order of current, is as follows: 10pA corresponds to 0000, 100pA to 0001, 500pA to 0010, 1nA to 0011, 4nA to 0100, 10nA to 0101, 25nA to 0110, 50nA to 0111, 85nA to 1000, 140nA to 1001, 200nA to 1010, 300nA to 1011, 600nA to 1100, 1μA to 1101, 1.7μA to 1110, and 3μA to 1111. In short, 16 current levels completely cover all 4-bit combinations. The write word line high level is set to 2V, and the low level is set to -1V; transistor carrier mobility... Gate oxide capacitance per unit area The width-to-length ratio of the channel .

[0049] The write process is executed; for example, 16 current levels can be written sequentially from smallest to largest, corresponding to 16 data states. The storage array contains 25 storage cells, numbered U1-U25. Sixteen independent tests are conducted for the 16 discrete current values ​​(corresponding to 16 4-bit data states). In each test, the same current level corresponding to the same data is written to all 25 storage cells. After each cell is written, the current is read and recorded. Multiple rounds of testing verify the consistency and accuracy of cell read / write operations under different data states. The specific test steps are as follows: First round of testing (data 0000, corresponding current 10pA).

[0050] Step (1) Select memory cell U1: Apply a 2V high level to the write word line corresponding to U1 through the address decoder to turn on the write transistor of U1; keep the write word lines of the other memory cells (U2-U25) at a low level of -1V, and turn off the write transistor to ensure that only U1 is in a writable state.

[0051] Step (2) Execute the write operation: Control the multi-value current source to turn on the current branch corresponding to 10pA, and output a preset write current of 10pA. This current is generated by the HPB1500 tester and transmitted to the bit line through the probe station. It flows into the storage node through the drain of the write transistor of U1 and out through the source, ultimately making the drain current of the read transistor of U1 equal to 10pA. Based on the transistor current formula, U1 adaptively generates the storage node voltage by combining the threshold voltage of its own read transistor, and locks the overdrive voltage uniquely corresponding to the data 0000.

[0052] Step (3) Perform the read operation: After the write operation is completed, set the write word line of U1 to -1V low level to turn off the write transistor; switch the bit line to constant voltage mode (set to 2V), and detect and record the read current on the bit line through the probe station. The actual measured read current is 40pA (falling within the preset range of 20pA-60pA, corresponding to...) Figure 6 The lowest current band fluctuation range).

[0053] Repeat steps (1)-(3) to select memory cells U2-U25 in sequence. The read current of U2 is 38pA; the read current of U3 is 45pA; ...; the read current of U25 is 52pA. The read current of all memory cells is stable in the range of 20pA-60pA, and the first round of testing is completed.

[0054] Next, the second round of testing will be conducted (data 0001, corresponding to a current of 100pA).

[0055] Step (1) Select memory cell U1: Apply a 2V high level to the write word line of U1 to turn on the write transistor; the write word lines of the other memory cells remain in a -1V off state.

[0056] (2) Perform write operation: control the multi-value current source to output 100pA preset write current, which is transmitted to U1 via the bit line to complete the adaptive generation of storage node voltage and overdrive voltage lockout.

[0057] (3) Perform read operation: Turn off the write transistor of U1, apply a constant voltage of 2V to the bit line, detect and record the read current of U1. The actual measured read current is 550pA (falls within the preset range of 300pA-800pA, corresponding to the second current band fluctuation range from bottom to top in Figure 6).

[0058] Repeat steps (1)-(3) to sequentially record the 100pA write and read current of the 25 memory cells U2-U25: U2 read current is 480pA; U3 read current is 620pA; ...; U25 read current is 750pA. All read currents are stable within the range of 300pA-800pA, and the second round of testing is complete.

[0059] It should be noted that in the multi-value storage scenario test of this type of 2T0C DRAM of the present invention, due to the influence of bit line mode switching (current source mode in the write stage → voltage source mode in the read stage), transistor drain voltage changes, and non-ideal process factors (such as channel width-to-length ratio and slight deviation in carrier mobility), the read current and write current are not exactly the same, and a certain offset will occur. This phenomenon is consistent with the process fluctuation law of semiconductor memory devices, and the offset is small and will not affect the accurate distinction of multi-value storage state.

[0060] The third through sixteenth rounds of testing are the same as above. Further details will not be provided here.

[0061] The data from all read currents of 25 memory cells across 16 rounds of testing were summarized to form the following: Figure 6 The bit line current distribution diagram shown is consistent with Figure 7 The probability distribution diagram shown shows that, through data analysis, the following can be observed: 1) Under the same data state, the read current distribution of the 25 storage cells is compact and has low dispersion; 2) The read current intervals corresponding to different data states do not overlap (for example, the read interval corresponding to 10pA does not overlap with the read interval corresponding to 100pA), ensuring that the multi-value storage states can be accurately distinguished, thus verifying the reliability and accuracy of the read / write method of this embodiment of the invention.

[0062] like Figure 8 As shown, this embodiment of the invention also provides a 2T0C DRAM read / write system for multi-value storage, which may include: a multi-value current source 810, a 2T0C DRAM storage array 820, and a read detection module 830; The 2T0C DRAM memory array 820 includes multiple memory cells arranged in an array; Each memory cell includes a write transistor and a read transistor, which share the same bit line; Each bit line is connected to a multi-value current source and a readout detection module, respectively; The multi-value current source 810 is used to deliver a preset write current that matches the data to be written to all target memory cells in the 2T0C DRAM memory array that need to be written with the same data. Each target memory cell is used to adaptively generate a memory node voltage based on a preset write current and the threshold voltage of its own read transistor, so that the overdrive voltage of each target memory cell is consistent and the overdrive voltage uniquely corresponds to the data to be written. The read detection module is used to detect the read current on the bit line to obtain the stored data when reading data; the read current is uniquely determined by the overdrive voltage.

[0063] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. Although the invention has been described in conjunction with specific features and embodiments, it is apparent that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and the accompanying drawings are merely exemplary descriptions of the invention as defined by the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Obviously, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A 2TOC DRAM read / write method for multi-value storage, characterized in that, include: A multi-value current source is used to deliver a preset write current that matches the data to be written to all target memory cells in the 2T0C DRAM memory array that need to be written with the same data. The write transistor and read transistor in the target memory cell share the same bit line; Based on the preset write current, each target memory cell adaptively generates its own memory node voltage by combining the threshold voltage of its respective read transistor, so that the overdrive voltage of each target memory cell is the same; the overdrive voltage uniquely corresponds to the data to be written. When reading data, the read current on the bit line is detected to obtain the stored data; the read current is uniquely determined by the overdrive voltage.

2. The 2TOC DRAM read / write method for multi-value storage according to claim 1, characterized in that, The preset write current and the overdrive voltage form a constraint relationship; the overdrive voltage is the difference between the storage node voltage and the threshold voltage; All target memory cells adaptively generate their respective memory node voltages based on the preset write current and the threshold voltage of their respective read transistors, so that the overdrive voltage of each target memory cell is the same, including: Based on the aforementioned constraints, target memory cells with different threshold voltages among all target memory cells adaptively adjust their own memory node voltages through the memory node, so that the overdrive voltages of all target memory cells are the same.

3. The 2TOC DRAM read / write method for multi-value storage according to claim 2, characterized in that, The constraint relationship is the transistor current formula: in, ; The voltage of the storage node; This is the gate-source voltage written to the transistor; The preset write current; Carrier mobility; The capacitance of the gate oxide layer per unit area; The width-to-length ratio of the channel; The width of the channel; This refers to the length of the channel; This is to read the threshold voltage of the transistor.

4. The 2TOC DRAM read / write method for multi-value storage according to claim 2, characterized in that, The drain of the write transistor and the drain of the read transistor are both connected to the bit line, and the bit line is directly connected to the multi-value current source; the gate of the write transistor is connected to the write word line. The source of the write transistor is connected to the memory node; the gate of the read transistor is connected to the memory node; the source of the read transistor is connected to the read word line and the read word line is always grounded; Using a multi-value current source, a preset write current matching the data to be written is delivered to all target memory cells in the 2T0C DRAM memory array that require the same data to be written, including: A preset high level is applied to the write word line to turn on the write transistor; The preset write current is transmitted through the bit line using the multi-value current source. The preset write current flows into the drain of the write transistor and out of the source of the write transistor, and then flows to the storage node of the target storage cell. When the storage node is fully charged, the current path of the write transistor is turned off, so that the drain current of the read transistor is equal to the preset write current.

5. The 2TOC DRAM read / write method for multi-value storage according to claim 4, characterized in that, Before detecting the read current on the bit line to obtain the stored data, the method further includes: After the data is written, the write word line is set to a preset low level, which turns off the write transistor and converts the current signal of the connected bit line into a voltage signal.

6. The 2TOC DRAM read / write method for multi-value storage according to claim 1, characterized in that, The multi-value current source includes Each branch outputs a discrete current value within a preset range, and each discrete current value corresponds to a multi-value storage state. The corresponding current branch is selected to input a matching current to the corresponding target storage unit. The number of bits for storing multiple values. Greater than or equal to 1.

7. The 2TOC DRAM read / write method for multi-value storage according to claim 6, characterized in that, The preset range of the discrete current values ​​output by the multi-value current source is 100pA-3μA.

8. The 2TOC DRAM read / write method for multi-value storage according to claim 1, characterized in that, The multi-value current source is simulated by a semiconductor parameter tester and a probe station. After being generated by the semiconductor parameter tester, the write current signal is applied to the corresponding bit line via the probe station; The read current signal on the bit line is transmitted to the semiconductor parameter tester via the probe station. The tester detects the read current signal and obtains the storage data of the target memory cell by combining it with a preset current data mapping relationship.

9. A 2T0C DRAM read / write system for multi-value storage, characterized in that, include: Multi-value current source, 2T0C DRAM memory array and read detection module; The 2T0C DRAM memory array includes multiple memory cells arranged in an array; Each of the memory cells includes a write transistor and a read transistor, the write transistor and the read transistor sharing the same bit line; Each bit line is connected to the multi-value current source and the readout detection module, respectively; The multi-value current source is used to deliver a preset write current that matches the data to be written to all target memory cells in the 2T0C DRAM memory array that need to be written with the same data. Each target memory cell is used to adaptively generate a memory node voltage based on the preset write current and the threshold voltage of its own read transistor, so that the overdrive voltage of each target memory cell remains consistent, and the overdrive voltage uniquely corresponds to the data to be written. The read detection module is used to detect the read current on the bit line to obtain the stored data when reading data; the read current is uniquely determined by the overdrive voltage.

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