Structure of passive waveguide butt joint laser and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor luminescent devices, and provides a passive waveguide butt joint laser structure and a manufacturing method thereof. The structure comprises a substrate, an epitaxial structure and a butt joint structure, the butt-joint structure comprises a first butt-joint part and a second butt-joint part, and the first butt-joint part is obtained by growing a plurality of functional layers in a butt-joint channel after the epitaxial structure is etched to obtain the butt-joint channel and a butt-joint step; the second butt joint part is obtained by growing a plurality of functional layers on the surface of the butt joint step and the surface of the first butt joint part; one or more functional layers in the first docking part are designed as current blocking structures; and the current blocking structure is a reverse PN junction or a semi-insulating doped growth structure containing Fe-InP. According to the invention, the current blocking structure is arranged in the butt joint structure, so that the loss caused by current leakage in the passive waveguide region can be reduced, the performance of the laser is improved, the current threshold is reduced, the reliability is improved, and the frequency response performance is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor light-emitting device technology, and in particular to the structure and fabrication method of a passive waveguide-connected laser. Background Technology

[0002] With the development of communication technology, people have put forward higher demands for communication speed. High-speed devices are the key to improving communication speed. Among them, high-reliability, high-speed, and low-cost semiconductor lasers are the prerequisite for the development of high-speed devices and high-speed integrated devices. Distributed-feedback lasers (DFB lasers) have the characteristics of single longitudinal mode and long transmission distance, making them suitable for the requirements of high-speed devices in 5G technology and data center applications. To improve the performance of high-speed DFB lasers, methods such as quantum well hybridization, selective area growth (SAG), butt-joint growth, and spot size converters (SSC) have been developed. However, in the fabrication of passive waveguide-joint lasers, we have found that while depositing a SiO2 insulating layer on the passive waveguide limits current propagation in the waveguide region, the P-cladding layer below the insulating layer provides a leakage path for the current. Furthermore, the background concentration gradually increases with the epitaxial growth cycle, leading to current diffusion and losses in the passive waveguide region. Therefore, existing fabrication processes have not achieved the desired results.

[0003] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0004] The technical problem to be solved by this invention is that the structure of existing passive waveguide-connected lasers is prone to current diffusion in the passive waveguide region, resulting in significant losses.

[0005] The present invention adopts the following technical solution:

[0006] In a first aspect, the present invention provides a structure for a passive waveguide docking laser, comprising a substrate 1, an epitaxial structure 2, and a docking structure 3;

[0007] The epitaxial structure 2 is obtained by growing multiple functional layers on the substrate 1;

[0008] The docking structure 3 includes a first docking portion 31 and a second docking portion 32. The first docking portion 31 is obtained by etching the epitaxial structure 2 to obtain a docking channel 21 and a docking step 22, and then growing multiple functional layers in the docking channel 21.

[0009] The second docking portion 32 is obtained by growing multiple functional layers on the surface of the docking step 22 and the surface of the first docking portion 31;

[0010] One or more functional layers in the first docking portion 31 are designed as current blocking structures; wherein the current blocking structure is a reverse PN junction or a semi-insulating doped growth structure containing Fe-InP.

[0011] Preferably, when the position of the first docking portion 31 near the second docking portion 32 is designed as a current blocking structure of a reverse PN junction, the epitaxial structure 2 includes, in sequence according to the growth direction, a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212;

[0012] The docking channel 21 is etched to the first InP spacer layer 204; the first docking portion 31 includes, in the order of growth direction, a second InP buffer layer 311, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, a second InP capping layer 315, a first P-InP layer 316, and a first N-InP layer 317; wherein, the first P-InP layer 316 and the first N-InP layer 317 constitute the current blocking structure.

[0013] Preferably, when the first docking portion 31 is designed as a current blocking structure of a reverse PN junction near the bottom of the docking channel 21, the epitaxial structure 2 includes, in sequence according to the growth direction, a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212;

[0014] The docking channel 21 is etched to the third anti-corrosion layer 213; the first docking portion 31 includes, in sequence according to the growth direction, a second InP buffer layer 311, a first P-InP layer 316, a first N-InP layer 317, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315; wherein, the first P-InP layer 316 and the first N-InP layer 317 constitute the current blocking structure.

[0015] Preferably, when the first docking portion 31 near the bottom of the docking channel 21 is designed as a current blocking structure containing a semi-insulating doped growth structure of Fe-InP, the epitaxial structure 2 includes, in sequence according to the growth direction, a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212;

[0016] The docking channel 21 is etched to the third anti-corrosion layer 213; the first docking portion 31 includes, in sequence according to the growth direction, a second InP buffer layer 311, a first N-InP layer 317, an Fe-InP layer 318, a second N-InP layer 319, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315; wherein, the first N-InP layer 317, the Fe-InP layer 318, and the second N-InP layer 319 constitute the current blocking structure.

[0017] Preferably, the second docking portion 32 includes, in sequence along the growth direction, a second P-InP layer 321, an InGaAs contact layer 322, and a metal thin film electrode layer 323.

[0018] Preferably, the applicable lasers include one or more of DFB lasers, FP lasers, and VCSEL lasers.

[0019] In a second aspect, the present invention provides a method for fabricating a passive waveguide docking laser structure as described in the first aspect, comprising:

[0020] An epitaxial structure 2 was fabricated on substrate 1;

[0021] A dielectric film is deposited on the epitaxial structure 2, and a preset docking pattern is photolithographically formed on the surface of the dielectric film. According to the preset docking pattern, the position of the preset docking pattern is etched to obtain the docking channel 21. The part outside the preset docking pattern forms the docking step 22.

[0022] Multiple functional layers are grown in the docking channel 21, and one or more of the multiple functional layers are designed as current blocking structures to obtain the first docking portion 31 of the docking structure 3; wherein, the current blocking structure is a reverse PN junction or a semi-insulating doped growth structure containing Fe-InP.

[0023] The dielectric film on the surface of the docking step 22 is removed, and a functional layer is grown on the surface of the first docking portion 31 and the docking step 22 to obtain the second docking portion 32 of the docking structure 3.

[0024] Preferably, when the position of the first docking portion 31 near the second docking portion 32 is designed as a current blocking structure of a reverse PN junction, the fabrication of the epitaxial structure 2 on the substrate 1 specifically includes:

[0025] A first InP buffer layer 201, a grating layer 202, and a grating protection layer 203 are sequentially grown on the surface of substrate 1; a grating is fabricated on the grating layer 202; a first InP spacer layer 204, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212 are sequentially grown on the surface of the grating protection layer 203.

[0026] The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the first InP spacer layer 204;

[0027] The first docking portion 31 of the docking structure 3 is obtained by growing multiple functional layers in the docking channel 21 and designing one or more of the multiple functional layers as current blocking structures, specifically including:

[0028] After etching to obtain the docking channel 21 and docking step 22, the epitaxial wafer is acid-treated and then cleaned and dried.

[0029] In the docking channel 21, a second InP buffer layer 311, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, a second InP capping layer 315, a first P-InP layer 316, and a first N-InP layer 317 are grown sequentially.

[0030] Preferably, when the position of the first docking portion 31 near the bottom of the docking channel 21 is designed as a current blocking structure of a reverse PN junction, the fabrication of the epitaxial structure 2 on the substrate 1 specifically includes:

[0031] A first InP buffer layer 201, a grating layer 202, and a grating protection layer 203 are sequentially grown on the surface of substrate 1; a grating is fabricated on the grating layer 202; a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212 are sequentially grown on the surface of the grating protection layer 203.

[0032] The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the third anti-corrosion layer 213;

[0033] The first docking portion 31 of the docking structure 3 is obtained by growing multiple functional layers in the docking channel 21 and designing one or more of the multiple functional layers as current blocking structures, specifically including:

[0034] After etching to obtain the docking channel 21 and docking step 22, the epitaxial wafer is acid-treated and then cleaned and dried.

[0035] In the docking channel 21, a second InP buffer layer 311, a first P-InP layer 316, a first N-InP layer 317, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315 are grown sequentially.

[0036] Preferably, when the first docking portion 31 near the bottom of the docking channel 21 is designed as a current-blocking structure containing a semi-insulating doped growth structure of Fe-InP, the fabrication of the epitaxial structure 2 on the substrate 1 specifically includes:

[0037] A first InP buffer layer 201, a grating layer 202, and a grating protection layer 203 are sequentially grown on the surface of substrate 1; a grating is fabricated on the grating layer 202; a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212 are sequentially grown on the surface of the grating protection layer 203.

[0038] The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the third anti-corrosion layer 213;

[0039] The first docking portion 31 of the docking structure 3 is obtained by growing multiple functional layers in the docking channel 21 and designing one or more of the multiple functional layers as current blocking structures, specifically including:

[0040] After etching to obtain the docking channel 21 and docking step 22, the epitaxial wafer is acid-treated and then cleaned and dried.

[0041] In the docking channel 21, a second InP buffer layer 311, a first N-InP layer 317, an Fe-InP layer 318, a second N-InP layer 319, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315 are grown sequentially.

[0042] Preferably, the step of growing a functional layer on the surfaces of the first docking portion 31 and the docking step 22 to obtain the second docking portion 32 of the docking structure 3 specifically includes:

[0043] The second docking portion 32 is obtained by sequentially growing a second P-InP layer 321, an InGaAs contact layer 322, and a metal thin film electrode layer 323 on the surfaces of the first docking portion 31 and the docking step 22.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows: by setting a current blocking structure in the docking structure, the present invention can reduce the loss caused by current leakage in the passive waveguide region, thereby improving laser performance, reducing the current threshold, improving reliability, and improving frequency response performance. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the structure of a passive waveguide docking laser provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the structure of a passive waveguide docking laser provided in an embodiment of the present invention;

[0048] Figure 3 This is a partial schematic diagram of the structure of a passive waveguide docking laser in the prior art, provided by an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of the structure of the first passive waveguide docking laser provided in the embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure of the second passive waveguide docking laser provided in the embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of the structure of the third passive waveguide docking laser provided in the embodiments of the present invention;

[0052] Figure 7 This is a schematic diagram of the structure of the fourth passive waveguide docking laser provided in the embodiments of the present invention;

[0053] Figure 8 This is a schematic diagram of the structure of the fifth passive waveguide docking laser provided in the embodiments of the present invention;

[0054] Figure 9 This is a schematic flowchart illustrating a method for fabricating a passive waveguide docking laser structure according to an embodiment of the present invention.

[0055] Figure 10 This is a schematic flowchart illustrating a method for fabricating another passive waveguide-connected laser structure provided in an embodiment of the present invention.

[0056] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0057] 1. Substrate; 2. Epitaxial structure; 21. Docking channel; 22. Docking step; 201. First InP buffer layer; 202. Grating layer; 203. Grating protection layer; 204. First InP spacer layer; 2041. First portion; 2042. Second portion; 205. Lower confinement layer; 206. Lower waveguide layer; 207. Multiple quantum well layer; 208. Upper waveguide layer; 209. Upper confinement layer; 210. Second InP spacer layer; 211. First anti-corrosion layer; 212. First InP capping layer; 213. Third anti-corrosion layer; 214. Fourth InP spacer layer; 3. Docking structure; 31. First docking portion; 311. Second InP buffer layer; 312. InGaAsP layer; 313. Third InP spacer layer; 314. Second anti-corrosion layer; 315. Second InP capping layer; 316. First P-InP layer; 317. First N-InP layer; 318. Fe-InP layer; 319. Second N-InP layer; 32. Second docking portion; 321. Second P-InP layer; 3211. Third portion; 3212. Fourth portion; 322. InGaAs contact layer; 323. Metal thin film electrode layer. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0059] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0060] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0061] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0062] In the description of this invention, the expression “A and / or B” (where A and B are used to formally represent specific features) will be used. The corresponding expression includes the following three combinations: only A, only B, and a combination of A and B.

[0063] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0064] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0065] Example 1:

[0066] In the fabrication of passive waveguide docking lasers, a SiO2 insulating layer is deposited on the passive waveguide to limit current propagation in the waveguide region. However, the P-cladding layer below the insulating layer provides a leakage path for the current, and its background concentration gradually increases with the epitaxial growth cycle, leading to current diffusion in the passive waveguide region, resulting in losses and reducing the performance of the DFB laser. To address these issues, Embodiment 1 of this invention provides a structure for a passive waveguide docking laser, as follows: Figure 1 and Figure 2 As shown, it includes a substrate 1, an epitaxial structure 2, and a docking structure 3; the epitaxial structure 2 is obtained by growing multiple functional layers on the substrate 1; the functional layer is a general term for the layers, and the specific material used as the functional layer is determined by those skilled in the art based on the requirements.

[0067] The docking structure 3 includes a first docking portion 31 and a second docking portion 32. The first docking portion 31 is obtained by etching the epitaxial structure 2 to obtain a docking channel 21 and a docking step 22, and then growing multiple functional layers in the docking channel 21. The etched area forms the docking channel 21, and the unetched area forms the docking step 22. In practical applications, a dielectric film is deposited on the surface of the epitaxial structure 2 before etching. After depositing the dielectric film, etching is performed to obtain the docking channel 21, and the dielectric film is removed after the first docking portion 31 is grown.

[0068] The second docking portion 32 is obtained by growing multiple functional layers on the surface of the docking step 22 and the surface of the first docking portion 31; one or more functional layers in the first docking portion 31 are designed as current blocking structures; wherein, the current blocking structure is a reverse PN junction or a semi-insulating doped growth structure containing Fe-InP.

[0069] This embodiment is applicable to the fabrication of any passive waveguide device containing AlGaInAs or InGaAsP materials. For example, the lasers applicable to this embodiment include one or more of the following: DFB lasers, Fabry-perot (FP) lasers, and Vertical Cavity Surface Emitting Lasers (VCSELs). The DFB laser can be an N-type grating structure DFB laser or a P-type grating structure DFB laser.

[0070] This embodiment reduces the loss caused by current leakage in the passive waveguide region by setting a current blocking structure in the docking structure 3, thereby improving laser performance, reducing the current threshold, improving reliability, and enhancing frequency response performance.

[0071] In the prior art, the second docking part 32 can be as follows: Figure 3 As shown, in this embodiment, because a current-blocking structure is introduced in the docking structure 3, the resistance of the passive region is enhanced, so there is no need to set an additional dielectric layer. For example, in an optional implementation, such as... Figure 4 As shown, the second docking portion 32 sequentially includes a second P-InP layer 321, an InGaAs contact layer 322, and a metal thin film electrode layer 323 according to the growth direction. By removing the dielectric layer, the fabrication of the dielectric layer and the metal stripping process of the passive waveguide portion are eliminated, thereby improving the fabrication efficiency of the DFB laser and reducing the process cost.

[0072] The current blocking structure can be designed at multiple locations within the first docking portion 31. In practical applications, to improve laser performance, this embodiment also designs the thickness, position, and material of each functional layer to make the overall refractive index of the first docking portion 31 similar to that of the docking step 22. Specifically, the thickness and composition of the docking portions of the first docking portion 31 and the docking step 22 are designed to achieve equivalent refractive indices on both sides of the docking. The morphology of the docking interface is designed to reduce interface reflection and improve anti-interference capability. Figure 2 For example, the boundary position of the corresponding functional layer in the first docking part is aligned with the boundary position of the corresponding functional layer in the docking step 22, so that the refractive index is equivalent by selecting appropriate materials when the thickness of the functional layers is consistent.

[0073] The following are examples of three optional implementation methods:

[0074] First implementation method: such as Figure 5As shown, when the position of the first docking portion 31 near the second docking portion 32 is designed as a current blocking structure of a reverse PN junction, the epitaxial structure 2 includes, in sequence according to the growth direction, a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212; the docking channel 21 is etched to the first InP spacer layer 204; the first docking portion 31 includes, in sequence according to the growth direction, a second InP buffer layer 311, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, a second InP capping layer 315, a first P-InP layer 316, and a first N-InP layer 317. The first P-InP layer 316 and the first N-InP layer 317 together constitute the current blocking structure.

[0075] In one alternative implementation, such as Figure 6 As shown, the first InP spacer layer 204 is etched to a preset position, which is obtained by those skilled in the art based on experience. This allows a portion of the structure of the first InP spacer layer 204 (also called the first part 2041) to be retained in the docking step 22. At the same time, a portion of the structure of the first InP spacer layer 204 (also called the second part 2042) is also retained below the docking channel 21. The first part 2041 and the second part 2042 are tightly connected as a complete structure, thereby providing a larger docking surface by forming a convex shape to enhance the stability of the docking structure.

[0076] A preferred embodiment is as follows: the first N-InP layer 317 is grown to be flush with the dielectric film, thereby creating a space at the top of the mating step 22 after the dielectric film is removed; the growth thickness of the second P-InP layer 321 is greater than the thickness of the dielectric film, so that the grown second P-InP layer 321 includes, as follows: Figure 6 The third part 3211, located above the docking step 22, and the fourth part 3212, located above the horizontal plane of the surface of the first N-InP layer 317, are shown. The third part 3211 and the fourth part 3212 are also tightly connected as a complete structure and are convex in the opposite direction to the convex part of the first InP spacer layer 204. The stability of the docking structure is achieved through the two relatively convex functional layers, the first InP spacer layer 204 and the second P-InP layer 321.

[0077] The second implementation method: as follows Figure 7As shown, when the first docking portion 31 is designed as a reverse PN junction current blocking structure near the bottom of the docking channel 21, the epitaxial structure 2 sequentially includes a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212; the docking channel 21 is etched to the third anti-corrosion layer 213; the first docking portion 31 sequentially includes a second InP buffer layer 311, a first P-InP layer 316, a first N-InP layer 317, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315. The material of the third anti-corrosion layer 213 is InGaAsP. In this embodiment and subsequent embodiments, P-InP is used as the abbreviation for P-type InP, and N-InP is used as the abbreviation for N-type InP. The first P-InP layer 316 and the first N-InP layer 317 together constitute the current blocking structure. The purpose of the third anti-corrosion layer 213 is to control the etching depth of the docking channel 21, so that the fourth InP spacer layer 214 is etched through while the first InP spacer layer 204 is preserved. The thickness of the second InP buffer layer 311, the first P-InP layer 316, and the first N-InP layer 317 can be the same as the thickness of the fourth InP spacer layer 214.

[0078] The third implementation method: such as Figure 8As shown, when the first docking portion 31 near the bottom of the docking channel 21 is designed as a current blocking structure containing a semi-insulating doped growth structure of Fe-InP, the epitaxial structure 2 sequentially includes, in the growth direction, a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, and an upper confinement layer 209. The first mating portion 31 comprises, in order of growth direction, a second InP buffer layer 311, a first N-InP layer 317, a Fe-InP layer 318, a second N-InP layer 319, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315. The first N-InP layer 317, the Fe-InP layer 318, and the second N-InP layer 319 together constitute the current blocking structure.

[0079] The purpose of the third anti-corrosion layer 213 is to control the etching depth of the docking channel 21, so that while the fourth InP spacer layer 214 is etched through, the first InP spacer layer 204 is preserved. Its purpose is to align the InGaAsP layer 312 in the first docking portion 31 with the lower confinement layer 205, lower waveguide layer 206, multiple quantum well layer 207, upper waveguide layer 208, and upper confinement layer 209 (collectively referred to as the active region) in the docking step 22. Due to structural requirements, the thickness of the InGaAsP layer 312 is fixed. Therefore, when the current blocking structure is designed near the bottom of the docking channel 21, this embodiment controls the degree of etching by introducing the third anti-corrosion layer 213 and controls the thickness of the first InP spacer layer 204 and the fourth InP spacer layer 214, thereby ensuring that the InGaAsP layer 312 located on the upper layer of the current blocking structure is aligned with the active region. The sum of the thicknesses of the first N-InP layer 317, the Fe-InP layer 318, the second N-InP layer 319, and the second InP buffer layer 311 can be the same as the thickness of the fourth InP spacer layer 214. In a preferred embodiment, the thickness of the first InP spacer layer 204 is greater than the sum of the thicknesses of the third anti-corrosion layer 213 and the fourth spacer layer 214.

[0080] This embodiment controls the thickness of the first InP spacer layer 204 and the fourth InP spacer layer 214, and introduces a third anti-corrosion layer 213 in some embodiments, thereby enabling the selective placement of the reverse PN junction and the designability of multiple reverse PN junctions in the docking portion, thus improving the degree of freedom in the location of the current blocking structure to meet the needs of different scenarios in actual use.

[0081] Of the three implementation methods described above, the first implementation method designs a reverse PN junction current blocking structure at the position of the first docking portion 31 near the second docking portion 32. There may be a small amount of electron leakage at the interface. However, since the current blocking structure is designed close to the second docking portion 32, the requirements for epitaxial growth process are relatively low, making it easier to implement compared to the second and third implementation methods.

[0082] In the second implementation, a current blocking structure of a reverse PN junction is designed at the position of the first docking portion 31 near the bottom of the docking channel 21. The current blocking effect is better, but the epitaxial growth process requires higher precision.

[0083] In the third embodiment, the first docking portion 31 is designed with a current blocking structure containing a semi-insulating doped growth structure of Fe-InP near the bottom of the docking channel 21. Compared with the first and second embodiments, the current blocking effect is better. However, excessive Fe doping can easily lead to poor crystal quality, introduce defects, and reduce the yield of the chip.

[0084] In practical use, those skilled in the art can select one of the three implementation methods described above according to the user's needs. For example, when the user needs a laser chip with high output and minimizes production losses, the first implementation method can be selected. When the user has higher requirements for the current blocking effect, the second or third implementation method can be selected.

[0085] In a preferred embodiment of this invention, the laser end face is also coated to reduce nonradiative recombination.

[0086] It should be noted that in this embodiment, the names of each functional layer are presented by the corresponding material name plus the name of the functional layer. For functional layers with the same material name and the same functional layer and name, terms such as "first" and "second" are used to distinguish them. For example, the first N-InP layer 317 represents that the material of this layer is N-type InP material, and the fourth InP spacer layer represents the spacer layer of InP material. The materials used in functional layers that do not carry the corresponding material name are well known to those skilled in the art and will not be described in detail in this embodiment.

[0087] Example 2:

[0088] After providing the structure of a passive waveguide docking laser described in Embodiment 1, this invention will further provide a method for fabricating the structure of the passive waveguide docking laser described in Embodiment 1. This is to elaborate on the fabrication method of the corresponding structure and function in Embodiment 1 and to further analyze its design principles in detail. It should be noted that the structure in Embodiment 1 is applicable to this Embodiment 2, and its structure will not be described again in this embodiment.

[0089] This embodiment provides a method for fabricating a passive waveguide docking laser structure, such as... Figure 9 As shown, it includes:

[0090] In step 401, an epitaxial structure 2 is fabricated on the substrate 1.

[0091] In step 402, a dielectric film is deposited on the epitaxial structure 2, and a preset docking pattern is photolithographically formed on the surface of the dielectric film. According to the preset docking pattern, the position of the preset docking pattern is etched to obtain the docking channel 21. The part outside the preset docking pattern forms the docking step 22. The preset docking pattern is obtained by those skilled in the art based on the requirements.

[0092] In step 403, multiple functional layers are grown in the docking channel 21, and one or more of the multiple functional layers are designed as current blocking structures to obtain the first docking portion 31 of the docking structure 3; wherein, the current blocking structure is a reverse PN junction or a semi-insulating doped growth structure containing Fe-InP.

[0093] In step 404, the dielectric film on the surface of the docking step 22 is removed, and a functional layer is grown on the surface of the first docking portion 31 and the docking step 22 to obtain the second docking portion 32 of the docking structure 3.

[0094] Specifically, growing a functional layer on the surface of the first docking portion 31 and the docking step 22 to obtain the second docking portion 32 of the docking structure 3 includes growing a second P-InP layer 321, an InGaAs contact layer 322 and a metal thin film electrode layer 323 sequentially on the surface of the first docking portion 31 and the docking step 22 to obtain the second docking portion 32.

[0095] This embodiment describes the fabrication method of the corresponding structure for each of the three implementation methods in Embodiment 1. Specifically:

[0096] For the first embodiment of Example 1, that is, when the position of the first docking portion 31 near the second docking portion 32 is designed as a current blocking structure of a reverse PN junction, the fabrication of the epitaxial structure 2 on the substrate 1 specifically includes: sequentially growing a first InP buffer layer 201, a grating layer 202, and a grating protection layer 203 on the surface of the substrate 1; fabricating a grating on the grating layer 202; and sequentially growing a first InP spacer layer 204, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212 on the surface of the grating protection layer 203. The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the first InP spacer layer 204.

[0097] Multiple functional layers are grown in the docking channel 21, and one or more of these functional layers are designed as current-blocking structures to obtain the first docking portion 31 of the docking structure 3, such as... Figure 10 As shown, it specifically includes:

[0098] In step 501, after etching the docking channel 21 and docking step 22, the epitaxial wafer is acid-treated and then cleaned and dried.

[0099] In step 502, a second InP buffer layer 311, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, a second InP capping layer 315, a first P-InP layer 316, and a first N-InP layer 317 are sequentially grown in the docking channel 21.

[0100] For the second embodiment in Example 1, that is, when the position of the first docking portion 31 near the bottom of the docking channel 21 is designed as a current blocking structure of a reverse PN junction, the fabrication of the epitaxial structure 2 on the substrate 1 specifically includes:

[0101] A first InP buffer layer 201, a grating layer 202, and a grating protection layer 203 are sequentially grown on the surface of substrate 1; a grating is fabricated on the grating layer 202; a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212 are sequentially grown on the surface of the grating protection layer 203.

[0102] The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the third anti-corrosion layer 213.

[0103] The process of growing multiple functional layers in the docking channel 21, and designing one or more of the multiple functional layers as current blocking structures to obtain the first docking portion 31 of the docking structure 3, specifically includes: after etching to obtain the docking channel 21 and the docking step 22, acid treatment and cleaning and drying of the epitaxial wafer; and sequentially growing a second InP buffer layer 311, a first P-InP layer 316, a first N-InP layer 317, an InGaAsP layer 312, a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315 in the docking channel 21.

[0104] For the third embodiment in Example 1, that is, when the position of the first docking portion 31 near the bottom of the docking channel 21 is designed as a current blocking structure containing a Fe-InP semi-insulating doped growth structure, the fabrication of the epitaxial structure 2 on the substrate 1 specifically includes:

[0105] A first InP buffer layer 201, a grating layer 202, and a grating protection layer 203 are sequentially grown on the surface of substrate 1; a grating is fabricated on the grating layer 202; a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, and a first InP capping layer 212 are sequentially grown on the surface of the grating protection layer 203.

[0106] The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the third anti-corrosion layer 213.

[0107] The first docking portion 31 of the docking structure 3 is obtained by growing multiple functional layers in the docking channel 21 and designing one or more of the multiple functional layers as current blocking structures, specifically including:

[0108] After etching to obtain the docking channel 21 and docking step 22, the epitaxial wafer is acid-treated and cleaned and dried; in the docking channel 21, the second InP buffer layer 311, the first N-InP layer 317, the Fe-InP layer 318, the second N-InP layer 319, the InGaAsP layer 312, the third InP spacer layer 313, the second anti-corrosion layer 314, and the second InP capping layer 315 are grown sequentially.

[0109] The following example illustrates a specific application scenario. The method for fabricating a passive waveguide docking laser structure described in this embodiment includes:

[0110] Step 1: Place the substrate 1 in a metal-organic chemical vapor deposition (MOCVD) apparatus and sequentially grow the following layers on the surface of the substrate 1: first InP buffer layer 201, first InP spacer layer 204, lower confinement layer 205, lower waveguide layer 206, multiple quantum well layer 207, upper waveguide layer 208, upper confinement layer 209, second InP spacer layer 210, first anti-corrosion layer 211, and first InP capping layer 212.

[0111] Step 2: Remove the epitaxial wafer, deposit a dielectric film on the epitaxial wafer, and photolithographically create the mating pattern on the dielectric film. Remove the dielectric film on the epitaxial area that needs to be etched, and then use dry etching and wet etching to create the mating step 22.

[0112] Step 3: Place the etched epitaxial wafer back into the MOCVD equipment for docking and growth. The process involves sequentially growing a second InP buffer layer 311, a quaternary InGaAsP bulk material of a specific wavelength (i.e., InGaAsP layer 312), and a second InP capping layer 315. After the second InP capping layer 315 is grown, a first P-InP layer 316 and a first N-InP layer 317 are grown to form a reverse PN junction. Alternatively, after the second InP buffer layer 311 is grown, the first P-InP layer 316 and the first N-InP layer 317 are grown sequentially, followed by the growth of the quaternary InGaAsP bulk material of the specific wavelength (i.e., InGaAsP layer 312) and the second InP capping layer 315. Or, after the second InP buffer layer 311 is grown, an Fe-InP semi-insulating doped structure (i.e., first N-InP layer 317, Fe-InP layer 318, and second N-InP layer 319) is grown sequentially, followed by the growth of the quaternary InGaAsP bulk material of the specific wavelength and the second InP capping layer 315.

[0113] Step 4: Remove the epitaxial wafer and remove the dielectric film on its surface.

[0114] Step 5: In the MOCVD equipment, continue the epitaxial growth of the second P-InP layer 321 and the heavily doped contact layer (i.e., InGaAs contact layer 322) to form a complete laser epitaxial structure.

[0115] Step 6: Deposit a SiO2 passivation film using conventional laser post-processing, then perform photolithography, sputtering, lift-off, and patterning to prepare the metal thin film electrode layer 323, and fabricate the ridge waveguide laser epitaxial wafer.

[0116] Example 3:

[0117] like Figure 5As shown, in the passive waveguide docking growth process, an N-InP / P-InP reverse PN junction growth structure is introduced after the docking material is grown to fabricate a DFB laser. Its epitaxial structure 2 includes a substrate 1 and a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, and a first anti-corrosion layer 211. The first InP capping layer 212, the second P-InP layer 321, the heavily doped contact layer (i.e., InGaAs contact layer 322), and the metal thin film electrode layer 323 are included. The epitaxial growth of the docking portion includes the second InP buffer layer 311, the quaternary InGaAsP bulk material of a specific wavelength (i.e., InGaAsP layer 312), the third InP spacer layer 313, the second anti-corrosion layer 314, the second InP capping layer 315, the first P-InP layer 316, and the first N-InP layer 317.

[0118] Step 1: Place substrate 1 into the MOCVD equipment and epitaxially grow the first InP buffer layer 201, grating layer 202, and grating protection layer 203.

[0119] Step 2: Remove the epitaxial wafer and fabricate a grating on the grating layer 202.

[0120] Step 3: Place the epitaxial wafer with the grating back into the MOCVD equipment for grating burial and epitaxial regrowth. The following layers are grown sequentially: first InP spacer layer 204, lower confinement layer 205, lower waveguide layer 206, multiple quantum well layer 207, upper waveguide layer 208, upper confinement layer 209, second InP spacer layer 210, first anti-corrosion layer 211, and first InP capping layer 212.

[0121] Step 4: Remove the epitaxial wafer and deposit a dielectric film on it.

[0122] Step 5: Use conventional chip photolithography to create the mating pattern on the dielectric film, which involves removing the dielectric film on the epitaxial region that needs to be etched.

[0123] Step 6: Using dry etching and wet etching methods, etch the areas on the epitaxial surface that are not covered by the dielectric film. Use a profilometer and scanning electron microscope to monitor the etching depth and surface condition until the first InP spacer layer 204 is reached.

[0124] Step 7: Acid treatment of the etched epitaxial wafer, followed by cleaning and drying.

[0125] Step 8: Place the material back into the MOCVD equipment for docking growth. The second InP buffer layer 311, a quaternary InGaAsP bulk material of a specific wavelength (i.e., InGaAsP layer 312), a third InP spacer layer 313, a second anti-corrosion layer 314, a second InP capping layer 315, a first P-InP layer 316, and a first N-InP layer 317 are then docked and grown sequentially.

[0126] Step 9: Remove the epitaxial wafer and remove the SiO2 mask (i.e., dielectric film) from the non-interlocking areas.

[0127] Step 10: Place the epitaxial wafer processed above back into the MOCVD equipment to epitaxially grow a second P-InP layer 321 and a heavily doped contact layer (i.e., InGaAs contact layer 322) to form a complete DFB epitaxial structure 2.

[0128] Step 11: Based on the conventional DFB laser post-processing for fabricating a ridge waveguide DFB laser, the fabrication of the dielectric layer and metal stripping process for the passive waveguide portion are omitted, resulting in a DFB laser consisting only of a 323 metal thin-film electrode layer.

[0129] Step 12: Unscramble the Bar strips to perform DFB laser coating tests.

[0130] Example 4:

[0131] like Figure 7 As shown, in the passive waveguide docking growth process, an N-InP / P-InP reverse PN junction growth structure is introduced before the docking material is grown to fabricate a DFB laser. Its epitaxial structure 2 includes a substrate 1 and a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, a first InP capping layer 212, a second P-InP layer 321, a heavily doped contact layer (i.e., an InGaAs contact layer 322), and a metal thin film electrode layer 323. The epitaxial growth of the docking portion includes a second InP buffer layer 311, a first P-InP layer 316, a first N-InP layer 317, a quaternary InGaAsP bulk material of a specific wavelength (i.e., InGaAsP layer 312), a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315.

[0132] Step 1: Place substrate 1 into the MOCVD equipment and epitaxially grow the first InP buffer layer 201, grating layer 202, and grating protection layer 203.

[0133] Step 2: Remove the epitaxial wafer and fabricate a grating on the grating layer 202.

[0134] Step 3: Place the epitaxial wafer with the grating back into the MOCVD equipment for grating embedding and epitaxial growth. The following layers are grown sequentially: first InP spacer layer 204, third anti-corrosion layer 213 (made of InGaAsP), fourth InP spacer layer 214, lower confinement layer 205, lower waveguide layer 206, multiple quantum well layer 207, upper waveguide layer 208, upper confinement layer 209, second InP spacer layer 210, first anti-corrosion layer 211, and first InP capping layer 212.

[0135] Step 4: Remove the epitaxial wafer and deposit a dielectric film on it.

[0136] Step 5: Use conventional chip photolithography to create the mating pattern on the dielectric film, which involves removing the dielectric film on the epitaxial region that needs to be etched.

[0137] Step 6: Using dry etching and wet etching methods, etch the areas on the epitaxial surface that are not covered by the dielectric film. Use a profilometer and scanning electron microscope to monitor the etching depth and surface condition. Etch to the fourth InP spacer layer 214 (specifically, etch through the fourth InP spacer layer 214 until the third anti-corrosion layer 213 is exposed).

[0138] Step 7: Acid treatment of the etched epitaxial wafer, followed by cleaning and drying.

[0139] Step 8: Place the material back into the MOCVD equipment for docking growth. The second InP buffer layer 311, the first P-InP layer 316, the first N-InP layer 317, the quaternary InGaAsP bulk material of a specific wavelength (i.e., InGaAsP layer 312), the third InP spacer layer 313, the second anti-corrosion layer 314, and the second InP capping layer 315 are then docked and grown sequentially.

[0140] Step 9: Remove the epitaxial wafer and remove the SiO2 mask from the non-interlocking areas.

[0141] Step 10: Place the epitaxial wafer processed above back into the MOCVD equipment to epitaxially grow a second P-InP layer 321 and a heavily doped contact layer (i.e., InGaAs contact layer 322) to form a complete DFB epitaxial structure 2.

[0142] Step 11: Based on the conventional DFB laser post-processing for fabricating a ridge waveguide DFB laser, the fabrication of the dielectric layer and metal stripping process for the passive waveguide portion are omitted, resulting in a DFB laser consisting only of a 323 metal thin-film electrode layer.

[0143] Step 12: Remove the bar strip and perform DFB laser coating test.

[0144] Example 5:

[0145] like Figure 8 As shown, in the passive waveguide docking growth process, a Fe-InP semi-insulating doped structure is introduced before the docking material is grown to fabricate a DFB laser. Its epitaxial structure 2 includes a substrate 1 and a first InP buffer layer 201, a grating layer 202, a grating protection layer 203, a first InP spacer layer 204, a third anti-corrosion layer 213, a fourth InP spacer layer 214, a lower confinement layer 205, a lower waveguide layer 206, a multiple quantum well layer 207, an upper waveguide layer 208, an upper confinement layer 209, a second InP spacer layer 210, a first anti-corrosion layer 211, a first InP capping layer 212, a second P-InP layer 321, a heavily doped contact layer (i.e., an InGaAs contact layer 322), and a metal thin film electrode layer 323. The epitaxial growth of the docking portion includes a second InP buffer layer 311, a first N-InP layer 317, an Fe-InP layer 318, a second N-InP layer 319, a quaternary InGaAsP bulk material of a specific wavelength (i.e., InGaAsP layer 312), a third InP spacer layer 313, a second anti-corrosion layer 314, and a second InP capping layer 315.

[0146] Step 1: Place substrate 1 into the MOCVD equipment and epitaxially grow the first InP buffer layer 201, grating layer 202, and grating protection layer 203.

[0147] Step 2: Remove the epitaxial wafer and fabricate a grating on the grating layer 202.

[0148] Step 3: Place the epitaxial wafer with the grating back into the MOCVD equipment for grating embedding and epitaxial growth. The following layers are grown sequentially: first InP spacer layer 204, third anti-corrosion layer 213, fourth InP spacer layer 214, lower confinement layer 205, lower waveguide layer 206, multiple quantum well layer 207, upper waveguide layer 208, upper confinement layer 209, second InP spacer layer 210, first anti-corrosion layer 211, and first InP capping layer 212.

[0149] Step 4: Remove the epitaxial wafer and deposit a dielectric film on it.

[0150] Step 5: Use conventional chip photolithography to create the mating pattern on the dielectric film, which involves removing the dielectric film on the epitaxial region that needs to be etched.

[0151] Step 6: Using dry etching and wet etching methods, etch the areas on the epitaxial surface that are not covered by the dielectric film. Use a profilometer and scanning electron microscope to monitor the etching depth and surface condition. Etch to the fourth InP spacer layer 214 (specifically, etch through the fourth InP spacer layer 214 until the third anti-corrosion layer 213 is exposed).

[0152] Step 7: Acid treatment of the etched epitaxial wafer, followed by cleaning and drying.

[0153] Step 8: Place the material back into the MOCVD equipment for docking growth. The following layers are grown sequentially: second InP buffer layer 311, first N-InP layer 317, Fe-InP layer 318, second N-InP layer 319, quaternary InGaAsP bulk material at a specific wavelength (i.e., InGaAsP layer 312), third InP spacer layer 313, second anti-corrosion layer 314, and second InP capping layer 315.

[0154] Step 9: Remove the epitaxial wafer and remove the SiO2 mask from the non-interlocking areas.

[0155] Step 10: Place the epitaxial wafer processed above back into the MOCVD equipment to epitaxially grow a second P-InP layer 321 and a heavily doped contact layer (i.e., InGaAs contact layer 322) to form a complete DFB epitaxial structure 2.

[0156] Step 11: Based on the conventional DFB laser post-processing for fabricating a ridge waveguide DFB laser, the fabrication of the dielectric layer and metal stripping process for the passive waveguide portion are omitted, resulting in a DFB laser consisting only of a 323 metal thin-film electrode layer.

[0157] Step 12: Remove the bar strip and perform DFB laser coating test.

[0158] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A structure for a passive waveguide-connected laser, characterized in that, It includes a substrate (1), an epitaxial structure (2), and a docking structure (3); The epitaxial structure (2) is obtained by growing multiple functional layers on a substrate (1); The docking structure (3) includes a first docking portion (31) and a second docking portion (32). The first docking portion (31) is obtained by etching the epitaxial structure (2) to obtain a docking channel (21) and a docking step (22), and then growing multiple functional layers in the docking channel (21). The second docking portion (32) is obtained by growing multiple functional layers on the surface of the docking step (22) and the surface of the first docking portion (31); One or more functional layers in the first docking portion (31) are designed as current blocking structures; wherein the current blocking structure is a reverse PN junction or a semi-insulating doped growth structure containing Fe-InP.

2. The structure of the passive waveguide docking laser according to claim 1, characterized in that, When the position of the first docking portion (31) near the second docking portion (32) is designed as a current blocking structure of a reverse PN junction, the epitaxial structure (2) includes, in sequence according to the growth direction, a first InP buffer layer (201), a grating layer (202), a grating protection layer (203), a first InP spacer layer (204), a lower confinement layer (205), a lower waveguide layer (206), a multiple quantum well layer (207), an upper waveguide layer (208), an upper confinement layer (209), a second InP spacer layer (210), a first anti-corrosion layer (211), and a first InP capping layer (212); The docking channel (21) is etched to the first InP spacer layer (204); the first docking portion (31) includes, in sequence according to the growth direction, a second InP buffer layer (311), an InGaAsP layer (312), a third InP spacer layer (313), a second anti-corrosion layer (314), a second InP capping layer (315), a first P-InP layer (316), and a first N-InP layer (317); wherein, the first P-InP layer (316) and the first N-InP layer (317) constitute the current blocking structure.

3. The structure of the passive waveguide docking laser according to claim 1, characterized in that, When the first docking portion (31) is designed as a current blocking structure of a reverse PN junction near the bottom of the docking channel (21), the epitaxial structure (2) includes, in sequence according to the growth direction, a first InP buffer layer (201), a grating layer (202), a grating protection layer (203), a first InP spacer layer (204), a third anti-corrosion layer (213), a fourth InP spacer layer (214), a lower confinement layer (205), a lower waveguide layer (206), a multiple quantum well layer (207), an upper waveguide layer (208), an upper confinement layer (209), a second InP spacer layer (210), a first anti-corrosion layer (211), and a first InP capping layer (212); The docking channel (21) is etched to the third anti-corrosion layer (213); the first docking portion (31) includes, in sequence according to the growth direction, a second InP buffer layer (311), a first P-InP layer (316), a first N-InP layer (317), an InGaAsP layer (312), a third InP spacer layer (313), a second anti-corrosion layer (314), and a second InP capping layer (315); wherein, the first P-InP layer (316) and the first N-InP layer (317) constitute the current blocking structure.

4. The structure of the passive waveguide docking laser according to claim 1, characterized in that, When the first docking portion (31) near the bottom of the docking channel (21) is designed as a current blocking structure containing a semi-insulating doped growth structure of Fe-InP, the epitaxial structure (2) includes, in sequence according to the growth direction, a first InP buffer layer (201), a grating layer (202), a grating protection layer (203), a first InP spacer layer (204), a third anti-corrosion layer (213), a fourth InP spacer layer (214), a lower confinement layer (205), a lower waveguide layer (206), a multiple quantum well layer (207), an upper waveguide layer (208), an upper confinement layer (209), a second InP spacer layer (210), a first anti-corrosion layer (211), and a first InP capping layer (212); The docking channel (21) is etched to the third anti-corrosion layer (213); the first docking portion (31) includes, in sequence according to the growth direction, a second InP buffer layer (311), a first N-InP layer (317), an Fe-InP layer (318), a second N-InP layer (319), an InGaAsP layer (312), a third InP spacer layer (313), a second anti-corrosion layer (314), and a second InP capping layer (315); wherein, the first N-InP layer (317), the Fe-InP layer (318), and the second N-InP layer (319) constitute the current blocking structure.

5. The structure of the passive waveguide docking laser according to any one of claims 1-4, characterized in that, The second docking portion (32) includes, in sequence according to the growth direction, a second P-InP layer (321), an InGaAs contact layer (322), and a metal thin film electrode layer (323).

6. The structure of the passive waveguide docking laser according to any one of claims 1-4, characterized in that, The applicable lasers include one or more of DFB lasers, FP lasers, and VCSEL lasers.

7. A method for fabricating a passive waveguide docking laser structure as described in any one of claims 1-6, characterized in that, include: An epitaxial structure (2) was fabricated on a substrate (1); A dielectric film is deposited on the epitaxial structure (2), and a preset docking pattern is photolithographically formed on the surface of the dielectric film. According to the preset docking pattern, the position of the preset docking pattern is etched to obtain a docking channel (21). The part outside the preset docking pattern forms a docking step (22). Multiple functional layers are grown in the docking channel (21), and one or more of the multiple functional layers are designed as current blocking structures to obtain the first docking portion (31) of the docking structure (3); wherein the current blocking structure is a reverse PN junction or a semi-insulating doped growth structure containing Fe-InP. Remove the dielectric film on the surface of the docking step (22), and grow a functional layer on the surface of the first docking portion (31) and the docking step (22) to obtain the second docking portion (32) of the docking structure (3).

8. The method for fabricating the passive waveguide docking laser structure according to claim 7, characterized in that, When the position of the first docking portion (31) near the second docking portion (32) is designed as a current blocking structure of a reverse PN junction, the fabrication of the epitaxial structure (2) on the substrate (1) specifically includes: A first InP buffer layer (201), a grating layer (202), and a grating protection layer (203) are sequentially grown on the surface of the substrate (1); a grating is fabricated on the grating layer (202); a first InP spacer layer (204), a lower confinement layer (205), a lower waveguide layer (206), a multiple quantum well layer (207), an upper waveguide layer (208), an upper confinement layer (209), a second InP spacer layer (210), a first anti-corrosion layer (211), and a first InP capping layer (212) are sequentially grown on the surface of the grating protection layer (203). The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the first InP spacer layer (204); The process involves growing multiple functional layers in the docking channel (21), and designing one or more of these functional layers as current-blocking structures to obtain the first docking portion (31) of the docking structure (3), specifically including: After etching to obtain the docking channel (21) and docking step (22), the epitaxial wafer is acid treated and then cleaned and dried; A second InP buffer layer (311), an InGaAsP layer (312), a third InP spacer layer (313), a second anti-corrosion layer (314), a second InP capping layer (315), a first P-InP layer (316), and a first N-InP layer (317) are sequentially grown in the docking channel (21).

9. The method for fabricating the passive waveguide docking laser structure according to claim 7, characterized in that, When the first docking portion (31) is designed as a current blocking structure of a reverse PN junction near the bottom of the docking channel (21), the epitaxial structure (2) fabricated on the substrate (1) specifically includes: A first InP buffer layer (201), a grating layer (202), and a grating protection layer (203) are sequentially grown on the surface of a substrate (1); a grating is fabricated on the grating layer (202); a first InP spacer layer (204), a third anti-corrosion layer (213), a fourth InP spacer layer (214), a lower confinement layer (205), a lower waveguide layer (206), a multiple quantum well layer (207), an upper waveguide layer (208), an upper confinement layer (209), a second InP spacer layer (210), a first anti-corrosion layer (211), and a first InP capping layer (212) are sequentially grown on the surface of the grating protection layer (203). The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the third anti-corrosion layer (213); The process involves growing multiple functional layers in the docking channel (21), and designing one or more of these functional layers as current-blocking structures to obtain the first docking portion (31) of the docking structure (3), specifically including: After etching to obtain the docking channel (21) and docking step (22), the epitaxial wafer is acid treated and then cleaned and dried; In the docking channel (21), a second InP buffer layer (311), a first P-InP layer (316), a first N-InP layer (317), an InGaAsP layer (312), a third InP spacer layer (313), a second anti-corrosion layer (314), and a second InP capping layer (315) are grown sequentially.

10. The method for fabricating the passive waveguide docking laser structure according to claim 7, characterized in that, When the first docking portion (31) is designed as a current-blocking structure containing a semi-insulating doped growth structure of Fe-InP near the bottom of the docking channel (21), the fabrication of the epitaxial structure (2) on the substrate (1) specifically includes: A first InP buffer layer (201), a grating layer (202), and a grating protection layer (203) are sequentially grown on the surface of a substrate (1); a grating is fabricated on the grating layer (202); a first InP spacer layer (204), a third anti-corrosion layer (213), a fourth InP spacer layer (214), a lower confinement layer (205), a lower waveguide layer (206), a multiple quantum well layer (207), an upper waveguide layer (208), an upper confinement layer (209), a second InP spacer layer (210), a first anti-corrosion layer (211), and a first InP capping layer (212) are sequentially grown on the surface of the grating protection layer (203). The etching of the preset docking pattern position specifically includes: etching according to the preset docking pattern until the etching reaches the third anti-corrosion layer (213); The process involves growing multiple functional layers in the docking channel (21), and designing one or more of these functional layers as current-blocking structures to obtain the first docking portion (31) of the docking structure (3), specifically including: After etching to obtain the docking channel (21) and docking step (22), the epitaxial wafer is acid treated and then cleaned and dried; In the docking channel (21), a second InP buffer layer (311), a first N-InP layer (317), an Fe-InP layer (318), a second N-InP layer (319), an InGaAsP layer (312), a third InP spacer layer (313), a second anti-corrosion layer (314), and a second InP capping layer (315) are grown sequentially.

Images