Short circuit protection circuit, controller and vehicle

Abstract

The embodiment of the invention relates to a short circuit protection circuit, a controller and a vehicle. The short-circuit protection circuit comprises a current detection circuit, a comparison circuit, a switching circuit and a latch circuit. The current detection circuit is configured to generate a target voltage according to a target current flowing from the first node to the second node and provide the target voltage to the third node. When the target current is greater than the short-circuit current threshold, the target voltage is higher than the reference voltage. The comparison circuit is configured to output a first level via the fourth node when a voltage of the third node is higher than a reference voltage. The switching circuit is configured to disconnect the connection between the first node and the second node when the fourth node is at the first level. The latch circuit is configured to maintain a voltage of the third node higher than a reference voltage when the fourth node is at a first level. The short-circuit protection circuit can disconnect a loop when the loop is short-circuited, thereby protecting the safety of other components in the loop.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to the field of circuit technology, and more specifically to short-circuit protection circuits, controllers, and vehicles. Background Technology

[0002] A short circuit occurs when a circuit or part of a circuit is shorted. During a short circuit, the current supplied by the power source will be much greater than the current supplied under normal conditions, which may burn out the power source or equipment. Summary of the Invention

[0003] Embodiments of this disclosure provide a short-circuit protection circuit, a controller, and a vehicle.

[0004] According to a first aspect of this disclosure, a short-circuit protection circuit is provided. The short-circuit protection circuit includes: a current detection circuit, a comparator circuit, a switching circuit, and a latching circuit. The current detection circuit is configured to generate a target voltage based on a target current flowing from a first node to a second node and to provide the target voltage to a third node. Wherein, if the target current is greater than a short-circuit current threshold, the target voltage is higher than a reference voltage. The comparator circuit is configured to output a first level via a fourth node when the voltage at the third node is higher than the reference voltage. The switching circuit is configured to disconnect the connection between the first node and the second node when the fourth node is at the first level. The latching circuit is configured to maintain the voltage at the third node higher than the reference voltage when the fourth node is at the first level.

[0005] According to a second aspect of this disclosure, a controller is provided. The controller includes a short-circuit protection circuit as described in the first aspect of this disclosure. A first node is coupled to the ground terminal of an interface circuit within the controller, and a second node is coupled to an external ground terminal.

[0006] According to a third aspect of this disclosure, a vehicle is provided. The vehicle includes a controller as described in a second aspect of this disclosure. Attached Figure Description

[0007] The above and other objects, features and advantages of this disclosure will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0008] Figure 1 The illustration shows a schematic diagram of an example environment in which a short-circuit protection circuit according to an embodiment of the present disclosure may be implemented;

[0009] Figure 2 A schematic block diagram of a short-circuit protection circuit according to an embodiment of the present disclosure is shown;

[0010] Figure 3A further schematic block diagram of a short-circuit protection circuit according to an embodiment of the present disclosure is shown;

[0011] Figure 4 A schematic circuit diagram of a short-circuit protection circuit according to an embodiment of the present disclosure is shown.

[0012] Figure 5 Another schematic circuit diagram of a short-circuit protection circuit according to an embodiment of the present disclosure is shown.

[0013] In the various accompanying figures, the same or corresponding labels indicate the same or corresponding parts. It should be noted that the elements in the accompanying figures are schematic and not drawn to scale. Detailed Implementation

[0014] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0015] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0016] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through at least one intermediate component.

[0017] As mentioned earlier, the current supplied by the power supply during a short circuit will be much greater than the current supplied under normal conditions, which may damage the power supply or equipment. Therefore, a short-circuit protection circuit can be designed in the circuit to protect the circuit in the event of a short circuit. Embodiments of this disclosure propose a short-circuit protection circuit.

[0018] The embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings, wherein... Figure 1 The illustration shows an example environment in which a short-circuit protection circuit according to an embodiment of the present disclosure may be implemented.

[0019] like Figure 1 As shown, example environment 1 includes vehicle 10. Vehicle 10 may include an electronic control unit (ECU), an ignition circuit 11, and other input / output circuits 12. The input voltage V1 (e.g., 48V) of the ECU may be stepped down to voltage V3 (e.g., 33V) via a first buck converter BUCK1. Voltage V3 may serve as the power supply voltage for interface chip IC1. Voltage V3 may be stepped down to voltage V4 (e.g., 3.3V) via a second buck converter BUCK2. Voltage V4 may serve as the power supply voltage for interface chip IC1 and other chip IC2. The first buck converter BUCK1, the second buck converter BUCK2, interface chip IC1, and other chip IC2 may all be connected to a first node N1.

[0020] Interface chip IC1 can be connected to ignition circuit 11 and other input / output circuits 12 via a wiring harness. With wear and tear on the wiring harness, or in the event of a vehicle collision, interface chip IC1 may be shorted to the input voltage V1. Since the power supply voltage that interface chip IC1 can withstand is lower than the input voltage V1, interface chip IC1 may be burned out if it is shorted to the input voltage V1.

[0021] In some implementations, a Zener diode can be added to each wiring harness connected to the first node N1 to protect the components on the corresponding harness from damage if the interface chip IC1 is shorted to the input voltage V1. However, the Zener diode itself may fail, causing the ECU's functional level to Failure Severity Classification (FSC) Level D, where component damage is irreversible. Furthermore, the hardware cost is high because a Zener diode needs to be added to every wiring harness. Consequently, the printed circuit board (PCB) area is also relatively large due to the need for a large number of Zener diodes.

[0022] refer to Figure 1The embodiments of this disclosure propose to provide a short-circuit protection circuit 200 between the first node N1 and ground (second node N2). The short-circuit protection circuit 200 is configured to disconnect the connection between the first node N1 and ground (second node N2) in the event of a short circuit, thereby breaking the loop between the interface chip IC1 and ground and preventing the interface chip IC1 from burning out.

[0023] Figure 2 A schematic block diagram of a short-circuit protection circuit 200 according to an embodiment of the present disclosure is shown. The short-circuit protection circuit 200 includes a current detection circuit 210, a comparison circuit 220, a switching circuit 230, and a latching circuit 240. The current detection circuit 210 and the switching circuit 230 are connected in series between a first node N1 and a second node N2.

[0024] Current sensing circuit 210 is coupled to second node N2 and switching circuit 230. Current sensing circuit 210 is also coupled to the input of comparator circuit 220 and latching circuit 240 via third node N3. Current sensing circuit 210 is configured to generate a target voltage Vtar based on the target current flowing from first node N1 to second node N2 and to provide the target voltage Vtar to third node N3. Specifically, when the target current is greater than a short-circuit current threshold, the target voltage Vtar is higher than a reference voltage Vref. When the target current is less than the short-circuit current threshold, the target voltage Vtar is lower than the reference voltage Vref. When the target current is equal to the short-circuit current threshold, the target voltage Vtar is equal to the reference voltage Vref. When the connection between first node N1 and second node N2 is broken, the target current is zero, and the target voltage Vtar is also zero.

[0025] Comparator circuit 220 is coupled to current detection circuit 210 via a third node N3 to obtain a target voltage Vtar generated by current detection circuit 210. Comparator circuit 220 is also coupled to a reference voltage terminal to obtain a reference voltage Vref from the reference voltage terminal. Comparator circuit 220 is coupled to switching circuit 230 and latching circuit 240 via a fourth node N4. Comparator circuit 220 is configured to output a first level via fourth node N4 when the voltage at third node N3 is higher than the reference voltage Vref. Comparator circuit 220 is also configured to output a second level via fourth node N4 when the voltage at third node N3 is lower than the reference voltage Vref. In some embodiments of this disclosure, comparator circuit 220 outputs a first level via fourth node N4 when the voltage at third node N3 is equal to the reference voltage Vref. Alternatively, in other embodiments of this disclosure, comparator circuit 220 outputs a second level via fourth node N4 when the voltage at third node N3 is equal to the reference voltage Vref. The output voltage of comparator circuit 220 is provided to switching circuit 230 and latching circuit 240.

[0026] Switching circuit 230 is coupled to first node N1 and current detection circuit 210. Switching circuit 230 is also coupled to comparator circuit 220 and latching circuit 240 via fourth node N4. Switching circuit 230 is configured to disconnect the connection between first node N1 and second node N2 when fourth node N4 is at a first level. Switching circuit 230 is also configured to connect first node N1 and second node N2 when fourth node N4 is at a second level.

[0027] The latch circuit 240 is coupled to the inputs of the current detection circuit 210 and the comparator circuit 220 via the third node N3. The latch circuit 240 is also coupled to the outputs of the switch circuit 230 and the comparator circuit 220 via the fourth node N4. The latch circuit 240 is configured to maintain the voltage of the third node N3 above the reference voltage Vref when the fourth node N4 is at a first level. The latch circuit 240 is also configured to stop operating when the fourth node N4 is at a second level, so as not to affect the voltage of the third node N3.

[0028] In some embodiments of this disclosure, the first level is low and the second level is high. It should be noted that, in this context, high and low levels are relative. The reference voltage Vref can be set based on the ratio between the target current and the target voltage Vtar, as well as the short-circuit current threshold.

[0029] Initially, the first node N1 and the second node N2 are connected. Figure 1 When the interface chip IC1 is operating normally, the target current flowing from the first node N1 to the second node N2 is less than the short-circuit current threshold. The target voltage Vtar generated by the current detection circuit 210 is lower than the reference voltage Vref. Therefore, the voltage of the third node N3 is lower than the reference voltage Vref. The comparator circuit 220 outputs a second level. In this case, the switching circuit 230 maintains the connection between the first node N1 and the second node N2, and the latching circuit 240 does not affect the voltage of the third node N3.

[0030] exist Figure 1 When the interface chip IC1 is shorted to the input voltage V1, the target current flowing from the first node N1 to the second node N2 is greater than the short-circuit current threshold. The target voltage Vtar generated by the current detection circuit 210 is higher than the reference voltage Vref. Therefore, the voltage of the third node N3 is higher than the reference voltage Vref. The comparator circuit 220 outputs a first level. In this case, the switch circuit 230 disconnects the connection between the first node N1 and the second node N2, and the latch circuit 240 maintains that the voltage of the third node N3 is higher than the reference voltage Vref. In this way, the comparator circuit 220 stably outputs the first level, thereby keeping the connection between the first node N1 and the second node N2 disconnected by the switch circuit 230.

[0031] The short-circuit protection circuit 200 of this disclosure can disconnect the circuit in the event of a short circuit, thereby protecting the safety of other components in the circuit. Furthermore, the short-circuit protection circuit 200 can maintain the open-circuit state of the circuit through the latching circuit 240, thereby preventing the circuit state from oscillating back and forth between short circuit and open circuit. Compared to implementations using Zener diodes, the embodiments of this disclosure significantly reduce hardware costs, save PCB area, and enable the ECU to achieve FSC Class C functionality. At FSC Class C, components are not damaged, and a power-on reset is required to restore functionality.

[0032] Figure 3 A further schematic block diagram of a short-circuit protection circuit 200 according to an embodiment of the present disclosure is shown. Figure 3 As shown, the latch circuit 240 includes: a pull-down circuit 241, a pull-up circuit 242, a first control circuit 243, and a second control circuit 244.

[0033] Pull-down circuit 241 is coupled to the output of comparator circuit 220 and switch circuit 230 via fourth node N4. Pull-down circuit 241 is also coupled to pull-up circuit 242 and first control circuit 243 via fifth node N5. Pull-down circuit 241 is configured to pull down the voltage of fifth node N5 to a first level when fourth node N4 is at a second level. Pull-down circuit 241 is also configured not to affect the voltage of fifth node N5 when fourth node N4 is at the first level.

[0034] Pull-up circuit 242 is coupled to the power supply voltage terminal Vcc. Pull-up circuit 242 is also coupled to pull-down circuit 241 and first control circuit 243 via fifth node N5. Pull-up circuit 242 is configured to pull up the voltage of fifth node N5 to a second level when fourth node N4 is at a first level. The second level can be equal to the power supply voltage from power supply voltage terminal Vcc.

[0035] The first control circuit 243 is coupled to pull-down circuit 241 and pull-up circuit 242 via a fifth node N5. The first control circuit 243 is also coupled to a second control circuit 244 via a sixth node N6. The first control circuit 243 is configured to pull down the voltage of the sixth node N6 to a first level when the voltage of the fifth node N5 is at a second level. The first control circuit 243 is also configured to stop operating when the voltage of the fifth node N5 is at the first level, so as not to affect the voltage of the sixth node N6.

[0036] The second control circuit 244 is coupled to the power supply voltage terminal Vcc. The second control circuit 244 is coupled to the first control circuit 243 via the sixth node N6. The second control circuit 244 is coupled to the input terminals of the current detection circuit 210 and the comparator circuit 220 via the third node N3. The second control circuit 244 is configured to pull up the voltage of the third node N3 to a second level when the voltage of the sixth node N6 is at a first level, and to stop operating in other cases (when the voltage of the sixth node N6 is not at the first level) so as not to affect the voltage of the third node N3. Here, the second level is higher than the reference voltage Vref.

[0037] Initially, the first node N1 and the second node N2 are connected. Figure 1 When the interface chip IC1 is operating normally, the target current flowing from the first node N1 to the second node N2 is less than the short-circuit current threshold. The target voltage Vtar generated by the current detection circuit 210 is lower than the reference voltage Vref. Therefore, the voltage of the third node N3 is lower than the reference voltage Vref. The comparator circuit 220 outputs a second level. In this case, the switching circuit 230 maintains the connection between the first node N1 and the second node N2. Since the fourth node N4 is at the second level, the pull-down circuit 241 pulls the voltage of the fifth node N5 down to the first level. The first control circuit 243 stops working. The second control circuit 244 also stops working. Therefore, the latching circuit 240 does not affect the voltage of the third node N3.

[0038] exist Figure 1 When the interface chip IC1 is shorted to the input voltage V1, the target current flowing from the first node N1 to the second node N2 is greater than the short-circuit current threshold. The target voltage Vtar generated by the current detection circuit 210 is higher than the reference voltage Vref. Therefore, the voltage of the third node N3 is higher than the reference voltage Vref. The comparator circuit 220 outputs a first level. In this case, the switch circuit 230 disconnects the connection between the first node N1 and the second node N2. Since the fourth node N4 is at the first level, the pull-up circuit 242 pulls the voltage of the fifth node N5 up to the second level. The first control circuit 243 pulls the voltage of the sixth node N6 down to the first level. The second control circuit 244 pulls the voltage of the third node N3 up to the second level. In this way, the latch circuit 240 maintains the voltage of the third node N3 higher than the reference voltage Vref. Therefore, the comparator circuit 220 can stably output the first level, thereby keeping the connection between the first node N1 and the second node N2 disconnected by the switch circuit 230.

[0039] Figure 4 The diagram shows Figure 3 A schematic circuit diagram of the short-circuit protection circuit 200. Figure 4In the example, pull-down circuit 241 includes a first resistor R1 and a first transistor M1. The first terminal of the first resistor R1 is coupled to a fourth node N4. The second terminal of the first resistor R1 is coupled to a second voltage terminal V2. The control electrode of the first transistor M1 is coupled to the first terminal of the first resistor R1. The first electrode of the first transistor M1 is coupled to the second voltage terminal V2. The second electrode of the first transistor M1 is coupled to a fifth node N5.

[0040] The pull-up circuit 242 includes a second resistor R2. The first end of the second resistor R2 is coupled to the power supply voltage terminal Vcc. The second end of the second resistor R2 is coupled to the fifth node N5.

[0041] The first control circuit 243 includes a third resistor R3 and a second transistor M2. The first terminal of the third resistor R3 is coupled to the fifth node N5. The second terminal of the third resistor R3 is coupled to the second voltage terminal V2. The control electrode of the second transistor M2 is coupled to the fifth node N5. The first electrode of the second transistor M2 is coupled to the second voltage terminal V2. The second electrode of the second transistor M2 is coupled to the sixth node N6.

[0042] The second control circuit 244 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a third transistor M3. The first terminal of the fourth resistor R4 is coupled to the power supply voltage terminal Vcc. The second terminal of the fourth resistor R4 is coupled to the sixth node N6. The first terminal of the fifth resistor R5 is coupled to the sixth node N6. The second terminal of the fifth resistor R5 is coupled to the control terminal of the third transistor M3. The first terminal of the sixth resistor R6 is coupled to the power supply voltage terminal Vcc. The second terminal of the sixth resistor R6 is coupled to the first terminal of the third transistor M3. The first terminal of the seventh resistor R7 is coupled to the second terminal of the third transistor M3 and the third node N3. The second terminal of the seventh resistor R7 is coupled to the second voltage terminal V2.

[0043] The switching circuit 230 includes a fourth transistor M4 and a fifth transistor M5. The control electrode of the fourth transistor M4 is coupled to the fourth node N4. The first electrode of the fourth transistor M4 is coupled to the first electrode of the fifth transistor M5. The second electrode of the fourth transistor M4 is coupled to the input terminal of the current detection circuit 210. The control electrode of the fifth transistor M5 is coupled to the fourth node N4. The second electrode of the fifth transistor M5 is coupled to the first node N1. The fourth transistor M4 and the fifth transistor M5 form a back-to-back structure, and their body diodes are oriented in opposite directions to prevent reverse current.

[0044] The current sensing circuit 210 includes an eighth resistor R8 and a first operational amplifier AMP1. The first terminal of the eighth resistor R8 is coupled to the second terminal of the fourth transistor M4. The second terminal of the eighth resistor R8 is coupled to the second node N2. The first input terminal of the first operational amplifier AMP1 is coupled to the first terminal of the eighth resistor R8. The second input terminal of the first operational amplifier AMP1 is coupled to the second terminal of the eighth resistor R8. The output terminal of the first operational amplifier AMP1 is coupled to the third node N3.

[0045] Comparator circuit 220 includes a second operational amplifier AMP2. A reference voltage Vref is provided to the first input terminal of the second operational amplifier AMP2. The second input terminal of the second operational amplifier AMP2 is coupled to a third node N3. The output terminal of the second operational amplifier AMP2 is coupled to a fourth node N4.

[0046] exist Figure 4 In the example, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 are N-type transistors. The third transistor M3 is a P-type transistor. The second voltage terminal V2 is grounded. The first input terminal of the first operational amplifier AMP1 is a non-inverting input terminal. The second input terminal of the first operational amplifier AMP1 is an inverting input terminal. The first input terminal of the second operational amplifier AMP2 is a non-inverting input terminal. The second input terminal of the second operational amplifier AMP2 is an inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 4 Any modifications to the circuit shown should also fall within the scope of this disclosure. In this modification, the voltage terminal may also have the same... Figure 4 The examples shown have different settings.

[0047] Initially, the fourth transistor M4 and the fifth transistor M5 are turned on. Figure 1 When the interface chip IC1 is operating normally, the target current flowing from the first node N1 to the second node N2 is less than the short-circuit current threshold. The voltage difference across the eighth resistor R8 is small, therefore the target voltage Vtar output by the first operational amplifier AMP1 is lower than the reference voltage Vref. At this time, the voltage of the third node N3 is lower than the reference voltage Vref, so the second operational amplifier AMP2 outputs a second level. In this situation, the fourth transistor M4 and the fifth transistor M5 remain on. Since the fourth node N4 is at the second level, the first transistor M1 is on, thereby pulling the voltage of the fifth node N5 down to the first level. In this situation, the second transistor M2 is off, thus causing the third transistor M3 to be off. Therefore, the latch circuit 240 does not affect the voltage of the third node N3.

[0048] exist Figure 1When the interface chip IC1 is shorted to the input voltage V1, the target current flowing from the first node N1 to the second node N2 exceeds the short-circuit current threshold. The voltage difference across the eighth resistor R8 increases, and the target voltage Vtar output by the first operational amplifier AMP1 is higher than the reference voltage Vref. At this time, the voltage of the third node N3 is higher than the reference voltage Vref, so the second operational amplifier AMP2 outputs the first level. In this case, the fourth transistor M4 and the fifth transistor M5 are turned off, and the target current becomes zero. Since the fourth node N4 is at the first level, the first transistor M1 is turned off, and the power supply voltage pulls the voltage of the fifth node N5 up to the second level via the second resistor R2. The second transistor M2 turns on, thereby pulling the voltage of the sixth node N6 down to the first level. Thus, the third transistor M3 turns on, thereby pulling the voltage of the third node N3 up to the second level. In this way, the latch circuit 240 maintains the voltage of the third node N3 above the reference voltage Vref. Therefore, the second operational amplifier AMP2 can stably output the first level, thereby keeping the fourth transistor M4 and the fifth transistor M5 off, and the target current remains zero.

[0049] Figure 5 Another schematic circuit diagram of a short-circuit protection circuit 200 according to an embodiment of the present disclosure is shown. Figure 4 In addition to the latch circuit 240, a power supply circuit is also included. The power supply circuit is configured to provide power voltage to the pull-up circuit 242 and the second control circuit 244.

[0050] In summary, the short-circuit protection circuit according to embodiments of this disclosure can disconnect the circuit in the event of a short circuit, thereby protecting the safety of other components in the circuit. Furthermore, the short-circuit protection circuit according to embodiments of this disclosure can maintain the open-circuit state of the circuit through a latching circuit, thereby preventing the circuit state from oscillating back and forth between short circuit and open circuit. The short-circuit protection circuit according to embodiments of this disclosure has low hardware cost and occupies a small area.

[0051] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or pervasive.

[0052] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with at least one other aspect. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0053] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A short-circuit protection circuit (200), comprising: A current detection circuit (210) is configured to generate a target voltage (Vtar) based on a target current flowing from a first node (N1) to a second node (N2) and to provide the target voltage (Vtar) to a third node (N3), wherein the target voltage (Vtar) is higher than a reference voltage (Vref) if the target current is greater than a short-circuit current threshold. A comparator circuit (220) is configured to output a first level via a fourth node (N4) when the voltage at the third node (N3) is higher than the reference voltage (Vref); A switching circuit (230) is configured to disconnect the connection between the first node (N1) and the second node (N2) when the fourth node (N4) is at the first level; as well as A latch circuit (240) is configured to maintain the voltage of the third node (N3) above the reference voltage (Vref) when the fourth node (N4) is at the first level.

2. The short-circuit protection circuit (200) according to claim 1, wherein when the target current is less than the short-circuit current threshold, the target voltage (Vtar) is lower than the reference voltage (Vref), the comparator circuit (220) is further configured to output a second level via the fourth node (N4) when the voltage of the third node (N3) is lower than the reference voltage (Vref), and the switch circuit (230) is further configured to connect the first node (N1) and the second node (N2) when the fourth node (N4) is at the second level.

3. The short-circuit protection circuit (200) according to claim 2, wherein the latching circuit (240) comprises: A pull-down circuit (241) is configured to pull down the voltage of the fifth node (N5) to the first level when the fourth node (N4) is at the second level; A pull-up circuit (242) is configured to pull up the voltage of the fifth node (N5) to the second level when the fourth node (N4) is at the first level; A first control circuit (243) is configured to pull down the voltage of the sixth node (N6) to the first level when the voltage of the fifth node (N5) is at the second level; A second control circuit (244) is configured to pull up the voltage of the third node (N3) to the second level when the voltage of the sixth node (N6) is at the first level, and to stop operating under other conditions, wherein the second level is higher than the reference voltage (Vref).

4. The short-circuit protection circuit (200) according to claim 3, wherein the pull-down circuit (241) comprises: The first resistor (R1) and the first transistor (M1), The first end of the first resistor (R1) is coupled to the fourth node (N4), and the second end of the first resistor (R1) is coupled to the second voltage terminal (V2). The control electrode of the first transistor (M1) is coupled to the first terminal of the first resistor (R1), the first electrode of the first transistor (M1) is coupled to the second voltage terminal (V2), and the second electrode of the first transistor (M1) is coupled to the fifth node (N5).

5. The short-circuit protection circuit (200) according to claim 3, wherein the pull-up circuit (242) comprises: The second resistor (R2), The first end of the second resistor (R2) is coupled to the power supply voltage terminal (Vcc), and the second end of the second resistor (R2) is coupled to the fifth node (N5).

6. The short-circuit protection circuit (200) according to claim 3, wherein the first control circuit (243) comprises: The third resistor (R3) and the second transistor (M2), The first end of the third resistor (R3) is coupled to the fifth node (N5), and the second end of the third resistor (R3) is coupled to the second voltage terminal (V2). The control electrode of the second transistor (M2) is coupled to the fifth node (N5), the first electrode of the second transistor (M2) is coupled to the second voltage terminal (V2), and the second electrode of the second transistor (M2) is coupled to the sixth node (N6).

7. The short-circuit protection circuit (200) according to claim 3, wherein the second control circuit (244) comprises: The fourth resistor (R4), the fifth resistor (R5), the sixth resistor (R6), the seventh resistor (R7), and the third transistor (M3) The first end of the fourth resistor (R4) is coupled to the power supply voltage terminal (Vcc), and the second end of the fourth resistor (R4) is coupled to the sixth node (N6). The first end of the fifth resistor (R5) is coupled to the sixth node (N6), and the second end of the fifth resistor (R5) is coupled to the control electrode of the third transistor (M3); The first end of the sixth resistor (R6) is coupled to the power supply voltage terminal (Vcc), and the second end of the sixth resistor (R6) is coupled to the first terminal of the third transistor (M3). The first end of the seventh resistor (R7) is coupled to the second terminal of the third transistor (M3) and the third node (N3), and the second end of the seventh resistor (R7) is coupled to the second voltage terminal (V2).

8. The short-circuit protection circuit (200) according to claim 3, wherein the latching circuit (240) further comprises: A power supply circuit (245) is configured to provide a power supply voltage to the pull-up circuit (242) and the second control circuit (244).

9. The short-circuit protection circuit (200) according to claim 1 or 2, wherein the switching circuit (230) comprises: The fourth transistor (M4) and the fifth transistor (M5), The control electrode of the fourth transistor (M4) is coupled to the fourth node (N4), the first electrode of the fourth transistor (M4) is coupled to the first electrode of the fifth transistor (M5), and the second electrode of the fourth transistor (M4) is coupled to the input terminal of the current detection circuit (210). The control electrode of the fifth transistor (M5) is coupled to the fourth node (N4), and the second electrode of the fifth transistor (M5) is coupled to the first node (N1).

10. The short-circuit protection circuit (200) according to claim 9, wherein the current detection circuit (210) comprises: The eighth resistor (R8) and the first operational amplifier (AMP1), The first end of the eighth resistor (R8) is coupled to the second terminal of the fourth transistor (M4), and the second end of the eighth resistor (R8) is coupled to the second node (N2). The first input terminal of the first operational amplifier (AMP1) is coupled to the first terminal of the eighth resistor (R8), the second input terminal of the first operational amplifier (AMP1) is coupled to the second terminal of the eighth resistor (R8), and the output terminal of the first operational amplifier (AMP1) is coupled to the third node (N3).

11. The short-circuit protection circuit (200) according to claim 1 or 2, wherein the comparator circuit (220) comprises: The second operational amplifier (AMP2), The reference voltage (Vref) is provided at the first input terminal of the second operational amplifier (AMP2), the second input terminal of the second operational amplifier (AMP2) is coupled to the third node (N3), and the output terminal of the second operational amplifier (AMP2) is coupled to the fourth node (N4).

12. A controller, comprising: The short-circuit protection circuit (200) according to any one of claims 1 to 11, wherein the first node (N1) is coupled to the ground terminal of the interface circuit in the controller, and the second node (N2) is coupled to the external ground terminal.

13. A vehicle (10), comprising: The controller according to claim 12.

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