Multi-phase controller, voltage regulator module, and method of operating multi-phase controller for voltage regulator module

Abstract

A multi-phase controller, a voltage regulator module, and a method of operating a multi-phase controller for a voltage regulator module are disclosed. The multi-phase controller includes a current mode adjustment circuit and a pulse distributor configured to: distribute a first set of pulses to a first power stage and a second set of pulses to a second power stage; and selectively enabling or disabling the second set of pulses to the second power stage based on a load condition. The multiphase controller also includes a current sense circuit coupled to receive a plurality of current monitoring signals from a plurality of power stages and configured to: provide a summing signal to the current mode adjustment circuit based on the plurality of current monitoring signals; a second current monitoring signal from the second power stage is replaced with a first current monitoring signal from the first power stage during a replacement period after recovery of the second set of pulses to the second power stage.

Description

Cross-references to related applications

[0001] This application claims the benefit of Provisional Patent Application No. 63 / 717,600, filed on 7 November 2024, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates in general to multiphase voltage regulator modules, and more particularly to a system and method for facilitating entry into and exit from ultralight load modes of multiphase voltage regulator modules. Background Technology

[0003] In the field of electronics, voltage regulator modules are used to supply power to processors included in computing devices such as desktop computers, laptops, notebooks, tablets, or smartphones. In recent years, government agencies around the world have developed and will continue to develop stringent rules and regulations regarding the power consumption of such devices. For example, according to Commission Regulation (Europe) 617 / 2013, desktop and notebook computers must have a low-power state that can be automatically activated (such as entering sleep mode after fifteen minutes of inactivity) or immediately activated by the end user. When connected to a mains line, power consumption in the low-power state should not exceed 0.5W.

[0004] Due to these rules and regulations regarding the power consumption of computing devices, system designers of such devices may require voltage regulator modules to accommodate various sleep and low-power states. Furthermore, the voltage regulator module itself must remain efficient and consume very little power during light-load conditions. The inventors of various embodiments of this disclosure have recognized that various components within the voltage regulator module can be disabled during light-load conditions to reduce the power consumption of the voltage regulator module itself during these conditions. The inventors of various embodiments of this disclosure have also recognized that disabling certain components within the voltage regulator module when exiting light-load or ultra-light-load conditions can lead to response time and / or stability issues. Embodiments of this disclosure address one or more of these challenges. Summary of the Invention

[0005] The example in this article implements a multiphase controller for a voltage regulator module that facilitates quick and stable exit from light load operation.

[0006] According to one embodiment, a multiphase controller includes: a current-mode regulation circuit configured to generate a PWM control signal based on load conditions of a voltage regulator module; a pulse distributor coupled to receive the PWM control signal from the current-mode regulation circuit and configured to: (i) distribute pulses to a plurality of power levels, including distributing a first set of pulses to a first power level and a second set of pulses to a second power level; and (ii) selectively enable or disable the second set of pulses to the second power level based on the load conditions of the voltage regulator module; and a current sensing circuit coupled to receive a plurality of current monitoring signals from the plurality of power levels and configured to: (i) provide a summation signal to the current-mode regulation circuit based on the plurality of current monitoring signals; and (ii) replace the second current monitoring signal from the second power level with the first current monitoring signal from the first power level during a replacement period after a pulse disable period and after the recovery of the second set of pulses to the second power level. In some embodiments, the current sensing circuit is configured to resume using the second current monitoring signal to generate the summation signal after the replacement period is completed. In the same or different embodiments, the replacement period is 2.5 seconds. Up to 6.0 Within the range. In the same or different embodiments, this replacement period is programmable. In the same or different embodiments, the current sensing circuit is coupled to the corresponding N Power level receiver N A current monitoring signal, and in which the NThe number of current sensing signals is in the range of 2 to 48. In the same or different embodiments, the current sensing circuit includes: a summing circuit configured to generate a summing signal based on a plurality of channel signals corresponding to the plurality of current monitoring signals; a first channel configured to provide a first channel signal to the summing circuit based on the first current monitoring signal from the first power level; a second channel configured to provide a second channel signal to the summing circuit, when enabled, based on a selection of the first current monitoring signal from the first power level and the second current monitoring signal from the second power level; and a redirection controller configured to: (i) disable the second channel in response to the cessation of the second set of pulses to the second power level; (ii) enable the second channel in response to the recovery of the second set of pulses to the second power level; (iii) instruct the second channel to select the first current monitoring signal during a replacement period occurring after the recovery of the second set of pulses; and (iv) instruct the second channel to select the second current monitoring signal after the expiration of the replacement period. In the same or different embodiments, the redirection controller is configured to instruct the second channel to select the first current monitoring signal after a waiting period following the cessation of the second set of pulses to the second power level. In the same or different embodiments, the first channel of the current sensing circuit includes: a first resistor configured to convert the first current monitoring signal into a first voltage signal; and a first transconductance amplifier configured to provide the first channel signal to the summing circuit based on the first voltage signal; and the second channel of the current sensing circuit includes: a second resistor configured to convert the second current monitoring signal into a second voltage signal; a multiplexer coupled to transmit one of the first voltage signal and the second voltage signal in response to the redirection controller; and a second transconductance amplifier configured to provide the second channel signal to the summing circuit based on the multiplexer output.

[0007] According to another embodiment, a voltage regulator module includes multiple power stages, each power stage including: a high-side switching transistor; a low-side switching transistor; and a current monitoring circuit configured to provide a current monitoring signal representing the total current through the high-side switching transistor and the low-side switching transistor. The voltage regulation module further includes a multiphase controller comprising: a current-mode regulation circuit configured to generate a PWM control signal based on load conditions of the voltage regulator module; a pulse distributor coupled to receive the PWM control signal from the current-mode regulation circuit and configured to: (i) distribute pulses to multiple power levels, including distributing a first set of pulses to a first power level and a second set of pulses to a second power level; and (ii) selectively enable or disable the second set of pulses to the second power level based on the load conditions of the voltage regulator module; and a current sensing circuit coupled to receive multiple current monitoring signals from the multiple power levels and configured to: (i) provide a summation signal to the current-mode regulation circuit based on the multiple current monitoring signals; and (ii) replace the second current monitoring signal from the second power level with the first current monitoring signal from the first power level during a replacement period after the pulse disabling period and after the recovery of the second set of pulses to the second power level. In some embodiments, the current sensing circuit is configured to resume using the second current monitoring signal to generate the summation signal after the replacement period is completed. In the same or different embodiments, the replacement period is 2.5 seconds. Up to 6.0 Within the range. In the same or different embodiments, this replacement period is programmable. In the same or different embodiments, the current sensing circuit is coupled to the corresponding N Power level receiver N A current monitoring signal, and in which the NThe number of current sensing signals is in the range of 2 to 48. In the same or different embodiments, the current sensing circuit includes: a summing circuit configured to generate a summing signal based on a plurality of channel signals corresponding to the plurality of current monitoring signals; a first channel configured to provide a first channel signal to the summing circuit based on the first current monitoring signal from the first power level; a second channel configured to provide a second channel signal to the summing circuit, when enabled, based on a selection of the first current monitoring signal from the first power level and the second current monitoring signal from the second power level; and a redirection controller configured to: (i) disable the second channel in response to the cessation of the second set of pulses to the second power level; (ii) enable the second channel in response to the recovery of the second set of pulses to the second power level; (iii) instruct the second channel to select the first current monitoring signal during a replacement period occurring after the recovery of the second set of pulses; and (iv) instruct the second channel to select the second current monitoring signal after the expiration of the replacement period. In the same or different embodiments, the redirection controller is configured to instruct the second channel to select the first current monitoring signal after a waiting period following the cessation of the second set of pulses to the second power level. In the same or different embodiments, the current monitoring circuit of the second power level is configured to enter a sleep state in response to the second power level not receiving the second set of pulses within a delay period, and to instruct the second channel to select the first current monitoring signal during a waiting period shorter than the delay period during which the current monitoring circuit enters the sleep state. In the same or different embodiments, the first channel of the current sensing circuit includes: a first resistor configured to convert the first current monitoring signal into a first voltage signal; and a first transconductance amplifier configured to provide the first channel signal to the summing circuit based on the first voltage signal; and the second channel of the current sensing circuit includes: a second resistor configured to convert the second current monitoring signal into a second voltage signal; a multiplexer coupled to transmit one of the first voltage signal and the second voltage signal in response to the redirection controller; and a second transconductance amplifier configured to provide the second channel signal to the summing circuit based on the output of the multiplexer.

[0008] Another embodiment provides a method for controlling a multiphase controller, wherein the method includes: (i) generating a PWM control signal using a current-mode regulation circuit based on load conditions of the voltage regulator module; (ii) distributing pulses to a plurality of power levels based on the PWM control signal, including distributing a first set of pulses to a first power level and a second set of pulses to a second power level; (iii) selectively enabling and disabling the second set of pulses to the second power level based on the load conditions of the voltage regulator module; (iv) receiving a plurality of current monitoring signals from the plurality of power levels; (v) generating a summation signal based on the plurality of current monitoring signals; (vi) generating the summation signal during a replacement period by using a first current monitoring signal from the first power level instead of a second current monitoring signal from the second power level in response to the recovery of the second set of pulses from a disabled period; and (vii) providing the summation signal to the current-mode regulation circuit for regulation of the voltage regulator module. In some embodiments, the method further includes resuming the generation of the summation signal using the second current monitoring signal after the replacement period following the recovery of the second set of pulses to the second power level. In the same or different embodiments, the replacement period is 2.5. Up to 6.0 Within the range. Attached Figure Description

[0009] A more complete understanding of this embodiment can be obtained by referring to the following description taken in conjunction with the accompanying drawings, in which similar reference numerals indicate similar features.

[0010] Figure 1 A top-level schematic diagram of a voltage regulator module (VRM) according to an embodiment of the present disclosure is illustrated.

[0011] Figure 2 A schematic diagram of a power stage according to an embodiment of the present disclosure is shown.

[0012] Figure 3 A schematic diagram of a multiphase controller according to an embodiment of the present disclosure is illustrated.

[0013] Figure 4 A waveform graph of a voltage regulator module according to an embodiment of the present disclosure is shown.

[0014] Figure 5 A schematic diagram of a current sensing circuit according to an embodiment of the present disclosure is shown.

[0015] Figure 6 A power state graph of an example system supported by a voltage regulator module according to an embodiment of the present disclosure is illustrated.

[0016] Figure 7 The operating steps for a voltage regulator module according to an embodiment of this disclosure are illustrated.

[0017] Figure 8 A method for operating a multiphase controller according to an embodiment of the present disclosure is illustrated. Detailed Implementation

[0018] Details of one or more embodiments are set forth in the following description and accompanying drawings. Other features will be apparent from the description, the drawings, and the claims. The disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended to be an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0019] Various terms are used to refer to specific system components. Different companies may use different names to refer to a component, and this disclosure is not intended to distinguish between components with different names but the same form and function. In the following discussion and in the claims, the terms "comprising" and "including" are used in an open form, and therefore, these terms should be interpreted as meaning "including but not limited to". Furthermore, the terms "coupled" or "coupled to" are intended to cover indirect or direct connections. Thus, if a first device is coupled to or coupled to a second device, the connection between the first device and the second device can be achieved through a direct connection or through an indirect connection via other devices and connectors.

[0020] Furthermore, although terms such as “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. Terms such as “first” and “second” may be used only to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element, without departing from the scope of this disclosure. Moreover, the identification of a “first” element does not necessarily require the presence of a “second” element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated entries listed.

[0021] Figure 1 A top-level schematic diagram of a voltage regulator module (VRM) 100 according to an embodiment of the present disclosure is illustrated. The VRM 100 can be implemented in any suitable manner according to the operation described in this disclosure. Figure 1As shown, VRM 100 may include a multiphase controller 110 and multiple buck converter stages 120a to 120n. Each of the multiple buck converter stages 120a to 120n converts an input voltage VIN into an output voltage VOUT to supply, for example, to the core of a processor in a computing system. The multiphase controller 110 may then include a positive sensing input VSP and a negative sensing input VSN, which are coupled to receive and thereby sense the output voltages (VCC and VSS) directly at the rails of the core. The multiphase controller 110 may also include multiple current monitor (IMON) inputs to receive current information from each of the buck converter stages 120a to 120n. The multiphase controller 110 may control the pulse width and / or frequency of the PWM signals supplied to the multiple power stages 121a to 121n to drive VOUT to a desired voltage level under a given load current drawn by the processor.

[0022] For the sake of simplicity, Figure 1 A multiphase controller 110 is illustrated, having various inputs and outputs most directly related to the functionality and improvements of this disclosure. However, the multiphase controller 110 and the plurality of power stages 121a to 121n may include additional inputs and outputs, for example, to communicate with each other and with a processor. For example, the multiphase controller 110 may include additional inputs, such as inputs for receiving communications via I2C or SMBus to request telemetry information. As another example, the multiphase controller 110 may include additional inputs to receive temperature information from one or more of the plurality of power stages 121a to 121n.

[0023] Each of the buck converter stages 120A to 120N may include a corresponding power stage from among multiple power stages 121A to 121N. See below for reference. Figure 2 As described in further detail, each of the multiple power stages 120a to 120n may include a high-side switching transistor coupled between the power input VIN and the switching node SW, and a low-side switching transistor coupled between the switching node SW and ground GND. The high-side and low-side switching transistors can be turned on and off according to corresponding PWM signals from the multiphase controller 110 (alternating with respect to each other). Figure 1As shown, buck converter stages 120a to 120n may each include an LC filter coupled to the switching node SW of the corresponding power stage. For example, the first buck converter stage 120a may include a first power stage 121a coupled to an inductor 131a and an output capacitor 132a. A bootstrap capacitor 134a may be coupled between the switching node SW and the bootstrap node BOOT of the first power stage 121a to power the high-side driver included therein. The second buck converter stage 120b may similarly include a second power stage 121b, an inductor 131b, an output capacitor 132b, and a bootstrap capacitor 134b. Additionally, the second... N The 120n buck converter stage can similarly include the first... N The power stage is 121n, the inductor is 131n, the output capacitor is 132n, and the bootstrap capacitor is 134n.

[0024] Despite VRM 100 in Figure 1 The VRM 100 is illustrated as having three buck converter stages, but it can include any suitable for a given application. N A buck converter stage. For example, VRM 100 may include 2, 4, 8, 16, 24, 48 or more buck converter stages connected in parallel. The multiphase controller 110 can then be configured to provide a PWM signal for each of the respective buck converter stages. In some implementations, such as Figure 1 As shown, each buck converter stage can be connected in parallel to provide power to the same voltage rail (such as VOUT). In other embodiments, different groups of one or more buck converter stages can be connected in parallel to provide power to multiple different power rails.

[0025] Figure 2 A schematic diagram of a power stage 121 according to an embodiment of the present disclosure is illustrated. The power stage 121 may be implemented in any suitable manner according to the operation described in this disclosure. Figure 2 The schematic diagram of power stage 121 shown above can be interpreted as described in the reference above. Figure 1 Example schematic implementation of each of the multiple power levels 121a to 121n described.

[0026] like Figure 2As shown, power stage 121 may include a PWM controller 210, a high-side driver 221, a low-side driver 222, a high-side switching transistor 231, and a low-side switching transistor 232. The PWM controller 210 may receive a PWM signal from the multiphase controller 110 via the PWM input of power stage 121. In response to the PWM signal, the PWM controller 210 may control the high-side driver 221 and the low-side driver 222 to turn the high-side switching transistor 231 and the low-side switching transistor 232 on and off, respectively. For example, in response to a logic high PWM signal, the PWM controller 210 may force the high-side switching transistor 231 to be on and force the low-side switching transistor 232 to be off. Conversely, in response to a logic low PWM signal, the PWM controller 210 may force the high-side switching transistor 231 to be off and force the low-side switching transistor 232 to be on. Additionally, the PWM controller 210 may detect a high-impedance state (Hi-Z state) at the PWM input. In response to the Hi-Z state forced by the multiphase controller 110 at the PWM input of power stage 121, the PWM controller 210 can force the high-side switching transistor 231 to the off state, and can also force the low-side switching transistor 232 to the off state after any recirculation current through the low-side switching transistor 232 reaches zero during the previous on state of the low-side switching transistor 232.

[0027] In some implementations, the high-side switching transistor 231 and the low-side switching transistor 232 can each be implemented as an n-type metal-oxide-semiconductor field-effect transistor (referred to as an n-type MOSFET or NMOS transistor). To drive the high-side switching transistor 231 in the on-state, the high-side driver 221 can drive the gate of the high-side switching transistor 231 with a voltage greater than VIN. (Refer to the above...) Figure 1 As described, the bootstrap capacitor can be coupled between the switching node SW and the bootstrap node BOOT of each power stage 121. And as... Figure 2 As shown, power stage 121 may include diode 240 having an anode coupled to VIN and a cathode coupled to bootstrap node BOOT. Therefore, the bootstrap capacitor and diode 240 can form a charge pump that provides a voltage greater than VIN in response to the voltage at node SW switching between GND and VIN. This voltage greater than VIN can then be used to power high-side driver 221, allowing high-side switching transistor 231 to be driven with a gate voltage greater than VIN when it is in the ON state.

[0028] Power stage 121 may also include a high-side current sensor 251 and a low-side current sensor 252. The high-side current sensor 251 and the low-side current sensor 252 can sense the corresponding currents through high-side switching transistor 231 and low-side switching transistor 232 without adding resistive sensing elements to the current path of the buck converter stage in which power stage 121 is implemented. For example, in some embodiments, high-side current sensor 251 may be implemented by a high-side sensing FET integrated with high-side switching transistor 231. Similarly, low-side current sensor 252 may be implemented by a low-side sensing FET integrated with low-side switching transistor 232. PWM controller 210 may use the current sensing information to control the on and / or off states of high-side switching transistor 231 and low-side switching transistor 232. For example, when the PWM input is in the Hi-Z state as described above, the PWM controller 210 can force the low-side switching transistor 232 into the on state until the low-side recirculation current reaches zero. At this time, the PWM controller 210 can force the low-side switching transistor 232 and the high-side switching transistor 231 into the off state together.

[0029] Power stage 121 may also include current monitoring circuitry 250 configured to provide a current monitoring signal IMON representing the total current through high-side switching transistor 231 and low-side switching transistor 232. For example, current monitoring circuitry 250 may aggregate high-side current sensing and low-side current sensing to generate current monitoring signal IMON representing the total current through both high-side switching transistor 231 and low-side switching transistor 232 (and thus representing the output current of the corresponding buck converter stage in which power stage 121 is implemented). In some embodiments, current monitoring signal IMON may be, for example, a value of 5 amperes per ampere measured by high-side switching transistor 231 and low-side switching transistor 232. The level of provision. For example... Figure 1 As shown, each of the multiple power stages 121a to 121n can provide a corresponding current monitoring signal IMON to the multiphase controller 110. And as referenced below... Figure 3 As described, the multiphase controller 110 can detect the total load current by using the sum of the corresponding current monitoring signals (IMON1, IMON2 to IMONn) and control the corresponding PWM signals of the multiple power stages 121a to 121n accordingly.

[0030] Figure 3 A schematic diagram of a multiphase controller 110 according to an embodiment of the present disclosure is illustrated. The multiphase controller 110 can be implemented in any suitable manner according to the operation described in this disclosure. Figure 3 The diagram shown above can be interpreted as a reference. Figure 1 The example schematic implementation of the described multiphase controller 110 is shown below.

[0031] like Figure 3 As shown, the multiphase controller 110 may include a current sensing circuit 310, a current mode conditioning circuit 320, and a pulse distributor 330. The current sensing circuit 310 may be coupled to multiple power stages 121a to 121n ( Figure 1 (As shown) it receives multiple current monitoring signals (IMON1, IMON2 to IMONn). See below for reference. Figure 4 In further detail, the current sensing circuit 310 can be configured to provide a summation signal IMON_SUM to the current mode conditioning circuit 320 based on multiple current monitoring signals (IMON1, IMON2 to IMONn).

[0032] The current-mode regulation circuit 320 can be configured to generate a PWM control signal PWM_CTL based on the load conditions of VRM 100. Specifically, the current-mode regulation circuit 320 can implement a current-mode feedback loop to control the pulse width and / or frequency of the PWM signal delivered to the respective power stages 121a to 121n based on both voltage and current feedback. In some embodiments, the current-mode regulation circuit 320 may include a feedback circuit 322, a reference circuit 323, a compensation circuit 324, a ramp generator 326, and a PWM comparator 328. The reference circuit 323 can provide a reference voltage representing the desired output voltage of VRM 100. The feedback circuit 322 can compare the differential output voltage (such as that sensed directly at the processor via VSP and VSN) with the reference voltage to generate an error signal ERR, which is scaled in part based on a summation signal IMON_SUM representing the sum of the currents through each respective buck converter stage 120a to 120n (and thus the load current drawn by the processor).

[0033] like Figure 3 As shown, the current-mode regulation circuit 320 may include a compensation circuit 324 to shape the frequency response of the feedback circuit 322, thereby stabilizing the current-mode control loop implemented by the current-mode regulation circuit 320. As described in further detail below, the various embodiments included herein can be used to maintain current-mode control (rather than reverting to voltage-mode control) even under extreme conditions, such as removal from ultra-light load conditions. Accordingly, the compensation circuit 324 can be implemented with a simple proportional-integral (PI) compensation scheme rather than a more complex proportional-integral-derivative (PID) compensation scheme, which might be required to maintain loop stability if the multiphase controller 110 reverts to voltage-mode control under certain conditions, such as removal from ultra-light load.

[0034] PWM comparator 328 compares a compensation error signal with a ramp signal from ramp generator 326. Based on this comparison, the PWM comparator generates a PWM control signal PWM_CTL for at least partial control of the pulse width and / or frequency of pulses to be distributed by pulse distributor 330 to the multiple power stages 121a to 121n. Ramp generator 326 can vary the amplitude and / or frequency of the ramp signal supplied to PWM comparator 328 based on several factors to change the PWM_CTL signal under various load conditions. These factors include, but are not limited to, the input voltage VIN, the desired output voltage VOUT, and the number of phases of VRM 100 active at a given time (the number of buck converter stages).

[0035] like Figure 3 As shown, pulse distributor 330 can be coupled to receive a PWM control signal PWM_CTL from current-mode regulation circuit 320. Pulse distributor 330 can be configured to distribute pulses to multiple power levels 121a to 121n, including, for example, distributing a first set of pulses to a first power level 121a (via PWM1), distributing a second set of pulses to a second power level 121b (via PWM2), and in some embodiments, distributing a third set of pulses to a second power level 121n. N Group pulses are assigned to the first N Power stage 121n (via PWMn).

[0036] Figure 4 A graph illustrating an example waveform of the VRM 100 according to an embodiment of this disclosure is provided. Specifically, Figure 4 A graph illustrating an example implementation of VRM 100 is provided, in which... N =3, meaning the VRM 100 includes three buck converter stages driven by three PWM signals (PWM1, PWM2 and PWMn).

[0037] The three PWM signals PWM1, PWM2, and PWMn can be interleaved relative to each other during normal load conditions, such as, for example, in Figure 4 As shown after time t4. Compared to similar single-phase buck converters, the interleaving of PWM pulses across different buck converter stages allows the VRM 100 to deliver a more stable output voltage VOUT to the processor load with less ripple under medium to heavy load currents. However, during light load conditions that may cause less ripple, the switching of PWM1, PWM2, and PWMn can be controlled to improve efficiency.

[0038] During periods of light load (e.g., when the processor is in sleep mode), one or more phases of the VRM 100 can be disabled to reduce the current consumption of the VRM 100 itself, thereby improving light load efficiency. For example, as Figure 4As shown, PWMn can be placed in the Hi-Z state at time t1 to disable the first... N Switching of power stage 121n. For the purposes of this disclosure, Hi-Z state is available. Figure 4 This is represented as the intermediate level between the logic high and logic low levels of the pulses shown for PWM1, PWM2, and PWMn. (See reference above.) Figure 2 As described, placing PWMn in the Hi-Z state forces power stage 121n to turn both its high-side and low-side switching transistors off accordingly. By disabling switching, power that might otherwise be consumed to charge and discharge the gates of these transistors is saved. Continuing to Figure 4 At time t2, PWM2 can also be placed in the Hi-Z state to disable the switching of the second power stage 121b, further saving power and improving light-load efficiency. Subsequently, at time t3, PWM1 can continue to switch low and high, but at a lower frequency. The continued switching of the first power stage 121a driven by PWM1 ensures the continued operation of the regulation loop of VRM 100 and ensures the operation of the bootstrap capacitor 134a. Figure 1 The transistor (shown) is refreshed and kept fully charged to power the high-side driver 221 within the first power stage 121a. Furthermore, the lower frequency of PWM1 reduces switching losses associated with turning off and on the high-side and low-side switching transistors of the first power stage 121a. Therefore, the lower frequency of PWM1 between time t3 and time t4 further improves the light-load efficiency of VRM 100 while still maintaining regulation of VOUT.

[0039] In addition to the power savings described above, when used in the second power stage 121b to the... N When the PWM pulse of power stage 121n stops, further power savings can be achieved by disabling certain circuits within these corresponding power stages. (See above reference.) Figure 3 As described, the pulse distributor 330 can be configured to distribute pulses to a plurality of power levels 121a to 121n, including, for example, distributing a first set of pulses to a first power level 121a (via PWM1), distributing a second set of pulses to a second power level 121b (via PWM2), and in some embodiments, distributing a third set of pulses to a second power level 121n. N Group pulses are assigned to the first N Power stage 121n (via PWMn). The second power stage 121b can be configured such that the current monitoring circuit 250 of the second power stage 121b enters a sleep state in response to the second power stage 121b not receiving a second set of pulses during a delay period. Similarly, the second... N Power stage 121n can be configured such that the first N The current monitoring circuit 250 of the power stage 121n responds to the firstN Power stage 121n did not receive the first signal during the delay period. N The system enters a sleep state by triggering a pulse. In some implementations, the delay period of the current monitoring circuit 250 can be, for example, 50 seconds. .

[0040] When exiting light load conditions, the previously disabled phase recovery switch of the VRM 100 is activated. For example, as... Figure 4 As shown, the load can be increased at time t4, after which the second set of pulses (via PWM2) and the... N The first pulse group (via PMWn) can be recovered. Upon recovery of the second pulse group, the current monitoring circuit 250 within the second power stage 121b can be woken up and resume normal operation. Similarly, upon recovery of the second pulse group... N During the group pulse, the first N The current monitoring circuit 250 within the power stage 121n can be woken up and resume normal operation. In some embodiments, the wake-up time of the current monitoring circuit 250 may be, for example, 2.5 seconds. Compared to 6.0 Between. In some such implementations, the wake-up time of the current monitoring circuit 250 may be, for example, 2.5 seconds. Compared to 4.0 Between. During this wake-up time, the second current monitoring signal (IMON2) and the first N The current monitoring signal (IMON3) may not accurately reflect the current in the second power stage 121b and the second... N The current flowing in the 121n power stage. See below for reference. Figure 5 As described, the current sensing circuit 310 can be configured to replace the invalid current monitoring information during the wake-up time in order to maintain stable current mode regulation when the VRM 100 exits light load conditions.

[0041] Figure 5 A schematic diagram of a current sensing circuit 310 according to an embodiment of the present disclosure is illustrated. The current sensing circuit 310 may be implemented in any suitable manner according to the operation described in the present disclosure. Figure 5 The diagram shown above can be interpreted as a reference. Figure 3 The described current sensing circuit 310 is illustrated in a specific example implementation. For example... Figure 5 As shown, the current sensing circuit 310 may include a redirection controller 402, a first channel 410, a second channel 420, and a third channel 420. N Channel 430 and summing circuit 440. Although illustrated with three channels, current sensing circuit 310 may include any suitable... N Each channel corresponds to a channel from N Power level NA current monitoring signal (IMON). For example, the current sensing circuit 310 can be coupled to a corresponding current monitoring signal. N Power level receiver N One current monitoring signal, among which N The number ranges from 2 to 48.

[0042] During normal load conditions, when each of the multiple power stages 121a to 121n is switching, the current sensing circuit 310 can sum various current monitoring signals (IMON1, IMON2, ..., IMONn) from the multiple power stages 121a to 121n to provide a summation signal representing the total load current to the current mode conditioning circuit 320. However, as described above, when VRM 100 is out of light load conditions and the second power stage 121b and the second power stage 121n switch over... N While the current monitoring circuit 250 of power stage 121n is still waking from sleep, the second current monitoring signal (IMON2) and the second current monitoring signal... N The current monitoring signal (IMON3) may not accurately reflect the current in the second power stage 121b and the second... N The current flowing in power stage 121n. In the absence of current from the second power stage 121b and the... N In the case of current monitoring information from power stage 121n, when the corresponding instance of the current monitoring circuit 250 in these power stages is woken up, the regulation loop can more closely resemble a voltage-mode regulation loop than the designed current-mode regulation. This voltage-mode operation would require a more complex compensation circuit 324 (e.g., PID compensation) than the compensation circuitry required for current-mode regulation. To save the cost of this more complex compensation scheme, the current sensing circuit 310 can be configured to replace the invalid current monitoring information during the wake-up time to maintain stable current-mode regulation when VRM 100 exits light load conditions.

[0043] As described in further detail below, the current sensing circuit 310 can replace the second current monitoring signal IMON2 from the second power stage 121b with the first current monitoring signal IMON1 from the first power stage 121a during the replacement period after the second set of pulses (via PWM2) resumes after the pulse disable period of PWM2. The current sensing circuit 310 can also be configured to resume using the second current monitoring signal IMON2 to generate the summation signal IMON_SUM after the replacement period of IMON2 is completed. Similarly, the current sensing circuit 310 can replace the second current monitoring signal IMON2 from the second power stage 121b during the replacement period after the pulse disable period of PWMn. N During the replacement period following the recovery of the pulse group (via PWMn), the first current monitoring signal IMON1 from the first power stage 121a is used instead of the signal from the second power stage 121a. N The first power stage 121n NThe current monitoring signal is IMONn. Furthermore, the current sensing circuit 310 can be configured to resume use after the replacement period of IMONn is completed. N The current monitoring signal IMONn is used to generate the summation signal IMON_SUM.

[0044] like Figure 5 As shown, the first channel 410 of the current sensing circuit 310 can be configured to provide a first channel signal I_CH1 (in the form of a current) to the summing circuit 440 based on a first current monitoring signal IMON1 from the first power stage 121a. In some embodiments, the first channel 410 of the current sensing circuit 310 may include a first resistor 411 and a first transconductance amplifier 412. The first resistor 411 may be coupled between the input of IMON1 and a voltage reference V_IMON_REF, and is therefore configured to convert the first current monitoring signal IMON (in the form of a current) into a first voltage signal. The first voltage signal may be applied across the input of the first transconductance amplifier 412, which may be configured to output the first channel signal I_CH1 based on the first voltage signal.

[0045] like Figure 5 As further shown, the second channel 420 can be configured, when enabled, to provide a second channel signal I_CH2 (in the form of a current) to the summing circuit 440 based on a selected one of a first current monitoring signal IMON1 from the first power stage 121a and a second current monitoring signal IMON2 from the second power stage 121b. For example, the second channel 420 of the current sensing circuit 310 may include a second resistor 421, a multiplexer 423, and a second transconductance amplifier 422. The second resistor 421 may be coupled between the IMON2 input and V_IMON_REF, and thus may be configured to convert the second current monitoring signal IMON2 (in the form of a current) into a second voltage signal. The multiplexer 423 may be coupled to transmit one of the first voltage signal (based on IMON1) and the second voltage signal (based on IMON2) in response to the redirection controller 402. Furthermore, the second transconductance amplifier 422 can be configured to provide the second channel signal I_CH2 to the summing circuit 440 based on the multiplexer output of the multiplexer 423.

[0046] In addition, the N Channel 430 can be configured to, when enabled, base its signal on a first current monitoring signal IMON1 from the first power stage 121a and a signal from the second power stage 121a. N The first power stage 121n N The selected one of the current monitoring signals IMONn is used to provide the first current to the summing circuit 440. NThe channel signal I_CHn (in the form of current). For example, the first current sensing circuit 310... N Channel 430 may include the first N Resistor 431, multiplexer 433 and the first N Transconductance amplifier 432. N Resistor 431 can be coupled between the IMONn input and V_IMON_REF, and can therefore be configured to... N The current monitoring signal IMONn (in the form of current) is converted into the first... N Voltage signal. Multiplexer 433 can be coupled to transmit a first voltage signal (based on IMON1) and a second voltage signal in response to redirection controller 402. N One of the voltage signals (based on IMONn). Furthermore, the... N Transconductance amplifier 432 can be configured to provide the first multiplexer output to summing circuit 440 based on multiplexer output 433. N Channel signal I_CHn.

[0047] The summing circuit 440 can be configured to generate a summation signal IMON_SUM based on multiple channel signals (ICH_1, ICH_2 to I_CHn) corresponding to multiple current monitoring signals (IMON1, IMON2, IMONn). In some embodiments, the summing circuit 440 can be implemented using a summing resistor 441, which is configured to receive each of the multiple channel signals (ICH_1, ICH_2 to I_CHn) in the form of current. Therefore, the summing resistor 441 can generate a voltage drop proportional to the sum of the multiple channel signals (ICH_1, ICH_2 to I_CHn). Accordingly, the summation signal IMON_SUM can thus be generated by the summing resistor 441 and passed to the current-mode conditioning circuit 320, such as... Figure 3 As shown.

[0048] Redirect controller 402 can be configured to enable and disable the second channel 420 to the third channel 420. N Channel 430, and the selection of multiplexers 423 and 433 respectively included therein. For example, redirection controller 402 may receive PWM information from pulse distributor 330, which indicates the state of each of PWM1, PWM2 to PWMn. Redirection controller 402 can then be configured to enable or disable the second channel 420 to the third channel 430. N Channel 430, and based on whether pulse distributor 330 actively, stopped, or resumed, provides pulses to the second power stage 121b (via PWM2) to the second power stage 121b. NPower stage 121n (via PWMn) controls the selection made by multiplexer 423 and multiplexer 433.

[0049] Return to reference Figure 4 The second set of pulses supplied to the second power stage 121b (via PWM2) may stop at time t2. The redirection controller 402 may be configured to disable the second channel 420 of the current sensing circuit 310 in response to the cessation of the second set of pulses to the second power stage 121b. For example, the redirection controller 402 may de-assert the Gm[2]_EN enable signal for the second transconductance amplifier 422 after a wait period following the cessation of the second set of pulses to the second power stage 121b at time t2 (via PWM2). When disabled, the power consumption of the second transconductance amplifier 422 may be reduced or eliminated. Accordingly, further power savings may be achieved by disabling the second transconductance amplifier 422 after the wait period following the cessation of the second set of pulses to the second power stage 121b at time t2 (via PWM2).

[0050] The redirection controller 402 can be further configured to instruct the second channel 420 to be enabled (or re-enabled) in response to the recovery of the second set of pulses (via PWM2) to the second power stage 121b. For example, as the load current increases and VRM 100 exits the light load condition, the second set of pulses (via PWM2) may recover after time t4. In response to the recovery of the second set of pulses (via PWM2) to the second power stage 121b, the redirection controller 402 may assert (or re-assert) the Gm[2]_EN enable signal for the second transconductance amplifier 422. Accordingly, the current sensing circuit 310 may include IMON2 (or replace IMON1 with IMON2 during the replacement period) when generating the summation signal IMON_SUM (via PWM2) to the second power stage 121b.

[0051] The redirection controller 402 can also instruct the second channel 420 to select the first current monitoring signal during a replacement period that occurs after the recovery of the second set of pulses to the second power stage 121b (via PWM2). For example, the redirection controller 402 can assert that the IMON2_REDIRECT signal instructs the multiplexer 423 to pass a first voltage signal (based on IMON1) to the second transconductance amplifier 422 at least during the replacement period after the recovery of the second set of pulses to the second power stage 121b (via PWM2). Figure 4As shown, the redirection controller 402 can be configured to instruct the second channel 420 to select the first current monitoring signal IMON1 after a waiting period following the cessation of the second set of pulses to the second power stage 121b. In some embodiments, the waiting period for instructing the second channel 420 to select the first current monitoring signal IMON1 may be shorter than the delay period during which the current monitoring circuit 250 of the second power stage 121b enters a sleep state. Accordingly, after the recovery of the second set of pulses to the second power stage 121b (via PWM2), at any time when the current monitoring circuit 250 begins to wake up, the second channel 420 may be ready to use the first current monitoring signal IMON1 instead of the second current monitoring signal IMON2.

[0052] Furthermore, the redirection controller 402 can instruct the second channel 420 to select the second current monitoring signal IMON2 after the replacement period expires. For example, after the replacement period expires, the redirection controller 402 can deassert the IMON2_REDIRECT signal to instruct the multiplexer 423 to pass the second voltage signal (based on IMON2) to the second transconductance amplifier 422. In some embodiments, the replacement period can be 2.5 seconds. Up to 6.0 Within the range. In some implementations, the replacement period can be 2.5. Up to 4.0 Within the range. This replacement period can be programmable, for example, in 2.5. Compared to 4.0 Between 0.5 For increments, or at 2.5 Compared to 6.0 Between 0.5 The replacement period can be programmed to correspond to the expected wake-up time of the current sensing circuit 250 in the second power stage 121b. Accordingly, when the current sensing circuit 250 wakes up and the second current sensing signal IMON2 is valid, the current sensing circuit 310 can resume using the second current sensing signal IMON2 to generate the summation signal IMON_SUM.

[0053] like Figure 5 As shown, the first N Channel 430 can be configured in a similar manner to the second channel 420. The redirection controller 402 can accordingly assert and deassert the Gm[n]_EN enable signal and the IMONn_REDIRECT signal in response to transmission to the second channel 420 in a manner similar to that described above for the second channel 420. N The first power stage 121n N The stop and resume of the group pulse (via PWMn) control the first N Channel 430. Second channel 420 and the first...N The other channels between channels 430 can also operate in a similar manner to that described above for the second channel 420.

[0054] Figure 6 A power state graph of an example system supported by VRM 100 according to an embodiment of this disclosure is illustrated.

[0055] In state 1, all blocks of VRM 100 can be active. For example, all blocks within the multiphase controller 110 (including the second transconductance amplifier 422 and the...) N The transconductance amplifier 432 and all blocks within the multiple power stages 121a to 121n (including a corresponding instance of the current monitoring circuit 250) can be enabled and activated.

[0056] In state 2, the first N The pulse group (via PWMn) can be stopped. For example, as Figure 4 As shown at time t1, PWMn can be placed in the Hi-Z state, thereby stopping the first... N The switching between the high-side switching transistor 231 and the low-side switching transistor 232 in the power stage 121n. This saves the time that might otherwise be achieved by driving the first... N The switching losses caused by the power consumed by the gates of the high-side switching transistor 231 and the low-side switching transistor 232 in power stage 121n are reduced, thus lowering the switching losses of the first stage. N The power consumption of power stage 121n. Accordingly, the overall power consumption of the system is reduced compared to state 1.

[0057] In state 3, the second set of pulses (via PWM2) can be stopped. For example, as Figure 4 As shown at time t2, PWM2 can be placed in the Hi-Z state, thereby stopping the switching of the high-side switching transistor 231 and the low-side switching transistor 232 of the second power stage 121b. This saves switching losses that would otherwise be caused by power consumed by driving the gates of the high-side switching transistor 231 and the low-side switching transistor 232 of the second power stage 121b, thus reducing the power consumption of the second power stage 121b. Correspondingly, the overall power consumption of the system is further reduced.

[0058] In state 4, the first N Transconductance amplifier 432 can be disabled to save the space that could originally be provided by the first amplifier. N The power consumed by the transconductance amplifier 432 when it is enabled. For example, as... Figure 4 As shown, 40 seconds after PWMn stops at time t1 During the waiting time, the GM[n]_EN signal can be forced low to disable the first... N Transconductance amplifier 432. Furthermore, the...N The current monitoring circuit 250 in power stage 121n can be put into sleep mode to save quiescent current consumption. Accordingly, the overall power consumption of the system is further reduced.

[0059] In state 5, the first set of pulses (via PWM1) can exit fixed-frequency operation and enter variable-frequency operation. For example, as Figure 4 As shown, at time t3, the first set of pulses (via PWM1) can have a lower frequency depending on the load. During fixed-frequency operation (before time t3), the first buck converter stage 120a can operate in continuous conduction mode (CCM). During variable-frequency operation (immediately after time t3), the first buck converter stage 120a can operate in discontinuous conduction mode, switching only when needed to support light loads and / or refresh the bootstrap capacitor 134a. Therefore, during light load conditions, the frequency can be reduced, for example, from 600kHz to 25kHz. Accordingly, the switching losses of the first power stage 121a can be reduced, thereby further reducing the overall power consumption of the system.

[0060] In state 6, the second transconductance amplifier 422 can be disabled to save power that might otherwise be consumed by the second transconductance amplifier 422 when it is enabled. For example, as Figure 4 As shown, 40 seconds after PWM2 stops. During the waiting period, the GM[2]_EN signal can be forced low to disable the second transconductance amplifier 422. Additionally, the current monitoring circuit 250 in the second power stage 121b can be put into sleep mode to save quiescent current consumption. Accordingly, the overall power consumption of the system is further reduced.

[0061] Prior to states 7 and 8, a large load event may occur. For example, the multiphase controller 110 can detect a drop in the feedback voltage caused by a sudden increase in load current. Therefore, in states 7 and 8, the multiphase controller 110 can recover the second set of pulses (via PWM2) and the... N Group pulse (via PWMn).

[0062] In state 7, and as Figure 4 As shown after time t4, the second set of pulses (via PWM2) can be recovered, and the Gm[2]_EN signal can be re-asserted to enable the second transconductance amplifier 422. In addition, the current monitoring circuit 250 in the second power stage 121b can be woken up in response to the recovery of the second set of pulses (via PWM2).

[0063] In state 8, and as Figure 4 As shown after time t4, the first NThe pulse group (via PWMn) can be recovered, and the Gm[n]_EN signal can be re-asserted to enable the first pulse. N Transconductance amplifier 432. Furthermore, the... N The current monitoring circuit 250 in the power stage 121n can respond to the first N Wake-up is achieved by the recovery of the pulse group (via PWMn).

[0064] Figure 7 The operating steps for VRM 100 according to an embodiment of this disclosure are illustrated.

[0065] At step 702, VRM 100 can operate in full-power mode. As described above for state 1, all blocks of VRM 100 can be active.

[0066] At step 704, the first step can be achieved by cutting off the second step. N This can reduce the power consumption of VRM 100. For example, as described above for state 2, the first step can be stopped. N Group pulses (via PWMn). For example... Figure 4 As shown at time t1, PWMn can be placed in the Hi-Z state, thereby stopping the first... N The switching of power stage 121n eliminates associated switching losses and thus reduces the power consumption of VRM 100. Furthermore, a timer within the redirection controller 402 can begin counting latency (e.g., 40...). ), to disable the N Transconductance amplifier 432.

[0067] At step 706, the power consumption of VRM 100 can be further reduced by cutting off the second phase. For example, as described above for state 3, the second set of pulses (via PWM2) can be stopped. Figure 4 As shown at time t2, PWM2 can be placed in the Hi-Z state, thereby stopping the switching of the second power stage 121b, eliminating the associated switching losses, and thus reducing the power consumption of VRM100. Furthermore, the timer within the redirection controller 402 can begin counting the waiting time (e.g., 40 seconds). ), to disable the second transconductance amplifier 422.

[0068] At step 708, when used to disable the first N When the wait time of the transconductance amplifier 432 expires, the power consumption of the VRM 100 can be further reduced. For example, as Figure 4 As shown, 40 seconds after PWMn stops at time t1 During the waiting time, the GM[n]_EN signal can be forced low to disable the first... NTransconductance amplifier 432.

[0069] At step 710, when the first phase enters the variable frequency discontinuous conduction mode (DCM), the power consumption of VRM 100 can be further reduced. During variable frequency operation ( Figure 4 (Example shown immediately after time t3) The first buck converter stage 120a can operate in discontinuous conduction mode, switching only when light loads and / or refresh bootstrap capacitor 134a are required. Accordingly, the switching losses of the first power stage 121a can be reduced, thereby further reducing the overall power consumption of VRM 100.

[0070] At step 712, when the wait time for disabling the second transconductance amplifier 422 expires, the power consumption of VRM 100 can be further reduced. For example, as Figure 4 As shown, 40 seconds after PWM2 stops. During the waiting time, the GM[2]_EN signal can be forced low to disable the second transconductance amplifier 422.

[0071] At step 714, a load step can be detected. For example, the multiphase controller 110 can detect a drop in the feedback voltage caused by a sudden increase in load current. Therefore, the multiphase controller 110 can recover the second set of pulses (via PWM2) and the... N Group pulses (via PWMn), as described below.

[0072] At step 716, the second set of pulses (via PWM2) can be recovered, and the Gm[2]_EN signal can be re-asserted to re-enable the second transconductance amplifier 422. In addition, the current monitoring circuit 250 in the second power stage 121b can be woken up in response to the recovery of the second set of pulses (via PWM2).

[0073] At step 718, the current sensing circuit 310 can use IMON1 instead of IMON2 to generate the summed current. For example, the redirection controller 402 can continue to assert the IMON2_REDIRECT signal to force the multiplexer 423 2.5 after the recovery of the second set of pulses (via PWM2). Up to 4.0 During the replacement period, a first voltage (based on IMON1 through the first resistor 411) is selected and transmitted to replace the second voltage (based on IMON2 through the second resistor 421).

[0074] At step 720, the first N The pulse group (via PWMn) can be recovered, and the Gm[n]_EN signal can be re-asserted to re-enable the first pulse group. N Transconductance amplifier 432. Furthermore, the...N The current monitoring circuit 250 in the power stage 121n can respond to the first N Wake-up is achieved by the recovery of the pulse group (via PWMn).

[0075] At step 722, the current sensing circuit 310 can use IMON1 instead of IMONn to generate the summation current. For example, the redirection controller 402 can continue to assert the IMONn_REDIRECT signal to force the multiplexer 433 at step 722. N 2.5 after recovery of the pulse group (via PWMn) Up to 4.0 During the replacement period, a first voltage (based on IMON1 through the first resistor 411) is selected and transmitted to replace the second voltage (based on IMON2 through the second resistor 431).

[0076] At step 724, the replacement period for IMON2 may expire. For example... Figure 4 As shown, after the replacement period of IMON2 expires, the redirection controller 402 can deassert the IMON2_REDIRECT signal to force the multiplexer 423 to select and pass the second voltage (based on IMON2 through the second resistor 421).

[0077] At step 726, the replacement period for IMONn may expire. For example... Figure 4 As shown, after the replacement period of IMONn expires, the redirection controller 402 can deassert the IMONn_REDIRECT signal to force the multiplexer 433 to select and transmit the first... N Voltage (based on the first) N Resistor 431 (IMONn).

[0078] Figure 8 A method 800 for operating a multiphase controller according to an embodiment of the present disclosure is illustrated. Method 800 can be performed by any suitable mechanism such as the multiphase controller 110. Method 800 can be performed using... Figure 8 The steps shown in the diagram can be performed in fewer or more steps. Furthermore, steps in method 800 can be omitted, repeated, performed in parallel, or combined with... Figure 8 The steps of method 800, though shown in order, may be executed sequentially or recursively. One or more steps of method 800, although shown in order, may be executed simultaneously or in a reordered manner.

[0079] Step 802 may include generating a PWM control signal using a current-mode regulation circuit based on the load conditions of the voltage regulator module. For example, as referenced above. Figure 3As described, the current-mode regulation circuit 320 can be configured to generate a PWM control signal PWM_CTL based on the load conditions of VRM 100. Specifically, the current-mode regulation circuit 320 can implement a current-mode feedback loop to control the pulse width and / or frequency of the PWM signals transmitted to the respective power stages 121a to 121n based on both voltage feedback and current feedback.

[0080] Step 804 may include distributing pulses to multiple power levels based on PWM control signals, including distributing a first set of pulses to a first power level and a second set of pulses to a second power level. For example, as referenced above. Figure 3 As described, the pulse distributor 330 of the multiphase controller 110 can be coupled to receive a PWM control signal PWM_CTL from the current-mode regulation circuit 320. The pulse distributor 330 can be configured to distribute pulses to multiple power levels 121a to 121n, including, for example, distributing a first set of pulses to a first power level 121a (via PWM1), distributing a second set of pulses to a second power level 121b (via PWM2), and in some embodiments, distributing a third set of pulses to a second power level 121n. N Group pulses are assigned to the first N Power stage 121n (via PWMn).

[0081] Step 806 may include selectively enabling and disabling a second set of pulses to the second power stage based on the load conditions of the voltage regulator module. For example, as Figure 4 As shown, the second set of pulses (via PWM2) supplied to the second power stage 121b can stop at time t2 during light load conditions and then resume after time t4 when the load increases.

[0082] Step 808 may include receiving multiple current monitoring signals from multiple power stages. For example, such as... Figure 1 and Figure 3 As shown in the diagram, the current sensing circuit 310 can sense current from multiple power stages (including a first power stage 121a, a second power stage 121b, and a third power stage 121c). N The power stage 121n receives multiple current monitoring signals IMON1, IMON2 to IMONn.

[0083] Step 810 may include generating a summation signal based on multiple current monitoring signals. For example, as referenced above. Figure 3 As described, the current sensing circuit 310 can generate a summation signal IMON_SUM based on multiple current monitoring signals (including IMON1, IMON2 to IMONn).

[0084] Step 812 may include, in response to the resumption of the second set of pulses from the second power level after the disabled period of the second set of pulses, replacing the second current monitoring signal from the second power level with a first current monitoring signal from the first power level during the replacement period to generate a summation signal. For example, as referenced above. Figure 3 and Figure 4 As described, the current sensing circuit 310 can respond to the recovery of the second set of pulses from the second power stage 121b after the second set of pulses is disabled for a period of time (via PWM2), and replace the second current monitoring signal IMON2 from the second power stage 121b with the first current monitoring signal IMON1 from the first power stage 121a during the replacement period.

[0085] Step 814 may include providing a summation signal to a current-mode conditioning circuit for use in regulating the voltage regulator module. For example, as... Figure 3 As shown, the current sensing circuit 310 can provide the summation signal IMON_SUM to the feedback circuit 322 within the current mode regulation circuit 320. The current mode regulation circuit 320 can then use the summation signal IMON_SUM as an indication of the total load current, thereby using current mode regulation to adjust the output voltage VOUT of VRM 100.

[0086] Step 816 may include resuming the generation of the summation signal using the second current monitoring signal after a replacement period following the recovery of the second set of pulses to the second power level. For example, as referenced above. Figure 4 As described, the redirection controller 402 can de-assert the IMON2_REDIRECT signal after the replacement period expires, forcing the multiplexer 423 to select the second voltage (based on IMON2 through the second resistor 421) and pass the second voltage to the second transconductance amplifier 422. Accordingly, after the replacement period of IMON2 is completed, IMON2 can be included in its own position again for generating the summation signal IMON_SUM.

[0087] Although examples have been described above, other modifications and variations can be made from this disclosure without departing from the spirit and scope of these examples. The description of the various embodiments above exemplifies the principles of the invention. Based on the above disclosure, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A multiphase controller for a voltage regulator module, the multiphase controller comprising: A current-mode regulation circuit is configured to generate a PWM control signal based on the load conditions of the voltage regulator module. A pulse distributor, coupled to receive the PWM control signal from the current-mode regulation circuit, and configured to distribute pulses to multiple power levels, including distributing a first set of pulses to a first power level and a second set of pulses to a second power level. And to selectively enable or disable the second set of pulses to the second power level based on the load conditions of the voltage regulator module; and A current sensing circuit, coupled to receive multiple current monitoring signals from the plurality of power stages, and configured to provide a summation signal to the current mode regulation circuit based on the plurality of current monitoring signals; And during the replacement period after the pulse disable period and after the recovery of the second set of pulses to the second power level, the second current monitoring signal from the second power level is replaced by the first current monitoring signal from the first power level.

2. The multiphase controller of claim 1, wherein the current sensing circuit is configured to: resume using the second current monitoring signal to generate the summing signal after the replacement period is completed.

3. The multiphase controller according to claim 1, wherein the replacement period is 2.5 seconds. Up to 6.0 Within the range.

4. The multiphase controller of claim 3, wherein the replacement period is programmable.

5. The multiphase controller of claim 1, wherein the current sensing circuit is coupled to receive current from... N Each power level receives the corresponding N A current monitoring signal, and wherein N It is in the range of 2 to 48.

6. The multiphase controller according to claim 1, wherein the current sensing circuit comprises: A summing circuit configured to generate the summing signal based on multiple channel signals corresponding to the plurality of current monitoring signals; A first channel is configured to provide a first channel signal to the summing circuit based on a first current monitoring signal from the first power stage; A second channel, configured to, when enabled, provide a second channel signal to the summing circuit based on a selection of a first current monitoring signal from the first power stage and a second current monitoring signal from the second power stage; and A redirection controller, configured to: The second channel is disabled in response to the cessation of the second set of pulses to the second power level; The second channel is enabled in response to the recovery of the second set of pulses to the second power level; During the replacement period that occurs after the recovery of the second group of pulses, the second channel is instructed to select the first current monitoring signal; as well as After the replacement period expires, the second channel is instructed to select the second current monitoring signal.

7. The multiphase controller of claim 6, wherein the redirection controller is configured to instruct the second channel to select the first current monitoring signal after a waiting period following the cessation of the second set of pulses to the second power level.

8. The multiphase controller according to claim 6, wherein: The first channel of the current sensing circuit includes: a first resistor and a first transconductance amplifier; The first resistor is configured to convert the first current monitoring signal into a first voltage signal; The first transconductance amplifier is configured to provide the first channel signal to the summing circuit based on the first voltage signal; and The second channel of the current sensing circuit includes: a second resistor and a second transconductance amplifier; The second resistor is configured to convert the second current monitoring signal into a second voltage signal; A multiplexer coupled to transmit one of the first voltage signal and the second voltage signal in response to the redirection controller; The second transconductance amplifier is configured to provide the second channel signal to the summing circuit based on the multiplexer output.

9. A voltage regulator module, the voltage regulator module comprising: Multiple power stages and multiphase controllers; Each power stage includes: a high-side switching transistor, a low-side switching transistor, and a current monitoring circuit; The current monitoring circuit is configured to provide a current monitoring signal representing the total current through the high-side switching transistor and the low-side switching transistor; The multiphase controller includes: a current-mode regulation circuit, a pulse distributor, and a current sensing circuit; The current-mode regulation circuit is configured to generate a PWM control signal based on the load conditions of the voltage regulator module. The pulse distributor is coupled to receive the PWM control signal from the current-mode regulation circuit and is configured to: distribute pulses to the plurality of power levels, including distributing a first set of pulses to a first power level and a second set of pulses to a second power level; and selectively enable or disable the second set of pulses to the second power level based on the load conditions of the voltage regulator module; and The current sensing circuit is coupled to receive multiple current monitoring signals from the plurality of power levels and is configured to: provide a summation signal to the current mode adjustment circuit based on the plurality of current monitoring signals; and, during a replacement period after the pulse disable period and after the recovery of the second set of pulses to the second power level, replace the second current monitoring signal from the second power level with the first current monitoring signal from the first power level.

10. The voltage regulator module of claim 9, wherein the current sensing circuit is further configured to resume using the second current monitoring signal to generate the summing signal after the replacement period is completed.

11. The voltage regulator module of claim 9, wherein the replacement period is 2.5 seconds. Up to 6.0 Within the range.

12. The voltage regulator module of claim 11, wherein the replacement period is programmable.

13. The voltage regulator module of claim 9, wherein the current sensing circuit is coupled to... N Each power level receives the corresponding N A current monitoring signal, and wherein N It is in the range of 2 to 48.

14. The voltage regulator module of claim 9, wherein the current sensing circuit comprises: A summing circuit configured to generate the summing signal based on multiple channel signals corresponding to the plurality of current monitoring signals; A first channel is configured to provide a first channel signal to the summing circuit based on a first current monitoring signal from the first power stage; A second channel, configured to, when enabled, provide a second channel signal to the summing circuit based on a selection of a first current monitoring signal from the first power stage and a second current monitoring signal from the second power stage; and A redirection controller, configured to: The second channel is disabled in response to the cessation of the second set of pulses to the second power level; The second channel is enabled in response to the recovery of the second set of pulses to the second power level; During the replacement period that occurs after the recovery of the second group of pulses, the second channel is instructed to select the first current monitoring signal; as well as After the replacement period expires, the second channel is instructed to select the second current monitoring signal.

15. The voltage regulator module of claim 14, wherein the redirection controller is configured to instruct the second channel to select the first current monitoring signal after a waiting period following the cessation of the second set of pulses to the second power level.

16. The voltage regulator module according to claim 15, wherein: The current monitoring circuit of the second power stage is configured to enter a sleep state in response to the second power stage not receiving the second set of pulses during a delay period; and The waiting period for instructing the second channel to select the first current monitoring signal is less than the delay period for the current monitoring circuit to enter the sleep state.

17. The voltage regulator module according to claim 14, wherein: The first channel of the current sensing circuit includes: A first resistor, configured to convert the first current monitoring signal into a first voltage signal; and A first transconductance amplifier is configured to provide the first channel signal to the summing circuit based on the first voltage signal; and The second channel of the current sensing circuit includes: A second resistor is configured to convert the second current monitoring signal into a second voltage signal; A multiplexer, coupled to transmit one of the first voltage signal and the second voltage signal in response to the redirection controller; and A second transconductance amplifier is configured to provide the second channel signal to the summing circuit based on the multiplexer output.

18. A method of operating a multiphase controller for a voltage regulator module, the method comprising: Based on the load conditions of the voltage regulator module, a PWM control signal is generated using a current-mode regulation circuit. The pulses are distributed to multiple power levels based on the PWM control signal, including distributing a first group of pulses to a first power level and distributing a second group of pulses to a second power level; The second set of pulses to the second power level is selectively enabled and disabled based on the load conditions of the voltage regulator module. Receive multiple current monitoring signals from the multiple power stages; A summation signal is generated based on the multiple current monitoring signals; In response to the resumption of the second set of pulses from the disabled period of the second set of pulses to the second power level, the summation signal is generated by replacing the second current monitoring signal from the second power level with the first current monitoring signal from the first power level during the replacement period. as well as The summation signal is provided to the current-mode regulation circuit for regulating the voltage regulator module.

19. The method of claim 18, further comprising, after the replacement period following the recovery of the second set of pulses to the second power level, resuming the generation of the summation signal using the second current monitoring signal.

20. The method of claim 18, wherein the replacement period is 2.5 hours. Up to 6.0 Within the range.

Images