Machine learning attack resisting circuit of PUF (Physical Unclonable Function)

Abstract

The invention provides an anti-machine learning attack circuit for a PUF (Physical Unclonable Function), and belongs to the field of PUFs, the anti-machine learning attack circuit comprises two SAC-PUF circuits, each SAC-PUF circuit comprises an arbiter D1 and n path exchange switches, n control ends of the n path exchange switches are respectively connected to values of n triggers, output ends of the jth and kth path exchange switches are respectively connected to arbiters D3 and D2, output ends of D1, D2 and D3 are connected to a confusion circuit, and the output ends of D1, D2 and D3 are respectively connected to the output ends of n triggers. The output end of the mixing circuit in the first SAC-PUF circuit is connected to the first control end of the tap unit and the first input end of the post-processing circuit, and the output end of the mixing circuit in the second SAC-PUF circuit is connected to the second control end of the tap unit and the second input end of the post-processing circuit. The output end of the post-processing circuit is connected to the second input end of each tap unit, and the first input end of each tap unit is connected to the value of the nth trigger; and the machine learning attack resistance is improved.

Description

Technical Field

[0001] This invention relates to the field of Physical Unclonable Function (PUF) technology, and more particularly to machine learning-resistant circuits for PUF. Background Technology

[0002] Hardware security technologies based on physically unclonable functions (PUFs) are widely used in IoT devices, identity authentication, and key generation due to their unique physical randomness, unclonability, and efficiency. PUFs generate unpredictable response signals by extracting inherent microscopic physical differences during chip manufacturing (such as random fluctuations in transistor threshold voltage), thus providing a lightweight solution for hardware security. However, in recent years, machine learning attacks (MLAs) targeting PUFs have gradually become a significant threat. MLAs train machine learning models by collecting challenge-response pairs (CRPs) of PUFs to predict their response behavior, thereby compromising the unpredictability and security of PUFs. For example, research on arbitrator PUFs or ring oscillator PUFs shows that algorithms such as linear regression and neural networks can achieve high-precision modeling with limited CRP samples, seriously threatening the practical deployment of PUFs.

[0003] In the process of improving the PUF's resistance to machine learning attacks, quantitative evaluation of its security is a core task. This can not only verify the effectiveness of existing protection technologies, but also identify the weak links in the PUF design, providing a basis for targeted reinforcement and optimization. At present, the main methods for evaluating the PUF's resistance to machine learning attacks are divided into two categories: (1) Actual modeling attack experiment method, which involves collecting the CRP dataset of the target PUF, directly training the attack model and statistically predicting the success rate. This method can truly reflect the PUF's defense capabilities, but it requires a lot of time to collect massive amounts of CRP data, and the experimental process may introduce bias due to the physical aging of the PUF or environmental noise. (2) Simulation modeling attack method, which involves simulating the physical characteristics of the PUF (such as delay distribution and nonlinear noise) through mathematical modeling, and generating CRP based on the simulation data to train the attack model. Compared with actual experiments, the simulation method has the advantages of strong controllability, low cost, and rapid iteration, but its accuracy is highly dependent on the model's fit to the real physical characteristics, which may underestimate the actual attack difficulty.

[0004] Practical modeling attacks are an important means of evaluating the security of PUFs. For PUF circuits, it is necessary to collect their stimulus-response pairs. Existing machine learning attacks need to consider resource overhead and the impact of machine learning attacks. While many existing strong PUF circuits have achieved good resistance to machine learning, they still face the problem of high resource consumption. For example, the paper "A Lightweight Authentication Protocol Against Modeling Attacks Based on a NovelLFSR-APUF" (Wang, Yao et al., Zhengzhou University, IEEE INTERNET OF THINGSJOURNAL, VOL.18, NO.9, SEPTEMBER2020) uses 388 LUTs and 399 DFFs. Although it achieves good resistance to modeling, the resource consumption is large, making it difficult to adapt to lightweight application scenarios. Similarly, other research has designed a dynamic attack framework based on gradient boosting trees, which improves modeling efficiency through adaptive feature selection. However, there may be room for further balancing the resources consumed by this adaptive selection module with the performance improvement obtained.

[0005] For example, the Chinese invention patent application CN113922990A, entitled "A Method for Resisting Machine Learning Attacks in a Strong PUF Based on Matrix Encryption," uses the response signals generated by multiple sets of different excitation signals applied to a strong PUF as the information to be encrypted, and arranges them into a plaintext matrix. Then, encryption operations are performed, using two plaintext matrices to generate a ciphertext matrix through matrix multiplication. The elements in the transformation matrix obtained after binary conversion of the ciphertext matrix are used as the final response, corresponding one-to-one with the original excitation signals, as the final CRP of the matrix-encrypted strong PUF. The advantage is that it can significantly improve the resistance of the strong PUF to machine learning attacks, and the prediction rate of machine learning attacks can be reduced to about 50%, which is close to random guessing. The risk of the strong PUF being attacked by machine learning is relatively small. However, implementing the matrix encryption function in hardware will inevitably consume more resources, resulting in a large hardware cost.

[0006] It is evident that existing PUF circuits for resisting machine learning attacks suffer from a tradeoff between resource overhead and improved resistance to machine learning. Therefore, there is an urgent need to develop a PUF circuit design scheme that supports lightweight scenarios and has sufficient resistance to machine learning attacks, in order to improve the efficiency and reliability of hardware security design. Summary of the Invention

[0007] The technical problem to be solved by this invention is: how to improve the resistance to machine learning attacks of PUF circuits while keeping them lightweight.

[0008] The present invention solves the above technical problems through the following technical solutions: The anti-machine learning attack circuit of the PUF includes two symmetric SAC-PUF circuits. Each SAC-PUF circuit includes an arbiter D1 and n path switching switches, where n is an integer greater than 0. The n control terminals of the n path switching switches are respectively connected to the values of n flip-flops. The output terminals of the j-th and k-th path switching switches are respectively connected to arbiters D3 and D2, where 0 ≤ j < n - 1, 0 ≤ k < n - 1, and j ≠ k. The output terminals of arbiters D1, D2, and D3 are connected to a confusion circuit. The output terminal of the confusion circuit in the first SAC-PUF circuit is respectively connected to the first control terminal of the tap unit and the first input terminal of the post-processing circuit. The output terminal of the confusion circuit in the second SAC-PUF circuit is respectively connected to the second control terminal of the tap unit and the second input terminal of the post-processing circuit. The output terminal of the post-processing circuit is connected to the second input terminal of each tap unit. The first input terminal of each tap unit is connected to the value of the n-th flip-flop. The output terminal of the tap unit is connected to the input terminal of the i-th flip-flop through a logic gate, where 0 < i < n.

[0009] The first control terminal and the second control terminal of the tap unit of the present invention are respectively connected to the values output by two symmetric SAC-PUF circuits. The process deviation quantization value output by the SAC-PUF branch, which is transformed from the inevitable circuit delay difference in the chip manufacturing process, has natural non-clonability. Through the dual-path structure process deviation feature extraction mechanism, the path delay difference is dynamically mapped to the tap unit of the linear feedback shift register, causing the feedback coefficient of the LFSR to change; the first input terminal of the tap unit is connected to the value of the n-th flip-flop, ensuring the timing continuity of sequence generation; the values output by the two SAC-PUF circuits are processed by the post-processing circuit to obtain the PUF circuit response value. By feeding back the PUF circuit response value to the second input terminal of the tap unit, the closed-loop correlation between excitation generation and response output is realized, causing the excitation to be confused. Under the combined action of the three, the feedback polynomial of the LFSR is no longer fixed, but changes dynamically with the chip physical characteristics and historical responses, making the generated excitation sequence break through the linear law of traditional pseudo-random sequences, cutting off the path for attackers to model through excitation characteristics from the source, and greatly enhancing the underlying ability to resist machine learning attacks.

[0010] Compared with one path signal of the LFSR in the prior art, the present invention increases the complexity of the structure. The selection of the tap is no longer always 0 / 1, but changes with the change of four input signals. By changing the tap each time, the change of the excitation is caused, realizing the non-linear perturbation of the excitation generation process, increasing the randomness of the circuit, and significantly improving the anti-machine learning performance. In the SAC-PUF circuit, the output values of the j-th and k-th path switching switches are respectively input into an arbiter, and the output values of the three arbiters are confused to increase the randomness of the output, making the PUF structure no longer linearized, and further improving the anti-machine learning performance. The SAC-PUF circuit only needs to add two arbiters on the basis of the existing APUF circuit, and realizes the accurate capture and random injection of bias features with extremely low resource increment.

[0011] Preferably, the tap unit includes an exclusive OR gate and two two-input MUXs. The control ends of the first two-input MUX and the second two-input MUX are respectively used as the first control end and the second control end of the tap unit. The input ends of the two two-input MUXs are configured to obtain the first input end and the second input end of the tap unit. The output ends of the two two-input MUXs are respectively connected to the exclusive OR gate, and the output end of the exclusive OR gate is used as the output end of the tap unit.

[0012] The present invention only uses a symmetric structural unit composed of two multiplexers (two-input MUXs) and an exclusive OR gate, which can increase the complexity of the circuit without consuming too many resources.

[0013] Preferably, the output ends of the three tap units are respectively connected to the input ends of the i1, i2, and i3 flip-flops through exclusive OR gates, where 0 < i1 < n, 0 < i2 < n, 0 < i3 < n, and i1 ≠ i2 ≠ i3. The first and second input ends of the first two-input MUX are connected and used as the first input end of the tap unit, and the first and second input ends of the second two-input MUX are connected and used as the second input end of the tap unit.

[0014] The three tap units of the present invention consume a total of 6 two-input MUXs and 3 exclusive OR gates, which improve the randomness of the PUF with a low resource overhead. Compared with the traditional fixed-tap LFSR (usually more than 60 exclusive OR gates are required to realize full-link feedback), the resource overhead of 60 exclusive OR gates is directly reduced, and the hardware occupancy rate is reduced by more than 90%, perfectly meeting the lightweight design requirements.

[0015] Preferably, the three tap units are a first tap unit, a second tap unit, and a third tap unit respectively. The output ends of the first, second, and third tap units are respectively connected to the input ends of the i1, i2, and i3 flip - flops through exclusive - OR gates, where 0 < i1 < n, 0 < i2 < n, 0 < i3 < n, and i1 ≠ i2 ≠ i3. In the first tap unit, the second input end of the first two - input MUX is connected to the second input end of the second two - input MUX and serves as the first input end of the tap unit, and the first input end of the first two - input MUX is connected to the first input end of the second two - input MUX and serves as the second input end of the tap unit; in the second tap unit, the first and second input ends of the first two - input MUX are connected and serve as the first input end of the tap unit, and the first and second input ends of the second two - input MUX are connected and serve as the second input end of the tap unit; in the third tap unit, the first input end of the first two - input MUX is connected to the first input end of the second two - input MUX and serves as the first input end of the tap unit, and the second input end of the first two - input MUX is connected to the second input end of the second two - input MUX and serves as the second input end of the tap unit.

[0016] Preferably, n is 64, the 64 flip - flops are connected end - to - end in sequence, i1, i2, and i3 are 16, 32, and 48 respectively, j is 28, and k is 43. The tap units are evenly deployed at the 16th, 32nd, and 48th nodes of the 64 - stage Galois - type LFSR to ensure the randomness and uniformity of the excitation sequence.

[0017] Preferably, the result of exclusive - OR operation on the output values of the confusion circuits in the two SAC - PUF circuits and the output values of the two confusion circuits are used as the inputs of the multiplexer. The historical output value of the post - processing circuit is fed back to the selection port of the multiplexer, and the outputs of the two multiplexers are exclusive - ORed to obtain the current output value of the post - processing circuit.

[0018] The present invention designs a symmetric minimalist response confusion post - processing unit, which breaks the linear correlation between excitation and response through non - linear transformation while maintaining the lightweight property of the hardware.

[0019] Preferably, the output value A of the confusion circuit in the first SAC - PUF circuit and the output value B of the confusion circuit in the second SAC - PUF circuit are 0 and 0 respectively, and the historical output value R of the post - processing circuit pre When it is 0, the current output value R of the post - processing circuit after Is 0; when A = 0, B = 0, and R pre = 1, R after = 0; when A = 0, B = 1, and R pre = 0, R after = 1; when A = 0, B = 1, and R pre = 1, R after=0; A=1, B=0, R pre When =0, R after =0; A=1, B=0, R pre When =1, R after =1; A=1, B=1, R pre When =0, R after =1; A=1, B=1, R pre When =1, R after =1.

[0020] This invention introduces the historical response R of the PUF circuit. pre As a selection control signal, a two-layer obfuscation mechanism of "XOR operation + historical feedback routing" is adopted to transform the overall structure of PUF from linear to nonlinear: on the one hand, the XOR operation has the inherent ability to obfuscate data and can disrupt the original characteristics of intermediate responses; on the other hand, the feedback routing of historical responses realizes the dynamic switching of responses in different time domains, making it impossible for attackers to build a fixed input-output mapping model through static CRPs datasets.

[0021] Preferably, the post-processing circuit includes a first XOR gate, a second XOR gate, a third two-input MUX, and a fourth two-input MUX. The output terminal of the obfuscation circuit in the first SAC-PUF circuit is connected to the first input terminal of the first XOR gate and the first input terminal of the third two-input MUX, respectively. The output terminal of the obfuscation circuit in the second SAC-PUF circuit is connected to the second input terminal of the first XOR gate and the second input terminal of the fourth two-input MUX, respectively. The output terminal of the first XOR gate is connected to the second input terminal of the third two-input MUX and the first input terminal of the fourth two-input MUX, respectively. The output terminals of the third two-input MUX and the fourth two-input MUX are connected to the first input terminal and the second input terminal of the second XOR gate, respectively. The output terminal of the second XOR gate is connected to the control terminals of the third two-input MUX and the fourth two-input MUX and serves as the output terminal of the post-processing circuit.

[0022] The post-processing circuit consists of only two MUXs and two XOR gates, and the overall hardware overhead is negligible.

[0023] Preferably, when the outputs X, Y, and Z of arbitrators D1, D2, and D3 are 0, 0, and 0 respectively, the output Out of the mixing circuit is 0; when X=0, Y=0, and Z=1, Out=0; when X=0, Y=1, and Z=0, Out=1; when X=0, Y=1, and Z=1, Out=0; when X=1, Y=0, and Z=0, Out=1; when X=1, Y=1, and Z=1, Out=0; when X=1, Y=1, and Z=0, Out=1; when X=1, Y=1, and Z=1, Out=1. The truth table shows that the mixing circuit exhibits good uniformity.

[0024] Preferably, the obfuscating circuit includes a first buffer, a second buffer, an inverter, a first AND gate, a second AND gate, a third AND gate, and an OR gate. The outputs of arbitrators D1 and D2 are connected to the inputs of the first buffer and the second buffer, respectively. The output of arbitrator D3 is connected to the input of the inverter. The output of the first buffer is connected to the first input of the first AND gate and the second AND gate, respectively. The output of the second buffer is connected to the second input of the second AND gate and the third AND gate, respectively. The output of the inverter is connected to the second input of the first AND gate and the first input of the third AND gate, respectively. The outputs of the first, second, and third AND gates are connected to the input of the OR gate, and the output of the OR gate serves as the output of the obfuscating circuit.

[0025] The advantages provided by this invention are:

[0026] 1. The SAC-PUF circuit of this invention adds only two flip-flops and one lookup table (LUT) to the traditional APUF, without large-scale circuit expansion. Its core is to achieve the characteristics of a strict avalanche criterion through the cascading and scrambling combination of three arbitrators, meaning that when any excitation bit flips, the probability of the output response flipping strictly approaches 50%. The three arbitrators correspond to signal paths of different lengths, and their outputs, after being scrambled by the LUT, eliminate the linear defect in traditional APUFs where "the front-end excitation bit does not affect the response, and the back-end excitation bit will inevitably flip the response," ensuring that the influence of each excitation bit on the response is equal and random.

[0027] 2. The SAC-PUF circuit of this invention adopts a symmetrical PUF cell structure, using the process deviation difference between a pair of symmetrical cells as the selection input for the LFSR tap cell. During chip manufacturing, the path delay of the symmetrical cells will have slight differences due to process fluctuations such as photolithography and etching. This difference is quantified into 0 / 1 logic values ​​and injected into the LFSR tap configuration logic, which is equivalent to directly integrating the chip's "physical fingerprint" into the stimulus generation process. This strengthens the physical binding relationship between stimulus and response and further improves the randomness of the response sequence. Testing shows that the uniformity of this branch output reaches 50.49%, very close to the ideal threshold of 50%, providing a solid random foundation for subsequent resistance to machine learning attacks.

[0028] 3. This invention performs robustness verification against four typical machine learning attacks—logistic regression (LR), support vector machine (SVM), deep neural network (DNN), and covariance matrix adaptive evolution strategy (CMA-ES)—on a scale of 100,000 CRPs. The prediction accuracy of the four attack models is consistently below 55.5%, approaching the theoretical random guessing baseline (50%), and the average anti-attack capability is improved by more than 35% compared to the traditional APUF scheme. Attached Figure Description

[0029] Figure 1This is a schematic diagram of a PUF (Public Arbitrator Function) in the prior art; Figure 2 This is a schematic diagram illustrating the working principle of the linear feedback shift register (LFSR) in the prior art. Figure 3(a) is a schematic diagram of a PUF anti-machine learning attack circuit provided in an embodiment of the present invention; Figure 3(b) is another schematic diagram of the anti-machine learning attack circuit of PUF provided in the embodiment of the present invention; Figure 4 A schematic diagram of the tap unit in the PUF anti-machine learning attack circuit provided in the embodiment of the present invention; Figure 5(a) is a schematic diagram of the tap unit in the anti-machine learning attack circuit of PUF provided in the embodiment of the present invention according to the first configuration method; Figure 5(b) is a schematic diagram of the tap unit in the anti-machine learning attack circuit of PUF provided in the embodiment of the present invention according to the second configuration method; Figure 5(c) is a schematic diagram of the tap unit in the anti-machine learning attack circuit of PUF provided in the embodiment of the present invention according to the third configuration method; Figure 6 A schematic diagram of the SAC-PUF circuit in the anti-machine learning attack circuit of PUF provided in the embodiment of the present invention; Figure 7 A schematic diagram of the obfuscation circuit in the PUF anti-machine learning attack circuit provided in the embodiment of the present invention; Figure 8 A schematic diagram of the post-processing circuit in the PUF anti-machine learning attack circuit provided in the embodiment of the present invention; Figure 9 Signal flow diagram of the anti-machine learning attack circuit of PUF provided in this embodiment of the invention implemented on an FPGA development board; Figure 10 The uniformity result of the PUF anti-machine learning attack circuit provided in the embodiment of the present invention; Figure 11 The uniqueness result of the PUF anti-machine learning attack circuit provided in the embodiments of the present invention; Figure 12(a) shows the reliability results of the PUF anti-machine learning attack circuit provided in the embodiment of the present invention under different voltages; Figure 12(b) shows the reliability results of the PUF anti-machine learning attack circuit provided in the embodiment of the present invention at different temperatures; Figure 13 The randomness result of the PUF anti-machine learning attack circuit provided in the embodiments of the present invention; Figure 14(a) shows the results of the PUF anti-machine learning attack circuit provided in the embodiment of the present invention under 5000 CRPs for four typical machine learning resistances; Figure 14(b) shows the results of the PUF anti-machine learning attack circuit provided in the embodiment of the present invention under 10,000 CRPs for four typical machine learning resistances; Figure 14(c) shows the results of the PUF anti-machine learning attack circuit provided in the embodiment of the present invention for four typical machine learning resistances under 50,000 CRPs; Figure 14(d) shows the results of the PUF anti-machine learning attack circuit provided in the embodiment of the present invention for four typical machine learning resistances under 100,000 CRPs; Figure 15 The results of the resistance of the PUF anti-machine learning attack circuit provided in the embodiments of the present invention to four typical machine learning attacks as the number of CRPs increases. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0031] See Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of an arbiter PUF (Arbiter-PUF, APUF) in the prior art. Figure 2 This is a schematic diagram illustrating the working principle of a linear feedback shift register (LFSR) in the prior art. The working principles of APUF and LFSR in the prior art are introduced below: See Figure 1 , Figure 1In this code, Challenge represents the stimulus, Response represents the response, and Arbiter represents the arbiter. The arbiter typically uses a D flip-flop, and DFF represents a D flip-flop. A D flip-flop includes two input ports and one output port. The two input ports are the D terminal and the CLK terminal, and the output port is the Out terminal. An n-bit APUF includes n path-switching switches and one arbiter. Each path-switching switch includes two two-input multiplexers (MUX), referred to as two-input MUXs in this embodiment. The two two-input MUXs are named two-input MUX1 and two-input MUX2. Each two-input MUX includes two input terminals, one control terminal, and one output terminal. The control terminals of two-input MUX1 and two-input MUX2 are connected together and controlled by a signal Ci. One input pulse signal is input to the first input terminal of two-input MUX1 and the second input terminal of two-input MUX2 (in this embodiment, the 0 port of the two-input MUX is defined as the first input terminal, and the 1 port of the two-input MUX is defined as the second input terminal). Another input pulse signal is input to the second input terminal of two-input MUX1 and the first input terminal of two-input MUX2. The two input pulse signals of the input path switching switch are bifurcated to form two pairs of path groups, one of which is Figure 1 The middle pair is a parallel black solid line, and the other pair is... Figure 1 The orange dashed lines intersect in the middle, and the two pairs of path groups are symmetrical to each other. Figure 1 The two solid black lines and two dashed orange lines represent the signal transmission delays of the four paths within the i-th path switching switch. Each input excitation bit Ci can be configured with one pair of path groups. After configuring n path switching switches with n input excitation bits, the APUF forms two symmetrical signal paths, allowing the input pulse signal to be transmitted to the two input terminals of the arbitrator.

[0032] Pre-configure n input excitation bits C0, C1, C2, ..., C n-1 n input excitation bits C0, C1, C2, ..., C n-1Each path-switching switch's control terminal is input one-to-one, and the control terminals of the path-switching switches are the ports connected to the control terminals of the two two-input MUXs. Then, a pulse signal is input. After passing through the two symmetrical paths configured for the excitation, the pulse signal enters the arbiter. The output response (0 or 1) is determined by judging the order of the two pulse signals. The arbiter typically uses a D flip-flop. The pulse signal from the upper path is input to the D terminal of the D flip-flop, and the pulse signal from the lower path is input to the CLK terminal of the D flip-flop. The D flip-flop outputs a one-bit response. Theoretically, any path selected for the input excitation is perfectly symmetrical. However, due to process deviations during manufacturing, the two paths have different delays. Therefore, the two signals entering the arbiter will have a delay deviation. The arbiter determines the order of arrival of the two signals and outputs 0 or 1, which is the APUF response. This allows the acquisition of APUF excitation-response pairs (CRPs).

[0033] Process deviation is the core basis for PUF to achieve physical non-cloning. The defect of APUF in the above-mentioned existing technology is that APUF has a coarse extraction granularity of process deviation, which easily leads to insufficient response randomness.

[0034] The Linear Feedback Shift Register (LFSR) is the core module for PUF stimulus generation. Traditional LFSRs have fixed taps (feedback coefficients). The following section discusses... Figure 2 The working mechanism of LFSR in the existing technology is introduced as follows: An LFSR consists of a set of registers and a set of logic gates that can shift bits in the registers and perform an XOR operation according to a specific feedback polynomial to generate the output for the next clock cycle. The output sequence of the LFSR depends on the initial state (seed) and the feedback polynomial. When the initial state and feedback polynomial are determined, the LFSR will generate a pseudo-random output sequence according to a certain rule. The tap, called the LFSR, or feedback coefficient, is located in... Figure 2 middle, The value is either 0 or 1, where 1 indicates that it exists in the feedback branch, equivalent to a wire, and 0 indicates that it does not exist, equivalent to the path being open. Its feedback polynomial is: ,in, and The value is always 1. An LFSR circuit consists of n flip-flops and can generate a circuit with a maximum period of 2^n. The output sequence is 1. The feedback polynomial corresponding to the maximum sequence is the primitive polynomial. In order for the output sequence to become the maximum sequence, it is also necessary to ensure that the initial seed is not all zero. The drawback of the existing LFSR is that the taps (feedback coefficients) of the LFSR are fixed, and the generated activation sequence is predictable, making it easy to become a breakthrough point for machine learning attacks.

[0035] To solve the problems in the prior art that the extraction granularity of process variations by the APUF in the PUF circuit is relatively coarse, resulting in insufficient response randomness, and the predictability of the excitation sequence generated by the LFSR leads to poor anti-machine learning attack ability of the PUF circuit, based on the traditional APUF, the present invention designs a SAC-PUF fine-grained process variation extraction branch, which achieves accurate capture and random injection of variation features with extremely low resource increment; and designs a lightweight dynamic configurable LFSR tap unit, which realizes non-linear perturbation of excitation generation and efficient utilization of hardware resources. The anti-machine learning attack circuit of the PUF of the present invention is introduced in detail below: As shown in FIGS. 3(a) and 3(b), the present embodiment provides an anti-machine learning attack circuit of a PUF, including two symmetric SAC-PUF circuits, which are respectively a first SAC-PUF circuit and a second SAC-PUF circuit. Each SAC-PUF circuit includes an arbiter D1 and n path switching switches, where n is an integer greater than 0. Each path switching switch includes two two-input MUXes, namely two-input MUX1 and two-input MUX2. Similar to the APUF in the above prior art, each two-input MUX includes two input terminals, a control terminal and an output terminal. The control terminals of the two-input MUX1 and the two-input MUX2 are connected together and controlled by a signal Ci. An input pulse signal is respectively input to the first input terminal of the two-input MUX1 and the second input terminal of the two-input MUX2, and another input pulse signal is respectively input to the second input terminal of the two-input MUX1 and the first input terminal of the two-input MUX2. The two input pulse signals input to the path switching switch are bifurcated to form two pairs of path groups.

[0036] The n control terminals of the n path switching switches are respectively connected to the values of n flip-flops in the register. The output terminals of the j-th and k-th path switching switches are respectively connected to arbiters D3 and D2, where 0≤j<n-1, 0≤k<n-1, and j≠k. The output terminals of arbiters D1, D2, and D3 are connected to the confusion circuit. The output terminal of the confusion circuit in the first SAC-PUF circuit is respectively connected to the first control terminal Sel1 of the tap unit and the first input terminal of the post-processing circuit. The output terminal of the confusion circuit in the second SAC-PUF circuit is respectively connected to the second control terminal Sel2 of the tap unit and the second input terminal of the post-processing circuit. The output terminal of the post-processing circuit is connected to the second input terminal IN2 of each tap unit. The first input terminal IN1 of each tap unit is connected to the value of the n-th flip-flop in the register. The output terminal of the tap unit is connected to the input terminal of the i-th flip-flop in the register through a logic gate, where 0<i<n.

[0037] See Figure 4The tapping unit includes an XOR gate and two two-input MUXs, designated as a first two-input MUX and a second two-input MUX. The control terminals of the first and second two-input MUXs serve as the first and second control terminals of the tapping unit, respectively. The input terminals of the two two-input MUXs are configured to obtain the first and second input terminals of the tapping unit. The output terminals of the two two-input MUXs are connected to the XOR gate, and the output terminal of the XOR gate serves as the output terminal of the tapping unit. This invention provides three configurations for the input terminals of the two two-input MUXs, resulting in three different tapping units: a first tapping unit, a second tapping unit, and a third tapping unit. These are described below: First configuration: Refer to Figure 5(a). The two two-input MUXs are the first two-input MUX and the second two-input MUX, respectively. The second input terminal of the first two-input MUX is connected to the second input terminal of the second two-input MUX and serves as the first input terminal of the tap unit. The first input terminal of the first two-input MUX is connected to the first input terminal of the second two-input MUX and serves as the second input terminal of the tap unit. The control terminal of the first two-input MUX is the first control terminal of the first tap unit, and the control terminal of the second two-input MUX is the second control terminal of the first tap unit.

[0038] The second configuration: Referring to Figure 5(b), the two two-input MUXs are a first two-input MUX and a second two-input MUX, respectively. The first and second input terminals of the first two-input MUX are connected and serve as the first input terminal of the tap unit, and the first and second input terminals of the second two-input MUX are connected and serve as the second input terminal of the tap unit. The control terminal of the first two-input MUX is the first control terminal of the first tap unit, and the control terminal of the second two-input MUX is the second control terminal of the first tap unit.

[0039] The third configuration: Referring to Figure 5(c), the two two-input MUXs are a first two-input MUX and a second two-input MUX, respectively. The first input terminal of the first two-input MUX is connected to the first input terminal of the second two-input MUX and serves as the first input terminal of the tap unit. The second input terminal of the first two-input MUX is connected to the second input terminal of the second two-input MUX and serves as the second input terminal of the tap unit. The control terminal of the first two-input MUX is the first control terminal of the first tap unit, and the control terminal of the second two-input MUX is the second control terminal of the first tap unit.

[0040] For ease of understanding, this embodiment uses n=64 to describe the anti-machine learning attack circuit of the PUF of the present invention: When n=64, at least three tap units are configured. The tap units can be the same or different. Since configuring three tap units can improve the anti-machine learning attack capability of the PUF circuit while achieving a lightweight design, the following description uses the configuration of three tap units: If the three tap units are the same, the present invention selects the tap unit of the second configuration mode (the second tap unit), that is, in the tap unit, the first input terminal and the second input terminal of the first two-input MUX are connected and used as the first input terminal of the tap unit, and the first input terminal and the second input terminal of the second two-input MUX are connected and used as the second input terminal of the tap unit. The output terminals of the three tap units are respectively connected to the input terminals of the i1, i2, and i3 flip-flops through exclusive-OR gates, where 0 < i1 < n, 0 < i2 < n, 0 < i3 < n, and i1 ≠ i2 ≠ i3. In this embodiment, i1, i2, and i3 are 16, 32, and 48 respectively. Referring to Fig. 3(b), that is, the output terminals of the three second tap units G31 are respectively connected to the input terminals of the 16th, 32nd, and 48th flip-flops through exclusive-OR gates.

[0041] If the three tap units are different, the present invention connects the output terminals of the first tap unit, the second tap unit, and the third tap unit to the input terminals of the i1, i2, and i3 flip-flops through exclusive-OR gates respectively, where 0 < i1 < n, 0 < i2 < n, 0 < i3 < n, and i1 ≠ i2 ≠ i3. Referring to Fig. 3(a), in this embodiment, i1, i2, and i3 are 16, 32, and 48 respectively. That is, the output terminal of the first tap unit G15 is connected to the input terminal of the 16th flip-flop through an exclusive-OR gate, the output terminal of the second tap unit G31 is connected to the input terminal of the 32nd flip-flop through an exclusive-OR gate, and the output terminal of the third tap unit G47 is connected to the input terminal of the 48th flip-flop through an exclusive-OR gate.

[0042] Starting from the configuration of the taps, the present invention makes it change dynamically, so that the generated excitation has randomness, thus strengthening the anti-machine learning ability of the PUF circuit at the source. The configuration unit only uses a relatively symmetric structural unit composed of two multiplexers (two-input MUX) and an exclusive-OR gate, which can improve the circuit complexity without consuming too many resources. According to the tap unit, it can be obtained that this unit has four inputs, namely IN1, IN2, Sel1, and Sel2. Among them, IN1 accesses the value returned by the 64th-stage flip-flop, IN2 accesses the value of the PUF circuit response feedback, Sel1 accesses the value output by a PUF branch guided by the strict avalanche criterion (the SAC-PUF designed by the present invention), and Sel2 accesses the PUF branch that is completely symmetric to it. Sel1 and Sel2 can reflect the result differences generated by two symmetric SAC-PUF circuits. By extracting the influence of process deviation on the output of the PUF circuit, the randomness of the circuit is increased, and the anti-machine learning performance is improved.

[0043] Due to unavoidable process variations, the logic value obtained after passing through the PUF circuit may change. Introducing this random variation into the LFSR structure alters the LFSR's feedback coefficient. Furthermore, since IN2 is connected to the PUF circuit's response value, the excitation becomes scrambled. Compared to a single signal in an existing LFSR, this invention increases structural complexity. The tap selection is no longer constant (0 / 1), but changes with the four input signals. Each tap change leads to a change in the excitation, significantly improving resistance to machine learning.

[0044] To enable the tap unit to better serve its role in stimulating confusion, this invention adds the configuration unit at the 16th, 32nd, and 48th levels, consuming a total of 6 two-input MUXs and 3 XOR gates. This improves the randomness of the PUF with low resource overhead, making the uniformity of the output result basically approach the ideal value of 50%, and also has a good resistance to modeling attacks.

[0045] See Figure 6 This invention designs a SAC-PUF circuit based on a strict avalanche criterion. The XOR result of the output values ​​of the obfuscating circuits in the two SAC-PUF circuits, along with the output values ​​of the two obfuscating circuits, serves as the input to a multiplexer. The historical output value of the post-processing circuit is fed back to the selection port of the multiplexer. The XOR result of the outputs of the two multiplexers yields the current output value of the post-processing circuit. The obfuscating circuit of this invention is a combinational logic block (Obfuscate). The obfuscating circuit includes a first buffer, a second buffer, an inverter, a first AND gate, a second AND gate, a third AND gate, and an OR gate. The outputs of arbitrators D1 and D2 are connected to the inputs of the first and second buffers, respectively. The output of arbitrator D3 is connected to the input of the inverter. The output of the first buffer is connected to the first inputs of the first and second AND gates, respectively. The output of the second buffer is connected to the second inputs of the second and third AND gates, respectively. The output of the inverter is connected to the second input of the first AND gate and the first input of the third AND gate, respectively. The outputs of the first, second, and third AND gates are connected to the inputs of the OR gate, and the output of the OR gate serves as the output of the obfuscating circuit. The truth table for the confusion circuit is shown in Table 1: Table 1 Truth Table of the Confusion Circuit

[0046] Referring to Table 1, when the outputs X, Y, and Z of arbitrators D1, D2, and D3 are 0, 0, and 0 respectively, the output Out of the mixing circuit is 0; when the outputs of arbitrators D1, D2, and D3 are 0, 0, and 1 respectively, the output Out of the mixing circuit is 0; when the outputs of arbitrators D1, D2, and D3 are 0, 1, and 0 respectively, the output of the mixing circuit is 1; when the outputs of arbitrators D1, D2, and D3 are 0, 1, and 1 respectively, the output of the mixing circuit is 0; when the outputs of arbitrators D1, D2, and D3 are 1, 0, and 0 respectively, the output of the mixing circuit is 1; when the outputs of arbitrators D1, D2, and D3 are 1, 1, and 0 respectively, the output of the mixing circuit is 1; when the outputs of arbitrators D1, D2, and D3 are 1, 1, and 1 respectively, the output of the mixing circuit is 1. From the truth table, it can be concluded that the mixing circuit has good uniformity.

[0047] This invention proposes an enhanced APUF architecture based on the Strict Avalanche Criterion (SAC). This design utilizes a dual-path structure process deviation feature extraction mechanism to dynamically map path delay differences to the tap configuration space of a Linear Feedback Shift Register (LFSR), thereby realizing nonlinear perturbations in the excitation generation process.

[0048] Compared to existing APUF technologies, the SAC-PUF circuit of this invention only uses two more arbitrators (in this embodiment, the arbitrators are flip-flops) and one look-up table (LUT), resulting in a relatively good gain. Taking a 64-order SAC-PUF as an example, the impact of excitations at different positions on response flipping varies. Excitations at earlier positions have virtually no impact on response flipping, while those at later positions will definitely cause response flipping, the process of which is unpredictable. Only excitations at the middle positions have a probability of approximately 50% of causing response flipping. This invention uses a PUF circuit with improved performance, namely the SAC-PUF circuit, sacrificing two flip-flops and one look-up table. With such minimal resource consumption, the probability of response flipping at each excitation position approaching 50% is achieved, thus obtaining a better response result for the PUF branch.

[0049] See Figure 8This invention constructs a post-processing circuit composed of a dual-channel multiplexer and an XOR gate, further enhancing security features through a response obfuscation mechanism. The post-processing circuit includes a first XOR gate, a second XOR gate, a third two-input MUX, and a fourth two-input MUX. The output of the obfuscation circuit in the first SAC-PUF circuit is connected to the first input of the first XOR gate and the first input of the third two-input MUX, respectively. The output of the obfuscation circuit in the second SAC-PUF circuit is connected to the second input of the first XOR gate and the second input of the fourth two-input MUX, respectively. The output of the first XOR gate is connected to the second input of the third two-input MUX and the first input of the fourth two-input MUX, respectively. The outputs of the third and fourth two-input MUXs are connected to the first and second inputs of the second XOR gate, respectively. The output of the second XOR gate is connected to the control terminals of the third and fourth two-input MUXs and serves as the output of the post-processing circuit.

[0050] This invention processes the outputs of two SAC-PUF circuits to increase the randomness of the outputs and further enhance their resistance to machine learning. This is achieved by connecting the two response results generated by the preceding SAC-PUF branch to a circuit such as... Figure 8 The post-processing circuit shown makes the PUF structure no longer linear, thus further improving its resistance to machine learning. According to this unit structure, the result of XORing inputs A and B, along with themselves, serves as the input to a multiplexer. The previous response is fed back to the multiplexer's selection port, and their outputs are XORed to obtain different results. Due to the presence of the excitation confusion module and the symmetrical SAC-PUF branch module, the output response already has good characteristics. To further protect the circuit, when R is 0, the logic value of the B interface is selected; when R is 1, the logic value of the A interface is selected. From the truth table in Table 2, the final output 0s and 1s are evenly distributed, each accounting for 1 / 2. Since PUF uniformity is used to characterize whether the number of 0s and 1s in the PUF output response is uniform (theoretically 50%), the structure of this design should have good uniformity.

[0051] Table 2 Truth Table of Post-processing Circuit

[0052] Referring to Table 2, the output value A of the obfuscation circuit in the first SAC-PUF circuit and the output value B of the obfuscation circuit in the second SAC-PUF circuit are 0 and 0 respectively, and the historical output value R of the post-processing circuit is... pre When it is 0, the current output value R of the post-processing circuit after =0; A=0, B=0, R pre When =1, R after=0; A=0, B=1, R pre When =0, R after =1; A=0, B=1, R pre When =1, R after =0; A=1, B=0, R pre When =0, R after =0; A=1, B=0, R pre When =1, R after =1; A=1, B=1, R pre When =0, R after =1; A=1, B=1, R pre When =1, R after =1.

[0053] The post-processing unit adopts a symmetrical structure, using only two two-input MUXs and two XOR gates. Based on different output combinations of the two symmetrical SAC-PUFs and the output of the overall PUF circuit feedback, different response outputs are generated, thereby achieving good anti-machine learning performance. For four types of machine learning, it can be basically controlled between 50% and 60%, which is close to the ideal value of 50%.

[0054] Working principle: Referring to Figures 3(a) and 3(b), the overall workflow of the anti-machine learning attack circuit of the PUF of this invention is as follows: n=64. First, the proposed tap units are configured at the corresponding positions of the tap section of the LFSR at levels 16, 32, and 48 to obtain the ideal random feedback polynomial. For lightweight design, a total of 6 MUXs and 3 XOR gates are consumed at the three positions, eliminating the XOR gates in the connection tap section between each stage of the original LFSR, thus reducing the number of XOR gates used by 60 compared to the ideal state. Different results are output according to the different feedback polynomials, serving as the stimulus for inputting the SAC-PUF.

[0055] The excitation signal is then input to the SAC-PUF circuit. Theoretically, the symmetrical structure should be identical, and the results should be completely consistent. However, due to process variations, the output results become diverse, making the final output unpredictable and further enhancing the unpredictability of the excitation signal. This characteristic significantly improves the circuit's performance, making it difficult for attackers to compromise the system by analyzing the excitation signal, thus providing a more reliable guarantee for hardware security. The first-stage response is then processed in two steps: fed back to the tap unit of the LFSR and input into the next stage post-processing circuit.

[0056] Finally, the two intermediate responses are input to the post-processing circuit. Based on the result of the previous response, different branch structures are selected as the output, which realizes the selection of one of them as the final response of PUF in different time domains, greatly increasing the randomness of the response. Moreover, it only consumes two two-input MUX and two XOR gates, further realizing the lightweight feature.

[0057] The tap unit adopts a minimalist architecture, consisting of only two multiplexers (MUX) and one XOR gate, with no additional redundant logic. To ensure the randomness and uniformity of the stimulus sequence, the tap unit can be evenly deployed at the 16th, 32nd, and 48th nodes of a 64-level Galois-type LFSR. The entire LFSR module consumes only 6 MUX and 3 XOR gates. Compared to traditional fixed-tap LFSRs (which typically require more than 60 XOR gates to achieve end-to-end feedback), this directly reduces the resource overhead of 60 XOR gates, lowering hardware occupancy by over 90%, perfectly meeting the requirements of lightweight design.

[0058] The configuration logic of the tap unit is determined by three key signals: first, the process deviation quantization value output by the SAC-PUF branch, which is derived from the unavoidable circuit delay differences during chip manufacturing and possesses inherent non-cloning properties; second, the historical response feedback value of the entire PUF circuit, realizing a closed-loop correlation between stimulus generation and response output; and third, the return value of the 64th stage flip-flop of the LFSR, ensuring the temporal continuity of sequence generation. Under the combined effect of these three factors, the feedback polynomial of the LFSR is no longer fixed but dynamically changes with the chip's physical characteristics and historical responses. This allows the generated stimulus sequence to break through the linear law of traditional pseudo-random sequences, cutting off the attacker's path to model stimulus features at the source and significantly improving the underlying resistance to machine learning attacks.

[0059] This invention designs a SAC-PUF fine-grained process deviation extraction branch, which achieves accurate capture and random injection of deviation features with extremely low resource increment.

[0060] The SAC-PUF circuit, based on the traditional APUF, adds only two additional flip-flops and one lookup table (LUT), without large-scale circuit expansion. Its core feature is the strict avalanche criterion achieved through the cascading and obfuscating combination of three arbitrators. This means that when any excitation bit flips, the probability of the output response flipping strictly approaches 50%. Specifically, the three arbitrators correspond to signal paths of different lengths. After their outputs are obfuscated by the LUT, the linear defect of traditional APUFs—where "front-end excitation bits do not affect the response, and back-end excitation bits inevitably flip the response"—is eliminated, ensuring that the influence of each excitation bit on the response is equally weighted and randomized.

[0061] Meanwhile, the SAC-PUF circuit adopts a symmetrical PUF cell structure, using the process deviation difference between a pair of symmetrical cells as the selection input for the LFSR tap cell. During chip manufacturing, the path delay of the symmetrical cells will have slight differences due to process fluctuations such as photolithography and etching. This difference is quantified into 0 / 1 logic values ​​and injected into the LFSR tap configuration logic, which is equivalent to directly integrating the chip's "physical fingerprint" into the stimulus generation process. This not only strengthens the physical binding relationship between stimulus and response but also further improves the randomness of the response sequence. Testing showed that the uniformity of this branch output reached 50.49%, very close to the ideal threshold of 50%, providing a solid random foundation for subsequent resistance to machine learning attacks.

[0062] The post-processing circuit of this invention is a lightweight response obfuscation post-processing unit. Even if the front-end module implements randomization of the stimulus and response, the linear output characteristics of the traditional PUF may still be fitted by a machine learning model. To address this, this invention designs a symmetric minimalist response obfuscation post-processing unit, which breaks the linear correlation between the stimulus and response through nonlinear transformation, while maintaining the lightweight nature of the hardware.

[0063] This unit consists of only two MUXs and two XOR gates, with negligible overall hardware overhead. Its core logic is divided into two steps: First, it receives the dual intermediate responses A and B from the SAC-PUF branch outputs and performs an XOR operation on them to generate a basic confusing signal. Second, it introduces the historical response R of the PUF circuit as the selection control signal for the MUX. When the historical response R=0, the MUX selects signal B as the branch output, and when R=1, it selects signal A. Finally, it performs an XOR operation on the two MUX outputs again to obtain the final response.

[0064] This dual-layer obfuscation mechanism of "XOR operation + historical feedback routing" transforms the overall PUF structure from linear to nonlinear: on the one hand, the XOR operation inherently possesses data obfuscation capabilities, disrupting the original characteristics of intermediate responses; on the other hand, the feedback routing of historical responses enables dynamic switching of responses in different time domains, preventing attackers from constructing a fixed input-output mapping model using static CRP datasets. Experimental verification shows that, after this unit works in conjunction with the preceding modules, even on a large-scale dataset of 1 million CRPs, the prediction accuracy of four mainstream machine learning attacks—logistic regression (LR), support vector machine (SVM), deep neural network (DNN), and covariance matrix adaptive evolution strategy (CMA-ES)—is all below 60%, approaching the theoretical random guessing baseline of 50%, achieving a perfect balance between "lightweight hardware overhead" and "high-strength anti-attack capability."

[0065] See Figure 9This invention uses Verilog HDL for circuit design and Xilinx's ISEDesign Suite 14.7 integrated design environment for compiling and generating the FPGA bitstream file. The FPGA model is a Xilinx Artix-7 development board. The specific implementation modules are simplified as follows: Figure 9 As shown: The clock is generated by the FPGA's onboard clock through a clock IP core, providing power to the circuit. After passing through various modules of the circuit, it produces the final response. Using ISE software, a soft core needs to be configured. This soft core is embedded in the original circuit to control input / output and extract data. The soft core's operation requires C language control of the output data within the SDK, thus enabling data interaction. After the above process is completed, Python code is used to test the performance of the output response. For the output stimulus-response pairs, we re-integrate the data and, similar to performance measurement, run different types of machine learning test code to obtain their respective prediction rates.

[0066] Figures 10 to 15 The experimental results of this invention will be described below: Depend on Figure 10 It can be clearly seen that in the 10 collected groups, each group has approximately 50,000 0 and 50,000 1 responses out of 100,000, which is basically evenly distributed, close to the 50% threshold. The actual results are consistent with the theoretical results, and this scheme has good uniformity. Figure 11 It can be clearly seen that the normal distribution obtained by fitting the uniqueness of multiple sets of data obtained at different locations under the same excitation has a mean of 50.12 and a standard deviation of 0.55. Therefore, the average uniqueness is 50.12%, which is basically at the 50% level. Thus, the present invention has good uniqueness.

[0067] As shown in Figures 12(a) and 12(b), this test was conducted under different voltage and temperature conditions. Specifically, 11 sets of reliability data were tested under 11 different voltage conditions. The best reliability performance was observed near 1V, and the average reliability of the circuit was approximately 94%. Relevant reliability data measured under 9 different temperature conditions showed that the values ​​were basically in the range of 93% to 94%, indicating that the PUF circuit has excellent reliability.

[0068] like Figure 13 As shown, the test results indicate that within the 95% confidence interval, the ACF value of the proposed PUF is 0.02 (close to the ideal value of 0), which can be considered as the response tending to be completely random and uncorrelated. Therefore, the PUF proposed in this paper has good randomness.

[0069] Figures 14(a), 14(b), 14(c), and 14(d) represent the performance against four types of machine learning for 10 sets of responses under 5000, 10000, 50000, and 100000 CRPs, respectively. The CRPs were divided into training and test sets, with 70% used for training and 30% for testing. The figures show good performance against different types of machine learning. As the number of CRPs increases, the resistance to DNNs becomes increasingly significant. At 10000 sets, the resistance to various machine learning methods remained below 54.5%. Even at 100000 sets, the performance of each metric remained below 55.5%, approaching the theoretical random guess baseline (50%). This represents an average improvement of over 35% in resistance to attacks compared to traditional APUF schemes. Therefore, this design exhibits excellent resistance to machine learning.

[0070] like Figure 15 As shown, to clearly understand the extent to which machine learning changes with CRPs, Figure 15 The performance trend is shown: Notably, the design exhibits a significant improvement in its resistance to attacks from deep neural networks (DNNs) as the number of stimulus-response pairs (CRPs) increases. The variation of the proposed circuit design's resistance to attacks from four types of machine learning algorithms with the number of CRPs is shown below. Figure 15 As shown in the figure, the resistance to machine learning attacks is presented when the number of CRPs is 1000, 10000, 100000, and 1000000, respectively. Even when the number of CRPs increases to 1 million, its resistance to attacks against the four types of machine learning algorithms remains below 60%, fully demonstrating the excellent resistance to machine learning attacks of the proposed design.

[0071] As shown in Table 3, PUF Design represents the PUF design scheme, Uniformity represents uniformity, Uniqueness represents uniqueness, Reliability represents reliability, Prediction Accuracy represents prediction rate, Attack Mode represents attack mode, and Hardware Consumption represents hardware overhead. In the PUF design scheme, FF-APUF (Feed-Forward Arbiter Physical Unclonable Function) is a feed-forward arbiter physically unclonable function, MRO-MRO PUF is a two-stage ring oscillator PUF based on a multiplexer, CT PUF (Configurable Tristate PUF) is a configurable tristate PUF, DEMUX-TDC PUF is a multiplexer-to-time-to-digital converter PUF, LFSR-APUF is a linear feedback shift register-arbiter PUF, RSO PUF (Random Set-based Obfuscation, RSO) refers to a strong physically unclonable function enhanced by random set obfuscation technology, and DDQ-PUF (Quantized Delay Difference-based Arbiter Physical Unclonable Function) is a high-reliability arbiter-type physically unclonable function based on quantization delay difference.

[0072] In the attack methods, CMA-ES represents the covariance matrix adaptive evolution strategy, LR represents logistic regression, ANN represents artificial neural network, SVM represents support vector machine, and DNN represents deep neural network.

[0073] Table 3 shows the performance comparison and resource overhead of various PUFs: the uniformity of this invention is 50.49%, and the uniqueness is 50.12%, both approaching the ideal threshold of 50%, demonstrating excellent response distribution randomness and robust inter-device differentiation capability; its reliability under voltage variation conditions is 93.90%, and its reliability under temperature variation conditions is 93.31%, achieving a good balance between practicality and stability. In terms of security, the prediction accuracy of this scheme against various machine learning attacks ranges from 53.62% to 54.99%, confirming its strong resilience against machine learning attacks. Of particular note is that this invention only generates hardware overhead of 142 lookup tables (LUTs) and 70 flip-flops (DFFs), significantly lower than most comparative schemes. For example, the multiplexer-time-to-digital converter PUF (DEMUX-TDC PUF) requires 526 LUTs, while the linear feedback shift register-arbitrator PUF (LFSR-APUF) requires 383 LUTs. This makes the present invention a highly competitive solution, achieving an excellent balance between performance and hardware efficiency, and thus is very suitable for resource-constrained application scenarios.

[0074] Table 3 Performance comparison and resource consumption of the PUF of this invention and existing PUFs

[0075] This invention achieves a significant leap in resistance to machine learning with extremely low hardware overhead (only adding 6 MUXs and 3 XOR gates) through dynamic mapping of process deviations and lightweight nonlinear obfuscation. Experimental results show that it has significant advantages in the security authentication of resource-constrained devices (such as RFID tags and sensor nodes), providing a new solution to address increasingly complex hardware security threats.

[0076] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PUF circuit resistant to machine learning attacks, characterized in that: It includes two symmetric SAC-PUF circuits. Each SAC-PUF circuit includes an arbiter D1 and n path switching switches, where n is an integer greater than 0. The n control terminals of the n path switching switches are respectively connected to the values of n flip-flops. The output terminals of the j-th and k-th path switching switches are respectively connected to arbiters D3 and D2, where 0 ≤ j < n - 1, 0 ≤ k < n - 1, and j ≠ k. The output terminals of arbiters D1, D2, and D3 are connected to a confusion circuit. The output terminal of the confusion circuit in the first SAC-PUF circuit is respectively connected to the first control terminal of the tap unit and the first input terminal of the post-processing circuit. The output terminal of the confusion circuit in the second SAC-PUF circuit is respectively connected to the second control terminal of the tap unit and the second input terminal of the post-processing circuit. The output terminal of the post-processing circuit is connected to the second input terminal of each tap unit. The first input terminal of each tap unit is connected to the value of the n-th flip-flop. The output terminal of the tap unit is connected to the input terminal of the i-th flip-flop through a logic gate, where 0 < i < n.

2. The PUF anti-machine learning attack circuit according to claim 1, characterized in that: The tap unit includes an exclusive-OR gate and two two-input MUXes. The control terminals of the first two-input MUX and the second two-input MUX are respectively used as the first control terminal and the second control terminal of the tap unit. By configuring the input terminals of the two two-input MUXes, the first input terminal and the second input terminal of the tap unit are obtained. The output terminals of the two two-input MUXes are respectively connected to the exclusive-OR gate, and the output terminal of the exclusive-OR gate is used as the output terminal of the tap unit.

3. The PUF anti-machine learning attack circuit according to claim 2, characterized in that: The output terminals of three tap units are respectively connected to the input terminals of the i1-th, i2-th, and i3-th flip-flops through exclusive-OR gates, where 0 < i1 < n, 0 < i2 < n, 0 < i3 < n, and i1 ≠ i2 ≠ i3. The first and second input terminals of the first two-input MUX are connected together and used as the first input terminal of the tap unit. The first and second input terminals of the second two-input MUX are connected together and used as the second input terminal of the tap unit.

4. The anti-machine learning attack circuit according to claim 2, characterized in that: The three tap units are respectively the first tap unit, the second tap unit, and the third tap unit. The output terminals of the first, second, and third tap units are respectively connected to the input terminals of the i1-th, i2-th, and i3-th flip-flops through exclusive-OR gates, where 0 < i1 < n, 0 < i2 < n, 0 < i3 < n, and i1 ≠ i2 ≠ i3. In the first tap unit, the second input terminal of the first two-input MUX is connected to the second input terminal of the second two-input MUX and used as the first input terminal of the tap unit. The first input terminal of the first two-input MUX is connected to the first input terminal of the second two-input MUX and used as the second input terminal of the tap unit. In the second tap unit, the first and second input terminals of the first two-input MUX are connected together and used as the first input terminal of the tap unit. The first and second input terminals of the second two-input MUX are connected together and used as the second input terminal of the tap unit. In the third tap unit, the first input terminal of the first two-input MUX is connected to the first input terminal of the second two-input MUX and used as the first input terminal of the tap unit. The second input terminal of the first two-input MUX is connected to the second input terminal of the second two-input MUX and used as the second input terminal of the tap unit.

5. The PUF anti-machine learning attack circuit according to claim 3 or 4, characterized in that: n is 64, and the 64 flip-flops are connected end to end in sequence. i1, i2, and i3 are 16, 32, and 48 respectively, j is 28, and k is 43.

6. The anti-machine learning attack circuit according to claim 1, characterized in that: The XOR result of the output values ​​of the confusion circuits in the two SAC-PUF circuits and the output values ​​of the two confusion circuits are used as the input of the multiplexer. The historical output value of the post-processing circuit is fed back to the selection port of the multiplexer. The XOR result of the outputs of the two multiplexers is used to obtain the current output value of the post-processing circuit.

7. The anti-machine learning attack circuit according to claim 6, characterized in that: The output value A of the obfuscation circuit in the first SAC-PUF circuit and the output value B of the obfuscation circuit in the second SAC-PUF circuit are 0 and 0 respectively, and the historical output value R of the post-processing circuit is... pre When it is 0, the current output value R of the post-processing circuit after =0; A=0, B=0, R pre When =1, R after =0; A=0, B=1, R pre When =0, R after =1; A=0, B=1, R pre When =1, R after =0; A=1, B=0, R pre When =0, R after =0; A=1, B=0, R pre When =1, R after =1; A=1, B=1, R pre When =0, R after =1; A=1, B=1, R pre When =1, R after =1.

8. The anti-machine learning attack circuit according to claim 1, characterized in that: The post-processing circuit includes a first XOR gate, a second XOR gate, a third two-input MUX, and a fourth two-input MUX. The output of the obfuscation circuit in the first SAC-PUF circuit is connected to the first input of the first XOR gate and the first input of the third two-input MUX, respectively. The output of the obfuscation circuit in the second SAC-PUF circuit is connected to the second input of the first XOR gate and the second input of the fourth two-input MUX, respectively. The output of the first XOR gate is connected to the second input of the third two-input MUX and the first input of the fourth two-input MUX, respectively. The outputs of the third two-input MUX and the fourth two-input MUX are connected to the first and second inputs of the second XOR gate, respectively. The output of the second XOR gate is connected to the control terminals of the third and fourth two-input MUX and serves as the output of the post-processing circuit.

9. The anti-machine learning attack circuit according to claim 1, characterized in that: When the outputs X, Y, and Z of arbitrators D1, D2, and D3 are 0, 0, and 0 respectively, the output Out of the confusion circuit is 0; when X=0, Y=0, and Z=1, Out=0; when X=0, Y=1, and Z=0, Out=1; when X=0, Y=1, and Z=1, Out=0; when X=1, Y=0, and Z=0, Out=1; when X=1, Y=1, and Z=1, Out=1.

10. The anti-machine learning attack circuit according to claim 1, characterized in that: The confusing circuit includes a first buffer, a second buffer, an inverter, a first AND gate, a second AND gate, a third AND gate, and an OR gate. The outputs of arbitrators D1 and D2 are connected to the inputs of the first and second buffers, respectively. The output of arbitrator D3 is connected to the input of the inverter. The output of the first buffer is connected to the first inputs of the first and second AND gates, respectively. The output of the second buffer is connected to the second inputs of the second and third AND gates, respectively. The output of the inverter is connected to the second input of the first AND gate and the first input of the third AND gate, respectively. The outputs of the first, second, and third AND gates are connected to the inputs of the OR gate, and the output of the OR gate serves as the output of the confusing circuit.

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