Semiconductor structure and preparation method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method of the semiconductor structure, a memory and a storage system.The semiconductor structure comprises a stacking structure and a connecting structure, the stacking structure comprises insulating layers and gate layers which are alternately stacked, and the connecting structure comprises a conductive layer and a first isolation layer; the conductive layer extends in the stack structure along a first direction and is connected with a gate layer on one side of the conductive layer along the first direction, and the first isolation layer is located between the conductive layer and the stack structure along a direction intersecting with the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for fabricating semiconductor structures, memories, and memory systems. Background Technology

[0002] Memory is one of the most important components in electronic systems. Flash memory is an important type of memory. Flash memory (also known as flash storage) is characterized by its ability to retain stored information for extended periods without power, and it boasts advantages such as high integration density, fast access speed, and ease of erasing and rewriting, making it the mainstream non-volatile memory. Based on its structure, flash memory is divided into NOR flash memory and NAND flash memory. Compared to NOR flash memory, NAND flash memory offers higher cell density, achieving higher storage density, and also provides faster write and erase speeds. With significant advancements in semiconductor manufacturing processes, three-dimensional (3D) flash memory applications have emerged to pursue lower production costs per unit of storage cell, such as 3D NAND flash memory. Summary of the Invention

[0003] This application provides semiconductor structures, methods for fabricating semiconductor structures, memories, and storage systems that can at least partially solve the problems described above or other problems in the art.

[0004] This application provides a semiconductor structure, including a stacked structure and a connection structure. The stacked structure includes alternately stacked insulating layers and gate layers. The connection structure includes a conductive layer and a first isolation layer. The conductive layer extends in the stacked structure along a first direction and connects to a gate layer on one side of the conductive layer along the first direction. The first isolation layer is located between the conductive layer and the stacked structure along a direction intersecting the first direction.

[0005] In some embodiments, the semiconductor structure further includes a first support structure located in the stacked structure and on one side of the connection structure along a first direction.

[0006] In some embodiments, a connecting structure is located on one side of a plurality of first support structures along the opposite direction to the first direction; or, a connecting structure is located on one side of a first support structure along the opposite direction to the first direction.

[0007] In some embodiments, the material of the first support structure includes an insulating dielectric material.

[0008] In some implementations, the first support structure is in contact with a portion of the conductive layer.

[0009] In some embodiments, the connection structure further includes a second isolation layer located between the conductive layer and the first support structure; wherein, in the direction intersecting the first direction, the size of the second isolation layer is smaller than the size of the end of the conductive layer along the first direction.

[0010] In some embodiments, the second isolation layer extends along a first direction through the gate layer between the first support structure and the conductive layer.

[0011] In some embodiments, the semiconductor structure further includes a semiconductor layer located on one side of the stacked structure along a first direction; wherein the first support structure extends into the semiconductor layer.

[0012] In some implementations, the size of the first support structure is smaller than the size of the conductive layer in the direction intersecting the first direction.

[0013] In some embodiments, the distance in the first direction from the surface of the conductive layer on the side opposite to the first direction to the surface of the stacked structure on the side of the first direction is greater than the distance in the first direction from the surface of the first insulating layer on the side opposite to the first direction to the surface of the stacked structure on the side of the first direction.

[0014] In some embodiments, the semiconductor structure further includes an isolation structure located on the side of the connection structure along a second direction and extending through the stacked structure along a first direction; wherein the second direction intersects the first direction.

[0015] In some embodiments, relative to the surface of the stacked structure along the first direction, in the first direction, the height of the surface of the isolation structure along the opposite direction is between the height of the surface of the first isolation layer along the opposite direction and the height of the surface of the conductive layer along the opposite direction.

[0016] In some embodiments, the sidewalls of the isolation structure along both sides of the second direction are wavy.

[0017] In some embodiments, the semiconductor structure further includes a second support structure located between the connection structure and the isolation structure in a second direction and penetrating the stacked structure along the first direction.

[0018] In some embodiments, the material of the second support structure includes an insulating dielectric material.

[0019] In some embodiments, the semiconductor structure further includes a channel structure located on the side of the interconnect structure along a third direction and penetrating the stacked structure along a first direction; wherein the third direction intersects the first direction.

[0020] This application also provides a method for fabricating a semiconductor structure, comprising: forming a stacked structure; forming a connection structure; wherein the stacked structure includes alternately stacked insulating layers and gate layers; wherein the connection structure includes: a conductive layer extending in the stacked structure along a first direction and connected to a gate layer connection along the first direction on one side of the conductive layer; and a first isolation layer located between the conductive layer and the stacked structure along a direction intersecting the first direction.

[0021] In some embodiments, forming a stacked structure includes: forming an initial stacked structure, the initial stacked structure including alternating layers of insulating layers and sacrificial dielectric layers; and replacing the sacrificial dielectric layers with gate layers to form a stacked structure; wherein forming a connection structure includes: forming a first opening extending in a first direction in the initial stacked structure; forming a first isolation layer on the sidewall of the first opening; forming a first sacrificial layer in the first opening; removing the first sacrificial layer in response to replacing the sacrificial dielectric layer with a gate layer; and forming a conductive layer in the first opening in response to removing the first sacrificial layer.

[0022] In some embodiments, forming a first isolation layer on the sidewall of the first opening includes: forming an initial isolation layer on the sidewall of the first opening and an inner wall of the first opening along a first direction; and etching a portion of the initial isolation layer located on the inner wall of the first opening along the first direction to expose a gate layer located on the first opening along the first direction, wherein the portion of the initial isolation layer located on the sidewall of the first opening forms the first isolation layer.

[0023] In some embodiments, etching a portion of the inner wall of the initial isolation layer located on the side of the first opening along the first direction includes: etching away a portion of the inner wall of the initial isolation layer located on the side of the first opening along the first direction, with the remaining portion of the initial isolation layer located on the side of the first opening along the first direction forming a second isolation layer; or, etching away the entire inner wall of the initial isolation layer located on the side of the first opening along the first direction.

[0024] In some implementations, a first isolation layer is formed on the sidewall of the first opening before the first sacrificial layer is formed.

[0025] In some embodiments, an initial isolation layer is formed before the first sacrificial layer is formed; after the first sacrificial layer is removed, the portion of the initial isolation layer located on the inner wall of the first opening along the first direction is etched.

[0026] In some embodiments, the preparation method further includes: forming a first support structure, the first support structure being located in the stacked structure and on one side of the connecting structure along a first direction.

[0027] In some embodiments, forming the first support structure includes: forming a first initial support structure that penetrates the initial stacked structure along a first direction; and removing a portion of the first initial support structure, with the remaining first initial support structure forming the first support structure; wherein, during the process of forming the first opening, a portion of the first initial support structure is removed.

[0028] In some embodiments, the preparation method further includes: forming an isolation structure located on the side of the connecting structure along a second direction and penetrating the stacked structure along a first direction; wherein the second direction intersects the first direction.

[0029] In some embodiments, forming an isolation structure includes: forming a second sacrificial layer that penetrates the initial stacked structure along a first direction, and a plurality of second sacrificial layers being spaced apart along a third direction; removing the second sacrificial layers to form an isolation groove extending along a third direction; and forming an isolation structure in the isolation groove.

[0030] In some embodiments, the preparation method further includes: forming a second support structure, the second support structure being located in a second direction between the connecting structure and the isolation structure and penetrating the stacked structure along the first direction.

[0031] In some embodiments, the preparation method further includes: forming a channel structure located on the side of the connecting structure along a third direction and penetrating the stacked structure along a first direction; wherein the third direction intersects with the first direction.

[0032] In some embodiments, a connecting structure is located on one side of a plurality of first support structures along the opposite direction to the first direction; or, a connecting structure is located on one side of a first support structure along the opposite direction to the first direction.

[0033] This application also provides a memory, including a memory cell array and peripheral circuitry. The memory cell array includes a semiconductor structure as described in any of the embodiments above, and the peripheral circuitry is coupled to the memory cell array.

[0034] In another aspect, this application provides a storage system, including a controller and a memory as mentioned in any of the embodiments above, wherein the controller is coupled to the memory and is used to control the memory to store data. Attached Figure Description

[0035] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0036] Figure 1 This is a view of a semiconductor structure according to an embodiment of this application along a first direction;

[0037] Figure 2 For along Figure 1 A cross-sectional view of tangent lines M2-N2 and M1-N1;

[0038] Figure 3 For along Figure 1 Another cross-sectional view of the tangent lines M2-N2 and M1-N1;

[0039] Figure 4 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;

[0040] Figures 5 to 19 This is a structural diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of this application;

[0041] Figure 20 This is a schematic diagram of the structure of a memory according to an exemplary embodiment of this application;

[0042] Figure 21 A block diagram of a system having a storage system according to an exemplary embodiment of this application; and

[0043] Figure 22 This is a schematic diagram of a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0044] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0046] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0047] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0048] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0049] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0050] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0051] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0052] This application provides a semiconductor structure 1000 in some embodiments. Figure 1 This is a view of a semiconductor structure 1000 according to one embodiment of this application along the first direction Z. To facilitate illustrating the positional relationship between the connecting structure 220, the first support structure 230, and the second support structure 210, the connecting structure 220, the first support structure 230, and the second support structure 210 are shown in the diagram. Figure 1 middle. Figure 2 For along Figure 1 A cross-sectional view of the tangent lines M2-N2 and M1-N1.

[0053] Figure 3 For along Figure 1 Another cross-sectional view of the tangent lines M2-N2 and M1-N1. Figure 2The diagram of the left-hand area is along Figure 1 Cross-sectional view of the tangent line M2-N2. Figure 2 The diagram of the right-hand area is along Figure 1 Cross-sectional view of the cutting line M1-N1. Figure 3 The diagram of the left-hand area is along Figure 1 Cross-sectional view of the tangent line M2-N2. Figure 3 The diagram of the right-hand area is along Figure 1 Cross-sectional view of the cutting line M1-N1.

[0054] Reference Figure 1 , Figure 2 and Figure 3 The semiconductor structure 1000 includes a stacked structure D and a connection structure 220.

[0055] Reference Figure 2 and Figure 3 The stacked structure D includes alternating layers of insulating layer 212 and gate layer 211. Exemplarily, the insulating layer 212 and gate layer 211 are alternately stacked along a first direction Z.

[0056] Reference Figure 2 and Figure 3 The connection structure 220 includes a conductive layer 222 and a first isolation layer 221. The conductive layer 222 extends along a first direction Z in the stacked structure D and connects to a gate layer 211 along the first direction Z on one side of the conductive layer 222. The first isolation layer 221 is located between the conductive layer 222 and the stacked structure D in a direction intersecting the first direction Z. For example, the first isolation layer 221 is located between the conductive layer 222 and the insulating layer 212 and between the conductive layer 222 and the gate layer 211 in a direction intersecting the first direction Z.

[0057] In at least one embodiment of this application, the conductive layer 222 is connected to a gate layer 211 along the first direction Z on one side of the conductive layer 222, which simplifies the semiconductor structure, reduces cost, and reduces the connection resistance between the conductive layer 222 and the gate layer 211.

[0058] Furthermore, as the demand for storage capacity in semiconductor structure 1000 continues to increase, the number of stacked layers in stacked structure D gradually increases. Stacked structure D may include multiple sub-stacked structures formed using techniques such as dual-stack or multi-stack. The number of stacked layers in each sub-stacked structure may be the same or different. The stacked structure D described below can be applied entirely or partially to structures composed of multiple sub-stacked structures, therefore related or similar content will not be repeated.

[0059] In some embodiments, the gate layer 211 is made of a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide; this application does not limit the specific materials used. For example, the gate layer 211 is made of a combination of titanium nitride and tungsten.

[0060] In some embodiments, the insulating layer 212 is made of an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0061] Furthermore, the number of insulating layer 212 and the number of gate layer 211 are not limited to... Figure 2 and Figure 3 The number of layers shown can be set separately as needed.

[0062] In some embodiments, the conductive layer 222 is made of a conductive material, which may include any one or a combination of a conductive metal material and a doped semiconductor material. The conductive metal material may be, for example, tungsten, cobalt, copper, aluminum, or titanium nitride, and the doped semiconductor material may be, for example, doped crystalline silicon or a silicide. This application does not limit the specific materials used. For example, the conductive layer 222 may be made of a combination of titanium nitride and tungsten.

[0063] In some embodiments, the material of the first insulating layer 221 is an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0064] In some embodiments, the semiconductor structure 1000 further includes a first support structure 230, which is located in the stacked structure D and on one side of the connection structure 220 along the first direction Z.

[0065] In some embodiments, the material of the first support structure 230 includes an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0066] In some implementations, reference Figure 1 A connecting structure 220 is located on one side of the plurality of first support structures 230 along a direction opposite to the first direction Z. It should be noted that... Figure 2 and Figure 3 For the sake of simplification, only one first support structure 230 is shown, and does not represent the actual number of first support structures 230.

[0067] In other embodiments, a connecting structure 220 is located on the side of a first support structure 230 opposite to the first direction Z; in other words, the connecting structure 220 corresponds one-to-one with the first support structure 230.

[0068] In some implementations, reference Figure 3 The first support structure 230 is in contact with a portion of the conductive layer 222.

[0069] In some implementations, reference Figure 2 The connection structure 220 also includes a second isolation layer 223, which is located between the conductive layer 222 and the first support structure 230; wherein, in the direction intersecting the first direction Z, the size of the second isolation layer 223 is smaller than the size of the end of the conductive layer 222 along the first direction Z.

[0070] For example, in the second direction X, the size of the second insulating layer 223 is smaller than the size of the end of the conductive layer 222 along the first direction Z; in the third direction Y, the size of the second insulating layer 223 is smaller than the size of the end of the conductive layer 222 along the first direction Z.

[0071] The second direction X intersects the first direction Z; for example, the second direction X is perpendicular to the first direction Z. The third direction Y intersects the first direction Z; for example, the third direction Y is perpendicular to the first direction Z. The third direction Y intersects the second direction X; for example, the third direction Y is perpendicular to the second direction X.

[0072] In some embodiments, the material of the second isolation layer 223 is the same as that of the first support structure 230, and there is no obvious boundary between the second isolation layer 223 and the first support structure 230.

[0073] In other embodiments, the material of the second isolation layer 223 is different from the material of the first support structure 230.

[0074] In some embodiments, the material of the second insulating layer 223 includes an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0075] In some implementations, the second isolation layer 223 and the first isolation layer 221 are made of the same material.

[0076] In some implementations, reference Figure 2 The second isolation layer 223 penetrates the gate layer 211 between the first support structure 230 and the conductive layer 222 along the first direction Z.

[0077] In one embodiment, the dimension of the second isolation layer 223 in the first direction Z is equal to the dimension of a gate layer 211 in the first direction Z.

[0078] In other embodiments, the size of the second isolation layer 223 in the first direction Z is smaller than the size of the gate layer 211 in the first direction Z.

[0079] In some implementations, reference Figure 2 and Figure 3 The semiconductor structure 1000 also includes a semiconductor layer 100, which is located on one side of the stacked structure D along the first direction Z; wherein the first support structure 230 extends to the semiconductor layer 100.

[0080] In some embodiments, the material of the semiconductor layer 100 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0081] In some embodiments, the size of the first support structure 230 is smaller than the size of the conductive layer 222 in the direction intersecting the first direction Z. For example, in the second direction X, the size of the first support structure 230 is smaller than the size of the conductive layer 222; in the third direction Y, the size of the first support structure 230 is smaller than the size of the conductive layer 222.

[0082] In some implementations, reference Figure 2 The distance d1 from the surface of the conductive layer 222 along the side opposite to the first direction Z to the surface of the stacked structure D along the first direction Z is greater than the distance d2 from the surface of the first insulating layer 221 along the side opposite to the first direction Z to the surface of the stacked structure D along the first direction Z. It should be noted that the relationship between d1 and d2 can be set... Figure 3 middle.

[0083] In some implementations, reference Figure 1 , Figure 2 and Figure 3 The semiconductor structure 1000 also includes an isolation structure 200, which is located on the side of the connection structure 220 along the second direction X and extends through the stacked structure D along the first direction Z. The isolation structure 200 may extend into the semiconductor layer 100. The isolation structure 200 extends along the third direction Y.

[0084] In some implementations, reference Figure 2 and Figure 3 The isolation structure 200 includes a semiconductor isolation layer 202 and an insulating isolation layer 201. The insulating isolation layer 201 is located on one side of the semiconductor isolation layer 202 along the first direction Z and on the sidewall of the semiconductor isolation layer 202. The semiconductor isolation layer 202 is made of a semiconductor material, such as polycrystalline silicon or doped polycrystalline silicon. The insulating isolation layer 201 is made of an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0085] In other embodiments, the material of the isolation structure 200 is an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide.

[0086] In some embodiments, the sidewalls of the isolation structure 200 along both sides of the second direction X are wavy.

[0087] In other embodiments, the sidewalls of the isolation structure 200 along both sides of the second direction X are planar.

[0088] In some implementations, reference Figure 2 Relative to the surface of the stacked structure D along the first direction Z, in the first direction Z, the height d3 of the surface of the isolation structure 200 along the opposite direction Z is between the height d2 of the surface of the first isolation layer 221 along the opposite direction Z and the height d1 of the surface of the conductive layer 222 along the opposite direction Z. It should be noted that the relative values ​​of d3, d2, and d1 can also be set... Figure 3 middle.

[0089] In some embodiments, the semiconductor structure 1000 further includes a channel structure 240 located on the side of the connection structure 220 along the third direction Y and penetrating the stacked structure D along the first direction Z.

[0090] In some embodiments, the channel structure 240 includes a channel layer, a functional layer, and a filling dielectric layer extending along a first direction Z. The channel structure 240 also includes a channel plug. The channel layer is located between the functional layer and the filling dielectric layer, and the channel plug is located on the side of the filling dielectric layer opposite to the first direction Z, and is connected to the channel layer. Exemplarily, the channel plug is located on the side of the filling dielectric layer opposite to the semiconductor layer 100. The functional layer includes a barrier layer, a charge trapping layer, and a tunneling layer. The barrier layer, charge trapping layer, and tunneling layer all extend along the first direction Z. The charge trapping layer is located between the barrier layer and the tunneling layer, and the tunneling layer is located between the charge trapping layer and the channel layer.

[0091] In some implementations, reference Figure 1 , Figure 2 and Figure 3 The semiconductor structure 1000 also includes a second support structure 210, which is located between the connection structure 220 and the isolation structure 200 in the second direction X and passes through the stacked structure D in the first direction Z.

[0092] It should be noted that the reference Figure 1A portion of the second support structure 210 is located between the connecting structure 220 and the isolation structure 200 in the second direction X. Another portion of the second support structure 210 is located between adjacent connecting structures 220 in the third direction Y. Another portion of the second support structure 210 is located between the connecting structure 220 and the channel structure 240 in the third direction Y. Another portion of the second support structure 210 is located between adjacent connecting structures 220 in the second direction X.

[0093] In some embodiments, the material of the second support structure 210 includes an insulating dielectric material.

[0094] Another embodiment of this application provides a method for fabricating a semiconductor structure, see reference. Figure 4 ,include:

[0095] Step S1: Form a stacked structure;

[0096] Step S2: Form the connection structure;

[0097] The stacked structure includes alternating layers of insulating layers and gate layers; the connection structure includes a conductive layer and a first isolation layer, the conductive layer extends in the stacked structure along a first direction and is connected to a gate layer on one side of the conductive layer along the first direction, and the first isolation layer is located between the conductive layer and the stacked structure along a direction intersecting the first direction.

[0098] In some embodiments, forming a stacked structure includes: forming an initial stacked structure comprising alternating layers of insulating layers and sacrificial dielectric layers; and replacing the sacrificial dielectric layers with gate layers to form the stacked structure.

[0099] In some embodiments, forming the interconnect structure includes: forming a first opening extending in a first direction in an initial stacked structure; forming a first isolation layer on the sidewall of the first opening; forming a first sacrificial layer in the first opening; removing the first sacrificial layer in response to replacing the sacrificial dielectric layer with a gate layer; and forming a conductive layer in the first opening in response to removing the first sacrificial layer.

[0100] In some embodiments, forming a first isolation layer on the sidewall of the first opening includes: forming an initial isolation layer on the sidewall of the first opening and an inner wall of the first opening along a first direction; and etching a portion of the initial isolation layer located on the inner wall of the first opening along the first direction to expose a gate layer located on the first opening along the first direction, wherein the portion of the initial isolation layer located on the sidewall of the first opening forms the first isolation layer.

[0101] In some embodiments, the method for fabricating the semiconductor structure further includes: forming an isolation structure located on the side of the interconnect structure along a second direction and penetrating the stacked structure along a first direction. Forming the isolation structure includes: forming a second sacrificial layer penetrating the initial stacked structure along the first direction, with a plurality of second sacrificial layers spaced apart along a third direction; removing the second sacrificial layers to form an isolation trench extending along the third direction; and forming the isolation structure in the isolation trench.

[0102] In some embodiments, the method for fabricating the semiconductor structure further includes: forming a channel structure located on the side of the interconnect structure along a third direction and penetrating the stacked structure along a first direction. Forming the channel structure includes: forming a channel sacrificial structure that penetrates the initial stacked structure along the first direction; and replacing the channel sacrificial structure with the channel structure.

[0103] In some embodiments, the method for fabricating the semiconductor structure further includes: forming a first support structure, the first support structure being located in the stacked structure and on one side of the connection structure along a first direction. Forming the first support structure includes: forming a first initial support structure, the first initial support structure penetrating the initial stacked structure along the first direction; and removing a portion of the first initial support structure, with the remaining first initial support structure forming the first support structure; wherein, during the formation of the first opening, a portion of the first initial support structure is removed.

[0104] The following is combined Figures 5 to 19 This section provides a detailed introduction to the fabrication process of semiconductor structures.

[0105] Reference Figure 5 and Figure 6 , Figure 6 for Figure 5 Cross-sectional views of tangent lines M1-N1 and M2-N2. Figure 6 The diagram showing the left-hand area is a cross-sectional view along the cutting line M2-N2. Figure 6 The diagram of the right-hand region is a cross-sectional view along the cutting line M1-N1, forming an initial stacked structure D1. For example, the initial stacked structure D1 is formed on the side of the substrate 100a opposite to the first direction Z. The initial stacked structure D1 includes alternating layers of insulating layer 212 and sacrificial dielectric layer 211a.

[0106] In some embodiments, the process for forming the insulating layer 212 is a deposition process, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The process for forming the sacrificial dielectric layer 211a includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0107] In some embodiments, the materials of the insulating layer 212 and the sacrificial dielectric layer 211a are different. During the subsequent removal of the sacrificial dielectric layer 211a, the sacrificial dielectric layer 211a has a higher etching selectivity than the insulating layer 212, thereby ensuring that the insulating layer 212 has a good morphology and accurate dimensions, which in turn makes the gate layer formed subsequently have a good morphology and accurate dimensions.

[0108] In some embodiments, the material of the sacrificial dielectric layer 211a may be silicon nitride, amorphous carbon, or polycrystalline silicon, and the material of the insulating layer 212 may include silicon oxide.

[0109] In some implementations, in conjunction with reference Figure 5 and Figure 6 The method for fabricating the semiconductor structure further includes: forming a second sacrificial layer 200a, the second sacrificial layer 200a penetrating the initial stacked structure D1 along the first direction Z, and multiple second sacrificial layers 200a being arranged at intervals along the third direction Y.

[0110] In some embodiments, the material of the second sacrificial layer 200a may be amorphous carbon or polycrystalline silicon.

[0111] In some embodiments, forming the second sacrificial layer 200a includes: forming an isolation via located in the initial stacked structure D1; and forming the second sacrificial layer 200a in the isolation via. The process for forming the isolation via is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the second sacrificial layer 200a in the isolation via includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0112] In other embodiments, forming the initial stacked structure D1 includes forming a plurality of sub-initial stacked structures stacked along a first direction. Forming the second sacrificial layer 200a includes forming a plurality of second sub-sacrificial layers stacked along the first direction Z. Forming the second sub-sacrificial layers includes forming sub-isolation vias in the sub-initial stacked structures and forming the second sub-sacrificial layers in the sub-isolation vias. The process for forming the sub-isolation vias is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the second sub-sacrificial layers in the sub-isolation vias includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0113] In some implementations, in conjunction with reference Figure 5 and Figure 6 The method for fabricating a semiconductor structure further includes: forming a first initial support structure 230a, the first initial support structure 230a penetrating the initial stacked structure D1 along the first direction Z; forming a second support structure 210, the second support structure 210 penetrating the initial stacked structure D1 along the first direction Z.

[0114] In some embodiments, the second support structure 210 is located around the side of the first initial support structure 230a in the direction intersecting the first direction Z.

[0115] The material of the second support structure 210 is as described in the aforementioned embodiment. The material of the first initial support structure 230a is as described in the aforementioned embodiment of the first support structure.

[0116] In some implementations, the second support structure 210 is formed during the formation of the first initial support structure 230a, which simplifies the process.

[0117] In other embodiments, the second support structure 210 is formed after the first initial support structure 230a is formed, or the first initial support structure 230a is formed after the second support structure 210 is formed.

[0118] In some embodiments, forming the first initial support structure 230a includes: forming a first hole penetrating the initial stacked structure D1; and forming the first initial support structure 230a within the first hole. The process for forming the first hole is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the first initial support structure 230a within the first hole includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0119] In other embodiments, forming the first initial support structure 230a includes: forming a plurality of first sub-initial support structures stacked along a first direction Z. Forming the first sub-initial support structure includes: forming a first sub-via in the sub-initial stacked structure; and forming a first sub-initial support structure in the first sub-via. The process for forming the first sub-via is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the first sub-initial support structure in the first sub-via includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0120] In some embodiments, forming the second support structure 210 includes: forming a second via penetrating the initial stacked structure D1; and forming the second support structure 210 within the second via. The process for forming the second via is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the second support structure 210 within the second via includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0121] In other embodiments, forming the second support structure 210 includes forming a plurality of second sub-support structures stacked along a first direction Z. Forming the second sub-support structure includes forming a second sub-via in the initial sub-stack structure; and forming a second sub-support structure in the second sub-via. The process for forming the second sub-via is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the second sub-support structure in the second sub-via includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0122] In some implementations, in conjunction with reference Figure 5 and Figure 6 The method for fabricating the semiconductor structure also includes: forming a channel sacrificial structure 240a, wherein the channel sacrificial structure 240a penetrates the initial stacked structure D1 along the first direction Z.

[0123] In some embodiments, forming the channel sacrificial structure 240a includes: forming a channel via penetrating the initial stacked structure D1 along a first direction Z; and forming the channel sacrificial structure 240a within the channel via. The process for forming the channel via is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the channel sacrificial structure 240a within the channel via includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0124] In other embodiments, forming the channel sacrificial structure 240a includes forming a plurality of sub-channel sacrificial structures stacked along a first direction Z. Forming the sub-channel sacrificial structure includes forming sub-channel vias in the initial sub-stacking structure; and forming sub-channel sacrificial structures within the sub-channel vias. The process for forming the sub-channel vias is an etching process, including one or a combination of dry etching and wet etching processes. The process for forming the sub-channel sacrificial structures within the sub-channel vias includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0125] In some implementations, the material of the channel sacrificial structure 240a can be amorphous carbon or polycrystalline silicon.

[0126] refer to Figure 7 , Figure 7 In order to be in Figure 6 Based on the schematic diagram, the channel sacrificial structure 240a is removed to form the channel hole 2401.

[0127] The process for removing the channel sacrificial structure 240a is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0128] refer to Figure 8 A channel structure 240 is formed in the channel hole 2401.

[0129] The structural description of the channel structure 240 is as described in the aforementioned implementation method.

[0130] refer to Figure 9 A first opening 2201 extending along the first direction Z is formed in the initial stacked structure D1. During the formation of the first opening 2201, a portion of the first initial support structure 230a is removed, and the remaining first initial support structure 230a forms the first support structure 230.

[0131] In some embodiments, the method for fabricating the semiconductor structure further includes: forming a first dielectric layer 2501 on the side of the initial stacked structure D1 facing away from the substrate 100a, wherein the first dielectric layer 2501 further covers the channel structure 240, the second support structure 210, the first initial support structure 230a, and the second sacrificial layer 200a. The formation of a first opening 2201 extending along the first direction Z in the initial stacked structure D1 includes: forming the first opening 2201 extending along the first direction Z in both the first dielectric layer 2501 and the initial stacked structure D1.

[0132] The material of the first dielectric layer 2501 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0133] In some embodiments, the process of forming the first dielectric layer 2501 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0134] In some embodiments, the process of forming the first opening 2201 is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0135] In some embodiments, forming the first opening 2201 includes: forming a first sub-opening, the first sub-opening extending along a first direction Z in the first dielectric layer 2501 and a portion of the initial stacked structure D1; removing a portion of the first initial support structure 230a during the formation of the first sub-opening; etching away a portion of the first initial support structure 230a on one side of the first sub-opening along the first direction Z; forming a second sub-opening on one side of the first sub-opening along the first direction Z; the size of the second sub-opening in the direction intersecting the first direction Z is smaller than the size of the first sub-opening in the direction intersecting the first direction Z. For example, the size of the second sub-opening in the second direction X is smaller than the size of the first sub-opening in the second direction X, and the size of the second sub-opening in the third direction Y is smaller than the size of the first sub-opening in the third direction Y.

[0136] In some embodiments, before the second sub-opening is formed, the bottom surface of the first sub-opening along the Z side of the first direction exposes a sacrificial dielectric layer 211a or an insulating layer 212. Figure 9 As an example, before the second sub-opening is formed, the bottom surface of the first sub-opening along the Z-side of the first direction exposes a sacrificial dielectric layer 211a, and the second sub-opening is located in a sacrificial dielectric layer 211a. When, before the second sub-opening is formed, the bottom surface of the first sub-opening along the Z-side of the first direction exposes an insulating layer 212, the second sub-opening is located in a sacrificial dielectric layer 211a and an insulating layer 212.

[0137] In some embodiments, the second sub-opening may extend through the sacrificial medium layer 211a between the first support structure 230 and the first sub-opening.

[0138] In some implementations, the first sub-aperture and the second sub-aperture are formed by continuous etching in a single etching process.

[0139] refer to Figure 10 An initial isolation layer 221a is formed on the sidewall of the first opening 2201 and on the inner wall of the first opening 2201 along the first direction Z. For example, the initial isolation layer 221a is formed on the sidewall of the first sub-opening, on the inner wall of the first sub-opening along the first direction Z, and in the second sub-opening.

[0140] In some embodiments, the process of forming the initial isolation layer 221a includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0141] The material of the initial isolation layer 221a is the same as that of the first isolation layer in the aforementioned embodiment.

[0142] refer to Figure 11 A first sacrificial layer 222a is formed in the first opening 2201.

[0143] In some embodiments, the material of the first sacrificial layer 222a may be polycrystalline silicon or amorphous carbon.

[0144] In some embodiments, the process of forming the first sacrificial layer 222a includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0145] refer to Figure 12 A second dielectric layer 2502 is formed on the side of the first dielectric layer 2501 away from the initial stacked structure D1. For example, after the first sacrificial layer 222a is formed, the second dielectric layer 2502 is formed, and the second dielectric layer 2502 also covers the first sacrificial layer 222a and the second sacrificial layer 200a. The second sacrificial layer 200a is removed to form an isolation groove 2001 extending in the third direction Y. For example, multiple second sacrificial layers 200a arranged in the third direction Y are removed to form an isolation groove 2001 extending in the third direction Y.

[0146] It should be noted that during the removal of the multiple second sacrificial layers 200a arranged along the third direction Y, the size of the isolation holes used to accommodate the second sacrificial layers 200a is enlarged along the third direction Y, so that the multiple isolation holes arranged along the third direction Y are connected, and the multiple connected isolation holes form an isolation groove 2001.

[0147] In some embodiments, the material of the second dielectric layer 2502 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0148] In some embodiments, the process of forming the second dielectric layer 2502 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0149] In some embodiments, the process for removing the second sacrificial layer 200a is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0150] In some embodiments, during the removal of the second sacrificial layer 200a, portions of the first dielectric layer 2501 and the second dielectric layer 2502 located on the side of the second sacrificial layer 200a opposite to the first direction Z are also removed, and the isolation groove 2001 is located in the initial stack structure D1, the second dielectric layer 2502 and the first dielectric layer 2501.

[0151] refer to Figure 13 The sacrificial dielectric layer 211a is replaced with the gate layer 211. The gate layer 211 and the insulating layer 212 constitute a stacked structure D.

[0152] refer to Figure 14 An isolation structure 200 is formed in the isolation groove 2001. The isolation structure 200 extends along the third direction Y.

[0153] In some implementations, reference Figure 14 The formation of the isolation structure 200 includes: forming an insulating isolation layer 201 on the inner wall of the isolation trench 2001; after forming the insulating isolation layer 201, forming a semiconductor isolation layer 202 in the isolation trench 2001, wherein the insulating isolation layer 201 is located on one side of the semiconductor isolation layer 202 along the first direction Z and on the side wall of the semiconductor isolation layer 202.

[0154] In some embodiments, the process for forming the insulating isolation layer 201 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof. The process for forming the semiconductor isolation layer 202 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0155] The materials of the semiconductor isolation layer 202 and the insulating isolation layer 201 are as described in the aforementioned embodiments.

[0156] In other embodiments, the material of the isolation structure 200 is an insulating dielectric material, such as silicon oxide, silicon oxynitride, or silicon oxycarbide. The process for forming the isolation structure 200 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0157] refer to Figure 15 A third dielectric layer 2503 is formed on the side of the second dielectric layer 2502 that is away from the stacked structure D.

[0158] In some embodiments, the material of the third dielectric layer 2503 is an insulating dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0159] In some embodiments, the process of forming the third dielectric layer 2503 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0160] The third dielectric layer 2503, the second dielectric layer 2502 and the first dielectric layer 2501 constitute the dielectric structure 250.

[0161] refer to Figure 16 In response to replacing the sacrificial dielectric layer 211a with the gate layer 211, the first sacrificial layer 222a is removed.

[0162] In some embodiments, the process for removing the first sacrificial layer 222a is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0163] In some embodiments, after the third dielectric layer 2503 is formed, the first sacrificial layer 222a is removed.

[0164] In some embodiments, before removing the first sacrificial layer 222a, the portion of the dielectric structure 250 located on the side of the first sacrificial layer 222a away from the stacked structure D is also removed.

[0165] refer to Figure 17 The portion of the inner wall of the initial isolation layer 221a located on the side of the first opening 2201 along the first direction Z is etched to expose a gate layer located on the side of the first opening 2201 along the first direction Z, wherein the portion of the initial isolation layer 221a located on the side wall of the first opening 2201 forms the first isolation layer 221.

[0166] In some embodiments, the process of etching the portion of the inner wall of the initial isolation layer 221a located on the side of the first opening 2201 along the first direction Z is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0167] In some embodiments, etching a portion of the inner wall of the initial isolation layer 221a located on the side of the first opening 2201 along the first direction Z includes: etching away a portion of the inner wall of the initial isolation layer 221a located on the side of the first opening 2201 along the first direction Z, and the remaining portion of the initial isolation layer 221a located on the side of the first opening 2201 along the first direction Z forms a second isolation layer 223.

[0168] In other embodiments, etching the portion of the inner wall of the initial isolation layer 221a located on the Z-side of the first opening 2201 includes etching away the entire inner wall of the initial isolation layer 221a located on the Z-side of the first opening 2201. Accordingly, no second isolation layer is formed.

[0169] In some embodiments, an initial isolation layer is formed before the first sacrificial layer is formed; after the first sacrificial layer is removed, the portion of the initial isolation layer located on the inner wall of the first opening along the first direction is etched.

[0170] In other embodiments, a first isolation layer is formed on the sidewall of the first opening before the first sacrificial layer is formed.

[0171] refer to Figure 18 After removing the first sacrificial layer 222a, a conductive layer 222 is formed in the first opening 2201.

[0172] In some embodiments, after the first sacrificial layer 222a is removed and the first isolation layer 221 is formed, a conductive layer 222 is formed in the first opening 2201.

[0173] In some embodiments, the process of forming the conductive layer 222 in the first opening 2201 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0174] The material of the conductive layer 222 is the same as that of the conductive layer 222 in the aforementioned embodiment.

[0175] In some embodiments, the conductive layer 222, the first insulating layer 221, and the second insulating layer 223 constitute a connection structure 220. In other embodiments, the conductive layer 222 and the first insulating layer 221 constitute a connection structure.

[0176] In some embodiments, the second support structure 210 is located between the connecting structure 220 and the isolation structure 200 in the second direction X and extends through the stacked structure D in the first direction Z.

[0177] In some embodiments, a portion of the second support structures 210 are located between the connecting structure 220 and the isolation structure 200 in the second direction X, another portion of the second support structures 210 may be located between adjacent connecting structures 220 in the third direction Y, another portion of the second support structures 210 may be located between the connecting structure 220 and the channel structure 240 in the third direction Y, and another portion of the second support structures 210 may be located between adjacent connecting structures 220 in the second direction X.

[0178] In some embodiments, the channel structure 240 is located on the side of the connection structure 220 along the third direction Y and extends through the stacked structure D along the first direction Z.

[0179] In some embodiments, the first support structure 230 is located in the stacked structure D and on one side of the connecting structure 220 along the first direction Z.

[0180] In some embodiments, a connecting structure 220 is located on one side of a plurality of first support structures 230 in the opposite direction to the first direction Z; or, a connecting structure 220 is located on one side of a first support structure 230 in the opposite direction to the first direction Z.

[0181] refer to Figure 19 Remove substrate 100a; after removing substrate 100a, form semiconductor layer 100 on the side of stacked structure D opposite to dielectric structure 250.

[0182] In some embodiments, the process for removing the substrate 100a is an etching process, which includes one or a combination of dry etching and wet etching processes.

[0183] In some embodiments, the process of forming the semiconductor layer 100 includes a deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0184] The material of the semiconductor layer 100 is as described in the aforementioned embodiment.

[0185] Another embodiment of this application also provides a memory, referenced... Figure 20 It includes a memory cell array F1 and a peripheral circuit F2. The memory cell array F1 includes the semiconductor structure provided in the above embodiments of this application, and the peripheral circuit F2 is coupled to the memory cell array F1.

[0186] The memory cell array F1 can be a 3D NAND flash memory cell array.

[0187] The semiconductor structure may be the same as the semiconductor structure described in any of the embodiments above, and will not be described again in the embodiments of this application.

[0188] In some implementations, the peripheral circuitry F2 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array F1. For example, the peripheral circuitry F2 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0189] Another embodiment of this application also provides a system 30000 having a storage system 32000. (See reference...) Figure 21 , Figure 21This is a block diagram of a system 30000 having a storage system 32000 according to one embodiment of this application. Figure 22 This is a schematic diagram of a storage system according to one embodiment of this application.

[0190] like Figure 21 As shown, system 30000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 32000 located therein). Figure 21 As shown, system 30000 may include host 31000 and storage system 32000, storage system 32000 having one or more memories 32100 and controller 32200. Host 31000 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). Host 31000 may be configured to send or receive data to and from memory 32100.

[0191] Memory 32100 may include the memory described in any embodiment of this application. According to some embodiments, controller 32200 is coupled to memory 32100 and host 31000 and is configured to control memory 32100. Controller 32200 can manage data stored in memory 32100 and communicate with host 31000. In some embodiments, controller 32200 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 32200 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device such as a smartphone, tablet, laptop, etc. The controller 32200 can be configured to control the operation of the memory 32100, such as read, erase, and program operations. The controller 32200 can also be configured to manage various functions related to data stored in or to be stored in the memory 32100, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the controller 32200 is further configured to process error correction codes (ECCs) related to data read from or written to the memory 32100. The controller 32200 can also perform any other appropriate functions, such as formatting the memory 32100. The controller 32200 can communicate with external devices (e.g., host 31000) according to a specific communication protocol. For example, the controller 32200 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-express, PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0192] The controller 32200 and one or more memories 32100 can be integrated into various types of storage systems, such as Universal Flash Memory (UFS) packaged products or eMMC packaged products, where the controller 32200 and one or more memories 32100 can be included in the same packaged product (such as a Universal Flash Memory (UFS) packaged product or an eMMC packaged product). Figure 22 In one example shown in (a), the controller 32200 and a single memory 32100 may be integrated into a memory card 33100. The memory card 33100 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 33100 may further include a connection between the memory card 33100 and a host (e.g., Figure 21 The host 31000 in the memory card connector 32300 is coupled to the host 31000. In such a... Figure 22 In another example shown in (b), the controller 32200 and multiple memories 32100 may be integrated into the solid-state drive 33200. The solid-state drive 33200 may further include a connection between the solid-state drive 33200 and a host (e.g., Figure 21 The solid-state drive connector 32400 is coupled to the host 3100. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 33200 is higher than that of the memory card 33100.

[0193] Although exemplary fabrication methods and structures of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor structure. Furthermore, the materials of the exemplified layers are merely exemplary.

[0194] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, comprising: A stacked structure comprising alternating layers of insulating and gate layers; Connection structure, including: A conductive layer extends in the stacked structure along a first direction and is connected to a gate layer along the first direction on one side of the conductive layer; as well as A first isolation layer is located between the conductive layer and the stacked structure along a direction intersecting the first direction.

2. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: A first support structure is located in the stacked structure and on one side of the connecting structure along the first direction.

3. The semiconductor structure according to claim 2, wherein, One of the connecting structures is located on one side of the plurality of first support structures along the opposite direction to the first direction; or, one of the connecting structures is located on one side of a first support structure along the opposite direction to the first direction.

4. The semiconductor structure according to claim 2, wherein, The material of the first support structure includes an insulating dielectric material.

5. The semiconductor structure according to claim 2, wherein, The first support structure is in contact with a portion of the conductive layer.

6. The semiconductor structure according to claim 2, wherein, The connection structure also includes: A second isolation layer is located between the conductive layer and the first support structure; Wherein, in the direction intersecting the first direction, the size of the second insulating layer is smaller than the size of the end of the conductive layer along one side of the first direction.

7. The semiconductor structure according to claim 6, wherein, The second isolation layer extends along the first direction through the gate layer between the first support structure and the conductive layer.

8. The semiconductor structure according to claim 2, wherein, The semiconductor structure also includes: A semiconductor layer is located on one side of the stacked structure along the first direction; The first support structure extends into the semiconductor layer.

9. The semiconductor structure according to claim 2, wherein, In the direction intersecting the first direction, the size of the first support structure is smaller than the size of the conductive layer.

10. The semiconductor structure according to claim 1, wherein, The distance in the first direction from the surface of the conductive layer on the side opposite to the first direction to the surface of the stacked structure on the side of the first direction is greater than the distance in the first direction from the surface of the first insulating layer on the side opposite to the first direction to the surface of the stacked structure on the side of the first direction.

11. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: An isolation structure is located on the side of the connecting structure along the second direction and extends through the stacked structure along the first direction; The second direction intersects with the first direction.

12. The semiconductor structure according to claim 11, wherein, Relative to the surface of the stacked structure along the first direction, in the first direction, the height of the surface of the isolation structure along the opposite direction is between the height of the surface of the first isolation layer along the opposite direction and the height of the surface of the conductive layer along the opposite direction.

13. The semiconductor structure according to claim 11, wherein, The isolation structure has wavy sidewalls along both sides of the second direction.

14. The semiconductor structure according to claim 11, wherein, The semiconductor structure also includes: The second support structure is located between the connecting structure and the isolation structure in the second direction, and extends through the stacked structure along the first direction.

15. The semiconductor structure according to claim 14, wherein, The material of the second support structure includes an insulating dielectric material.

16. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: A channel structure is located on the side of the connecting structure along a third direction and extends through the stacked structure along the first direction; Wherein, the third direction intersects with the first direction.

17. A method for fabricating a semiconductor structure, comprising: Forming a stacked structure; Forming a connection structure; The stacked structure includes alternating layers of insulating layers and gate layers; The connection structure includes: A conductive layer extending in the stacked structure along a first direction and connected to a gate layer along the first direction on one side of the conductive layer; and A first isolation layer is located between the conductive layer and the stacked structure along a direction intersecting the first direction.

18. The preparation method according to claim 17, wherein, Forming the stacked structure includes: An initial stacked structure is formed, the initial stacked structure comprising alternating layers of insulating layers and sacrificial dielectric layers; and The sacrificial dielectric layer is replaced with the gate layer to form the stacked structure; The connection structure includes: A first opening extending along the first direction is formed in the initial stacked structure; The first isolation layer is formed on the sidewall of the first opening; A first sacrificial layer is formed in the first opening; In response to replacing the sacrificial dielectric layer with the gate layer, the first sacrificial layer is removed; and In response to the removal of the first sacrificial layer, the conductive layer is formed in the first opening.

19. The preparation method according to claim 18, wherein, Forming the first isolation layer on the sidewall of the first opening includes: An initial isolation layer is formed on the sidewall of the first opening and the inner wall of the first opening along the first direction; and The portion of the inner wall of the initial isolation layer located on the side of the first opening along the first direction is etched to expose a gate layer located on the side of the first opening along the first direction, wherein the portion of the initial isolation layer located on the sidewall of the first opening forms the first isolation layer.

20. The preparation method according to claim 19, wherein, Etching the portion of the inner wall of the initial isolation layer located on one side of the first opening along the first direction includes: Etching removes a portion of the inner wall of the initial isolation layer located on the side of the first opening along the first direction, and the remaining portion of the initial isolation layer located on the side of the first opening along the first direction forms a second isolation layer; Alternatively, the entire inner wall of the initial isolation layer located on one side of the first opening along the first direction can be etched away.

21. The preparation method according to claim 18, 19 or 20, wherein, Before the first sacrificial layer is formed, the first isolation layer is formed on the sidewall of the first opening.

22. The preparation method according to claim 19 or 20, wherein, Before forming the first sacrificial layer, the initial isolation layer is formed; after removing the first sacrificial layer, the portion of the initial isolation layer located on the inner wall of the first opening along the first direction is etched.

23. The preparation method according to claim 18, wherein, The preparation method further includes: A first support structure is formed, which is located in the stacked structure and on one side of the connecting structure along the first direction.

24. The preparation method according to claim 23, wherein, The first support structure includes: A first initial support structure is formed, the first initial support structure penetrating the initial stacked structure along the first direction; and Remove a portion of the first initial support structure, and the remaining first initial support structure forms the first support structure; In the process of forming the first opening, a portion of the first initial support structure is removed.

25. The preparation method according to claim 18, wherein, The preparation method further includes: An isolation structure is formed, the isolation structure being located on the side of the connecting structure along the second direction and penetrating the stacked structure along the first direction; wherein the second direction intersects the first direction.

26. The preparation method according to claim 25, wherein, Forming the isolation structure includes: A second sacrificial layer is formed, which penetrates the initial stacked structure along the first direction, and a plurality of second sacrificial layers are spaced apart along a third direction; Remove the second sacrificial layer to form an isolation trench extending along the third direction; The isolation structure is formed in the isolation groove.

27. The preparation method according to claim 25, wherein, The preparation method further includes: A second support structure is formed, which is located between the connecting structure and the isolation structure in the second direction and extends through the stacked structure along the first direction.

28. The preparation method according to claim 17, wherein, The preparation method further includes: A channel structure is formed, the channel structure being located on the side of the connecting structure along a third direction and penetrating the stacked structure along the first direction; Wherein, the third direction intersects with the first direction.

29. The preparation method according to claim 23, wherein, One of the connecting structures is located on one side of the plurality of first support structures along the opposite direction to the first direction; or, one of the connecting structures is located on one side of a first support structure along the opposite direction to the first direction.

30. A memory comprising: A memory cell array, comprising the semiconductor structure as described in any one of claims 1 to 16; The peripheral circuitry is coupled to the memory cell array.

31. A storage system, comprising: The memory as described in claim 30; as well as A controller, coupled to the memory, is used to control the memory to store data.

Images